Using Synthesis Techniques for Power Reduction

Zia Khan, Ph.D.

Graphics Components Division
Intel Corporation

ABSTRACT

Minimizing power consumption of ICs is an important design goal. With the

advent of mobile and hand held devices this goal has taken an increasing
importance. Optimization for power generally comes at a cost; circuit
performance, design complexity and development schedule.

This paper presents the use of synthesis based techniques for reducing power in
designs. The Power Compiler (v1997.08) from Synopsys was used to reduce
power consumption of a graphics chip. Often synthesis-based techniques
provide significant power reduction but at high area penalty. This paper presents
methods that can minimize the area penalty from 15% to less than 2%.
1.0 Introduction

Technological advances in semiconductor manufacturing have made it possible

to put millions of transistors on a single chip. Demand for higher performance
requires switching transistors in these large chips at increasingly higher clock
frequencies. This poses difficult problems for dissipation and distribution of
power on the chips. A significant portion of the total cost of a product is due to
the cost of the heat dissipation mechanisms such as special packaging, heat
sinks and fans. In addition, the need to prolong battery life of mobile products
poses additional demand to reduce power dissipated in designs.

Power consumption is a function of capacitance, voltage and frequency of a

design. There are several methods employed to reduce power consumption.
These methods run the whole gamut; from architectural changes, to clock gating
and voltage reduction. Significant reductions can be achieved using
architectural changes in design to reduce signal activity. These methods call for
selectively switching off portions of a chip if those portions are not needed
during certain modes of operation. For instance, the floating point arithmetic unit
of a processor can be turned off if all computations are being conducted in
integer arithmetic. Power can also be reduced by using a more advanced
process technology that operates at lower voltage and has less gate
capacitance.

In most cases voltage and frequency of a design are dictated by external

requirements and are fixed by design specification. Hence reducing power
consumption is achieved by minimizing the capacitance that is charged and
discharged during each clock cycle.

A simple approach is to consider the toggle rates, also called activity factors, of
various nodes in the netlist and try to reduce the capacitance of nodes that
toggle most often. This approach is supported by a synthesis based
methodology where the synthesis tool is directed to use power consumption as
one of the goals of circuit optimization.

In this paper we present the results of our work using Synopsys’ Power
Compiler (v1997.08). This tool attempts to reduce the amount of capacitance
that is most frequently switched (i.e. charged and discharged) during each clock
period. Power Compiler uses activity factor data from gate level simulations to
determine the frequency of switching of various capacitance values.

In subsequent sections we first describe how Power Compiler measures and

optimizes power consumption of a design. We present the details of how we
evaluated this tool for actual power reduction work. We show power reduction
can be achieved at minimal area cost.

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2.0 Power Reduction Methodology

In any power optimization work the first requirement is to provide the means of
estimating the power of a design. This power estimate can then be used for
setting targets for power reduction work. In following sections we first present the
requirements for power estimation. Then we describe how power reduction tool
can reduce power.

3.0 Power Estimation

The total power consumed by a design consists of three components: switching

power, cell internal power and leakage power. Switching power is due to
charging and discharging of gate and net capacitances when signals are
switching. Cell internal power, also called short circuit power, is due to the
internal switching of transistors in the macro cells (a short circuit path is formed
momentarily when both pull up and pull down devices are turned on). Power
dissipated when the design is in standby mode (i.e. not switching) is the leakage
power.

Synopsys’Design Power is a power estimation tool that uses activity factors and
capacitance information to compute power consumption [1]. It has two basic
modes of operation; probabilistic and simulation. In probabilistic mode the tool
uses user defined activity factors at the inputs of a design and propagates them
through the design. In simulation mode, the actual toggle rates are annotated for
every net in the design. Design Power estimates all three components of power;
switching power, cell internal power and leakage power.

The activity factors, also known as toggle rates, are obtained either from gate
level netlist simulations or from probabilistic estimations. The simulation method
is more accurate than the probabilistic method but has longer run time. The
capacitance information is obtained from the cell library (Synopsys synthesis
library) and parasitics from back annotation files.

4.0 Power Optimization

Once power consumed by a design has been determined, the next step is to find
ways to minimize it. Power Compiler is a logic optimization tool and attempts to
reduce power by using power as one of the cost functions, in addition to timing
and area, to optimize the design [1]. The tool operates at gate level and it can do
one or more of the following transformations to achieve power goals:

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• Gate sizing to match gates to the load. This sizing may result in down sizing
of cells and reduce gate capacitances. Lower gate capacitance results in
lower power.
• Improving the transition time of a signal helps reduce the short circuit current
and thus power. The tool inserts buffers or upsizes cells to improve the edge
rate of signals.
• Trading off positive slack (on non-critical paths) the tool down sizes gates
and reduces gate capacitance. This also reduces power.
• Pin swapping to reduce capacitance on more frequently switching paths.
• Re-constructing logic blocks to minimize capacitance along high activity
paths.

Design Compiler uses the following priority order to meet design objectives: (1)
design rules, max_transition, max_capacitance, etc. (2) timing targets, and (3)
area goals. Because power is an important criteria, Power Compiler changes the
priority order as follows: (1) design rules, (2) timing goals, (3) power targets, and
(4) area goals. Hence, the tool first fixes all design rule violations. Then it
attempts to meet timing goals of the design. After meeting timing goals the tool
attempts to trade positive slack in design to meet power goals. Finally it
attempts to meet area goals.

It is important to note that optimization priority order gives higher precedence to

timing than power and area. Therefore, if a design does not meet timing targets,
the tool first tries to meet timing goals and power optimization is only done after
timing goals have been met (or are determined to be unachievable).

Since Power Compiler uses netlist transformations to achieve power reduction it

only works on synthesizable sections of the design. Thus, IOs or embedded
blocks (such as RAMs/ROMs) are not considered. To implement a
comprehensive power reduction strategy the designers should consider
optimizing circuits for IOs and embedded blocks also.

5.0 Evaluation Methodology

The feasibility and effectiveness of using Power Compiler for reducing the power
of a design was evaluated. A set of experiments were designed to achieve the
following goals:

• Achieve significant power reduction (10-15%) in design

• Require minimal impact to design methodology
• Minimize area penalty (less than 2%)

These goals reflected the requirements of design and marketing teams.

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6.0 Test Case Selection

The validation of power reduction methodology was demonstrated using a

number of test cases. The test cases were selected from an existing database of
a large graphics chip. These designs were selected on the basis of the following
criteria:

• design should already have been optimized and meet timing goals.
• design should not have any finite state machines.
• design should be small enough that many experiments can be run but not too
small that the data is not representative.

Based on these criteria three designs were selected.

7.0 Activity Factor Calculations

An important aspect of power estimation is the availability of a "representative"

vector set for simulation. A representative vector set exercises the design in a
manner that is very similar to the use of the chip in a real system. Given the
variety of applications the personal computers are used for, this is a very difficult
requirement to comply with. For work reported in this paper we estimated toggle
rates by assuming that clock signals toggle two times per cycle (once for going
high and once for going low) and all other signals change 0.25 times per cycle.
These toggle rates were applied to the primary inputs of circuits and activity
factors for all nodes were computed using probabilistic estimations.

8.0 Power Compiler Experiments

The first set of experiments were designed to determine the maximum power
saving that can be achieved by Power Compiler. To measure the quality of
results we defined a number of criteria; cell area, power, cell count and slack.
The cell area is the area of cell in square microns and is obtained from the cell
library. Power Compiler computes the power consumed by a design based on
specific toggle information. It is reported in mW. Cell count refers to the number
cell instances in a netlist. It helps determined the “size” of the netlist. Slack is the
amount of positive margin in the design and is measured in pico seconds.

All designs were synthesized using a 0.35 micron process library at 3.3 V and
125 degree C operating conditions. This library had been characterized for
power. The designs were first optimized for timing and area to achieve smallest

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possible designs that do not have any negative slack. Then power optimization
was used to reduce power. The power target for each design was set at 0 mW
so that maximum power reduction can be achieved. The results of these
experiments are shown in Table 1.

Table 1: Power optimization data for maximum power savings

Design Version Power goal Area Area% Power Power% #cells Cells% Slack
design_1 rev_1 None 293386 100% 60.78 100% 1585 100% 571
rev_2 0 347016 118% 40.01 66% 2224 140% 2.2

Design Version Power goal Area Area% Power Power% #cells Cells% Slack
design_2 rev_1 None 86846 100% 20.92 100% 377 100% 556
rev_2 0 112212 129% 17.47 84% 621 165% 556

Design Version Power goal Area Area% Power Power% #cells Cells% Slack
design_3 rev_1 None 313014 100% 70.28 100% 1749 100% 1
rev_2 0 363218 116% 50.89 72% 2267 130% 1

rev_1 = Original design netlist

rev_2 = Netlist after power optimization using power target = 0 mW

This data shows that even though very significant power savings (~16-34%) are
possible, it comes at a very high area cost (16-29%). The area reported in these
tables is the cell area and does not include routing area. It is often more
instructive to consider increase in cell count as an indicator of area growth. The
cell count increases are very significant (30-65%).

These results, although excellent for power savings, were not very encouraging
due to high area cost. By default the priority order is design rules, timing, power
and area. To find a way to reduce power without incurring a high area penalty
we looked into feasibility of changing the priority order of the tool so that area
reduction has higher priority than power optimization. We asked the vendor if it
is possible to change the priority order of the tool so that area reduction has
higher priority than power reduction. We were informed that this priority order is
fixed (hard coded in the tool) and can not be changed.

Looking for alternative solutions to help reduce the area penalty we thought
about changing the power goals to see if that might help change the cost
function. We started with an area optimized design and computed it’s power
(before any power optimizations were done). This was defined as the base line
power value (= 100%). Then we ran several power optimization experiments and
adjusted power targets to 90%, 80%, etc. The results of these experiments as
shown in Table 2:

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 Table 2: Power optimization data for various power targets (below 100%)

Design Version Power goal Area Area% Power Power% #cells Cells% Slack
design_1 rev_1 None 297131 100% 60.35 100% 1622 100% 571
rev_2 100% 329889 111% 40.64 67% 2029 125% 1
rev_3 90% 334695 113% 40.24 67% 2092 129% 0
rev_4 80% 351025 118% 39.91 66% 2269 140% 2
rev_5 70% 351044 118% 39.62 66% 2272 140% 5

Design Version Power goal Area Area% Power Power% #cells Cells% Slack
design_2 rev_1 None 97797 100% 20.17 100% 443 100% 556
rev_2 100% 112607 115% 17.50 87% 627 142% 23
rev_3 90% 112607 115% 17.50 87% 627 142% 23
rev_4 80% 112518 115% 17.50 87% 623 141% 23
rev_5 70% 112679 115% 17.51 87% 625 141% 30

Design Version Power goal Area Area% Power Power% #cells Cells% Slack
design_3 rev_1 None 315187 100% 71.15 100% 1761 100% 15
rev_2 100% 353772 112% 50.16 70% 2149 122% 0
rev_3 90% 367640 117% 50.48 71% 2307 131% 1
rev_4 80% 368065 117% 50.39 71% 2320 132% 0
rev_5 70% 368190 117% 50.43 71% 2319 132% 1

rev_1 = Original design netlist

rev_2 = Netlist after power optimization using power target = 100%
rev_3 = Netlist after power optimization using power target = 90%
rev_4 = Netlist after power optimization using power target = 80%
rev_5 = Netlist after power optimization using power target = 70%

This data shows that area penalty for power reduction was less if the power
target was set at 100% or 90%. The tool still did significant power reduction at
considerably less area penalty (~18%). However, this area penalty was still
unacceptably high making this tool unsuitable for our needs. Our goal was to
limit area penalty to no more 2-3%.

Looking for alternatives, we decided to experiment with setting power goals

higher than the original netlist. The rationale for this attempt was that even if the
power target is set at 100% or 90% the tool seemed to do more than desired
power reduction. What if we set a higher target? Since power reduction
algorithm is still invoked it would do power reduction but perhaps would use less
area. Following this line of argument, we designed experiments that set power
targets higher that 100%. The results of these experiments are shown in Table
#3:

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 Table 3: Power Optimization data for various power targets (above 100%)

Design Version Power goal Area Area% Power Power% #cells Cells% Slack
design_1 rev_1 None 293386 100% 60.78 100% 1585 100% 571
rev_2 100% 326445 111% 41.67 69% 1937 122% 7
rev_3 125% 311121 106% 43.06 71% 1779 112% 3
rev_4 150% 298392 102% 44.17 73% 1628 103% 8
rev_5 175% 297934 102% 45.93 76% 1613 102% 6
rev_6 200% 297934 102% 45.93 76% 1613 102% 6

Design Version Power goal Area Area% Power Power% #cells Cells% Slack
design_2 rev_1 None 86846 100% 20.92 100% 377 100% 556
rev_2 100% 93372 108% 15.89 76% 510 135% 431
rev_3 125% 86610 100% 17.48 84% 448 119% 556
rev_4 150% 86596 100% 17.43 83% 446 118% 556
rev_5 175% 87007 100% 18.71 89% 431 114% 556
rev_6 200% 84255 97% 18.49 88% 382 101% 556

Design Version Power goal Area Area% Power Power% #cells Cells% Slack
design_3 rev_1 None 313014 100% 70.28 100% 1749 100% 1
rev_2 100% 373415 119% 49.59 71% 2325 133% 0
rev_3 125% 357305 114% 51.55 73% 2151 123% 0
rev_4 150% 357305 114% 51.56 73% 2151 123% 0
rev_5 175% 314120 100% 55.92 80% 1752 100% 3
rev_6 200% 317748 102% 55.41 79% 1778 102% 1

rev_1 = Original design netlist

rev_2 = Netlist after power optimization using power target = 100%
rev_3 = Netlist after power optimization using power target = 125%
rev_4 = Netlist after power optimization using power target = 150%
rev_5 = Netlist after power optimization using power target = 175%
rev_6 = Netlist after power optimization using power target = 200%

This data shows that best results, i.e. least area penalty for most power
reduction, are obtained when power target is set at 175% or 200% of the original
design. The final results for three designs are shown below.

Design Area Penalty % Power Reduction % Cells Increase %

design_1 2% -24% 2%
design_2 -3% -12% 1%
design_3 2% -21% 2%

Thus, the area penalty is less than 2% which is acceptable for our design
needs.

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9.0 Conclusions

Significant power reduction can be achieved by using synthesis tools that aim to
reduce capacitance of frequently switching nodes in a design. The area penalty
due to power saving can be minimized by appropriately adjusting the cost
function of the tool. The work reported here shows Power Compiler is capable
of reducing power consumption of design by 15-20% with area penalty of no
more than 2%. Synthesis for power can be an additional step in synthesis flow
after a netlist has been optimized for timing and area goals.

The authors would like to suggest that following enhancements be considered

for future versions of Power Compiler:

• The tool should allow the user to change the priority order so that area goals
could be prioritized over power targets. Better yet, the user should be able to
specify the acceptable area overhead that can be traded off to achieve power
target.
• The tool should have an exit criteria so that it quits optimization once the
power target has been achieved. In our experiments we noticed that even the
power target was set at 100% the tool did further optimizations.
• The tool should have a downsize only option that allows the user to restrict
the tool to use only cell downsizing for power optimization.

10.0 Acknowledgment
The author would like to thank Omar Malik for his help in setting direction and
scope of this effort.

11.0 References

1. Power Compiler Reference Manual, Synopsys Inc., 1997.

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