DFT Compiler Scan

Replacement User Guide

(DB Mode)
Version X-2005.09, September 2005
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DFT Compiler Scan Replacement User Guide (DB Mode), X-2005.09

ii
 Contents

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

1. Scan Replacement Process

Scan Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
The Scan Replacement Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Selecting a Scan Replacement Strategy . . . . . . . . . . . . . . . . . . . . . . . . . 3
Preventing Scan Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Identifying Barriers to Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
No Appropriate Scan Cells in Technology Library . . . . . . . . . . . . . . . . . . 5
Unsupported Sequential Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Invalid Clock Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Invalid Asynchronous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2. Scan Styles
DFT Compiler Scan Styles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Scan Style Selection Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Setting the Scan Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multiplexed Flip-Flop Scan Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clocked Scan Scan Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

iii
 Level-Sensitive Scan Design (LSSD) Scan Style . . . . . . . . . . . . . . . . . . . . . . 16

3. Verifying Scan Equivalents in the Technology Library

Checking the Technology Library for Scan Cells . . . . . . . . . . . . . . . . . . . . . . . 17
Checking for Scan Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4. Scan Cell Replacement Strategies

Specifying Scan Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Restricting the List of Available Scan Cells . . . . . . . . . . . . . . . . . . . . . . . 21
Some Sample Scan Cell Replacement Strategies. . . . . . . . . . . . . . . . . . 22
Mapping Sequential Gates In Scan Replacement . . . . . . . . . . . . . . . . . . 23
Multibit Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
What are Multibit Components?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
How DFT Compiler Assimilates Multibit Components . . . . . . . . . . . . . . . 25
Controlling Multibit Test Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Performing Multibit Component Scan Replacement . . . . . . . . . . . . . . . . 26
To Disable Multibit Component Support. . . . . . . . . . . . . . . . . . . . . . . . . . 27

5. Test-Ready Compile
What is Test-Ready Compile? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
The Test-Ready Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Preparing for Logical and Physical Test-Ready Compile . . . . . . . . . . . . . . . . . 31
Performing Test-Ready Compile in the Logical Domain. . . . . . . . . . . . . . 31
Performing Test-Ready Compile in the Physical Domain . . . . . . . . . . . . . 32
Controlling Test-Ready Compile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Comparing Default Compile and Test-Ready Compile . . . . . . . . . . . . . . . . . . 33
Complex Compile Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6. Validating Your Netlist

Running the link Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Running the check_design Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Index

iv
 About This Manual

The DFT Compiler Scan Replacement User Guide describes scan replacement
strategies when using DFT Compiler.

Audience
This manual is intended for ASIC deisgn engineers who have some exposure
to testability concepts and strategies. It is also useful for test and
design-for-test engineers who want to understand how basic test automation
concepts and practices relate to DFT Compiler.

Related Publications
For additional information about DFT Compiler, see:
• Documentation on the Web, which provides HTML and PDF documents and
is available through SolvNet at:
http://solvnet.synopsys.com
• The documentation installed with the DFT Compiler software and available
through the DFT Compiler Help menu
• Synopsys Online Documentation (SOLD), which is included with the
software for CD users or is available to download through the Synopsys
Electronic Software Transfer (EST) system

v
About This Manual
Conventions

You might also want to refer to the documentation for the following related
Synopsys products:
• Design Compiler
• BSD Compiler
• TetraMAX

Conventions
The following conventions are used in Synopsys documentation.
Convention Description

Courier Indicates command syntax.

Courier italic Indicates a user-defined value in Synopsys syntax, such as

object_name.

Courier bold Indicates user input—text you type verbatim—in Synopsys

syntax and examples.

Regular bold User input that is not Synopsys syntax, such as a user
name or password you enter in a GUI.

[] Denotes optional parameters, such as

pin1 [pin2 ... pinN]

... Indicates that a parameter can be repeated as many times

as necessary

| Indicates a choice among alternatives, such as

low | medium | high
(This example indicates that you can enter one of three
possible values for an option: low, medium, or high.)

_ Connects terms that are read as a single term by the

system, such as set_annotated_delay

Control-c Indicates a keyboard combination, such as holding down

the Control key and pressing c.

\ Indicates a continuation of a command line.

vi
 About This Manual
Customer Support

Convention Description

/ Indicates levels of directory structure.

Edit > Copy Indicates a path to a menu command, such as opening the
Edit menu and choosing Copy.

Customer Support
Customer support is available through SolvNet online customer support and
through contacting the Synopsys Technical Support Center.

Accessing SolvNet
SolvNet includes an electronic knowledge base of technical articles and
answers to frequently asked questions about Synopsys tools. SolvNet also
gives you access to a wide range of Synopsys online services including
software downloads, documentation on the Web, and “Enter a Call to the
Support Center.”
To access SolvNet:

1. Go to the SolvNet Web page at http://solvnet.synopsys.com.

2. If prompted, enter your user name and password. (If you do not have a
Synopsys user name and password, follow the instructions to register with
SolvNet.)
If you need help using SolvNet, click SolvNet Help in the Support Resources
section.

Contacting the Synopsys Technical Support Center

If you have problems, questions, or suggestions, you can contact the Synopsys
Technical Support Center in the following ways:
• Open a call to your local support center from the Web by going to
http://solvnet.synopsys.com (Synopsys user name and password required),
then clicking “Enter a Call to the Support Center.”
• Send an e-mail message to your local support center.
- E-mail support_center@synopsys.com from within North America.

vii
About This Manual
Customer Support

- Find other local support center e-mail addresses at

http://www.synopsys.com/support/support_ctr.
• Telephone your local support center.
- Call (800) 245-8005 from within the continental United States.
- Call (650) 584-4200 from Canada.
- Find other local support center telephone numbers at
http://www.synopsys.com/support/support_ctr.

viii
 1
Scan Replacement Process1

This chapter discusses the scan replacement process.

Scan Replacement
The scan replacement process inserts scan cells into your design by replacing
nonscan sequential cells with their scan equivalents. If you start with an HDL
description of your design, scan replacement occurs during the initial mapping
of your design to gates. You can also start with a gate-level netlist. When you
do, scan replacement occurs as an independent process.
With either approach, scan synthesis considers the design constraints and the
impact of both the scan cells themselves and the additional loading due to scan
chain routing to minimize the impact of the scan structures on the design.
Figure 1 shows the flow for the scan replacement process. This figure assumes
that you are starting with an HDL description of the design. If you are starting
with a gate-level netlist instead, you must use constraint-optimized scan
insertion.

1
Scan Replacement Process
Scan Replacement

Figure 1 Synthesis and Scan Replacement Flow

Start

Select
scan style

HDL Read HDL

file description

Violations
Change Check test
design design rules
No
violations

Prepare for
synthesis

Synthesize and
replace scan

Assemble scan chains

The Scan Replacement Process

To perform scan replacement, follow these steps:
1. Select a scan style.
DFT Compiler requires a scan style to perform scan synthesis. The scan
style dictates the appropriate scan cells to insert during optimization. You
must select a single scan style and use this style on all modules of your
design.
2. Check test design rules of the HDL-level design description.
3. Prepare for synthesis.
You can perform logic or physical synthesis on your design. DFT Compiler
functionality supports either form.
4. Synthesize your design.

2
 Scan Replacement Process
Scan Replacement

Test-ready compile maps all sequential cells directly to scan cells. During
optimization, DFT Compiler considers the design constraints and the impact
of both the scan cells themselves and the additional loading due to scan
chain routing to minimize the impact of the scan structures on the design.

Selecting a Scan Replacement Strategy

Select the scan replacement strategy based on the status of your design. If you
have an optimized gate-level design and will not be using the compile
command to perform further optimization, use constraint-optimized scan
insertion. In all other cases, use test-ready compile to insert the scan cells.
Figure 2 shows how to determine the appropriate scan replacement strategy.
Figure 2 Selecting a Scan Replacement Strategy

Optimized Yes Use

Gate-Level Constraint-Optimized
Design? Scan Insertion

No

Use
Test-Ready Compile

Test-ready compile offers these advantages:

• Single-pass synthesis
With test-ready compile, the Synopsys tools converge on true one-pass
scan synthesis. As a practical matter, design constraints usually result in
some cleanup and additional optimization after compile, but test-ready
compile is more straightforward than previous methods.
• Better quality of results
Test-ready compile offers better quality of results (QOR) than past methods.
Including scan cells at the time of first optimization results in fewer design
rule violations and other constraint violations due to scan circuitry.
• Simpler overall flow
Test-ready compile requires fewer optimization iterations than previous
methods.

3
Scan Replacement Process
Identifying Barriers to Scan Replacement

Preventing Scan Replacement

When running test-ready compile on a gate-level netlist, DFT Compiler
respects the following attributes that prevent scan replacement:
• dont_touch
• scan_element false
When either of these attributes exist on a mapped sequential cell, test-ready
compile does not replace the cell with a scan equivalent.

Identifying Barriers to Scan Replacement

In full-scan designs, constraint-optimized scan insertion replaces all sequential
cells with scan equivalents except those that
• Have test design rule violations
• Have a scan_element false or dont_touch attribute
• Are scan replaced (for example, by test-ready compile)
• Are part of a scan segment.
In general, nonscan sequential cells reduce the achievable fault coverage.
Before executing constraint-optimized scan insertion, perform test design rule
checking to identify conditions that prevent scan replacement. Use the
dft_drc command to invoke test design rule checking.
Test design rule checking identifies the following conditions that prevent scan
replacement:
• The technology library does not contain an appropriate scan cell for the
sequential cell.
• DFT Compiler does not support scan replacement for the sequential cell.
• The sequential cell has an attribute that prevents scan replacement.
• An invalid net drives the clock pin of the sequential cell.
• An invalid net drives the asynchronous pin of the sequential cell.
The following sections provide details about each of these conditions.

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 Scan Replacement Process
Identifying Barriers to Scan Replacement

No Appropriate Scan Cells in Technology Library

If a scan equivalent does not exist for a sequential cell, scan replacement
cannot occur for that cell. DFT Compiler generates this message when a scan
equivalent does not exist for a sequential cell:
Warning: No scan equivalent exists for cell %s (%s).
(TEST-120)

This warning message can occur when:

• The technology library does not contain scan cells
If DFT Compiler does not find scan cells in the technology library, it also
generates this message:
Warning: Target library for design contains no
scan-cell models. (TEST-224)

Check with your semiconductor vendor to see if the vendor provides a

technology library that supports scan synthesis.
• The technology library contains scan cells but does not support a scan
equivalent for the nonscan cell
• The technology library contains scan cells but incorrectly models the scan
equivalent for the nonscan cell
If DFT Compiler finds a scan cell in the technology library that is not the
obvious replacement cell you expect, the reason could be:
• The chosen scan equivalent results in a lower-cost implementation overall.
• The technology library has a problem. In that case, contact the ASIC vendor
for more information.

Unsupported Sequential Cell

DFT Compiler supports sequential cells that have these characteristics:
• During functional operation, the cell functions as a D flip-flop, a D latch, or a
master-slave latch.
• During scan operation, the cell functions as a D flip-flop or a master-slave
latch.
• The cell stores a single bit of data.

5
Scan Replacement Process
Identifying Barriers to Scan Replacement

Edge-triggered cells that violate this requirement cause DFT Compiler to

generate this message:

Warning: Cell %s (%s) is not supported because it has

too many states (%d states). This cell is being
black-boxed.(TEST-462)

Master-slave latch pairs with extra states cause DFT Compiler to generate
one of these messages (depending on the situation):

Warning: Master-slave cell %s (%s) is not supported

because state pin %s is neither master nor slave. This
cell is being black-boxed.(TEST-463)
Warning: Master-slave cell %s (%s) is not supported
because there are two or more master states. This cell
is being black-boxed.(TEST-464)
Warning: Master-slave cell %s (%s) is not supported
because there are two or more slave states. This cell
is being black-boxed.(TEST-465)

• The cell has a three-state output.

Cells that violate this requirement cause DFT Compiler to generate this
message:

Warning: Cell %s (%s) is not supported because it is a

sequential cell with three-state outputs. This cell is
being black-boxed.(TEST-468)

• The cell uses a single clock per internal state (the cell might use different
clocks for functional and test operations).
Cells that violate this requirement cause DFT Compiler to generate one of
these messages:

6
 Scan Replacement Process
Identifying Barriers to Scan Replacement

Warning: Cell %s (%s) is not supported because state

pin %s has no clocks. This cell is being black-boxed.
(TEST-466)
Warning: Cell %s (%s) is not supported because state
pin %s is multi-port. This cell is being black-boxed.
(TEST-467)

Your design contains unsupported sequential cells only if you instantiate them.
DFT Compiler does not insert unsupported sequential cells in your design.

Attributes
The following attributes prevent scan replacement:
• scan_element false
A scan_element false attribute excludes sequential cells from scan
replacement. Just remember that nonscan sequential cells generally reduce
the fault coverage results for full-scan designs.
• dont_touch
A dont_touch attribute on a flip-flop prevents scan replacement but still
allows scan routing of the flip-flop if it is already scan replaced. A
dont_touch attribute also prevents AutoFix from fixing a clock or reset
violation on a flip-flop.
Be aware that a dont_touch attribute on the top-level design does not
prevent scan replacement on the design.
These attributes differ in that the dont_touch attribute can be assigned at any
level, but the scan_element attribute is ignored unless you apply it at the
same level where you issue the insert_dft command.
DFT Compiler generates the following message when a sequential cell has a
scan_element false attribute:
Information: Cell %s (%s) will not be scanned due to a
or set_scan_element command. (TEST-202)

DFT Compiler generates this message when a nonscan sequential cell has a
dont_touch attribute:

7
Scan Replacement Process
Identifying Barriers to Scan Replacement

Information: Cell %s (%s) could not be made scannable as

it is dont_touched. (TEST-121)

The set_dont_touch command is intended to prevent logic optimization; do

not use this command to prevent scan replacement.
If you do not want to exclude the affected cells from scan replacement, locate
and remove the attribute causing the violation. Locate the attribute using the
get_attribute or report_attribute command. Remove the attribute
using the remove_attribute command.
When you use the set_scan_transparent command on a latch cell, the
fault coverage estimation mechanism uses a transparent (pseudo-
combinational) model for the latch cell.
DFT Compiler generates the following message when a latch has a
scan_latch_transparent attribute:

Information: Latch cell %s (%s) assumed non-scan and

transparent for testing. (TEST-204)

Invalid Clock Nets

The term system clock refers to a clock used in the parallel capture cycle. The
term test clock refers to a clock used during scan shift. Multiplexed flip-flop
designs use the same clock as both the system clock and the test clock.
In a nonscan design, an invalid clock net (whether system clock or test clock)
prevents scan replacement of all sequential cells driven by that clock net.
The requirements for valid clocks in DFT Compiler include the following:

8
 Scan Replacement Process
Identifying Barriers to Scan Replacement

• A system or test clock used during scan testing must be driven from a single
top-level port.
An active clock edge at a sequential cell must be the result of a clock pulse
applied at a top-level port, not the result of combinational logic driving the
clock net.
• A system or test clock used during scan testing must not be driven from a
bidirectional port.
DFT Compiler does not support the use of bidirectional ports as clock ports.
When a bidirectional port drives a clock net, DFT Compiler forces the net to
X, and cells clocked by the net become black box sequential cells.
• A system or test clock used during scan testing must be generated in a
single tester cycle.
The clock pulse applied at the clock port must reach the sequential cells in
the same tester cycle. DFT Compiler does not support sequential gating of
clocks, such as clock divider circuitry.
• A system or test clock used during scan testing cannot be the result of
multiple clock inputs.
DFT Compiler does not support the use of combinationally combined clock
signals (even if the same port drives the signal).
Note:
If the same port drives the combinationally combined clock signal (as in
the design on the left in Figure 3 or the design in Figure 4), DFT
Compiler does not detect the problem in nonscan or unrouted scan
designs.
Figure 3 shows sample designs that use combinationally combined clocks.
When multiple clock signals drive a clock net, DFT Compiler forces the net
to X, and cells clocked by the net become black box sequential cells.
Figure 3 Examples of Combinationally Combined Clock Nets

d q d q

clk clk1
clk2

9
Scan Replacement Process
Identifying Barriers to Scan Replacement

By default, DFT Compiler supports the use of reconvergent clocks, such as

clocks driven by parallel clock buffers. Figure 4 shows an example of a
design that uses a reconvergent clock net. To prevent dft_drc from
allowing such reconvergent clocks in your design, set the
test_allow_clock_reconvergence variable to false.
Figure 4 Example of a Reconvergent Clock Net

d q

clk

• A test clock must remain active throughout the scan shift process.
To load the scan chain reliably, make sure the test clock remains active until
scan shift completes. For combinationally gated clocks, you must configure
the design to disable the clock gating during scan shift.
DFT Compiler supports combinational clock gating during the parallel
capture cycle.
Test design rule checking on a nonscan design might not detect invalid clock
nets. DFT Compiler identifies all invalid clock nets only in existing scan designs.
DFT Compiler cannot control the clock net when:
• A sequential cell drives the clock net
• A multiplexer with an unspecified select line drives the clock net (test clocks
only)
• Combinational clock-gating logic can generate an active edge on the clock
net
DFT Compiler generates this message when it detects an uncontrollable clock:
Warning: Normal mode clock pin %s of cell %s (%s) is
uncontrollable. (TEST-169)

10
 Scan Replacement Process
Identifying Barriers to Scan Replacement

Because uncontrollable clock nets prevent scan replacement, you should

correct uncontrollable clocks. Sequentially driven clocks require test-mode logic
to bypass the violation. You can bypass violations caused by other sources of
uncontrollable clocks using test configuration or test-mode logic.
DFT Compiler can control a combinationally gated test clock that cannot
generate an active clock edge. However, DFT Compiler considers this type of
clock invalid, because the clock might not remain active throughout scan shift.
In this case, DFT Compiler generates this message:
Warning: Shift clock pin %s of cell %s (%s) is illegally
gated. (TEST-186)

Because invalid gated-clock nets prevent scan replacement, you should correct
invalid gated clocks. You can use AutoFix to bypass invalid gated clocks when
using the multiplexed flip-flop scan style. You might also be able to change the
test configuration to bypass the violation.

Invalid Asynchronous Pins

DFT Compiler considers a net driving an asynchronous pin valid if it can
disable the net from an input port or a combination of input ports. DFT Compiler
cannot control an asynchronous pin driven by ungated sequential logic.
In a nonscan design, a net with an uncontrollable asynchronous pin prevents
scan replacement of all sequential cells connected to that net.
DFT Compiler generates this message when it detects an uncontrollable
asynchronous pin:
Warning: Asynchronous pins of cell FF_A (FD2) are
uncontrollable. (TEST-116)

Because nets with an uncontrollable asynchronous pin prevent scan

replacement, you should correct uncontrollable nets. Use Autofix (if you are
using the multiplexed flip-flop scan style), test configuration, or test-mode logic
to bypass uncontrollable asynchronous pin violations.

11
Scan Replacement Process
Identifying Barriers to Scan Replacement

12
 2
Scan Styles2

This chapter discusses the four scan styles supported by DFT

Compiler.

DFT Compiler Scan Styles

DFT Compiler supports four scan styles:
• Multiplexed flip-flop
• Clocked scan
• Level-sensitive scan design (LSSD), which includes clocked LSSD
• Auxiliary-clock LSSD
Note:
For the purposes of this document, the term LSSD refers to LSSD, clocked
LSSD, and auxiliary-clock LSSD.

13
Scan Styles
Scan Style Selection Considerations

Scan Style Selection Considerations

Consider the following questions when selecting a scan style:
• Which scan styles are supported in your technology library?
To implement internal scan structures in the scan style you select,
appropriate scan cells must be present in the technology libraries specified
in the target_library variable.
Use of sequential cells that do not have a scan equivalent always results in
a loss of fault coverage in full-scan designs. Techniques to verify scan
equivalents are discussed in Chapter 3, “Verifying Scan Equivalents in the
Technology Library.”
• What is your design style?
If your design is predominantly edge-triggered, use the multiplexed flip-flop,
clocked scan, clocked LSSD, or auxiliary-clock LSSD scan style.
If your design has a mix of latches and flip-flops, use the clocked scan or
LSSD scan style.
If your design is predominately level-sensitive, use the LSSD scan style.
• How complete are the models in your technology library?
The quality and accuracy of the scan and nonscan sequential cell models in
the Synopsys technology library affect the behavior of DFT Compiler.
Incorrect or incomplete library models can cause incorrect results during
test design rule checking.
DFT Compiler requires a complete functional model of a scan cell to perform
test design rule checking. The Library Compiler UNIGEN model supports
complete functional modeling of all supported scan cells. However, the
usual sequential modeling syntax of Library Compiler only supports
complete functional modeling for multiplexed flip-flop scan cells.
When the technology library does not provide a functional model for a scan
cell, the cell is a black box for DFT Compiler.
For information on the scan cells in the technology library you are using, see
your ASIC vendor. For information on creating technology library elements
or to learn more about modeling scan cells, see the information about
defining test cells in the Library Compiler documentation.

14
 Scan Styles
Setting the Scan Style

Setting the Scan Style

You must select a single scan style and use this style for all modules of your
design. Specify the scan style by setting the test_default_scan_style
variable.
dc_shell-t> set test_default_scan_style style

The scan style defined by the test_default_scan_style variable applies

to all designs in the current session. You can also use the
set_scan_configuration -style command to specify the scan style.
However, this command applies only to the current design. If your selected
scan style differs from the default scan style, you must execute this command
for each module.
Table 1 shows the scan style keywords used to specify the scan style. Use
these keywords with either the test_default_scan_style variable or the
set_scan_configuration -style command.
Table 1 Scan Style Keywords
Scan style Keyword

Multiplexed flip-flop multiplexed_flip_flop

Clocked scan clocked_scan

Level-sensitive scan design lssd

Auxiliary-clock LSSD aux_clock_lssd

Multiplexed Flip-Flop Scan Style

DFT Compiler supports multiplexed flip-flop scan equivalents for D, JK, and
master-slave flip-flops and for D latches. The multiplexed flip-flop scan
equivalents for all flip-flop styles must be fully functionally modeled in the
technology library. This scan style has the following advantages:
• Multiplexed flip-flop is the most widely known and understood scan style.
• If the technology library does not contain scan cells, you can create flip-flop
scan equivalents from discrete multiplexer and flip-flop components. To use
this technique, you must add a dummy scan cell to the technology library.

15
Scan Styles
Clocked Scan Scan Style

The multiplexed flip-flop scan style has the disadvantage that hold-time or clock
skew problems can occur on the scan path because of a short path from a scan
cell’s scan output pin to the next scan cell’s scan input pin. DFT Compiler can
reduce the occurrence of these problems by considering hold-time violations
during optimization.

Clocked Scan Scan Style

DFT Compiler supports clocked scan equivalents for D and JK flip-flops and for
D latches. The clocked-scan style is well suited for use in multiple-clock
designs because of the dedicated test clock. The clocked-scan style also has
some disadvantages:
• Hold-time or clock skew problems can occur on the scan path because of a
short path from a scan cell’s scan output pin to the next scan cell’s scan
input pin. DFT Compiler can reduce the occurrence of these problems by
considering hold-time violations during optimization.
• This scan style requires the routing of two edge-triggered clocks. Routing
clock lines is difficult because you must carefully control the clock skew.

Level-Sensitive Scan Design (LSSD) Scan Style

DFT Compiler supports LSSD equivalents for D, JK, and master-slave flip-flops,
and for D latches. Timing problems on the scan path are unlikely in LSSD
designs because of the use of nonoverlapping two-phase clocks during the
scan operation.
The LSSD scan style also has some disadvantages:
• This scan style requires greater wiring area than the multiplexed flip-flop or
clocked-scan styles.
• DFT Compiler does not support the more complex LSSD cells, such as
multiple data port master latches.
When you use the LSSD scan style, define the clock waveforms so that the
master and slave clocks have nonoverlapping waveforms (the master and slave
latches are never active simultaneously).

16
 3
Verifying Scan Equivalents in the Technology Library3

Before starting scan synthesis, confirm that your technology

library contains scan cells, then verify that the scan cells are
suitable for the selected scan style.

Checking the Technology Library for Scan Cells

You can determine whether the technology library contains scan cells using
either of the following methods:
• Search the library .db file.
Every scan cell, regardless of the scan style, must have a scan input pin and
a scan output pin. You can determine whether the technology library
contains scan cells by using the filter command to search for scan input
(or scan output) pins.
Depending on its polarity, a scan input pin can have a signal_type
attribute of either test_scan_in or test_scan_in_inverted in the
technology library. A scan output pin can have a signal_type attribute of
either test_scan_out or test_scan_out_inverted in the technology
library, depending on its polarity.

17
Verifying Scan Equivalents in the Technology Library
Checking for Scan Equivalents

The following command sequence shows the use of the filter command:
dc_shell-t> read_db class.db
dc_shell-t> get_pin class/*/* -filter "@signal_type ==
test_scan_in"

If the library contains scan cells, the filter command returns a list of pins;
if the library does not contain scan cells, the filter command returns an
empty list.
• Check the test design rules.
As one of the first checks it performs, the dft_drc command determines
the presence of scan cells in the technology library. If the technology
libraries identified in the target_library variable do not contain scan
cells, dft_drc generates the following message:
Warning: Target library for design contains no
scan-cell models. (TEST-224)

You must define the current_design before you run the dft_drc
command.
If your technology library does not contain scan cells, check with your
semiconductor vendor to see if the vendor provides a technology library that
supports test synthesis.

Checking for Scan Equivalents

To verify that the technology library contains scan equivalents for the sequential
cells in your design, run the dft_drc command on your design or on a design
containing the sequential cells likely to be used in your design.
If the technology library does not contain a scan equivalent for a sequential cell
in a nonscan design, dft_drc generates the following message:
Warning: No scan equivalent exists for cell instance
(reference). (TEST-120)

In verbose mode (dft_drc -verbose), the TEST-120 message lists all scan
equivalent pairs available in the target library in the selected scan style. If the
target library contains no scan equivalents in the chosen scan style, no scan
equivalents are listed.
Suppose you have a design containing D flip-flops, but the target technology
library only contains scan equivalents for JK flip-flops. Example 1 shows the

18
 Verifying Scan Equivalents in the Technology Library
Checking for Scan Equivalents

warning message issued by dft_drc, along with the scan equivalent

mappings to available scan cells.
Example 1 Scan Equivalent Listing
Warning: No scan equivalent exists for cell q_reg (FD1P). (TEST-
120)

Scan equivalent mappings for target library are:

FJK3 -> FJK3S

FJK2 -> FJK2S
FJK1 -> FJK1S

19
Verifying Scan Equivalents in the Technology Library
Checking for Scan Equivalents

20
 4
Scan Cell Replacement Strategies4

This chapter describes how to select the set of scan cells and
multibit components to use in your scan replacement strategy.

Specifying Scan Cells

Before you perform scan cell replacement you need to specify the set of scan
cells to be used by DFT Compiler. This section discusses the following topics:
• Restricting the List of Available Scan Cells
• Some Sample Scan Cell Replacement Strategies
• Mapping Sequential Gates In Scan Replacement

Restricting the List of Available Scan Cells

The set_scan_register_type command lets you specify which flip-flop
scan cells are to be used by compile -scan to replace nonscan cells. The
command restricts the choices of scan cells available for scan replacement.
You can apply this restriction to the current design, to particular designs, or to
particular cell instances in the design.

21
Scan Cell Replacement Strategies
Specifying Scan Cells

Note:
The set_scan_register_type command applies to the operation of
both the compile -scan command and the insert_dft command.
The set_scan_register_type command has the following syntax:
set_scan_register_type [-exact]
-type scan_flip_flop_list [cell_or_design_list]

The scan_flip_flop_list is the list of scan cells that compile -scan is allowed
to use for scan replacement. There must be at least one such cell named in the
command. Specify each scan cell by its cell name alone (without the library
name).
The cell_or_design_list is a list of designs or cell instances where the restriction
on scan cell selection is to be applied. In the absence of such a list, the
restriction applies to the current design (as set by the current_design
command) and to all lower-level designs in the design hierarchy.
The -exact option determines whether the restriction on scan cell selection
also applies to back-end delay and area optimization done by insert_dft or
by subsequent synthesis operations such as compile -incremental. If -
exact is used, the restriction still applies to back-end optimization. In other
words, scan cells will only be replaced by other scan cells in the specified list. If
-exact is not used, the optimization algorithm is free to use any scan cell in
the target library.

Some Sample Scan Cell Replacement Strategies

Here are some examples of set_scan_register_type commands:
set_scan_register_type -exact -type FD1S

This command causes compile -scan to use only FD1S scan cells to replace
nonscan cells in the current design. Because of the -exact option, this
restriction applies to both initial scan replacement and subsequent
optimization.
set_scan_register_type -exact
-type {FD1S, FD2S} {add2, U1}

This command causes compile -scan to use only an FD1S or FD2S scan
cell to replace each nonscan cell in all designs and cell instances named add2
or U1. In all other designs and cell instances, compile -scan can use any
scan cells available in the target library. The -exact option forces any back-

22
 Scan Cell Replacement Strategies
Specifying Scan Cells

end delay optimization to respect the scan cell list, thus allowing only FD1S and
FD2S to be used.
set_scan_register_type -type {FD1S FD2S} {add2 U1}

This command is the same as the previous example, except that the -exact
option is not used. This means that the back-end optimization algorithm is free
to replace the FD1S and FD2S cells with any compatible scan cells in the target
library.
If you use the set_scan_register_type command on generic cell
instances, be sure to include the -scan option in the compile command.
Otherwise, the scan specification will be lost.
To determine the current settings resulting from previous use of the
set_scan_register_type command, execute the following command:
report_test -register
This returns a report on all set_scan_register_type settings currently in
effect.
To cancel all set_scan_register_type settings currently in effect, execute
the following command:
remove_scan_register_type

Mapping Sequential Gates In Scan Replacement

To effectively use the set_scan_register_type command, it is important
to understand the scan replacement process.
The compile -scan command maps sequential gates into scan flip-flops and
latches using three steps:
1. The compile -scan command maps each sequential gate in the generic
design description into an initial nonscan latch or flip-flop from the target
library. In the absence of any set_scan_register_type specification,
compile -scan chooses the smallest area-cost flip-flop or latch. For a
design or cell instance that has a set_scan_register_type setting in
effect, compile -scan chooses the nonscan equivalent of a scan cell in
the scan_flip_flop_list.
2. The compile -scan command replaces the nonscan flip-flops with scan
flip-flops, using only the scan cells specified in the
set_scan_register_type command, where applicable.

23
Scan Cell Replacement Strategies
Multibit Components

If compile -scan is unable to use a scan cell from the scan_flip_flop_list,

it uses the best possible matching scan cell from the target library and
issues a warning.
3. If the -exact option is not used in the set_scan_register_type
command, Design Compiler and DFT Compiler attempt to remap each scan
flip-flop into another component from the target library to optimize the delay
or area characteristics of the circuit. If the -exact option is used,
optimization is restricted to using the scan cells in the scan_flip_flop_list.
The operation of step 1 above can be controlled by the set_register_type
command in Design Compiler. The set_register_type command specifies
a list of allowed cells for implementing functions specified in the HDL
description of the design. However, you need to be careful about using this
command in conjunction with scan replacement. For example, if you tell the
compile command to use a sequential cell that has no scan equivalent, then
that cell will be used, which cannot be scan-replaced by DFT Compiler.
The set_scan_register_type command affects only the replacement of
nonscan cells with scan cells. It cannot be used to force existing scan cells to
be replaced with new scan cells. To make this type of design change, you need
to go back to the original nonscan design and apply a new
set_scan_register_type specification, followed by a new compile
-scan or insert_dft operation.

Multibit Components
Multibit components are supported by DFT Compiler during scan replacement.
In this section, the following topics are discussed:
• What are Multibit Components?
• How DFT Compiler Assimilates Multibit Components
• Controlling Multibit Test Synthesis
• Performing Multibit Component Scan Replacement

What are Multibit Components?

A multibit component is a sequence of cells with identical functionality. The
multibit component can consist of single-bit cells or the set of multibit cells
supported by Design Compiler. Cells can have identical functionality even if

24
 Scan Cell Replacement Strategies
Multibit Components

they have different bit widths. Multibit synthesis ensures regularity and
predictability of layout.
HDL Compiler infers multibit components through HDL directives. See the HDL
Compiler for Verilog Reference Manual for more information about multibit
inference. Specify multibit components using the Design Compiler
create_multibit command and remove_multibit command. Control
multibit synthesis using the set_multibit_options command. See the
Design Compiler Reference Manual: Optimization and Timing Analysis for
details.
When you create a new multibit component with the create_multibit
command, choose a name that is different from the name of any existing object
in your design. This will prevent possible conflicts later when you use the
set_scan_path and set_scan_segment commands.
Structured logic synthesis is a special case of multibit synthesis in which the
individual bits of a multibit component are implemented as distinct elements.
Use the set_multibit_options -mode structured command to enable
structured logic synthesis.

How DFT Compiler Assimilates Multibit Components

Multibit components have the following properties:
• All the synthesis and optimization that DFT Compiler performs is as
prescribed by the multibit mode in effect.
• Scan chain allocation and routing result in a layout that is as regular as
possible.
To achieve these goals, DFT Compiler assimilates sequential multibit
components into synthesizable segments.
A synthesizable segment is an extension of the user segment concept. A
synthesizable segment has the following properties:
• Its implementation is not fixed at the time of specification.
• It consists of a name and a sequence of cells that implicitly determine an
internal routing order.
• It lacks access pins and possibly internal routing.
• It need not be scan-replaced.
• Test synthesis controls the implementation.

25
Scan Cell Replacement Strategies
Multibit Components

A synthesizable segment that cannot be synthesized into a valid user segment

is invalid. Only multibit synthesizable segments are supported.

Controlling Multibit Test Synthesis

You control multibit test synthesis through the specification of the scan
configuration. You do this using the following commands:
• set_scan_configuration
• set_scan_transparent
• remove_scan_specification
• set_scan_segment
• set_scan_path
• set_scan_element
Commands that accept segment arguments also accept multibit components.
You can refer by instance name to multibit components from the top-level
design through the design hierarchy. Commands that accept sets of cells also
accept multibit components. When you specify a multibit component as being a
part of a larger segment, the multibit component is included in the larger user-
defined segment without modification.

Performing Multibit Component Scan Replacement

Use the compile -scan command or the insert_dft command to perform
multibit component scan replacement. These commands perform a
homogeneous scan replacement. Bits of a multibit component are either all
scan-replaced or all not scan-replaced. Bits are then assembled into multibit
cells as specified by the set_multibit_options command.
The number of cells after scan replacement can change. For example, a 4-bit
cell can be scan-replaced by two 2-bit cells. If this occurs, the two 2-bit cells get
new names. If the cell is scan-replaced with a cell of equal width, a 4-bit cell
replaced by a 4-bit cell for example, the name of the cell remains the same.
You control the scan replacement of multibit components using the
set_scan_element command.
You control the transparency of level-sensitive multibit components using the
set_scan_transparent command.

26
 Scan Cell Replacement Strategies
Multibit Components

When specifying individual cells using either of these commands, do not

specify an incomplete multibit component unless you previously disabled
multibit optimization.

To Disable Multibit Component Support

You can disable structured logic and multibit component support by doing one
of the following:
• Remove some or all of the multibit components using the
remove_multibit command.
• Turn off scan synthesis using the set_scan_configuration -
multibit_segments false command.
• Turn off scan synthesis on a specific scan segment using the
set_scan_segment -synthesizable false command.

27
Scan Cell Replacement Strategies
Multibit Components

28
 5
Test-Ready Compile5

Scan cell replacement will work most efficiently if you perform

this process when you compile your design.

What is Test-Ready Compile?

Test-ready compile integrates logic optimization and scan replacement. During
the first synthesis pass of each HDL design or module, test-ready compile
maps all sequential cells directly to scan cells. The optimization cost function
considers the impact of the scan cells themselves and the additional loading
due to the scan chain routing. By accounting for the timing impact of internal
scan design from the start of the synthesis process, test-ready compile
eliminates the need for an incremental compile after scan insertion.
During optimization, DFT Compiler cannot determine whether the sequential
cells in your HDL description meet the test design rules, so it maps all
sequential cells to scan cells. Later in the scan synthesis process, DFT
Compiler can convert some sequential cells back to nonscan cells. For
example, test design rule checking might find scan cells with test design rule
violations. In other circumstances, you might manually specify some sequential
cells as nonscan elements. In these cases, DFT Compiler converts the scan
cells to nonscan equivalents during execution of the insert_dft command.
Typically, the input to test-ready compile is an HDL design description. You can
also perform test-ready compile on a nonscan gate-level netlist that requires

29
Test-Ready Compile
What is Test-Ready Compile?

optimization. For example, a gate-level netlist resulting from technology

translation usually requires logic optimization to meet constraints. In this case,
use test-ready compile to perform scan replacement.

The Test-Ready Compile Flow

Figure 5 shows the test-ready compile flow and the commands required to
complete this flow.
Figure 5 Test-Ready Compile Flow

Select scan style

(test_default_scan_style = style)

Read design description

(read)

Prepare for synthesis

Perform test-ready compile

(compile -scan)

Before performing test-ready compile:

• Select a scan style
For information about selecting a scan style, see Chapter 2, “Scan Style
Selection Considerations.”
• Prepare for logic synthesis
For information about preparing for logic synthesis, see the next section,
“Preparing for Logical and Physical Test-Ready Compile” on page 31.
The result of test-ready compile is an optimized design that contains unrouted
scan cells. The optimization performed during test-ready compile accounts for
both the impact of the scan cell and the additional loading due to the scan
chain routing. A design in this state is an unrouted scan design.

30
 Test-Ready Compile
Preparing for Logical and Physical Test-Ready Compile

Preparing for Logical and Physical Test-Ready Compile

Figure 6 shows the synthesis preparation steps. For more information about
these steps, see the Design Compiler User Guide.
Figure 6 Synthesis Preparation Steps

Specify technology
requirements
Select
Library objects compile strategy
link_library
target_library Top-down hierarchical compile
symbol_library time-budget compile
bottom-up hierarchical compile
Design rules
set_max_transition
set_max_fanout
Set
set_max_capacitance
design constraints

create_clock
Define set_clock_skew
design environment set_input_delay
set_output_delay
set_operating_conditions set_max_area
set_wire_load
set_drive
set_driving_cell Resolve multiple
set_load design instances
set_fanout_load

Performing Test-Ready Compile in the Logical Domain

The compile -scan command invokes test-ready compile. You must enter
this command from the dc_shell-t command line; the Design Analyzer menus
do not support the -scan option.
dc_shell-t> compile -scan

For details of how to constrain your design and for other compile options, see
the Design Compiler Reference Manual: Optimization and Timing Analysis.

31
Test-Ready Compile
Controlling Test-Ready Compile

Performing Test-Ready Compile in the Physical Domain

If you want to perform scan replacement and physical optimization in separate
steps, use the following command sequence:
psyn> compile -scan
psyn> physopt

If you want to perform scan replacement and physical optimization in one step,
use the following command:
psyn> compile_physical -scan

You must be in the Physical Compiler environment to perform physical scan

synthesis. For details on using Physical Compiler, see the Physical Compiler
User Guide.

Controlling Test-Ready Compile

You can use the following variable and commands to control scan
implementation by compile -scan:
• test_default_scan_style or
set_scan_configuration -style
• set_scan_element element_name true | false
• set_scan_register_type [-exact]
-type scan_flip_flop_list [cell_or_design_list]
• set_scan_configuration -multibit_segments
set_scan_segment -synthesizable
The test_default_scan_style variable determines which scan style the
compile -scan command uses for scan implementation. You can also use
the set_scan_configuration -style command for the same purpose.
You might not want to include a particular element on a scan chain. If this is the
case, first analyze and elaborate the design. Then, use the
set_scan_element false command on the GTECH sequential element.
Subsequently, when you use the compile -scan command, this element is
implemented as an ordinary sequential element and not as a scan cell.
Example 2 shows an example script.

32
 Test-Ready Compile
Comparing Default Compile and Test-Ready Compile

Example 2 Script that Uses set_scan_element false on

Generics

analyze -format VHDL -library WORK switch.vhd

elaborate -library WORK -entity switch -arch rtl
set_scan_element false Q_reg
compile -scan

Note:
Use the set_scan_element false statement sparingly. For
combinational ATPG, using nonscan elements generally results in lower
fault coverage.
You might want to specify which flip-flop scan cells are to be used for replacing
nonscan cells in the design. In that case, use the set_scan_register_type
command as described in the next section.

Comparing Default Compile and Test-Ready Compile

The following example shows the effect of test-ready compile on a small
design. The Verilog description shown in Example 3 and the VHDL description
shown in Example 4 each describe a small design containing two flip-flops: one
a simple D flip-flop and one a flip-flop with a multiplexed data input.
Example 3 Verilog Design Example

module example (d1,d2,d3,sel,clk,q1,q2);

input d1,d2,d3,sel,clk;
output q1,q2;
reg q1,q2;
always @ (posedge clk) begin
q1 = d1;
if (sel) begin
q2=d2;
end else begin
q2=d3;
end
end
endmodule

33
Test-Ready Compile
Comparing Default Compile and Test-Ready Compile

The following command sequence performs the default compile process on the
Verilog design example:

dc_shell-t> set target_library class.db

dc_shell-t> read -format verilog example.v
dc_shell-t> set_max_area 0
dc_shell-t> compile

Example 4 VHDL Design Example

--------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--------------------------------------------------
entity EXAMPLE is
port( d1:in STD_LOGIC;
d2:in STD_LOGIC;
d3:in STD_LOGIC;
sel:in STD_LOGIC;
clk:in STD_LOGIC;
q1:out STD_LOGIC;
q2:out STD_LOGIC
);
end EXAMPLE;
--------------------------------------------------
architecture RTL of EXAMPLE is
begin
process
begin
wait until (clk’event and clk = ‘1’);
q1 <= d1;
if (sel = ‘1’) then
q2 <= d2;
else
q2 <= d3;
end if;
end process;
end RTL;

34
 Test-Ready Compile
Comparing Default Compile and Test-Ready Compile

The following command sequence performs the default compile process on the
VHDL design example:

dc_shell-t> set target_library class.db

dc_shell-t> analyze -format vhdl \
-library work example.vhd
dc_shell-t> elaborate -library work EXAMPLE
dc_shell-t> set_max_area 0
dc_shell-t> compile

Figure 7 shows the result of the default compile process on the design
example. Design Compiler uses the D flip-flop (FD1) and the multiplexed flip-
flop scan cell (FD1S) from the class technology library to implement the
specified functional logic.
Figure 7 Gate-Level Design: Default Compile

FD1

FD1S

Using default compile increases the scan replacement runtime and can result
in sequential cells that do not have scan equivalents.
To invoke test-ready compile, specify the scan style before optimization and
use the -scan option of the compile command.
dc_shell-t> set test_default_scan_style = multiplexed_flip_flop
dc_shell-t> compile -scan

35
Test-Ready Compile
Complex Compile Strategies

Figure 8 shows the result of the test-ready compile process on the design
example. During test-ready compile, DFT Compiler:
• Implements the scan equivalent cells using the multiplexed flip-flop scan cell
(FD1S)
• Ties the scan enable pins (SE) to logic 0 to enable the functional logic
• Connects the Q output of the flip-flops to the scan input pins (SI) to reflect
the scan loading effect
During scan routing, DFT Compiler replaces the temporary scan connections
with the appropriate scan connections.
Figure 8 Gate-Level Design: Test-Ready Compile

A scan equivalent might not exist for the exact implementation defined, such as
for the simple D flip-flop in the previous example. If the target library contains a
scan cell that can be degenerated to the required implementation (for example,
the scan cell has asynchronous pins that can be tied off), test-ready compile
automatically uses that scan cell.

Complex Compile Strategies

For larger designs, or for designs with more aggressive timing goals, you might
need to use more complex compile strategies, such as bottom-up compile, or
you might need to use incremental compiles. To include test-ready compile in
your compile scripts, always use the -scan option of the compile command
when compiling each current design, even if there are no sequential elements
in the top level of the current design.

36
 Test-Ready Compile
Complex Compile Strategies

Example 5 illustrates this guideline. It shows how to perform a bottom-up

compile for a design TOP that has no sequential elements at the top level but
instantiates two sequential modules A and B (details of constraining the
designs are omitted for clarity). Note the use of the compile -scan command
at the top level even though there are no sequential elements at the top level of
the design.
Example 5 Bottom-Up Compile Script

dc_shell-t> current_design A
dc_shell-t> compile -scan

dc_shell-t> current_design B
dc_shell-t> compile -scan

dc_shell-t> current_design TOP

dc_shell-t> compile -scan

37
Test-Ready Compile
Complex Compile Strategies

38
 6
Validating Your Netlist6

Before you assemble the scan structures, use the link and
check_design commands to check the correctness of your
design. Fix any errors reported by these commands to
guarantee the highest possible fault coverage.

Running the link Command

The link command attempts to find models for the references in your design.
The command searches the design files and library files defined by the
link_library variable. If the link_library variable does not specify a
path for a design file or library file, the link command uses the directory
names defined in the search path. Specifying the asterisk character (*) in the
link_library variable forces the link command to search the designs in
memory. See the man pages for more information about the link command.
If the link command reports unresolved references (missing designs or library
cells) in your netlist, resolve these references to provide a complete netlist to
DFT Compiler. DFT Compiler operates on the complete netlist. DFT Compiler
does not know the functional behavior of a missing cell, so it cannot predict the
output of that cell. As a result, output from the missing reference is not
observable. Each missing reference results in a large number of untestable
faults in the vicinity of that cell and lower total fault coverage.

39
Validating Your Netlist
Running the check_design Command

If the unresolved reference involves a simple cell, you can often fix the problem
by adding the cell to the library or by replacing the reference with a valid library
cell.
Handling a compiled cell requires a more complex solution. If the compiled cell
does not contain internal gates (for example, a ROM or programmable logic
array), you can compile a behavioral model of the cell into gates, then run DFT
Compiler on the equivalent gates.
For more information about missing references or link errors, see the Design
Compiler User Guide.

Running the check_design Command

The check_design command reports electrical design errors that might lower
fault coverage, such as port mismatches and shorted outputs. For best fault
coverage results, correct any design errors identified in your design. For more
information about the check_design command, see the Design Compiler
User Guide.

40
 Index

A clock
asynchronous pins bidirectional ports 9
invalid
uncontrollable 11
fault coverage impact 8
correcting 11
gated 11
fault coverage impact 11
identifying 10
attributes
uncontrollable 10
dont_touch 7
locating 8 reconvergent 10
removing 8 requirements 8
scan_element 7 system 8
test 8
clocked scan 16
B clocking constraints
bidirectional port, using as clock 9 requirements for valid clocks 8
bottom-up compile 36 commands
check_design 40
compile 31
C create_multibit 25
check_design command 40 dft_drc 18
check_test command 18 filter 17
identifying link 39
scan cells 18 remove_multibit 25
messages, information 7 remove_scan_register_type 23
(see also messages, information) report_test
-register option 23
set_dont_touch 8
set_multibit_options 25
set_scan_configuration
-style option 32
set_scan_register_type 21
compile -scan command 31
specifying scan cells 21
constraint-optimized scan insertion, when to use 3

41
correcting LSSD
invalid clock gating 11 advantages 16
uncontrollable asynchronous pins 11 disadvantages 16
uncontrollable clocks 11
unresolved references 39
M
create_multibit command 25
messages
information
D TEST-121 8
definitions TEST-202 7
scan replacement 1 TEST-204 8
system clock 8 warning
TEST-116 11
test clock 8
TEST-120 5, 18
test-ready compile 29
TEST-169 10
unresolved reference 39
TEST-186 11
design state, unrouted scan 30
TEST-224 5, 18
dft_drc command
identifying TEST-462 6
scan equivalents 18 TEST-463 6
identifying invalid clock nets 10 TEST-464 6
dont_touch attribute 7 TEST-465 6
TEST-466 7
TEST-467 7
F TEST-468 6
fault coverage multibit
impact component scan replacement 26
invalid clock nets 8 components 24
uncontrollable asynchronous pin 11 controlling test synthesis 26
fault coverage, impact multiplexed flip-flop, advantages and
scan equivalents 14 disadvantages 15, 16
filter command 17
flows
scan replacement 2 N
netlist, validating 39
I
identifying O
scan cells 17, 18 optimization
scan equivalents 18 default compile
identifying invalid clock nets 10 Verilog example 34
VHDL example 35
incremental compiles 36
insert_scan command preparing for 31
specifying scan cells 21 test-ready compile 29, 35

L R
link command 39 reference, unresolved 39
link_library variable 39 remove_multibit command 25
listing scan equivalents 18 remove_scan_register_type command 23
removing attributes 8

42
report_test command T
-register option 23
test clock 8
requirements, clocks 8
test_allow_clock_reconvergence variable 10
test_default_scan_style variable 15
S TEST-116 message 11
scan cell 18 TEST-120 message 5, 18
determining scan functionality 14 TEST-121 message 8
library description 14 TEST-169 message 10
specifying 21 TEST-186 message 11
scan equivalents
TEST-202 message 7
fault coverage impact 14
TEST-204 message 8
identifying 18
listing 18 TEST-224 message 5, 18
scan implementation, controlling 32 TEST-462 message 6
-scan option, compile command 31 TEST-463 message 6
scan replacement TEST-464 message 6
definition 1 TEST-465 message 6
flow 2 TEST-466 message 7
preventing 7 TEST-467 message 7
process 4 TEST-468 message 6
selecting a strategy 3 test-ready compile 29
using test-ready compile 29 benefits 3
scan style bottom-up compile 36
selecting 14 complex compiles 36
specifying 15 controlling 32
supported options 13 controlling scan implementation 32
scan_element attribute 7 degeneration support 36
selecting example 35
scan replacement strategy 3 incremental compiles 36
scan style 14 invoking 31
set_dont_touch command 8 when to use 3
set_multibit_options command 25
set_scan_configuration command
-style option 15, 32 U
set_scan_register_type command 21 uncontrollable asynchronous pin 11
specifying correcting 11
scan style 15 fault coverage impact 11
structured logic uncontrollable clock 10
defining 25 unresolved reference 39
disabling 27 unrouted scan design, after test-ready compile 30
-style option, set_scan_configuration command 15
synthesis 31
synthesizable segment
V
defining 25 validating
system clock 8 netlist 39

43
variables
link_library 39
test_allow_clock_reconvergence 10

test_default_scan_style 15

44