ARM Cortex®- M0 Processor Core

An Overview

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ARM Processors Portfolio
Processor
Class

ARM7
ARM9
ARM11

M
R
A
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Equipment Adopting ARM Cores

M Intelligent toys
Utility Meters
IR Fire Detector
Exercise
Machines Energy Efficient Appliances
Intelligent Vending

Tele-parking

A
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ARM Cortex-M Series Family
ARM Core Hardware Hardware Saturated DSP Floating
Processor Thumb® Thumb®-2
Architecture Architecture Multiply Divide Math Extensions Point

Cortex-M0 ARMv6-M Von Neumann Most Subset Optional No No No No

Cortex-M0+ ARMv6-M Von Neumann Most Subset Optional No No No No

Cortex-M1 ARMv6-M Von Neumann Most Subset Optional No No No No

Cortex-M3 ARMv7-M Harvard Entire Entire Optional Yes Yes No No

Cortex-M4 ARMv7E-M Harvard Entire Entire Optional Yes Yes Yes Optional

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 ARM Cortex-M0 Processor

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Cortex-M0 Overview
 ARMv6-M Architecture
 Von-Neumann Architecture
 32-bit Architecture
 Thumb technology

 Nested Vector Interrupt Controller (NVIC)

 AHB-Lite Master Interface

 Optional Ultra-low power Support

 Optional CoreSight-compliant Debug

 RTL is configurable

 Synthesizable
 Gate count 12 ~ 25K

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Cortex-M0 Processor Programmers Model
 The Cortex-M0 is designed to be programmed fully in C
 No need to write assembly code
 Thumb technology
 16-bit and 32-bit instructions

 Set of processor core and memory-mapped registers are provided

 Architecturally defined memory map
 Forwards compatible with other M-profile processors
 Binary compatible

 In-order execution of instructions

 Multi-cycle instructions are abandoned and restarted on interrupt
 Multiple memory accesses (LDM/STM) are interrupted between transfers
 Deterministic instruction execution

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 Cortex-M0 Block Diagram
ARM Cortex-M0 Microprocessor
Interrupt
Requests and
NMI JTAG/Serial-Wire
Nested Vector Debug Interface
Interrupt Processor Debug
Controller Core Subsystem
(NVIC)

Wakeup
Interrupt
Controller (WIC) Internal Bus System

Power management
interface AHB LITE
Bus interface

Memory and peripherals

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Cortex-M0 Registers
Register bank R0
R1
R2
R3
Low
R4 Registers

R5
General purpose
register
R6
R7
R8
R9
R10 High
Registers
R11
R12 MSP
Stack Pointer (SP) R13(banked) Main Stack Pointer

Link Register (LR) R14 PSP

Program Counter (PC) R15 Process Stack Pointer

Special registers Program Status

x PSR APSR EPSR IPSR
Registers (PSR)
Interrupt mask register PRIMASK Application Execution Interrupt
PSR PSR PSR
Stack definition CONTROL

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Reduced Instruction Set
 Only 56 Instructions
 Mostly coded on 16-bit
 Operate on the 32-bit registers
 Option for fast MUL 32x32 bit in 1
cycle
 Instruction types
 Branch instructions
 Data-processing instructions
 Load and store instructions
 Status register access instructions
 Miscellaneous instructions

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 Cortex-M: binary upwards compatibility
Floating Point

DSP (SIMD, fast MAC)

ARMv7-M
Architecture

Advanced data processing

Bit field manipulations
ARMv6-M
Architecture

General data processing

I/O control tasks

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 ARM Cortex-M0 Processor

Memory Architecture

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Cortex-M0 Memory Map (Example)
Chip Silicon

PPB NVIC
Cortex-M0 SCS
Debug Ctrl

AHB bus

On-chip FLASH On-chip SRAM Timer UART GPIO

External memory interface External device interface

External SRAM,
External LCD SD card
FLASH

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Cortex-M0 Memory Map (Example)
Chip Silicon

NVIC
Cortex-M0 PPB SCS
Debug Ctrl

AHB bus

On-chip FLASH On-chip SRAM Timer UART GPIO

(Code Region) (SRAM Region) Peripheral Region

External memory interface External device interface

(External RAM Region) (External Device Region)

External SRAM,
External LCD SD card
FLASH

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Cortex-M0 Memory Map
Reserved for other purposes 0xFFFFFFFF Debug Control
ROM table
Reserved
0xE0100000 System Control Block
512MB Reserved (SCB)
Private peripherals 0xE00FFFFF
e.g. NVIC, SCS Private Peripheral Bus Nested Vectored
0xE0000000
System Control Space Interrupt Controller
0xDFFFFFFF
(SCS) (NVIC)
Mainly used for external peripherals
e.g. SD card External Device 1GB
Reserved
Reserved
SysTick Timer
0xA0000000 Break point unit
0x9FFFFFFF Reserved
Data watch point unit
Mainly used for external memories
e.g. external DDR, FLASH, LCD
External RAM 1GB Reserved

0x60000000
Mainly used for on-chip peripherals 0x5FFFFFFF
e.g. AHB, APB peripherals Peripherals 512MB
0x40000000
0x3FFFFFFF
Mainly used for data memory
e.g. on-chip SRAM, SDRAM SRAM 512MB
0x20000000
0x1FFFFFFF
Mainly used for program code Code 512MB
e.g. on-chip FLASH
0x00000000

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Cortex-M0 Program Image
Code region

Interrupt vectors
0x00000040

0x0000003C
SysTick vector
0x00000038
PendSV vector

Start-up routine & Reserved

Program code &
C library code 0x0000002C
Program SVC vector
Image

Reserved

0x0000000C
Hard fault vector
0x00000008
NMI vector

Reset vector 0x00000004

Vector table
0x00000000 Initial MSP value 0x00000000

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 Cortex – M0 Reset Behaviour
 After reset: Reset

1. First reads the initial MSP value;

Fetch initial value for MSP
2. Then reads the reset vector; (Read address 0x00000000)

3. Branches to the starting of the programme execution

Fetch reset vector
address (reset handler); (Read address 0x00000004)
4. Subsequently executes program instructions.
Fetch 1st instruction
(Read address of reset vector)

Fetch 2nd instruction

(Read subsequent instructions)

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Cortex M0 Design Start

 Fixed configuration of the Cortex-M0 processor

 Low cost access to Cortex-M0 processor technology by offering a subset of the full
product.
 Pre-configured and obfuscated, but synthesizable,Verilog version of the full Cortex-M0
processor
 Fully working version of the Cortex-M0 processor
 Used as the basis for production hardware and software designs.
 Gate count is ~16K
 Cortex M0 Processor gate count is 12k to 26K depending on the configuration

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Cortex M0 Design Start vs Full Cortex M0

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Lab

 Consider you have a simple Cortex M0 based Micro-controller with the following
memory map
 Internal SRAM – 1 KB – Starting Address 0x0000 0000
 A LED Peripheral – One word – Address 0x5000 0000

 We will write assembly program to toggle the LEDs and simulate the program

 We will analyse the resulting binary file and the disassembly file

 In the Next Section we will see how to design AHB-Lite Compliant LED Peripheral

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