ARM Processors

• ARM processors are based on RISC architecture philosophy (fixed size and
uniform instructions)
• Consume less area and power as compared to CISC
• Dominates embedded system market

Earlier Architectures of ARM:

ARM Core Features ISA Thumb
family (32 bit) version version
ARM7TDMI 3-state pipeline, MAC ARMv4T v1
ARM7 ARM 720T Same as ARM7TDMI + cache
ARM 920T 5-stage pipeline, thumb, data and ARMv4T
inst. cache, MMU
ARM946E 5-stage pipeline, thumb, Enhanced ARMv5TE
ARM9 DSP instructions, caches, MPU
ARM926EJ 5-stage pipeline, thumb, Jazelle DBX, ARMv5TEJ
Enhanced DSP instructions, caches,
MMU
ARM11 ARM1156T2(F) 8-stage pipeline, SIMD, Thumb-2, ARMv6T2 v2
VFP, Enhanced DSP instructions

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 ARM Cortex Processors

• Cortex A Series:
• High end processors for general Application e.g. mobile phones, PDAs
• High clock frequency, MMU, Support for full feature OS e.g. android,
linux, iOS
• Cortex R Series:
• Designed for real time application such as automotive, missile
guidance, flight control, high speed routers
• More cache and tightly coupled memory
• Very responsive to hardware events, low latency and support of RTOS
• Cortex M Series:
• Energy efficient, moderate clock rate, shorter pipeline
• Application => Embedded market (Home appliances, Office
automation, Communication devices, Portable systems etc.)

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ARM Cortex processors

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 ARM Microcontroller

• ARM is not manufacturer of chip instead it only designs embedded processors and other
digital systems
• Both Soft IP and Hard IP are licensed by ARM to semiconductor vendors

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Instruction set of Cortex M family

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 Performance
DMIPS:
• Dhryston in benchmark program that includes integer arithmetic, string manipulation, logic
and memory access operations
• The Dhrystone figure of given computing system is calculated by measuring the number of
Dhrystones executed per second and dividing that by 1757. So if a computing system able
to execute 140560 dhrystones per second, then its DMIPS rating is 140560/1757 = 80
DMIPS.
• Above figure can be normalized by Clock freq. E.g. if clock freq. is 50MHz then
performance of computing system 1.6 DMIPS/MHz
Coremark MIPS:
• Core mark is new Bench mark program for embedded processors that also commonly used
algorithms such as Matrix multiplication, Linked list, FSM and CRC (cyclic redundancy
check)
• CPU Performance: Coremark /MHz
Power & Performance:
µW /MHz (at given IC Tech. & Supply Voltage)
DMIPS/ µW or Coremarks/µW (at given IC Tech. & Supply Voltage)

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 Features of Cortex M0/M0+

• OS Support
− Two exceptions (SVCall and PendSV) for accessing OS service
− 24-bit hardware timer SysTick for OS time keeping
− M0+ supports privileged and unprivileged execution modes
• Debug
− Debug interface based on either JTAG protocol (4 wire) or Serial Wire Debug
protocol (2 wire)
− Supports four Hardware break points and two Data watch points
− Unlimited software break points with BKPT instruction
• Linear memory addressing with 4GB space
• Small gate count, Energy efficient
• High performance (high DMIPS/MHz)
• Software portability between Cortex-M processors

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 Features of Cortex M0/M0+

• MPU: (available in M0+)

− Preventing application software from corrupting stack or data memory used
by other programs and the OS kernel
− Preventing unprivileged functions from accessing certain peripherals that can
be critical to the reliability
− Defining RAM space as nonexecutable to prevent code injection attacks
− MPU Use is essential in following systems:
System with cache memory, Networked embedded systems, Secure
industrial control and automotive systems

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 Cortex M0 Architecture

• AHB - Advanced High-

performance Bus
• MPU – Memory protection
unit
• MTB - Micro Trace Buffer
• NMI – Non maskable interrupt
• JTAG - Joint Test Action
Group

• Units with dotted lines are optional that can be omitted by MCU chip vendor
• Cortex M0+ = Cortex M0 + MPU + single cycle I/O + interface to MTB

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 Features of Cortex M0/M0+
• 32-bit RISC Pipeline CPU (3 stages in Cortex M0 and 2 stages in Cortex M0+)
• Majority instructions are 16-bit wide while few are 32-bit wide
• Based on ARMv6-M ISA which is Thumb-2 technology
• Low power using sleep modes (using WFI and WFE instructions)
• Supports Wakeup Interrupt Controller (WIC). Processor can be put in power down mode and
can be woken up by interrupt event through WIC
• Built in Nested Vector Interrupt Controller (NVIC) can handle 32 interrupt requests (IRQs), a
non-maskable interrupt (NMI) and exceptions
• On chip 32-bit AMBA AHB-Lite bus interface for interfacing ROM, RAM, DMA controller
• Peripherals may use less complex APB protocol and connected to AHB-Lite bus via bridge
• Fault handling

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 Architecture

• R0-R12 are general purpose registers. Many Thumb instruction only access R0-R7
• LR stores return address when subroutine is called
• xPSR content is combination of various fields of APSR, EPSR, IPSR

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 Cortex M0/M0+ Architecture

• When Cortex M0/M0+ is running program, it is in Thumb state.

• In thumb state, processor can be either in Handler mode or Thread mode
• By default, Thread mode runs in Privileged level.
• Program running in Privileged level can itself switch to Unprivileged level by programming
CONTROL register but cannot switch back itself to Privileged level.

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 Architecture
• Stack pointers=> MSP (default) and PSP.
• Link register (LR):
• When BL or BLX is executed (for subroutine call), LR stores return address
• At the end of subroutine, LR is copied to PC to return to main program
• Program Counter (PC):
• It is readable and writeable
• Read value = Address of current instruction +4
• PRIMASK register disables all programmable interrupts and exceptions if LSB of register is 1.
• CONTROL register:
• Bit 1 (LSB) can be SET (during thread mode) to switch stack pointer to PSP
• Bit 0 can be SET to switch to unprivileged level during thread mode

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Unprivileged
The software:
• has limited access to the MSR and MRS instructions
• cannot access the system timer, NVIC, or system control block
• might have restricted access to memory or peripherals.

Privileged
The software can use all the instructions and has access to all14resour
 Architecture

• C flag in APSR is Reset if result of Subtraction or Compare operation is negative

• V (overflow flag) is normally used for detecting Signed overflow
• N flag indicates MSB of result
• Z flag is set when result of operation is zero
• When exception is accepted, exception no. is written in “ISR Number” field

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 Assembler Pseudo Instructions
• LDR R0, =0x55AA1234 ; pseudo instruction to load any 32-bit value
• LDR Rd, =label ; pseudo instruction to load address of label
into Rd (address of the label must be word aligned)
• ADR Rd, Label ; pseudo instruction to load address of ‘Label’ into Rd.
Label should be near to current instruct ion

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 Endianness & Sign extend

• Endianness : defines order of bytes in memory and registers

• Sign Extend : required when manipulating signed values of variable lengths

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 Cortex M0 Instructions
• Most instructions of Cortex M0/M0+ are 16-bit but few are 32-bit in size
• Instructions that update flags use Suffix S after assembly mnemonic. CMP, CMN & TST
instructions don’t requires suffix S although they update flags
[1] Data Transfer:
• MOV Rd, Rm ; copy content of Rm to Rd
• MOVS Rd, Rm ; copy content of Rm to Rd and update flags
• MOVS Rd, #imm8 ; load 8-bit constant in Rd
• MVNS Rd, Rm ; copy 1s complement of Rm to Rd (Rd  Rm’ )
• MRS Rd, Special_reg. ; copy data from special register to Rd (Rd  Special Reg.)
• MSR Special_reg, Rd

[2] Memory Access:

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imm must be between:
• 0 and 1020 and an integer multiple of four for LDR and STR using SP
as the base register
• 0 and 124 and an integer multiple of four for LDR and STR using R0-R7
as the base register
• 0 and 62 and an integer multiple of two for LDRH and STRH
• 0 and 31 for LDRB and STRB.

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 Cortex M0 Instructions
• LDR Rt, [Rn, Rm]
; transfer 32-bit word from memory to register Rt i.e. Rt  M [Rn+Rm]
• LDR Rt, [Rn, #imm5] || Rt, [PC, #imm8] || Rt, [SP, #imm8]
;32-bit word transfer Rt  M [ Rn, (#imm5 <<2) ]
• LDRSH Rt, [Rn, Rm]
; transfer half word from memory to Rt and sign extend it
• LDRH Rt, [Rn, Rm] || Rt, [Rn, #imm5]
; transfer Half word (16-bit) i.e. Rt  M [Rn+ (imm5 <<1)]
• LDRSB Rt, [Rn, Rm] ; transfer byte from memory to Rt and sign extend it
• LDRB Rt, [Rn, Rm] || Rt, [Rn, #imm5] ; transfer Byte (8-bit)
• STR Rt, [Rn, Rm]
; transfer 32-bit word from Rt to memory (memory write) i.e. M [Rn+Rm]  Rt
• STR Rt, [Rn, #imm5] || Rt, [SP, #imm8]
; word transfer with constant offset i.e. M [ Rn, (#imm5 <<2) ]  Rt
• STRH/STRB Rt, [Rn, Rm] || Rt, [Rn, #imm5]
; half word and byte transfer Rt, Rn must be from R0 to R7
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 Cortex M0 Instructions
• LDM Rn, {R0, R1, . . .} ; read multiple words from memory and load into multiple
registers. Rn is pointer to memory
• LDM Rn!, {R0, R1, . . .} ; same as LDM but Rn is updated after data transfer
• STM Rn!, {R0, R1, . . .} ; copy multiple register values into memory and update Rn
• PUSH {R4, R5, R7, LR} ; push registers into stack pointed by SP
• POP {R0, R1, . . . , LR} ; retrieve registers from stack pointed by SP

Reglist and Rn are limited to R0-R7

LDMIA and STMIA are synonyms

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 Cortex M0 Instructions

[3] Arithmetic:
• ADDS Rd, Rn, Rm || Rd, Rn, #immed3 || Rd, #immed8 || Rd, Rm
• ADD Rd, SP, Rd || SP, Rm || Rd, SP, immed8 || SP, SP, #immed7
• ADCS Rd, Rm ; add with carry and update APSR
• SUBS Rd, Rn, Rm || Rd, Rn, #imm3 || Rd, #imm8

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 Cortex M0 Instructions

• SUB SP, #imm7 ; subtract 7-bit constant from stack pointer

• SBCS Rd, Rm ; Rd = Rd - Rm- Borrow (subtract with borrow)
• RSBS Rd, Rm, #0 ; Rd= 0 - Rm (2’s complement of Rm is copied to Rd)
• MULS Rd, Rm, Rd ; Rd= Rd*Rm (saves lower 32-bits of product in Rd)
• CMP Rn, Rm || Rn, #imm8 ; compare by performing Rn – Rm
• CMN Rn, Rm ; compare by performing Rn – (2’s complement of Rm)

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 Cortex M0 Instructions
(4) LOGICAL :
• ANDS Rd, Rm ; Rd = Rd AND Rm
• ORRS Rd, Rm ; Rd = Rd OR Rm
• EORS Rd, Rm ; Rd = Rd XOR Rm
• BICS Rd, Rm ; Rd = Rd AND (not Rm)
• TST Rn, Rm ; update flags after Rn AND Rm operation
(5) Shift and Rotate:
• ASRS Rd, Rm || Rd, #imm5 ; arithmetic shift right
• LSLS Rd, Rm || Rd, #imm5 ; logical shift left
• LSRS Rd, Rm || Rd, #imm5 ; logical shift right
• RORS Rd, Rm ; rotate right

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 Cortex M0 Instructions

• Each shift operation affects carry flag

• For shifting singed data (2’s complement form) LSLS and ASRS are used

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 Cortex M0 Instructions

(6) Extend and Reverse Ordering

• SXTB Rd, Rm ; sign extend byte
• SXTH Rd, Rm
• UXTB Rd, Rm ; 0 extend byte
• UXTH Rd, Rm
• REV Rd, Rm
• REV16 Rd, Rm
• REVSH Rd, Rm
(7) Branching:
• B Label ; range ± 2KB
• B <cc> label ; range -256 to +254 bytes
• BL label ; range ± 16MB
• BX Rm ; any add. Given in Rm
• BLX Rm ; any add. Given in Rm

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Function Call
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Nested Function Call
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Condition Codes for Branch Instructions

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 Instruction Set

• Control Transfer/Others:
• SVC #imm8 ; supervisor call exception is generated
• CPSIE I ; Enable all programmable interrupts & exceptions
• CPSID I ; Disable all programmable interrupts & exceptions
• WFI ; enters sleep mode unconditionally
• WFE ; if internal event register is set, it clears event register. Otherwise, enters into
sleep mode
• SEV ; set event register and send out event pulse to other processors
• BKPT #immed8 ; Software breakpoint instruction. Processor is halted on this instruction.
The debugger uses 8-bit identifier for break point operation
• NOP

Note:
• BL, MRS, MSR, DSB, DMB, ISB are 32-bit Thumb instructions

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ARM Assembler Directives

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 ARM Assembler Directives

Moving constants and ASCII Char. to registers:

• MOVS R1, #12 (decimal)
• MOVS R1, #0xC (hex constant)
• MOVS R1, #037 (octal constant)
• MOVS R1, #’A’

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 Example Programs (Tool- Keil ARM-MDK)
AREA code1, CODE, READONLY
• LDR R3, = NUM1 ; Get the add. of NUM1
• LDR R4, [R3] ; Read the value & save into R4
• LDR R0, =TEXT1 ; Get the starting address of TEXT1
• BL PrintText ; Call a function “PrintText”‘ to display string.
Here
• B Here ; suspend the program

AREA data1, DATA, READWRITE ; declare Code Section

NUM1 DCD 0x12345678 ; 32-bit data
NUM2 DCW 0xAA55, 0xA050, 0xAAFF, 0xFF00 ; array of 16-bit data
TEXT1 DCB "Hello world \n", 0 ; Null terminated string
END ; end of assembly file

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 Cortex M0 based system

• A typical MCU with Cortex M0 core, other components and buses

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 Exceptions and Interrupts
• Exceptions are events generated internally by CPU e.g. hard fault
• Interrupts (IRQs) are generated by on chip peripherals and I/O pins
• Exception Handler: Software routine that executes when an exception occurs

• ISR : Software routine that executes when an interrupt occurs

• The starting address of ISR / Exception Handler (also called Vector address) is equal to
exception no. multiplied by 4.

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 Cortex M0+: Exceptions and Interrupts
List of exceptions & interrupts:
• CPU identifies each interrupt and exception event by unique exception number

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 Exceptions and Interrupts
• Stacking and Unstacking
• Current state of processor is saved in stack before switching to exception handler
(or ISR)
• When an exception/ Interrupt is accepted, following actions are taken
automatically
─ Registers R0 to R3, R12, LR, PC and xPSR are saved (stacking) in stack
memory
─ Then, link register LR is written with a special value EXC_RETURN
─ Vector address is loaded in PC and handler/ISR start to execute
• When exception handler /ISR ends with BX LR instruction
─ The LR value (EXC_RETURN) is loaded in PC. CPU decodes EXC_RETURN
─ Then, processor checks if there any pending exception/ interrupt
─ If not, register values are restored (unstacking), and interrupted program
resumes
• Other registers not saved automatically, can be saved and restored using PUSH
and POP instructions

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Exceptions and Interrupts

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 Exceptions and Interrupts

• Stacking operation begins after decrement of SP by 4

• Lower index registers are stored at lower address in stack

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 Exceptions and Interrupts
Exception / Interrupt priority:
• Cortex M0/M0+ supports 3 High priority exceptions (Reset, NMI and Hard fault). Each has
fixed priority. Priority level of other exceptions / IRQs are programmable.
• If two exceptions /IRQs with same priority level occurs at the same time, lower indexed
(numbered) exception will be processed.
• Newly occurred exception /IRQ enters in pending state if its priority is same or lower than
currently running exception
• PRIMASK register can disable all IRQs and configurable exceptions if its Bit[0]=1.
• NVIC is programmable unit of Cortex M0+ that manages Interrupts and Exceptions
• NVIC accepts interrupts (IRQ) signals as
− High Level interrupt
− Pulsed (min. 1 clock period) interrupt

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 Exceptions and Interrupts
• 32 Interrupts are IRQ#0, IRQ#1, . . ., IRQ#31
• There are four priority levels. The priority level of an interrupt can be assigned using Interrupt
Priority level register (NVIC -> IP). The priority level of exception can be set using System
Handler Priority register (SCB -> SHP)
• Priority Levels: Level 0(highest priority), Level 1, Level 2 and Level 3 (lowest priority)
• When processor detects interrupt, it sets pending state of that interrupt. When CPU starts
executing ISR, pending state is cleared.
• Cortex M0/M0+ accept exception/interrupt under following conditions:
o The corresponding exception/interrupt is enabled
o Processor is not halted for debugging
o The exception /interrupt is not blocked by PRIMASK register

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 Interrupt and Pending state behavior

• When interrupt occurs, pending status is set automatically by processor

• Pending status of interrupt cleared automatically when ISR starts
• High level of IRQ line should be cleared by ISR

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 Interrupt and Pending state behavior

• If IRQx line is remains high after completion of ISR, it will be accepted as new interrupt
and ISR will run again (skipping unstacking)

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 Interrupt - Tail chaining

• Assume that priority of Interrupt B is lower or equal to A

• After servicing A, unstacking is Skipped and interrupt B is served (tail chaining)

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 Interrupt - Late arrival

• When Interrupt B occurs, Stacking operation initiated by A is not suspended.

• After stacking, CPU services interrupt B

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Registers access using CMSIS

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Embedded C

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 Interrupts
NVIC Registers for controlling IRQs:
• NVIC registers can be used to
‒ Enable/Disable individual interrupt
‒ Controlling priority level of interrupts
‒ Access and modify the pending status of each interrupt
• NVIC registers can only be accessed in Privileged state of Thread mode
(1) Enable/Disable Interrupt:
• Status of interrupts (IRQs) can be viewed by either reading ISER or ICER
registers
(if a bit [n] is 1 => IRQn enabled, if a bit [n] is 0 => IRQn disabled)
• Interrupts can be enabled/ disabled by writing 1 in ISER /ICER register

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Interrupts

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 Interrupts
(2) Interrupt Pending Set and Clear:
• If an interrupt is raised but cannot be processed, it is pended (Pending status is set).
• Pending status get cleared automatically (if processor start servicing the pending
interrupt)
• Pending status of IRQs can be manually set /clear by ISPR /ICPR register
• Pending status can be viewed by reading either ISER or ICER
(if a bit [n] is 1 => IRQn pended, if a bit [n] is 0 => IRQn not pended)

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 Interrupts
(3) Configure Interrupt Priority level:
• Each word in Priority Level registers handles 4 interrupt sources
• There are 4 priority levels i.e. 0,1,2 & 3 set by two MSBs of each byte as shown
• Valid byte values are 0x00, 0x40, 0x80 and 0xC0

Note: for Cortex-M processors, content of Memory mapped registers can be accessed with
Data pointer in C
e.g. * ((volatile unsigned long*) (ADDRESS) ) ; where ADDRESS is 32bit register add.

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 Interrupts
Example-
Assembly Program to set priority Level 2 and Level 3 for IRQ#0 and IRQ#2 respectively.
• LDR R0, =0xE000E400 ; Load address of interrupt priority register in R0
• LDR R1, [R0] ; Get Interrupt Priority register (32bit)
• LDR R2, =0xFF00FF00 ; Mask for clearing IRQ#0 and IRQ#2 fields
• ANDS R1, R1, R2 ; R1 = R1 AND ( (0xFF00FF00))
• LDR R2, =0x00C00080 ; New value for setting priority of IRQ#0 and IRQ#2
• ORRS R1, R1, R2 ;
• STR R1,[R0] ; write back new values

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 OR (equivalent C code)
• uint32_t temp = 0xFF00FF00; // prepare mask and save in 32bit variable
• NVIC -> IP[0] = NVIC -> IP[0] & temp; // clear fields of IRQ#0 and IRQ#2
• NVIC -> IP[0] = NVIC -> IP[0] | 0x00C00080 ; // set priority Levels

Configure Priority of Exceptions:

• SVC, PendSV, and SysTick exceptions are programmed using two System Handler Priority
Registers (SHP) as shown
• The SHP[0] and SHP[1] are part of SCB (System Control Block)

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