Received March 14, 2019, accepted March 31, 2019, date of current version April 29, 2019.

Digital Object Identifier 10.1109/ACCESS.2019.2909831

Real-Time Implementation of a 31-Level

Asymmetrical Cascaded Multilevel Inverter
for Dynamic Loads
C. DHANAMJAYULU 1 , G. ARUNKUMAR1 , B. JAGANATHA PANDIAN1 , C. V. RAVI KUMAR2 ,
M. PRAVEEN KUMAR1 , A. RINI ANN JERIN 1 , AND P. VENUGOPAL2
1 School of Electrical Engineering, Vellore Institute of Technology, Vellore 632014, India
2 School of Electronics Engineering, Vellore Institute of Technology, Vellore 632014, India
Corresponding author: C. Dhanamjayulu (dhanush403@gmail.com)

ABSTRACT Among the renewable energy applications, the most popular inverters are cascaded multilevel
inverters. Irrespective of numerous benefits these inverters face reliability issues due to the presence of more
circuit components in the design. This has been a critical challenge for researchers in designing inverters
with enhanced reliability by reducing the total harmonic distortion (THD). This paper proposes a 31-level
asymmetric cascaded multilevel inverter for renewable energy applications. The proposed topology produces
waveforms consisting of the staircase with a high number of output levels with lesser components with
low THD. The investigations on the feasibility and performance of MLI under steady-state, transient, and
dynamic load disturbances. The results are validated from a 1.6kW system which provides the proposed
inverter.

INDEX TERMS Multilevel inverter (MLI), total harmonic distraction (THD), staircase modulation
technique.

I. INTRODUCTION topologies, balancing the voltages and sharing them is a com-

In high power applications, like variable frequency drives, plex task for higher voltage levels [2]. A survey of topologies,
electric vehicles, HVDC, FACT, active power filters and controls and applications of multilevel inverters was done
hybridization of renewable energy sources, multilevel in 2002 [3]. The investigation of cascaded MLIs with asym-
inverter played an important role. It is mainly effective for metric, symmetric, multi-cell and hybrid configurations were
medium voltage motor drive system based applications, due presented in [4]. In which, a new symmetric dc-source hybrid
to their less switch voltage stress. Multilevel converters, MLI topology with minimal number of switch counts was
with different topologies, have been used in various indus- proposed [5]. It is possible to extend this topology to higher
trial processes. These topologies are Cascaded H-Bridge number of levels. Multi - carrier pulse width modulation
(CHB), Flying Capacitor Converter(FCC) and Neutral Point techniques [5] are adopted for triggering the gate pulses. The
Clamped(NPC) topologies [1]. The simple structures of operation of the proposed topology is explained with the
CHBs makes it popular in varieties of applications. Also 15-level output voltage. Following it, a novel Proportional-
CHBs can be configures to operate in symmetrical and asym- Integral(P+I) control strategy for resistive and motor loads
metrical configurations [2]. In symmetrically configured using genetic algorithm(GA) was proposed [6], here the
CHBs, values of all the DC-voltages are equal and in case of controller constants generated maintains the stable output
asymmetrically configured CHBs, the values of DC-voltage voltage at steady state under load disturbances and transient
sources are unequal in order to achieve required higher conditions [6].
voltage levels. CHB methods are employed for medium Cascaded multilevel inverter with improved characteristics
and higher voltage levels, whereas under DCC and FCC was presented by [7]. In the enhanced CMLI topology,
the number of switching devices are marginally increased.
The associate editor coordinating the review of this manuscript and
However, the level of the MLI obtained is doubled for the
approving it for publication was Reinaldo Tonkoski. same number of switching devices [7], [8]. A novel family
2169-3536 2019 IEEE. Translations and content mining are permitted for academic research only.
51254 Personal use is also permitted, but republication/redistribution requires IEEE permission. VOLUME 7, 2019
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

of H Bridge MLI with transistor clamp to increase the num- TABLE 1. Switching states of proposed seven-level inverter.
ber of output levels was presented by [10]. The proposed
topology was able to achieve operation at a higher volt-
age (HV) and higher power level without increasing the
device rating [9]. This topology is controlled by carrier-based
Pulse Width Modulation (CBPWM) which reduce switching
losses at higher switching frequencies and thereby improv-
ing the energy efficiency of the system [11]–[15]. A Total
Harmonic Distortion and efficiency improvement in multi-
level inverters through an open end wind configuration were peak voltage of 405 V at the load terminals. The load used
analyzed in 2016 [16]. for testing is 100 ohm resistor and 175 mH respectively.
High-frequency switching causes high power loss in high Figure.10 and Figure.11 depicts the simulation and experi-
power applications [16]–[19]. Most of the proposed topolo- mental output voltage and current of seven-level inverter.
gies use more switches in the configuration which makes The design of circuit parameters is discussed in the next
the circuit bulky and the generation process of gate pulses sub-section.
also is complex. This also results in higher THD and hence
poor efficiency. The topology proposed in this article over- A. DESIGN OF CIRCUIT PARAMETERS
comes this problem significantly [20], [21]. The thirty-one These sub-section discuss the method of choosing the number
level single phase asymmetric cascaded multilevel inverter of sources, switches, and output voltage levels.
is suggested in the present study. Several advantages have The quantity of output levels can be estimated as follows:
resulted from the reduced number of circuit components in
the suggested topology. These advantages include few DC Nlevels = 2k+1 − 1 (1)
sources with low THD, fewer number of switches, and the where k is the number of DC voltage sources on each leg
generation of higher number of output voltage levels. Addi- Number of switches can be obtained using
tionally, the dynamic condition is also examined [22], [23].
The suggested multilevel inverters are suitable for renewable Nswitches = 2k + 2 (2)
energy and industrial [18] applications.
Number of sources can be estimated using
This article organized in the following manner. The suc-
ceeding section disuses the details of the proposed seven-level Nsources = k (3)
topology. Section III presents the particulars of thirty-one
level inverter along with simulation results, section IV Maximum blocking voltage of all switches can be represented
presents the comparison, section V presents the loss & as
efficiency calculations, VI presents the experimental results Vblock = VA1 + VB1 (4)
respectively.
Maximum output voltage of inverter can be represented as
II. PROPOSED TOPOLOGY
The configuration of the suggested seven-level single-phase Vo,max = VAk + VBk (5)
inverter is depicted in Figure.1 [24]. Two switching elements The value of the switch blocking voltages and the magnitude
are connected to two DC power supplies and are added in of the DC voltage sources constitute the other significant
the conventional full-bridge inverter. The two DC voltages parameters in the evaluation of a multilevel inverter’s total
are represented as VA1 , VB1 and the power switches are cost. The total cost of inverter decreases with the reduction
represented as SA1 , SA2 ,SB1 , SB2 , SP ,SQ . The simultaneous in value of the switch blocking voltages, reduction in DC
turning (ON/OFF) of the power switches (SA1 , SA2 ) and (SB1 , voltage variations, and reduction in number of DC voltage
SB2 ) causes a short circuit and must be prevented. Further- sources.
more, the simultaneous switching ON of SP and SQ must
be avoided. VA1 = 1P.U and VB1 = 2P.U are the DC Kvariation = 2k (6)
voltage sources, whose magnitude is illustrated in Figure.1.
The maximum magnitude of the power switch blocking volt-
As depicted in Figure.1, seven switching states constitute
ages is computed by using the following pattern. The block-
the proposed inverter functioning. The levels of output volt-
ing voltages of VSA1 , VSA2 , VSB1 , and VSB2 are estimated as
age are as per the switch-ON and switch-OFF conditions
follows (Fig.1).
(Table 1) and Figure.2 to Figure.8 depict the conventional
inverter states of functioning. The generation of gate signals, VSA1 = VSA2 = VA1 (7)
by using a staircase modulation technique, constitutes the VSB1 = VSB2 = VB1 (8)
proposed switching strategies as shown in Figure.9. In this
proposed topology, all the input voltage sources are fixed as where VSA1 , VSA2 ,VSB1 and VSB2 are the blocking voltage of
VA1 = 135 V and VB1 = 270 V for acquiring the maximum SA1 , SA2 , SB1 and SB2 respectively. The following is used to

VOLUME 7, 2019 51255

 C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

FIGURE 1. Basic proposed seven-level inverter.

FIGURE 2. Mode 1. FIGURE 3. Mode 2.

For the presented seven-level multilevel inverter, the number

estimate the maximum blocking voltage of all of the proposed of voltage levels, number of switches and magnitude of output
seven-level inverters switches. voltage shall be inferred from the following equations (1), (2),
(3) and (5) respectively. The number of output voltage levels
Vblock,1 = VSA1 + VSA2 + VSB1 + VSB2 + VSP + VSQ can be calculated using equation (1).
= 4(VA1 + VB1 ) (9) Nlevels = 2k+1 − 1 = 22+1 − 1 = 7 (10)

51256 VOLUME 7, 2019

C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

where k = 2 is the number of DC voltage sources on each

leg, then the number of switches, sources shall be calculated
using equation.(2) and (3) respectively.
Nswitches = 2 ∗ 2 + 2 = 6 (11)
and
Nsources = k = 2 (12)
Maximum output voltage of inverter can be represented by
using equation (5).
Vo,max = VAk +VBk = VA1 +VB1 = 135+270 = 405V (13)

III. PROPOSED THIRTY-ONE LEVEL ASYMMETRIC

MULTILEVEL INVERTER
Four power switches and two additional DC voltage sources FIGURE 4. Mode 3.

are added to the seven-level inverter to obtain the suggested

topology that can be used for the thirty-one level inverter
configuration. the thirty-one level limitation is found to be
existing in the asymmetric type of cascade h-bridge multi-
level inverter, shown in Figure.12. The proposed topology
is utilized for producing more number of voltage levels,
without increasing the quantity of DC voltage sources and
switches. Ten unidirectional power switches and four DC
voltage sources comprise the suggested topology. The power
switches were represented as SA1 , SA2 , SA3 , SA4 , SB1 , SB2 ,
SB3 , SB4 , SP , SQ and four DC voltage source represented as
VA1 , VA2 , VB1 , VB2 . The DC voltage sources if (VA1 , VA2 ,
VB1 , VB2 ) would be initially short-circuited, if the power
switches of (SA1 , SA2 ) (SA3 , SA4 ) (SB1 , SB2 ) and (SB3 , SB4 ) are
simultaneously turned ON. Hence, the power switches must
not be turned ON simultaneously. Similarly, the simultane-
FIGURE 5. Mode 4.
ous turning-ON of SP and SQ must be avoided. DC voltage
sources magnitude was considered, where VA1 = 1P.U,
VA2 = 5P.U, VB1 = 2P.U, and VB2 = 10P.U. The pulses are
generated individually and fed to the switches to obtain the
required output voltage as shown in Figure.22 and Figure.23
respectively. The control states of the power switches are
illustrated in Table 2. As depicted in Figure.12, thirty-one
switching states constitute the proposed inverter functioning.
A few output voltage levels are generated according to the
switch-ON and switch-OFF conditions as shown in Figure.13
to Figure.20, which depict the conventional inverter states of
functioning. In this proposed topology, all the input voltage
sources are fixed as VA1 = 22.5 V, VA2 = 45 V,VB1 = 112.5
V and VB2 = 225 V for acquiring the maximum peak voltage
of 405 V at the load terminals. The load used for testing is
100 ohm resistor and 175 mH respectively. Figure.24 and
Figure.25 depicts the simulation output voltage, current and FIGURE 6. Mode 5.
THD of thirty-one level inverter.
For the proposed thirty-one level multilevel inverter,
the number of voltage levels, number of switches and mag- where k = 4 is the number of DC voltage sources on each
nitude of output voltage shall be inferred from the following leg, then the number of switches, sources shall be calculated
equations (1), (2), (3) and (5) respectively. The number of using equation.(2) and (3) respectively.
output voltage levels can be calculated using equation (1)
Nlevels = 2k+1 − 1 = 24+1 − 1 = 31 (14) Nswitches = 2 ∗ 4 + 2 = 10 (15)

VOLUME 7, 2019 51257

 C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

FIGURE 7. Mode 6.

FIGURE 9. Typical output and gate pulses of seven-level inverter.

FIGURE 8. Mode 7.

and
Nsources = k = 4 (16)
Maximum output voltage of inverter can be represented as by
using equation (5).
Vo,max = VAk +VBk = 22.5+45+112.5+225 = 405V (17) FIGURE 10. Simulation output waveform of seven-level inverter.

IV. COMPARISON the DC-link capacitors are not essential for the proposed
The recommended topology employs only ten power topology, it is free from voltage balancing problem. In addi-
switches and four DC sources. Henceforth, the number tion to that, it does not require any clamping capacitor and
of gate driver modules are identical to the number of clamping diodes. However, each topology has its own merits
power switches. Then, the proposed asymmetric topology and demerits. The recommended topology has several bene-
is compared with conventional MLIs (DCMLI, FCMLI and fits, such as fewer number of switching devices, DC source
CHBMLI) in Table 3. In Table 3, every component is count and driver circuits and a least number of conducting
deliberate for a similar number of voltage levels. Although switches per voltage level. Also, the value of 3.7% total
all the conventional topologies need 60 switches to pro- harmonic distortion (THD) in asymmetric topology satisfies
vide a 31-level output voltage levels, the proposed topology the IEEE 519 standard. Therefore, it can be concluded that
involves only 10 switches. The significantly compact size of the proposed topology requires smallest switch count using
switches in the proposed topology compared with the conven- both high and fundamental switching frequencies, thereby
tional topology to products enhanced results creates it addi- reducing the power losses and cost. In the next sub section,
tional anticipated for a future renewable application. Since, losses and efficiency are discussed.

51258 VOLUME 7, 2019

C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

TABLE 2. Switching states of proposed thirty-one level inverter.

FIGURE 11. Experimental output waveform of seven-level inverter.

FIGURE 12. Proposed thirty-one level inverter.

V. LOSSES AND EFFICIENCY CALCULATION

The losses can be determined as follows Switching losses
and conduction losses are the two primary losses that
are associated with switches. The conduction loss of an
switches (Pc,Switch(t)) and the conduction loss of switch
(IGBT/MoSFET) is estimated.

Pc,switch (t) = Vswitch + Rswitch iβ (t) i(t)

 
(18)
β
 
Pc,mosfet (t) = Vmosfet + Rmosfet i (t) i(t) (19)

where Vswitch(IGBT/MOSFET) is the forward voltage drop

of IGBT/MOSFET and Vd is the forward voltage drop of
diodes. b is a constant with regards to the IGBTs/MOSFET
specification [25], and Rswitch(IGBT/MOSFET) is the
IGBTs/MOSFET equivalent resistance and Rd is the
FIGURE 13. Mode 1: Vo = (VA2 + VB2 ).
diodes equivalent resistance. The average value of the
multilevel inverter’s conduction power loss (Pc) can

VOLUME 7, 2019 51259

 C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

FIGURE 14. Mode 2: Vo = (VA2 + VB2 − VA1 ).

FIGURE 16. Mode 4: Vo = (VA2 + VA1 + VB1 + VB2 ).

FIGURE 15. Mode 3: Vo = (VB2 + VA2 − VB1 ).

FIGURE 17. Mode 5: Vo = (VA1 + VB2 ).

be given as follows [25], considering that there are
Nswitch(IGBT/MOSFET) transistor and Nd diodes at time
instant t in the current path. switching losses is witnessed. The linear variations of the
1  switching current and voltage are considered to avoid com-
Pc = Nswitch (t)pc,T (t) + ND (t)pc,D (t) d(t) (20) plexities. The following relations are derived on the basis of
2
this assumption.
The estimation of the energy loss is utilized as the basis
Z toff
for calculating the switching losses. The turn-ON and the 1
Joff ,k = v(t)i(t)d(t) = Vsw,k Itoff (21)
turn-OFF are the periods during which the occurrence of 0 6
51260 VOLUME 7, 2019
C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

FIGURE 18. Mode 16: Vo = 0.

FIGURE 20. Mode 18: Vo = -(VB1 ).

TABLE 3. Comparison with conventional topologies.

turn-OFF time of the switch k. Vsl,k is the off-state voltage

on the switch, I is the switch current before turning off,
and I is the switch current after turning on. In the output
voltages fundamental cycle, the sum of all turn-OFF and
turn-ON energy losses is equivalent to the switching power
loss (Psl ) [26].
 
X Non,k
Nswitch X X,k
Noff
Psl = f  Jon,ki + Joff ,ki  (23)
k=1 i=1 i=1

where Noff ,k is the number of switches turned-OFF, Non,k is

FIGURE 19. Mode 17: Vo = -(VA1 ).
the number of switches turned-ON, and f is the fundamental
Z ton frequency of the switch k, during a fundamental cycle. More-
1
Jon,k = v(t)i(t)d(t) = Vsw,k I 0 ton (22) over, Jk,off is the energy loss of the switch k during the ith
0 6 turn-OFF and Jon,ki is the energy loss of the switch k during
where Jkon is the turn-ON loss and Jkoff is the turn-OFF loss the ith turn-ON. The sum of the switching losses and the
of the switch k [26]. Ton is turn-ON time and Toff is the conduction losses constitutes the multilevel converters total

VOLUME 7, 2019 51261

 C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

FIGURE 21. Simulation output waveforms of input power, output power &
efficiency.

TABLE 4. Component specifications.

loss (Ploss ), which is as follows:

Ploss = Pc + Psl (24)
FIGURE 22. Gate pulses-1 of inverter.
Eventually, the inverters efficiency (n) is computed as fol-
lows:
Pout Pout
η= = (25) in MATLAB-SIMULINK. In order to facilitate real-time
Pin Pout + Ploss interfacing application, 20 output pins are possessed by the
where Pout denotes the inverters output power and Pin denotes digital I/O ports. TLP 250 driver generates the input pulses
the inverters input powers. The efficiency and total losses from the dSPACE RTI 1104. The PWM pulse pattern can
analysis is computed in the MATLAB simulation for the pro- be boosted by the gate driver from 5 V to 15 V. The power
posed thirty-one level inverter. In this inverter, IRF840 MOS- switches can be turned-ON by the 15 V pulse. The prototype
FET is undertaken for the simulation. The values of Rds (on) model component specifications are given in Table 4, the pro-
is 0.85 â"ę and VDS (on) is 0.8V respectively are assigned totype experimental results are validated at steady state, load
for the switches, the net inputs power is fed into the inverter disturbance conditions are performed with resistive, inductive
is 1600W. The load output power is obtained as 1568 W loads and THD are shown in Figure.26 to Figure.32 respec-
and efficiency is achieved as 98%. The simulation results tively. The steady state testing is done with resistive load
of input power, output power and efficiency with respect to (unity power factor load) with 400 V output voltage. The
time are shown in Figure.21. and total obtained total losses is output current is obtained with 4 A value. The RMS value
32W(switching + conduction loss). of the output current and voltage are obtained with 282.78 V
and current 2.828 A respectively. The hardware results are
VI. EXPERIMENTAL RESULTS shown in Figure.26 and Figure.27 respectively. The prototype
The prototype hardware set-up for thirty-one level inverter experimental results evidently show that with thirty-one
systems is established and tested experimentally. Figure.33 level in the output voltage. The waveform visibly shows
depicts the prototype of the suggested multilevel inverter. The that the phase angle between the load current and the load
downloading of simulation block sets is done into dSPACE voltage is zero. After the completion of steady-state testing
RTI 1104 digital I/O ports and the implementation of the with a resistive load, the inductive load (lagging power factor
staircase modulation PWM method (for gate pulses) is done load) with 400 V output voltage is introduced. The output

51262 VOLUME 7, 2019

C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

FIGURE 25. Simulation THD of thirty-one level inverter.

FIGURE 26. Experimental output voltage of thirty-one level inverter.

FIGURE 23. Gate pulses-2 of inverter.

FIGURE 27. Steady-State voltage and current with resistive load.

FIGURE 24. Simulation output voltage and current of thirty-one level

inverter.
in Figure.28. The results evidently show that with thirty-one
level in the output voltage. The waveform clearly shows that
current is found with 4 A value. The RMS value of the output the phase angle between the load current and the load voltage
current and voltage are attained with 282.78 V and current is lagging. In certainty, loads rarely exist distinctly. They
2.828 A respectively, the achieved hardware results are tabu- will always occur in a combination of resistive and inductive
lated in Table 5. The observed experimental results are given loads. Usually, in any particular place, when a resistive load

VOLUME 7, 2019 51263

 C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

FIGURE 31. Experimental voltage thd of thirty-one level inverter.

FIGURE 28. Steady-State voltage and current response with inductive
load.

FIGURE 32. Experimental current thd of thirty-one level inverter.

FIGURE 29. Unity power factor to lagging power factor load disturbance
response.

FIGURE 33. Experimental step-up of inverter.

as per IEEE standards are shown in Figure.31 and Figure.32

respectively.
FIGURE 30. Lagging power factor to unity power factor load disturbance The presented topology provides seven-level and thirty-one
response. level output voltage with only 6 and 10 switches respec-
tively in asymmetrical conditions. Under simulation a THD
value of 3.62% is obtained using SIMULINK. under exper-
is being utilized an abrupt accumulation of inductive load in imental conditions the computed THD value is 3.7%. The
parallel to the resistive load or vice versa is identical likely. ability of presented multilevel inverter topology has been
Even at these circumstances, the output voltage must stay verified using both the experimental setup and the sim-
stable is shown in Figure.29 and Figure.30 respectively. The ulation and the outcomes are presented for both condi-
proposed inverter will generate higher output voltage levels tions. The experimental output parameters are shown in
and with fewer circuit components with relatively low THD Table 5.

51264 VOLUME 7, 2019

C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

TABLE 5. Experimental output parameters. [11] S. De Caro, S. Foti, G. Sceiba, T. Scimone, and A. Testa, ‘‘A six-level
asymmetrical hybrid photovoltaic inverter with inner MPPT capability,’’
in Proc. 6th Int. Conf. Clean Electr. Power (ICCEP), 2017, pp. 631–635.
[12] M. M. C. Merlin et al., ‘‘The alternate arm converter: A new hybrid
multilevel converter with dc-fault blocking capability,’’ IEEE Trans. Power
Del., vol. 29, no. 1, pp. 310–317, Feb. 2014.
[13] C. A. Silva, L. A. Cordova, P. Lezana, and L. Empringham, ‘‘Implemen-
tation and control of a hybrid multilevel converter with floating DC links
for current waveform improvement,’’ IEEE Trans. Ind. Electron., vol. 58,
VII. CONCLUSION no. 6, pp. 2304–2312, Jun. 2016.
The proposed inverter is tested experimentally with resistive [14] G. P. Adam, I. A. Abdelsalam, K. H. Ahmed, and B. W. Williams, ‘‘Hybrid
multilevel converter with cascaded H-bridge cells for HVDC applications:
and inductive loads. The output waveforms obtained dur- Operating principle and scalability,’’ IEEE Trans. Power Electron., vol. 30,
ing the resistive load test clearly show that the phase angle no. 1, pp. 65–77, Jan. 2015.
between current and voltage is zero. And the inductive load [15] D. A. Ruiz-Caballero, R. M. Ramos-Astudillo, S. A. Mussa, and
M. L. Heldwein, ‘‘Symmetrical hybrid multilevel DC–AC converters with
testing results show that the current is lagging voltage. To test reduced number of insulated DC supplies,’’ IEEE Trans. Ind. Electron.,
the robustness of the proposed scheme, a load disturbances vol. 57, no. 7, pp. 2307–2314, Jul. 2010.
test is conducted. It is observed that the proposed topology [16] S. Sabyasachi, V. B. Borghate, R. R. Karasani, S. K. Maddugari, and
H. M. Suryawanshi, ‘‘Hybrid control technique-based three-phase
is well stabilized under load disturbances conditions. The cascaded multilevel Inverter topology,’’ IEEE Access, vol. 5,
presented topology provides seven-level and thirty-one level pp. 26912–26921, 2017.
output voltage with only 6 and 10 switches respectively [17] S.-J. Park, F.-S. Kang, M. H. Lee, and C.-U. Kim, ‘‘A new single-phase
five-level PWM inverter employing a deadbeat control scheme,’’ IEEE
in asymmetrical conditions. Under simulation a THD value Trans. Power Electron., vol. 18, no. 3, pp. 831–843, May 2003.
of 3.62% is obtained using SIMULINK. under experimental [18] S. Kouro et al., ‘‘Recent advances and industrial applications of multilevel
conditions the computed THD value is 3.7%. The ability of converters,’’ IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553–2580,
Aug. 2010.
presented MLI topology has been verified using both simula- [19] H. Mao, F. C. Y. Lee, X. Zhou, H. Dai, M. Cosan, and
tion and experimental setups and the results are demonstrated D. Boroyevich, ‘‘Improved zero-current transition converters for high-
for both conditions. The suggested topology is appropriate power applications,’’ IEEE Trans. Ind. Appl., vol. 53, no. 5, pp. 1220–1232,
Sep./Oct. 1997.
for the integration of medium-voltage renewable energy and [20] M. Rodríguez, A. Rodríguez, P. F. Miaja, D. G. Lamar, and J. S. Zúniga,
power quality improvement in DVR, DStatcom and FACTs. ‘‘An insight into the switching process of power MOSFETs: An improved
analytical losses model,’’ IEEE Trans. Power Electron., vol. 25, no. 6,
pp. 1626–1640, Jun. 2010.
REFERENCES [21] B. Gu, J. Dominic, J.-S. Lai, C.-L. Chen, T. LaBella, and B. Chen, ‘‘High
[1] T. Porselvi and R. Muthu, ‘‘Comparison of cascaded H-Bridge, neutral reliability and efficiency single-phase transformerless inverter for grid-
point clamped and flying capacitor multilevel inverters using multicarrier connected photovoltaic systems,’’ IEEE Trans. Power Electron., vol. 28,
PWM,’’ in Proc. Annu. IEEE India Conf., Dec. 2011, pp. 1–4. no. 5, pp. 2235–2245, May 2013.
[2] M. A. Hosseinzadeh, M. Sarbanzadeh, E. Sarbanzadeh, M. Rivera, and [22] S. S. Lee, ‘‘A single-phase single-source 7-level inverter with triple voltage
R. Grégor, ‘‘Back-to-back modified T-type half-bridge module for cas- boosting gain,’’ IEEE Access, vol. 6, pp. 30005–30011, 2018.
caded multi-level inverters with decreased number of components,’’ in [23] C. Dhanamjayulu and S. Meikandasivam, ‘‘Implementation and compari-
Proc. IEEE Int. Conf. Electr. Syst. Aircraft, Railway, Ship Propuls. Road son of symmetric and asymmetric multilevel inverters for dynamic loads,’’
Vehicles Int. Transp. Electrific. Conf. (ESARS-ITEC), Nov. 2018, pp. 1–6. IEEE Access, vol. 6, pp. 738–746, 2017.
[3] J. Rodríguez, J.-S. Lai, and F. Z. Peng, ‘‘Multilevel inverters: A survey of [24] V. Sumathi and P. Venugopal, ‘‘Investigation on DC-AC converter with
topologies, controls, and applications,’’ IEEE Trans. Ind. Electron., vol. 49, reduced device count,’’ in Proc. IEEE Innov. Power Adv. Comput. Technol.
no. 4, pp. 724–738, Aug. 2002. (i-PACT), Apr. 2017, pp. 1–6.
[4] Y. Suresh, J. Venkataramanaiah, A. K. Panda, C. Dhanamjayulu, and [25] E. Babaei, S. Alilu, and S. Laali, ‘‘A new general topology for cascaded
P. Venugopal, ‘‘Investigation on cascade multilevel inverter with symmet- multilevel inverters with reduced number of components based on devel-
ric, asymmetric, hybrid and multi-cell configurations,’’ Ain Shams Eng. J., oped H-bridge,’’ IEEE Trans. Ind. Electron., vol. 61, no. 8, pp. 3932–3939,
vol. 8, no. 2, pp. 263–276, 2017. Aug. 2014.
[5] N. Prabaharan, A. H. Fathima, and K. Palanisamy, ‘‘New hybrid mul- [26] E. Babaei, S. Laali, and S. Bahravar, ‘‘A new cascaded multi-level inverter
tilevel inverter topology with reduced switch count using carrier based topology with reduced number of components and charge balance con-
pulse width modulation technique,’’ in Proc. IEEE Conf. Energy Convers. trol methods capabilities,’’ Electr. Power Compon. Syst., vol. 43, no. 19,
(CENCON), Oct. 2015, pp. 176–180. pp. 2116–2130, 2015.
[6] A. Gopal, I. Gnanambal, and S. Naresh, ‘‘Boost inverter: A new propor-
tional integral control strategy for resistive and motor loads using genetic
algorithm,’’ Int. J. Appl. Eng. Res., vol. 10, no. 2, pp. 37022–37027, 2010.
[7] A. Ali and J. Nakka, ‘‘Improved performance of cascaded multilevel C. DHANAMJAYULU received the B.Tech. degree
inverter,’’ in Proc. Int. Conf. Microelectron., Comput. Commun. (Micro- in electronics and communication engineer-
Com), 2016, pp. 1–5. ing from JNTU University, Hyderabad, India,
[8] A. Ali, H. Bhattacherjee, and J. Nakka, ‘‘Improved power rating of cas- the M.Tech. degree in control and instrumentation
caded H-Bridge multilevel inverter,’’ in Proc. IEEE Annu. India Conf.
systems from the IIT, Madras, India, and the Ph.D.
(INDICON), Dec. 2015, pp. 1–5.
degree in electronics engineering from the Vellore
[9] N. B. Deshmukh, R. D. Thombare, M. M. Waware, and D. S. More,
‘‘A novel family of three phase transistor clamped h-bridge multi-
Institute of Technology, Vellore, India. He is cur-
level inverter with improved energy efficiency,’’ in Proc. IEEE Int. rently a Faculty and a Member of the Control and
Conf. Power Electron., Drives Energy Syst. (PEDES), Dec. 2016, Automation Department with the School of elec-
pp. 1–5. trical engineering, Vellore Institute of Technology,
[10] N. B. Deshmukh, R. D. Thombare, M. M. Waware, and D. S. More, where he is also a Senior Assistant Professor with the School of Electrical
‘‘A novel family of three phase transistor clamped H-bridge multilevel Engineering. Since 2010, he has been a Senior Assistant Professor with the
inverter with improved energy efficiency,’’ in Proc. IEEE Int. Conf. Power Vellore Institute of Technology. His research interests include multilevel
Electron., Drives Energy Syst. (PEDES), Dec. 2016, pp. 1–5. inverters, power converters, and active power filters and power quality.

VOLUME 7, 2019 51265

 C. Dhanamjayulu et al.: Real-Time Implementation of a 31-Level Asymmetrical Cascaded MLI for Dynamic Loads

G. ARUNKUMAR received the bachelor’s degree M. PRAVEEN KUMAR received the B.E. degree
in electrical and electronics engineering and the in electronics and instrumentation engineering
master’s degree in power electronics, in 2002 and from Andhra University, Visakhapatnam, India,
2005, respectively, and the Ph.D. degree from the M.Tech. degree in instrumentation and control
Anna University, Tamilnadu, India, in 2015. Since systems from the Jawaharlal Nehru Technological
2015, he has been an Associate Professor with the Institute (JNTU), Kakinada, India, and the Ph.D.
School of Electrical Engineering, Vellore Institute degree in electrical engineering from the Vellore
of Technology, Vellore. Institute of Technology (VIT), Vellore, India. He is
currently a Senior Assistant Professor with the
School of Electrical Engineering, VIT University,
Vellore, Tamilnadu, India. He has authored more than 10 research papers in
journals and conferences. His interests include process control and virtual
instrumentation.
B. JAGANATHA PANDIAN received the M.E.
degree from the Madras Institute of Technology,
Anna University, Chennai. He is currently an
Assistant Professor with the School of Electri- A. RINI ANN JERIN received the bachelor’s
cal Engineering, Vellore Institute of Technology, degree in electrical and electronics engineering
Vellore. His research interests include machine and the master’s degree in power electronics,
learning, nonlinear control, and system identifica- in 2008 and 2010, respectively, and the Ph.D.
tion and optimization. degree from the Vellore Institute of Technology,
Tamilnadu, India.

C. V. RAVI KUMAR received the B.Tech. degree

in electronics and communication engineering
from Anna University, Chennai, India, in 2006, P. VENUGOPAL received the B.Tech. degree
the M.Tech. degree in digital electronics and in EEE from JNTU University, in 2003,
communication systems from JNTU Ananthapur, the M.Tech. degree from IIT Madras, in 2006, and
India, in 2009, and the Ph.D. degree in wire- the Ph.D. degree from the Vellore Institute of Tech-
less communication from the Vellore Institute of nology (VIT), Vellore, Tamilnadu, India, in 2010.
Technology, Vellore, India, in 2018, where he is Since 2010, he has been a Senior Assistant Pro-
currently an Assistant Professor with the School fessor with the School of Electronics Engineering,
of Electronics (SENSE). His research interests VIT.
include wireless networking, MC-CDMA, artificial intelligence, soft com-
puting techniques, and neural networks.

51266 VOLUME 7, 2019