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DLD ECE Mid-II QP

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JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCES

(AUTONOMOUS)
NARSAMPET WARANGAL – 506332(TS)
B.TECH II –YEAR I-SEMESTER MID-II EXAMINATIONS, Jan -2024

BRANCH: ----II B.Tech I sem-ECE


SUBJECT: Digital Logic Design

Time: 1 ½ HoursDATE:
Max. Marks : 30

Note: This question Paper Contains two parts. Part A & B


Course Outcomes for Assessment in this Test:
Cos Course Outcome
Understand the numerical information in different forms and Applying Boolean Algebra theorems for
1
simplifying Boolean Expression using different techniques
Design and analyze the combinational and sequential circuits and verifying the circuit to solve real
2
world problems.
3 Optimize combinational and sequential logic circuits.

4 Understand the concepts logic families and programmable logic devices( CPLD, FPGAs )
PART – A(20X ½= 10Marks)
Marks
Tabular method is also known as _____________ ½
1. a)Karnaugh map b) Quine Mc-cluskey c)Prime Implicant d)all the above
When T=1 the next state(Qn+1) will be ½
2. a)Same as present state b) complement of present state c) none of these d) either a or
b
If Qn=1 & Qn+1=0 then flip flop inputs of JK are. ½
3.
a) 0.X b) 1,X c) X, 0 d) X,1.
n
For N states ,where N=2 , the number of required flip flop to design the circuit is. ½
4. a)n2 b) 2n c) n d) n-1.

Which of the following combinational circuits that has n inputs and 2n output line. ½
5. a)De-multiplixer b)Decoder c)Multiplexer d)Encoder

How many AND gates are required for a 1-to-16 De-multiplexer ½


6.
a)2 b)16 c)5 d)8
The minimum number of NAND gates required to implement A+AB’+AB’C is equal ½
7. to
a) Zero b) One c) Four d) Seven
8. ½
A MOD-2 Counter is followed by a MOD-5 counter is .

a) same as a MOD-5 counter followed by a MOD-2 counter


b) A decade counter
c)MOD-7 Counter
d)None of the above
A ring counter is same as _____
9. a)up-down counter b)parallel counter c)shift register d)none of these
Sequential operations in digital system are described by
10. a)MAP b)ASM Chart c)Flow chart d)Graph
The characteristic equation of JK flip flop is______________ ½
11

12. The number of flip flop required to design a MOD-16 counter ________ ½

13. The elements of ASM Chart is __________,_________& _________ ½


The output depends on present state and present input is______ machine and the ½
14.
output depends on present state is ________ machine.
15. ___________ is a logic circuit which can add three binary numbers ½
If present state is 1 then next state 1 is JK inputs_________ ½
16.
If s=1 and r=0 in S-R flip flop then Q=___________ ½
17

18. DE-Multiplexer is also known as___________ ½


In merger graph _______ symbol is used if output are changing from 0 to 1 and 1 to 0
19.
while comparing two states
20. State equivalence theorem states that __________

PART – B (5 X4 = 20 Marks) Bloom’s


Mappi
ANSWER ANY THREE QUESTIONS Taxonomy Mark
ngCos
Levels
a).Implement the following Boolean function using 8Χ1 MUX 2,3 VI 4
F(A,B,C,D) = ∑m(1,2,4,6,7,8,11,13,15).
1 b). Design a 3-to-8 Decoder .and implement the following
Boolean functions f1(x,y,z)=∑m(0,1,4,5).
f2(x,y,z)=∑m(2,5,6,7) into 3×8decoder
a) Explain the operation of JK flip flop using NAND gates. 2,3 II 4
2
b) convert T to JK Flip Flop.
2 VI 4
3 Explain in detail about shift register.
3 VI 4
Design a 3-bit synchronous counter using JK-flip flop
4

a). Diffrencence between mealy and Moore machine. 4 II,IV 4


5
b).State the limitation and capabilities of FSM.
6. a)Find the maximal compatibles by means of a merger diagram
to the following incompletely specified machine
b)What is an ASM block.Draw an ASM chart with one example
of FSM.

Assessment Summary

Design/
Remember Understand Apply Analyze Evaluate
COs Create Total
(I) (II) (III) (IV) (V)
(VI)
1 3
2 3
3 3 3
4 3

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