DLD ECE Mid-II QP
DLD ECE Mid-II QP
DLD ECE Mid-II QP
(AUTONOMOUS)
NARSAMPET WARANGAL – 506332(TS)
B.TECH II –YEAR I-SEMESTER MID-II EXAMINATIONS, Jan -2024
Time: 1 ½ HoursDATE:
Max. Marks : 30
4 Understand the concepts logic families and programmable logic devices( CPLD, FPGAs )
PART – A(20X ½= 10Marks)
Marks
Tabular method is also known as _____________ ½
1. a)Karnaugh map b) Quine Mc-cluskey c)Prime Implicant d)all the above
When T=1 the next state(Qn+1) will be ½
2. a)Same as present state b) complement of present state c) none of these d) either a or
b
If Qn=1 & Qn+1=0 then flip flop inputs of JK are. ½
3.
a) 0.X b) 1,X c) X, 0 d) X,1.
n
For N states ,where N=2 , the number of required flip flop to design the circuit is. ½
4. a)n2 b) 2n c) n d) n-1.
Which of the following combinational circuits that has n inputs and 2n output line. ½
5. a)De-multiplixer b)Decoder c)Multiplexer d)Encoder
12. The number of flip flop required to design a MOD-16 counter ________ ½
Assessment Summary
Design/
Remember Understand Apply Analyze Evaluate
COs Create Total
(I) (II) (III) (IV) (V)
(VI)
1 3
2 3
3 3 3
4 3
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