K.L.E.

Society’s

K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI

Dept of Electrical and Electronics Engg.
K.L.E.S

MODULE-1 QUESTIONS (Previous 3years VTU Questions Papers)

1. Explain the following

Practical diode model
Ideal diode model
Piece wise linear diode model (8M)
2. Explain the operation of negative clamper. (6M)
3. Explain the operation of positive clamper. (6M)
4. Explain the operation of the circuit show below fig draw the output waveform and
transfer characteristics. (8M)

5. Write the procedure for analyzing the clamper circuits. Determine the output voltage for
the network shown. Assume f= 1000Hz. And ideal diode. (8M)

6. For clipping circuit shown obtain the transfer characteristics. Ramp input varies form 0 –
50V. indicates the slopes. Assume ideal diode. (8M)
 K.L.E. Society’s

K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI

Dept of Electrical and Electronics Engg.
K.L.E.S

7. Design the ideal clamper circuit to obtain the output wave form as shown(8M)

8. Consider a fixed bias circuit of a transistor. Obtain the expression for stability factor for
SIco, SVbe and SB . draw the circuit diagram. (8M)
9. Design the voltage divider biasing circuit for given conditions Ic= 1mA, Sico 20, B=100,
Ve = 1V, Vce=6V, Vcc= 12V. draw the circuit diagram. (8M)
10. What is biasing?. Discus the factor causes for bias instability in a transistor. (8M)
11. With neat circuit diagram, explain the emitter stabilized bias ciruit. Write the necessary
equation. (8M)
12. For the circuit shown in fig find Ic, Vb, Ve and S ico. (8M)

13. Derive the expression for Ib,Ic and Vce for voltage divider bias using exact analysis.
(8M)
14. For the circuit shown below determine Ib, Ic, Vce (8M)
15. Determine the Rb and Rc for the transistor inverter . if Ic= 10mA, Ib= 150% of Ib(max)
(8M)
 K.L.E. Society’s

K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI

Dept of Electrical and Electronics Engg.
K.L.E.S

16. Name different biasing methods of transistor. With neat circuit diagram analyze the fixed
bias circuit, with effect of variation in Ib, Rc and Vcc on Q point of the load line. (8M)
17. Explain the circuit of transistor switch being used as an inverter. (6M)
18. In voltage divider bias circuit of BJT, Vcc=20V, Rc=10K Re=1.5K(8M)
19. R1=40K, R2= 4K. assume silicon transistor with B=150. Find Ic, Vce and Ic(sat) using
exact analysis method. (8M)
20. Consider a voltage divider bias circuit of a transistor. Obtain the expression for stability
factor for SIco, SVbe and SB . draw the circuit diagram. (8M)
 K.L.E. Society’s

K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI

Dept of Electrical and Electronics Engg.
K.L.E.S

MODULE-4 QUESTIONS (Previous 3years VTU Questions Papers)

1. Give the classification of power amplifiers with their input and output waveform.

2. Explain the working of a transformer coupled class B push pull amplifier and also show
that its efficiency is d 78.50% and maximum power dissipation. (10M)

3. With neat circuit diagram explain the operation of a transformer coupled class A power
amplifiers. Derive the expression for efficiency (10M)

4. State barkhausen criteria for sustained oscillation, apply this to wein bridge oscillator and
explain its operation. (10M)

5. Explain working of a hartley oscillator. In hartley oscillator L1=20mH,L2=20mH and c is

variable. Find the range of c for frequency is varied from 1MHz to 2.5MHz. (10M)

6. With neat circuit diagram explain the RC phase shift oscillator using BJT. 8M

7. In hartley oscillator the two inductances are 2mH and 20 micro H, while the frequency is
to be changed from 950 KHz to 2050 KHz. Calculate the range over which the capacitor
is to be varied. 6M
8. With circuit diagram explain the crystal oscillator in series resonant mode. A crystal has
following parameters L=0.334 H, C= 0.065 pico F and R=5.5K ohms calculate the
resonant frequency. 6M
9. A colpitts oscillator uses a transistor with hfe= 120. Find the values of C1, C2 and L for a
frequency of oscillation of 150 KHz. Assume C1= 1000pF.

10. Explain the operation of transformer coupled class B amplifiers convert and derive its
conversion efficiency 10M

11. Explain the operation of wein bridge oscillator. 8M

12. With neat sketch explain the operation of colpitts oscillator. 8M

 K.L.E. Society’s

K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI

Dept of Electrical and Electronics Engg.
K.L.E.S

13. What is harmonic distortion? Derive the expression for second harmonic distortion in
power amplifiers, using 3 point method. (10M)

14. The following reading obtained for a power amplifier VCEQ=10 V Vmax=14V and
Vmin= 6V. Calculate second harmonic distortion. If RL= 15 ohms determine the power
delivered to the load6M

15. A single transistor amplifier with transformer coupled load produces harmonic
amplitudes in the output as follows
Bo= 1.5mA, B1= 120mA, B2=10mA, B3=4mA, B4= 2mA, B5= 1mA.
a. Determine the percentage total harmonic distortion
b. Assume a 2nd transistor is used along with suitable transformer to provide push pull
operation determine new total harmonic distortion
c. If RL= 25 ohms calculate the total power output in each case. 8 M

16. A complementary symmetry push pull amplifier is operated with Vcc = + 10V. RL= 5Ω.
Determine maximum output power, power rating of transistor and DC input power.
(10M).

17. Explain the concept of positive feedback used in oscillators. 5M

18. List out the comparison between RC phase shift and wein bridege oscillator.5M

19. Obtain an expression for frequency of oscillation in colpitts oscillator. 10M

20. Obtain an expression for frequency of oscillation in Hartley oscillator. 10M

21. In RC phase shift oscillator using transistor f0= 10KHz, R1= 25KΩ, R2= 57KΩ,
Rc=20KΩ, R= 7.1KΩ and hie=1.8KΩ. calculate the capacitor C and h fe. Draw the circuit
diagram. 5M

22. Explain the complementary symmetry class B amplifier. 8M

 K.L.E. Society’s

K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI

Dept of Electrical and Electronics Engg.
K.L.E.S

23. A series fed class A amplifier shown in fig operates from dc source and applied ac input
signal generates peak base current of 9mA. Calculate IcQ, VCEQ Pdc, Pac and efficiency.
Assume beta= 50 and VBE= 0,7 V. 8M

MODULE-2 QUESTIONS (Previous 3years VTU Questions Papers)

1. For the common collector circuit fig 1., the transistor h parameter are hfe=101, hre=1
hoc=25microA / v, hie=1.2K. determine the Ri, Ai,Av and Ro for the circuit. (10m)

2. State and prove Miller’s theorem.(5)

3. Obtain re parameter model for CB mode.(5)
4. Explain the low frequency response of single state RC coupled amplifier.(10)
 K.L.E. Society’s

K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI

Dept of Electrical and Electronics Engg.
K.L.E.S

5. For an amplifier, the mid band gain is 100 and lower cut off freq 1KHz calculate the gain
of the amplifier at frequency of 20Hz.
6. Define the h parameter and hence derive the h parameter model of CE BJT
7. For the circuit shownin fig, the transistor parameter are hib = 22 ohm, hfb= 0.98,
hob=0.49micro A / v and hrb=2.9 8 10-4. Calculate 1. Input resistance 2. Out put
resistance 3. Current gain 4. Voltage gain 5. Overall voltage and current gain

8. Explain the low frequency and high frequency response of RC coupled amplifier.
9. Describe miller’s effect and derive an equation for miller input and output capacitance.
10. Obtaine the expression forvoltage gain Zin and Zo of common base configuration using
AC equivalent circuit with re model
11. Explain with a neat circuit , emitter follower configuration, justify how voltage gain is
unity.
12. For the circuit shown determine the Vcc if Av= -160 and r0 = 100K take beta= 100.

13. Describe the factors that affecting the low frequency response of BJT CE amplifiers.
 K.L.E. Society’s

K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI

Dept of Electrical and Electronics Engg.
K.L.E.S

MODULE-5 QUESTIONS (Previous 3years VTU Questions Papers)

1. Consider a n- channel JFET using voltage divider biasing. Explain the its Dc analysis.
Also derive the expression for transconductance.
2. Design a fixed bias circuit of fig to have ac gain of -15. Calculate the value of RD to get
this gain. If VDD= 40V, Rg=10Mohms, IDss= 10 mA, Vp= - 4 , Yos=20 microS,
C1= 0.1 micro F

3. Draw the JFET amplifier using fixed bias configuration. Derive Zi, Zo and Av using
small signal Model.
4. For the JFET amplifier shown in fig calculate 1. Gm 2. Rd 3. Zi 4. Zo 5. Av.
Take IDss = 5mA , Vp= -6 Yos= 40 micro S

5. For JFET amplifier shown in fig calculate Zi ,Zo Av

 K.L.E. Society’s

K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI

Dept of Electrical and Electronics Engg.
K.L.E.S

6. List the diffrence between i) FET and BJT ii)Enchancement and Depletion Type
MOSFET.
7. Explain the construction and working of JFET with their transfer charectristics.
8. Explain the constuction and working of E-MOSFET with their transfer charectrisitics.
9. Derive the mathematical eepression for transconductnce of JFET
10. Derive the mathematical eepression for transconductnce of E-MOSFET
11. Derive the relationship between gm and ID
12. For the circuit shown in fig VGsQ= - 2.5 and IDQ= 2.5 mA find, gm, rd Zi, Zo, Av.
Assume IDss= 8mA Vp= - 6V Yos= 20 microS

13. For E-MOSFET voltage divider biasing circuit. Derive the expression for Zi, Zo, and
Av.
14. For E-MOSFET drain feedback biasing circuit. Derive the expression for Zi, Zo, and Av.