Unit-4 (INPUT-OUTPUT ORGANIZATION)

PERIPHERAL DEVICES

A computer peripheral is a device that is connected to a computer but is not part of the core
computer architecture.
The core elements of a computer are the central processing unit, power supply, motherboard
and the computer case that contains those three components.
Input or output devices that are connected to computer are called Peripheral Devices. These
devices are designed to read information into or out of the memory unit upon command from
the CPU and are considered to be the part of computer system.
Peripheral devices can be External or Internal. For example, a printer is an external device
that you connect using a cable, while an optical disc drive is typically located inside the
computer case. Internal peripheral devices are also referred to as integrated peripherals. When
most people refer to peripherals, they typically mean external ones.
Types of Peripheral Devices

There are many different peripheral devices, but they fall into three general categories:

1. Input devices- The input devices are defined as it converts incoming data and
instructions into a pattern of electrical signals in binary code that are
comprehensible to a digital computer.
Example: Keyboard, mouse, scanner, microphone etc.
2. Output devices - An output device is generally reverse of the input process and
generally translating the digitized signals into a form intelligible to the user. The
output device is also performed for sending data from one computer system to
another. For some time punched-card and paper-tape readers were extensively used
for input, but these have now been supplanted by more efficient devices.
Example: Monitors, headphones, printers etc.

3. Storage devices - Storage devices are used to store data in the system which is
required for performing any operation in the system. The storage device is one of the
most requirement devices and also provide better compatibility.
Example: Hard disk, magnetic tape, Flash memory etc.

Advantage of Peripheral Devices:

Peripheral devices provide more feature due to this operation of the system is easy. These are
given below:
 It is helpful for taking input very easily.
 It is also provided a specific output.
 It has a storage device for storing information or data
 It also improves the efficiency of the system.
 I/O INTERFACE

Input-Output Interface is used as a method which helps in transferring of information

between the internal storage devices i.e. memory and the external peripheral device.
A peripheral device is that which provide input and output for the computer, it is also called
Input-Output devices.
For Example: A keyboard and mouse provide Input to the computer are called input devices
while a monitor and printer that provide output to the computer are called output devices.
Just like the external hard-drives, there is also availability of some peripheral devices which
are able to provide both input and output.
In micro-computer base system, the only purpose of peripheral devices is just to
provide special communication links for the interfacing them with the CPU. To resolve the
differences between peripheral devices and CPU, there is a special need for communication
links.

The major differences are as follows:

1. The nature of peripheral devices is electromagnetic and electro-mechanical. The
nature of the CPU is electronic. There is a lot of difference in the mode of
operation of both peripheral devices and CPU.
2. There is also a synchronization mechanism because the data transfer rate of
peripheral devices are slow than CPU.
3. In peripheral devices, data code and formats are differ from the format in the CPU
and memory.
4. The operating mode of peripheral devices are different and each may be controlled
so as not to disturb the operation of other peripheral devices connected to CPU.

There is a special need of the additional hardware to resolve the differences between CPU
and peripheral devices to supervise and synchronize all input and output devices.
Functions of Input-Output Interface:

1. It is used to synchronize the operating speed of CPU with respect to input-output

devices.
2. It selects the input-output device which is appropriate for the interpretation of the
input-output device.
3. It is capable of providing signals like control and timing signals.
4. In this data buffering can be possible through data bus.
5. There are various error detectors.
6. It converts serial data into parallel data and vice-versa.
7. It also converts digital data into analog signal and vice-versa.

ALU ASYNCHRONOUS DATA TRANSFER

The internal operations in individual unit of digital system are synchronized by means of clock
pulse, means clock pulse is given to all registers within a unit, and all data transfer among
internal registers occur simultaneously during occurrence of clock pulse.

Now, suppose any two units of digital system are designed independently such as CPU and I/O
interface. And if the registers in the interface (I/O interface) share a common clock with CPU
registers, then transfer between the two units is said to be Synchronous.

But in most cases, the internal timing in each unit is independent from each other in such a way
that each uses its own private clock for its internal registers. In that case, the two units are said
to be asynchronous to each other, and if data transfer occur between them this data transfer is
said to be Asynchronous Data Transfer.

The Asynchronous Data Transfer between two independent units requires that control signals
be transmitted between the communicating units so that the time can be indicated at which they
send data.

This asynchronous way of data transfer can be achieved by two methods:

1. One way is by means of strobe pulse which is supplied by one of the units to another
unit. When transfer has to occur. This method is known as “Strobe Control”.

2. Another method commonly used is to accompany each data item being transferred with
a control signal that indicates the presence of data in the bus. The unit receiving the
data item responds with another signal to acknowledge receipt of the data. This method
of data transfer between two independent units is said to be “Handshaking”.
Methods of asynchronous data transfer are :

1. Strobe Control:

The Strobe Control method of asynchronous data transfer employs a single control line to
time each transfer. This control line is also known as strobe and it may be achieved either by
source or destination, depending on which initiate transfer.

Source initiated strobe for data transfer: The block diagram and timing diagram of strobe
initiated by source unit is shown in figure below:

In block diagram we see that strobe is initiated by source, and as shown in timing diagram, the
source unit first places the data on the data bus. After a brief delay to ensure that the data settle
to a steady value, the source activates a strobe pulse.

The information on data bus and strobe control signal remains in the active state for a sufficient
period of time to allow the destination unit to receive the data. Actually, the destination unit,
uses a falling edge of strobe control to transfer the contents of data bus to one of its internal
registers.

The source removes the data from the data bus after it disables its strobe pulse. New valid data
will be available only after the strobe is enabled again.
 Destination-initiated strobe for data transfer: The block diagram and timing diagram of
strobe initiated by destination is shown in figure below:

In block diagram, we see that, the strobe initiated by destination, and as shown in timing
diagram, the destination unit first activates the strobe pulse, informing the source to provide
the data.

The source unit responds by placing the requested binary information on the data bus.The
data must be valid and remain in the bus long enough for the destination unit to accept it.

The falling edge of strobe pulse can be used again to trigger a destination register. The
destination unit then disables the strobe. And source removes the data from data bus after a
per determine time interval.

2. Handshaking:

The disadvantage of strobe method is that source unit that initiates the transfer has no way of
knowing whether the destination has actually received the data that was placed in the bus.
Similarly, a destination unit that initiates the transfer has no way of knowing whether the source
unit, has actually placed data on the bus.

This problem can be solved by handshaking method.

Hand shaking method introduce a second control signal line that provides a replay to the unit
that initiates the transfer.

In it, one control line is in the same direction as the data flow in the bus from the source
to destination. It is used by source unit to inform the destination unit whether there are valid
data in the bus.

The other control line is in the other direction from destination to the source. It is used by the
destination unit to inform the source whether it can accept data. And in it also, sequence of
control depends on unit that initiate transfer. Means sequence of control depends whether
transfer is initiated by source and destination. Sequence of control in both of them are described
below:

Source initiated Handshaking: The source-initiated transfer using handshaking lines is

shown in figure below:

In its block diagram, we see that two handshaking lines are "data valid", which is generated
by the source unit, and "data accepted", generated by the destination unit.

The timing diagram shows the timing relationship of exchange of signals between the two
units. Means as shown in its timing diagram, the source initiates a transfer by placing data on
the bus and enabling its data valid signal.

The data accepted signal is then activated by destination unit after it accepts the data from the
bus. The source unit then disable its data valid signal which invalidates the data on the bus.

After this, the destination unit disables its data accepted signal and the system goes into initial
state. The source unit does not send the next data item until after the destination unit shows
its readiness to accept new data by disabling the data accepted signal.
Destination initiated handshaking: The destination-initiated transfer using handshaking
lines is shown in figure below:

In its block diagram, we see that the two handshaking lines are "data valid", generated by the
source unit, and "ready for data" generated by destination unit. Note that the name of signal
data accepted generated by destination unit has been changed to ready for data to reflect its
new meaning.

In it, transfer is initiated by destination, so source unit does not place data on data bus until
it receives ready for data signal from destination unit. After that, hand shaking process is some
as that of source initiated.

The sequence of event in it are shown in its sequence diagram and timing relationship between
signals is shown in its timing diagram.

Thus, here we can say that, sequence of events in both cases would be identical. If we
consider ready for data signal as the complement of data accept. Means, the only difference
between source and destination-initiated transfer is in their choice of initial state.
 MODES OF DATA TRANSFER

The different types of parallel data transfer schemes. We have:

 Programmed I/O Data Transfer

 Interrupt Driven I/O Data Transfer
 Device or Direct Memory Access (DMA) Data Transfer

1) Programmed I/O
 In the programmed I/O method, the I/O device does not have direct access to
memory.
 A transfer from an I/O device to memory requires the execution of several
instructions by the CPU, including an input instruction to transfer the data from the
device to the CPU and a store instruction to transfer the data from the CPU to memory.

 Other instructions may be needed to verify that the data are available from the device
and to count the numbers of words transferred.

 An example of data transfer from an I/O device through an interface into the CPU is
shown in Fig. 10. The device transfers bytes of data one at a time as they are available.

 When a byte of data is available, the device places it in the I/O bus and enables its
data valid line.

 The interface accepts the byte into its data register and enables the data accepted line.
 The interface sets a bit in the status register that we will refer to as an F or "flag" bit.
The device can now disable the data valid line, but it will not transfer another byte until
the data accepted line is disabled by the interface.

 A program is written for the computer to check the flag in the status register to
determine if a byte has been placed in the data register by the I/O device.

 This is done by reading the status register into a CPU register and checking the value
of the flag bit.
  If the flag is equal to 1, the CPU reads the data from the data register.

 The flag bit is then cleared to 0 by either the CPU or the interface, depending on how
the interface circuits are designed.

 Once the flag is cleared, the interface disables the data accepted line and the device
can then transfer the next data byte.

 A flowchart of the program that must be written for the CPU is shown in Fig. 11. It
is assumed that the device is sending a sequence of bytes that must be stored in memory.
 The transfer of each byte requires three instructions:
1. Read the status register.
2. Check the status of the flag bit and branch to step 1 if not set or to step 3 if set.
3. Read the data register.

 Each byte is read into a CPU register and then transferred to memory with a store
instruction. A common I/O programming task is to transfer a block of words from an
I/O device and store them in a memory buffer.

Types-
1) Synchronous Data Transfer
2) Asynchronous Data Transfer
 Strobe
 Handshaking

Interrupt-Initiated I/O

 An alternative to the CPU constantly monitoring the flag is to let the interface inform
the computer when it is ready to transfer data.

 This mode of transfer uses the interrupt facility. While the CPU is running a program,
it does not check the flag.

 However, when the flag is set, the computer is momentarily interrupted from
proceeding with the current program and is informed of the fact that the flag has been
set.
 The CPU deviates from what it is doing to take care of the input or output transfer.
 After the transfer is completed, the computer returns to the previous program to
continue what it was doing before the interrupt.

 The CPU responds to the interrupt signal by storing the return address from the
program counter into a memory stack and then control branches to a service routine that
processes the required I/O transfer.
  The way that the processor chooses the branch address of the service routine varies
from one unit to another.

In principle, there are two methods for accomplishing this.

 One is called vectored interrupt and the other, non-vectored interrupt. In a non-
vectored interrupt, the branch address is assigned to a fixed location in memory.
 In a vectored interrupt, the source that interrupts supply the branch information to the
computer. This information is called the interrupt vector.
 In some computers the interrupt vector is the first address of the I/O service routine.
 In other computers the interrupt vector is an address that points to a location in
memory where the beginning address of the I/O service routine is stored.

 In multiprocessor system, there are more than one processors, which requires control
of the system bus at a time.
 Hence an appropriate priority resolving mechanism is required, to decide which
processor should get control of bus.
 This is called bus arbitration.

Following three methods are used to resolve bus arbitration.

1) Daisy chain method :

 All bus master uses the same line for bus request.
 If the bus busy line is inactive, the bus controller gives the bus grant signal.
 Bus grant signal is propagated serially through all masters starting from nearest one.
 The bus master which requires system bus, stops this signal, activates the bus busy
line and takes control of system bus.
Advantages:
a) Simple design
b) Less no. of control lines.
Disadvantages:
 a) Priority depends on the physical location of master.
b) Propagation delays due to serially granting of bus.
c) Failure of one of the devices may fail entire system.

2) Parallel Priority

This technique uses an external priority encoder and decoder as shown in figure.
Each bus arbiter in the parallel scheme has a bus request output line and a bus acknowledge
input line.
When processor wants to access system bus at that time arbiter of that processor enables request
line. The processor takes control of the bus if it acknowledges input line is enabled.

Figure shows the request lines from four arbiters going into a 4 x 2 priority encoder.

The output of the encoder generates a 2-bit code, which represents the highest-priority unit
among those requesting the bus.

The 2-bit code from the encoder output drives a 2×4 decoder which enables the proper
acknowledge line to grant bus access to the highest-priority unit.

Advantage

Separate pair of bus request and bus grant signals, so it is faster.

Disadvantage

Require more bus request and grant signal.

 3) Independent request method

 All bus masters have their individual bus request and bus grant lines.
 The controller thus knows which master has requested, so bus is granted to that
master.
 Priorities of the masters are predefined so on simultaneous bus requests, the bus is
granted based on the priority, provided the bus busy line is not active.
 The controller consists of encoder and decoder logic for priorities.
Advantages:
a) Bus arbitration is fast.
b) Speed independent of no. of devices connected.
Disadvantages:
a) No. of control lines required is more. Hence connecting a large number of bus
masters is difficult.
 DMA(Direct Memory Access)

The data transfer between a fast storage media such as magnetic disk and memory unit is
limited by the speed of the CPU(MP). Thus, we can allow the peripherals directly
communicate with each other using the memory buses, removing the intervention of the CPU.
This type of data transfer technique is known as DMA or direct memory access.
During DMA the CPU is idle and it has no control over the memory buses. The DMA
controller takes over the buses to manage the transfer directly between the I/O devices and
the memory unit.
Bus Request: It is used by the DMA controller to request the CPU to relinquish the control
of the buses.

Bus Grant: It is activated by the CPU to Inform the external DMA controller that the buses
are in high impedance state and the requesting DMA can take control of the buses. Once the
DMA has taken the control of the buses it transfers the data. This transfer can take place in
many ways.

Types of DMA transfer using DMA controller:

The DMA transfers the data in three modes which include the following.

a) Burst Mode: In this mode DMA handover the buses to CPU only after completion of whole
data transfer. Meanwhile, if the CPU requires the bus it has to stay ideal and wait for data
transfer.
b) Cycle Stealing Mode: In this mode, DMA gives control of buses to CPU after transfer of
every byte. It continuously issues a request for bus control, makes the transfer of one byte and
returns the bus. By this CPU doesn’t have to wait for a long time if it needs a bus for higher
priority task.
c) Transparent Mode: Here, DMA transfers data only when CPU is executing the instruction
which does not require the use of buses.
 DMA CONTROLLER

DMA Controller is a hardware device that allows I/O devices to directly access memory with
less participation of the processor. DMA controller needs the same old circuits of an interface
to communicate with the CPU and Input/Output devices.
The unit communicates with the CPU through data bus and control lines. Through the use of
the address bus and allowing the DMA and RS register to select inputs, the register within
the DMA is chosen by the CPU. RD and WR are two-way inputs. When BG (bus grant) input
is 0, the CPU can communicate with DMA registers. When BG (bus grant) input is 1, the
CPU has relinquished the buses and DMA can communicate directly with the memory.

The DMA controller has three registers as follows.

 Address register – It contains the address to specify the desired location in
memory.
 Word count register – It contains the number of words to be transferred.
 Control register – It specifies the transfer mode.

Note –
All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the CPU
can both read and write into the DMA registers under program control via the data bus.

The CPU initializes the DMA by sending the given information through the data bus.
 The starting address of the memory block where the data is available (to read) or
where data are to be stored (to write).
 It also sends word count which is the number of words in the memory block to be
read or write.
 Control to define the mode of transfer such as read or write.
 A control to begin the DMA transfer.
 IOP(Input/Output Processor)
An input-output processor (IOP) is a processor with direct memory access capability. In this,
the computer system is divided into a memory unit and number of processors.

Each IOP controls and manage the input-output tasks. The IOP is similar to CPU except that
it handles only the details of I/O processing. The IOP can fetch and execute its own
instructions. These IOP instructions are designed to manage I/O transfers only.

The communication between the IOP and the devices is similar to the program control
method of transfer. And the communication with the memory is similar to the direct memory
access method.

In large scale computers, each processor is independent of other processors and any processor
can initiate the operation.

The CPU can act as master and the IOP act as slave processor. The CPU assigns the task of
initiating operations but it is the IOP, who executes the instructions, and not the CPU. CPU
instructions provide operations to start an I/O transfer. The IOP asks for CPU through
interrupt.

Instructions that are read from memory by an IOP are also called commands to distinguish
them from instructions that are read by CPU. Commands are prepared by programmers and
are stored in memory. Command words make the program for IOP. CPU informs the IOP
where to find the commands in memory.
 COMMUNICATION MODES (TRANSMISSION MODES)
o The way in which data is transmitted from one device to another device is known
as transmission mode.
o The transmission mode is also known as the communication mode.
o Each communication channel has a direction associated with it, and transmission media
provide the direction. Therefore, the transmission mode is also known as a directional
mode.
o The transmission mode is defined in the physical layer.
The Transmission mode is divided into three categories:

o Simplex mode
o Half-duplex mode
o Full-duplex mode
  Simplex mode

o In Simplex mode, the communication is unidirectional, i.e., the data flow in one
direction.
o A device can only send the data but cannot receive it or it can receive the data but cannot
send the data.
o This transmission mode is not very popular as mainly communications require the two-
way exchange of data. The simplex mode is used in the business field as in sales that
do not require any corresponding reply.
o The radio station is a simplex channel as it transmits the signal to the listeners but never
allows them to transmit back.
o Keyboard and Monitor are the examples of the simplex mode as a keyboard can only
accept the data from the user and monitor can only be used to display the data on the
screen.
o The main advantage of the simplex mode is that the full capacity of the communication
channel can be utilized during transmission.
Advantage of Simplex mode:
o In simplex mode, the station can utilize the entire bandwidth of the communication
channel, so that more data can be transmitted at a time.
Disadvantage of Simplex mode:
o Communication is unidirectional, so it has no inter-communication between devices.

 Half-Duplex mode

o In a Half-duplex channel, direction can be reversed, i.e., the station can transmit and
receive the data as well.
o Messages flow in both the directions, but not at the same time.
 o The entire bandwidth of the communication channel is utilized in one direction at a
time.
o In half-duplex mode, it is possible to perform the error detection, and if any error occurs,
then the receiver requests the sender to retransmit the data.
o A Walkie-talkie is an example of the Half-duplex mode. In Walkie-talkie, one party
speaks, and another party listens. After a pause, the other speaks and first party listens.
Speaking simultaneously will create the distorted sound which cannot be understood.
Advantage of Half-duplex mode:
o In half-duplex mode, both the devices can send and receive the data and also can utilize
the entire bandwidth of the communication channel during the transmission of data.
Disadvantage of Half-Duplex mode:
o In half-duplex mode, when one device is sending the data, then another has to wait, this
causes the delay in sending the data at the right time.

 Full-duplex mode

o In Full duplex mode, the communication is bi-directional, i.e., the data flow in both the
directions.
o Both the stations can send and receive the message simultaneously.
o Full-duplex mode has two simplex channels. One channel has traffic moving in one
direction, and another channel has traffic flowing in the opposite direction.
o The Full-duplex mode is the fastest mode of communication between devices.
o The most common example of the full-duplex mode is a telephone network. When two
people are communicating with each other by a telephone line, both can talk and listen
at the same time.
Advantage of Full-duplex mode:
o Both the stations can send and receive the data at the same time.
Disadvantage of Full-duplex mode:
o If there is no dedicated path exists between the devices, then the capacity of the
communication channel is divided into two parts.
Data transfer can happen in two ways. They are-

 Serial communication
 Parallel communication

 SERIAL COMMUNICATION
Serial communication is a technique used to send data bit by bit using a two-wires i.e.
transmitter (sender) and receiver.

Serial communication is the process of sequentially transferring the information/bits on the

same channel. Due to this, the cost of wire will be reduced, but it slows the transmission speed.

Generally, communication can be described as the process of interchanging information

between individuals in the form of audio, video, verbal words, and written documents.

The serial protocol is run on every device that can be our mobile, personal computers, and
many more with the help of following some protocols. The protocol is a type of reliable and
secure form of communication that contains a set of rules addressed with the help of a source
host and a destination host.

In serial communication, binary pulses are used to show the data. Binary contains the two
numbers 0 and 1. 0 is used to show the LOW or 0 Volts, and 1 is used to show the HIGH or 5
Volts.

The serial communication can either be asynchronous or synchronous.

Synchronous Communication

In synchronous communication, the frames or data will be constructed with the help of
combining the groups of bits. That frames will be continuously sent in time with a master clock.
It uses a synchronized clock frequency to operate the data of sender or receiver.

In synchronous communication, there is no need to use the gaps, start bits and stop bits. The
time taken by the sender and receiver is synced that's why the frequency of timing error will
be less, and the data will move faster.

On the basis of the timing being synced correctly between the sender and receiver devices, the
data accuracy is totally dependent.
The synchronous serial transmission is more expensive as compared to asynchronous serial
transmission.

Asynchronous Communication

In asynchronous communication, the groups of bits will be treated as an independent unit,

and these data bits will be sent at any point in time.

In order to make synchronization between sender and receiver, the stop bits and start bits are
used between the data bytes. These bits are useful to ensure that the data is correctly sent.

The time taken by data bits of sender and receiver is not constant, and the time between
transmissions will be provided by the gaps.

In asynchronous communication, we don't require synchronization between the sender and

receiver devices, which is the main advantage of asynchronous communication.

This method is also cost-effective. In this method, there can be a case when data transmission
is slow, but it is not compulsory, and it is the main disadvantage of the asynchronous method.

 Parallel Communication

There is another type of communication known as parallel communication, which is described

as follows:
Parallel communication is used to transmit a huge amount of data signals simultaneously on
the different channels within the same radio path or cable at a time. It is used to comprise a
huge amount of wired channels in parallel. In parallel communication, the data transfer between
sender and receiver is done with the help of multiple channels. The data bus in the parallel
devices is wider as compared to the serial devices. That's why it can transfer the data from
source to destination at a time. The parallel transmission bit rate is higher as compared to the
serial transmission bit rate.

The costs of multiple wires are higher as compared to the single wire. The parallel cable gets
longer that's why it requires a high cost. If the distance is larger, synchronization timing
between more than one channel becomes more sensitive. A constant clocking signal is used to
provide the timing in parallel communication. The signal is sent with the help of a separate
wire within the parallel cable. So we can say parallel communication is synchronous.

Advantages of Serial communication over Parallel communication

Mostly people have a misconception that the parallel ports/buses are faster than the serial
ports/buses because, in serial communication, the data transmission is only a bit per unit of
time. Even the parallel buses will be clocked considerably at a slower rate as compared to the
serial buses. There are various factors that are used to specify that serial communication is
better than parallel communication, which is described as follows:

No Clock Required: If there is a case of the asynchronous and unclocked type of serial
communication, the problem related to the clock skew between channels will not exist.

Need less Space: At the time of configuration of serial communication, it needs less amount
of space because the serial connection needs less amount of cable. Hence because of this
feature, we will have an additional space, which can be used to provide better isolation of data
lanes/channels from the components of neighbouring communication.

No Cross Talks: The serial communication contains fewer amounts of conductors in the
nearby space. That's why the possibility of cross-talk is rare.

Low cost: The serial communication contains the serial link. The cost of this link is less than
the parallel link.