Notes By Prof.

Tanya Shrivastava

UNIT – 1

COMPUTER ORGANIZATION AND ARCHITECTURE

 COMPARE COMPUTER ORGANIZATION AND COMPUTER ARCHITECTURE

S.
No. Computer Architecture Computer Organization

Architecture describes what the

The Organization describes how it does it.
1. computer does.

Computer Architecture is concerned

Computer Organization is concerned with the
with the way hardware components
structure and behavior of a computer system as
are connected together to form a
seen by the user.
2. computer system.

It act as an interface between It deals with the components of a connection in a

3. hardware and software. system.

While designing a computer system An organization is done on the basis of

4. architecture is considered first. architecture.

Computer Architecture deals with the

Computer Organization deals with a structural
functional behavior of computer
relationship.
5. systems.

6. It deals with high-level design issues. It deals with low-level design issues.

7. Architecture indicates its hardware. Whereas Organization indicates its performance.

As a programmer, you can view

The implementation of the architecture is called
architecture as a series of instructions,
organization.
8. addressing modes, and registers.

For designing a computer, its For designing a computer, an organization is decided

9. architecture is fixed first. after its architecture.

Computer Architecture is also called Computer Organization is frequently called

10. Instruction Set Architecture (ISA). microarchitecture.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

S.
No. Computer Architecture Computer Organization

Computer Architecture comprises

logical functions such as instruction Computer Organization consists of physical units like
sets, registers, data types, and circuit designs, peripherals, and adders.
11. addressing modes.

It makes the computer‟s hardware

It offers details on how well the computer performs.
12. visible.

Organizational qualities include hardware elements

Examples- Intel and AMD created the
that are invisible to the programmer, such as
x86 processor. Apple, IBM, and
interfacing of computer and peripherals, memory
Motorola created the PowerPC.
13. technologies, and control signals.

 FUNCTIONAL UNITS OF DIGITAL SYSTEM AND THEIR

INTERCONNECTIONS

 A general-purpose computer system is the best-known example of a digital system.

 The basic functional components or elements of a digital computer system basically the hardware and
software. The hardware is the physical component/part such as a keyboard, mouse, monitor, etc. The
software is the set of programs and instructions which perform several specific operations.
 Both hardware and software together act as functional components. They help to complete the
functional cycle which consists of input, processing, and output. Let us learn about the different
functional components of a digital computer and their working and interconnections. Let us study the
basic components of a computer.
 A computer consists of six main components namely, Input unit, Central Processing Unit, Memory
unit Arithmetic & Logical unit, Control unit and an Output unit.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Input Unit:
 The input unit consists of input devices that are attached to the computer.
 Input refers to any information or data that is sent to a computer for processing.
 A computer will only respond when a command is given to the device and these commands can
be given using the input unit or the input devices.
 Input devices are: Keyboard (querty keyboard, wired keyboard, wireless keyboard, mechanical
keyboard, numeric keyboard, ergonomic keyboard, Bluetooth keyboard, magic keyboard, backlit
keyboard, gaming keyboard, membrane keyboard, chiclet keyboard, wireless laser keyboard
etc.), Mouse (wired mouse, wireless mouse, Bluetooth mouse, trackball mouse, laser mouse,
magic mouse, USB mouse, gaming mouse, vertical mouse etc.), Scanner, Light Pen, OMR,
MICR, OCR, Bar Code Reader, Joysticks, touch screen, Camera, Mic etc.
Question: Explain any four input devices.

Output Unit:
 When we command a computer to perform a task, then computer process that commands and
gives us a result. This result is called output.
 The output of a computer is the information that it displays on a screen or prints on paper as a
result.
 There is various output devices connected to the computer. The most basic of which is a
monitor. Whatever we write using a keyboard or click using a mouse, is all displayed on the
monitor.
 Output devices are: Monitor (also known as VDU, Visual Display Unit), Projector, Speaker
and Printer etc.
Question: Explain any four output devices.

Control Unit:
 Control unit is used to control the signals.
 The control unit is also known as the nerve center of a computer system.
 The control unit controls and monitors communications between the hardware attached to the
computer. It controls the input and output of data, checks that signals have been delivered
successfully, and makes sure that data goes to the correct place at the correct time.
 It tells the computer's memory, arithmetic/logic unit and input and output devices how to
respond to a program's instructions.
Memory Unit:
 When we enter the data into the computer using an input device, the entered information
immediately gets saved in the memory unit of the Central Processing Unit (CPU).
 Also known as storage unit, the Memory Unit transmits the data further to the other parts of the
CPU.
 Similarly, when the output of our command is processed by the computer, it is saved in the
memory unit before giving the output to the user.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Arithmetic & Logic Unit:

 As the name suggests, all the mathematical calculations or arithmetic and logical operations are
performed in the Arithmetic and Logical Unit of the CPU.
 Arithmetic Unit: Like Addition, Subtraction, Multiplication and Division.
 Logical unit: Like AND, OR, NOT, NOR, NAND gate, less than, greater than etc.

CPU:
The Central Processing Unit is the core of any computer devices. It is also known as the “Brain of
Computer” and no action can be conducted by a device without the execution and permission of the
Central Processing Unit. It comprises three major components:

 Memory Unit
 Control Unit
 Arithmetic and Logical Unit

All these 3 units are elements of CPU and together help in the efficient working and processing of data.

Interconnection between Functional Components: After learning about the functional

components we will learn about their interconnections. The functional components usually use bus
architecture for communication. A bus is a collection of wires used for the communication of different parts
of a computer. Further, it uses electric signals to pass the data and information.

Fig. Bus Architecture

Different Types of Buses are:

Data Bus: The data bus is bidirectional. The data bus is used to communicate or send the data from
one part to another.
Address Bus: The address bus is unidirectional. The address bus is used to communicate the address of
the given data and instructions.
Control Bus: The control bus is unidirectional. The control bus is used to control the signals between
different devices.
Therefore, in conclusion, we can say that these functional components communicate through this bus
architecture. The input device takes the input, then the data is processed and the output devices display the
results. Besides, the system bus performs all the communication that the cycle involves.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 BUS
A bus is a collection of small wires and a communication system that transfers data between the
internal components of the computer or between the computers.
A bus is a collection of wires used for the communication of different parts of a computer. Further, it uses
electric signals to pass the data and information.

 BUS ARCHITECTURE

 Fig. Bus Architecture

 TYPES OF BUSES
Data Bus: The data bus is bidirectional. The data bus is used to communicate or send the data from
one part to another.
Address Bus: The address bus is unidirectional. The address bus is used to communicate the address of
the given data and instructions.
Control Bus: The control bus is unidirectional. The control bus is used to control the signals between
different devices.

 BUS ARBITRATION
 It is deciding who get access to the bus for reading or writing for any transaction called Bus
Arbitration.
 A multiple devices may need to use the bus at the same time, so the bus has to decide which device
has to be handed the bus first.
 The Bus Arbitration is a Master which is going to decide which device will served first, only one
device can be served one at a time. Means in a figure there is a single bus line in which several
devices are connected, so with the help of bus arbitration, the bus will decide which device will be
served first, or the bus decide in which device data will be send first.
 A device that initiates data transfers on the bus at any given time is called a Bus Master.

BUS

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

 Bus arbitration is a process by which next device becomes the bus controller by transferring bus
master ship to another bus.
 Bus arbitration is needed to resolve conflicts when two or more devices want to become the bus
master at the same time. In short, arbitration is the process of selecting the next bus master from
among multiple candidates.
 Bus arbitration scheme usually try to balance two properties:
 Bus priority – highest priority device will be served first after the lowest priority device.
 Fairness – fairness means whether it is giving services to all the devices or not.

There are 3 Arbitration mechanism / 3 types of Bus Arbitration:

1. Daisy Chain Bus Arbitration

2. Polling Bus Arbitration
3. Independent Request

1. Daisy Chain Mechanism

The deciding can be done by only the Master, every system will only have one Master in case of Daisy
Chain, according to the priority bus master will send the data and here only one Master is there:
Highest Priority Lowest Priority

BUS Device 1 Device 2 Device 3

GRANT
REQUEST

Releases

BUS Bus Request

MASTER
Bus Busy

 Whenever the bus is free the Device can make a Bus Request with the Bus Master.
 Bus Request is send to the bus master.
 Bus master will send the data to the highest priority Device first.
 Now in Case of Daisy chain one by one Device can be served, here Device 1 has the highest
priority and Device 3 has the lowest priority.
 Now the Highest Priority Device will make the Bus Request first, means Device 1 will make
the bus request to the Bus Master. (Device 1 sense that bus is free, so it will make a request)
 So the Bus Master will send the Bus Grant Request to the Device 1, and it will send the Busy
Signal, now the bus is busy so „NO‟ other Devices will send the bus request to the Bus Master.
 After the work is over of Device 1 it releases the Bus, now the bus is free.
 Whenever the bus is free only then other Devices will make the Bus Request with the Bus
master.
 When the bus is free then Device 2 will make the bus request to the bus master. After the work
of Device 2 is over it releases the bus then Device 3 will make the bus request with the bus
master.
 So this is a Daisy Chain Process one after other.

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

Advantages:
 Simplicity and Scalability.
 The user can add more devices anywhere along the chain, up to a certain maximum
value.
Disadvantages:
 The value of priority assigned to a device depends on the position.
 Propagation delay arises in this method. Means last devices will receive the data late,
last device is waiting for the data.
 Slower, time taken.
 If one device fails then the entire system will stop working.

2. Polling Mechanism
Here the Bus Master decides which Device has to be served first. The priority of the Devices is decided
by the bus master. Here 3 lines are present one is for Bus Request, one is for Bus Busy and one is for
Polling.

Device 1 Device 2 Device 3

BUS GRANT
REQUEST

Releases

BUS Bus Request

MASTER
Bus Busy
ID ID ID
Polling

 Whenever the bus is free Device will make the Bus Request from the Bus Master.
 So if bus is not busy the device will make the request.
 The master decides by checking each device which is having the highest priority by placing the
Device ID’s on polling line. So each Device will have only one ID. ID‟s will be decided by bus
master.
Suppose:
Device 1 ID is 8
Device 2 ID is 4
Device 3 ID is 6
 Now in Case of Polling, the data will send to the highest priority and the priority will be set
according to the ID‟s.
 Now the Highest Priority Device will make the Bus Request first, means Device 2 will make the
bus request to the Bus Master, because the ID of Device 2 is 4.
 So the Bus Master will send the Bus Grant Request to the Device 2, and it will send the Busy
Signal, now the bus is busy so „NO‟ other Devices will send the bus request to the Bus Master.
 After the work is over of Device 2 it releases the Bus, now the bus is free.
 Whenever the bus is free only then other Devices will make the Bus Request with the Bus
master.

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

 When the bus is free then Device 3 will make the bus request to the bus master because the ID
of Device 3 is 6. After the work of Device 3 is over it releases the bus, then Device 1 will make
the bus request with the bus master because the ID of Device 1 is 8.
 So this is a Polling the data will be send is depending on various ID‟s.

Advantages:
 This method does not favor any particular device and processor.
 The method is also quite simple.
 If one device fails then the entire system will not stop working.
Disadvantages:
 Adding more than one bus masters is difficult also increases the number of poll lines of the
circuit.
 Polling delay. (Last device has to wait for data)

3. Independent Request Mechanism

Each device sends the request independently to the bus master. Here R1, R2, R3 is the Request and
BGR is the Bus Grant Request.

BGR

BGR
Device 1 Device 2 Device 3

BGR

Releases
R1
BUS R2
MASTER
R3

Bus Busy
 Whenever the bus is free Device will make the Bus Request from the Bus Master.
 Suppose the bus is free and if Device 3 will make the bus request first, so the bus master will send
the Bus Grant Request to the Device 3 first, and send the busy signal. After the work of Device 3
will be done it releases the bus.
 After that another device will request for the bus suppose Device 1, so bus master will send the Bus
Grant signal to the Device 1, and the work of Device 1 is completed so it will release the bus.
 In case of Independent Request Mechanism all the devices randomly ask for the Bus request to the
Bus Master. But the limitation is when the bus is busy bus master could not receive the request of
other devices; bus master can only receive the request when the running device will release the bus
or the bus is free.
Advantages:
 This method generates a fast response.
Disadvantages:
 Hardware cost is high as a large no. of lines or wires is required.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

REGISTER, BUS AND MEMORY TRANSFER

 REGISTER

What is Register?

Registers:

 Register is an electronic component that is used to hold the information as bits.

 Register are used by processor (CPU) to store small amount of data.
 A register can be 2 bit register, 4 bit register, 8 bit register, 16 bit register,
32 bit register, 64 bit register etc.
 Register provides fast execution, fast accessing, fast fetching.
 CPU is a fast processor because it contains registers that provides fast speed.
 Register is a collection of various flip-flops.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 Flip flop means a single cell that is capable to store a single bit.
 1 cell stores 1 bit.
 1 cell = 1 flip-flop
Example: this 8 bit register contains 8 cells or we can say 8 flip-flops.

1 0 1 1 0 1 0 0
Types of Registers are:

 Program Counter (PC)

 Memory Address Register (MAR)
 Memory Data Register (MDR)/Memory Buffer Register (MBR)
 Instruction Register (IR)
 Accumulator (AC)
 Input Register (INPR)
 Output Register (OUTR)
 Temporary Register (TR)

Program Counter (PC)

 Program counter is a register in the CPU.
 Program counter is also known as digital counter.
 Controls sequence of instructions.
 A program counter is a register in the CPU containing the address of the next instruction to be
executed from memory.
 It holds the address of the memory/RAM. Address of RAM like – 0,1,2,3 etc.

Memory Address Register (MAR)

 MAR is a register in the CPU it contains address of the memory or RAM.

 Stores memory address/RAM address.
 The memory/RAM address store in the program counter (0, 1, 2, 3 etc.) is copied into the MAR
(0, 1, 2, 3 etc.).

Memory Data Register (MDR)/Memory Buffer Register (MBR)

 MDR/MBR is a register in the CPU. Stores and process the memory.

 Memory Data Register also known as Memory Buffer Register.
 It is used to hold the contents of the memory/RAM. Contents like – Load 4, ADD 5, Store 6
these are the contents of the RAM.
 The main purpose of MDR is: if a CPU contains a 4-bit register and we have data of 100 bits, so
MDR converts the 100 bits data into 4-4 bits, and then it will be executed. (Split large data into
small pieces).

Instruction Register (IR)

 The memory content store in the MDR is copied into the Instruction Register (IR).

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 It is used to store the instructions like LOAD, ADD, SUB, DIV, MUL, STORE, MOV, EXE etc.
 Instruction Register (IR) is also known as Current Instruction Register (CIR).

Accumulator (AC)

 It contains results.
 It is used to perform calculations. For Ex. 3+6=9.
 It is processor register used for processing.

Input Register (INPR): Carries input character.

Output Register (OUTR): Carries output character.

Temporary Register (TR): It holds temporary data.

 REGISTER TRANSFER / REGISTER TRANSFER LANGUAGE (RTL)

Register Transfer: The information transformed from one register to another register is represented
in symbolic form by replacement operator is called Register Transfer.
Replacement Operator:

In the statement, R2 R1, acts as a replacement operator. This statement defines the transfer of
content of register R1 into register R2.

Register Transfer Language (RTL): Register Transfer Language (RTL) means the symbolic
language is used to transfer the data from one place to another is known as Register Transfer
Language. Now another meaning of RTL means Right To Left, means data is always transfer from
right to left. For example R2 R1, the data of R1 register is transfer to the R2 register from right to
left.

There are various methods of RTL –

1. General way of representing a register is by the name of the register enclosed in a rectangular box
as shown in (a).
2. Register is numbered in a sequence of individual bits as shown in (b).
3. The numbering of bits in a register can be marked on the top of the box as shown in (c).
4. A 16-bit register PC is divided into 2 parts- Bits (0 to 7) are assigned with lower byte of 16-bit
address and bits (8 to 15) are assigned with higher bytes of 16-bit address as shown in (d).

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Basic symbols of RTL:

Symbol Description Example

Letters and
Denotes a Register MAR, R1, R2
Numbers

R1(8-bit) it shows register is of 8 bits

R1(0-7) it shows lower byte of register
( ) parenthesis Denotes a part of register
R1 (L) it shows left side of register or
higher byte of register 8-15.

arrow Denotes a transfer of information R2 <- R1

Specify two micro-operations of R1 <- R2 , R2 <- R1

,
Register Transfer

P : R2 <- R1
: Denotes conditional operations
if P=1

Naming Denotes another name for an

Ra := R1
Operator (:=) already existing register/alias

Register Transfer Operations:

The operation performed on the data stored in the registers is referred to as register transfer
operations. There are different types of register transfer operations:
1. Simple Transfer – R2 R1
The content of R1 is copied into R2 without affecting the content of R1. It is a simple type of
transfer operation. R2 R1.

2. Conditional Transfer –
It indicates that if P=1, then the content of R1 is transferred to R2. It is a unidirectional
operation. If P=1 then R2 R1
3. Simultaneous Operations –
If 2 or more micro operations are to occur simultaneously (means at the same time) then they
are separated with comma (,). Like R1 <- R2, R2 <- R1

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

 REGISTER USED IN IAS COMPUTER

The IAS computer was named for the Institute for Advanced Study in Princeton, N.J., where it
was developed. Work on the IAS was begun in 1946 and completed in 1952.

 The IAS computer was the first to store the program in the same memory as the data.
 The logic of the IAS machine was implemented with vacuum tubes.
 The memory of the IAS machine was implemented with cathode ray tubes.
 The word size is 40 bits.
 Memory is word addressed (not byte addressed.)
 Numbers were stored as fractions, not as integers.

The IAS machine has 7 registers: Accumulator, Arithmetic Register, Control Counter, Control
Register, Function Table Register, Memory Address Register, Selectron Register.

Accumulator: used to store the results or to perform calculations.

Arithmetic Register: used to perform arithmetic operations like addition, subtraction, multiplication
and division etc.

Control Counter: also known as CNTCR.

- it enables the counter
- controls the counter frequency
- And controls counter behaviour during debug.

Control Register: A control register is a processor register that changes or controls the general
behaviour of a CPU or other digital device.

Function Table Register: describes a function by displaying inputs and outputs in tabular form.

Memory Address Register: MAR is a register in the CPU it contains address of the memory.

Selectron Register: the current data value being read from or written to memory.

 VON-NEUMANN COMPUTER ARCHITECTURE OR ISA

The basic structure is like this:

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

It is also known as ISA (Instruction set architecture) computer it contains:

1. The Central Processing Unit (CPU): Memory unit, Control unit, ALU, Registers.
3. The Input/output Devices

Let’s consider them in detail.

CPU:
The Central Processing Unit is the core of any computer devices. It is also known as the “Brain of
Computer” and no action can be conducted by a device without the execution and permission of the
Central Processing Unit. It comprises four major components:

 Memory Unit
 Control Unit
 Arithmetic and Logical Unit
 Registers

All these 4 units are elements of CPU and together help in the efficient working and processing of data.

Control Unit:
 Control unit is used to control the signals.
 The control unit is also known as the nerve center of a computer system.
 The control unit controls and monitors communications between the hardware attached to the
computer. It controls the input and output of data, checks that signals have been delivered
successfully, and makes sure that data goes to the correct place at the correct time.
 It tells the computer's memory, arithmetic/logic unit and input and output devices how to
respond to a program's instructions.
Memory Unit:
 When we enter the data into the computer using an input device, the entered information
immediately gets saved in the memory unit of the Central Processing Unit (CPU).
 Also known as storage unit, the Memory Unit transmits the data further to the other parts of the
CPU.
 Similarly, when the output of our command is processed by the computer, it is saved in the
memory unit before giving the output to the user.
Arithmetic & Logic Unit:
 As the name suggests, all the mathematical calculations or arithmetic and logical operations are
performed in the Arithmetic and Logical Unit of the CPU.
 Arithmetic Unit: Like Addition, Subtraction, Multiplication and Division.
 Logical unit: Like AND, OR, NOT, NOR, NAND gate, less than, greater than etc.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Bus
A bus is a collection of small wires and a communication system that transfers data between the
internal components of the computer or between the computers.
A bus is a collection of wires used for the communication of different parts of a computer. Further, it uses
electric signals to pass the data and information.
Types of buses
Data Bus: The data bus is bidirectional. The data bus is used to communicate or send the data from
one part to another.
Address Bus: The address bus is unidirectional. The address bus is used to communicate the address of
the given data and instructions.
Control Bus: The control bus is unidirectional. The control bus is used to control the signals between
different devices.

Registers:

 Register is an electronic component that is used to hold the information as bits.

 Register are used by processor (CPU) to store small amount of data.
 A register can be 2 bit register, 4 bit register, 8 bit register, 16 bit register,
32 bit register, 64 bit register etc.
 Register provides fast execution, fast accessing, fast fetching.
 CPU is a fast processor because it contains registers that provides fast speed.
 Register is a collection of various flip-flops.
 Flip flop means a single cell that is capable to store a single bit.
 1 cell stores 1 bit.
 1 cell = 1 flip-flop
Example: this 8 bit register contains 8 cells or we can say 8 flip-flops.

1 0 1 1 0 1 0 0

Types of Registers are:

 Program Counter (PC)

 Memory Address Register (MAR)
 Memory Data Register (MDR)/Memory Buffer Register (MBR)
 Instruction Register (IR)
 Accumulator (AC)
 Input Register (INPR)
 Output Register (OUTR)
 Temporary Register (TR)

Program Counter (PC)

 Program counter is a register in the CPU.
 Program counter is also known as digital counter.
 Controls sequence of instructions.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 A program counter is a register in the CPU containing the address of the next instruction to be
executed from memory.
 It holds the address of the memory/RAM. Address of RAM like – 0,1,2,3 etc.

Memory Address Register (MAR)

 MAR is a register in the CPU it contains address of the memory or RAM.

 Stores memory address/RAM address.
 The memory/RAM address store in the program counter (0, 1, 2, 3 etc.) is copied into the MAR
(0, 1, 2, 3 etc.).

Memory Data Register (MDR)/Memory Buffer Register (MBR)

 MDR/MBR is a register in the CPU. Stores and process the memory.

 Memory Data Register also known as Memory Buffer Register.
 It is used to hold the contents of the memory/RAM. Contents like – Load 4, ADD 5, Store 6
these are the contents of the RAM.
 The main purpose of MDR is: if a CPU contains a 4-bit register and we have data of 100 bits, so
MDR converts the 100 bits data into 4-4 bits, and then it will be executed. (Split large data into
small pieces).

Instruction Register (IR)

 The memory content store in the MDR is copied into the Instruction Register (IR).
 It is used to store the instructions like LOAD, ADD, SUB, DIV, MUL, STORE, MOV, EXE etc.
 Instruction Register (IR) is also known as Current Instruction Register (CIR).

Accumulator (AC)

 It contains results.
 It is used to perform calculations. For Ex. 3+6=9.
 It is processor register used for processing.

Input Register (INPR): Carries input character.

Output Register (OUTR): Carries output character.

Temporary Register (TR): It holds temporary data.

INPUT/OUTPUT Devices:

I/O devices are the pieces of hardware used by a human (or other system) to communicate with a
computer. For instance, a keyboard or computer mouse is an input device for a computer, while
monitors and printers are output devices.

Hence this is a Von-Neumann Computer Architecture Or ISA.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 MEMORY TRANSFER / MEMORY TRANSFER MICROOPERATIONS

Memory Transfer means reading data from memory or writing data in to memory.

Memory transfers simply mean to a transfer from a specific location of memory to a register. However a
memory transfer can be either ways. It can work either from Memory to Register or from Register to
Memory. Memory is designated by the letter “M”. The Address register contains address is designated
by AR or MAR (memory address register) and data register contains data is designated by DR.

 A transfer from Memory to Register is called READ operation.

 A transfer from Register to Memory is called WRITE operation.

Memory Read Operation: A memory read operation first searches for a location in the memory and
then transfers the value located at that location to a register. Ex.: with the help of figure and micro
operations.

Memory Write Operation: A memory write operation simply extracts data from a register
and transfers it to a memory location. Ex.: with the help of figure and micro operations.

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

 BUS TRANSFER
 A bus transfer is the most effective method to send data by using a common bus system.
 Now to transfer the data between registers we don‟t use thousands of wires, instead of
thousands wires we just use single common BUS system.

The two methods that can be used in Bus transfer are as follows −

1. Using multiplexer
2. Using three states bus buffers

1. Using Multiplexer: Multiplexer allow the process of transmitting different type of data such as audio
video at the same time using a single transmission line.

 Multiplexer: means multiple inputs but single output. Also known as MUX.
 DE multiplexer: means single input but multiple outputs. Also known as DEMUX.

The following block diagram shows a Bus system for four registers each register is of 4 bits. It is
constructed with the help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and
two selection inputs (S1 and S2).

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 If the no. of multiplexers is 4 then the bits of registers is also 4.

 If the size of multiplexer is 4 bit then size of registers is also 4 bit.
 4*1 means: 4 inputs and 1 output.

Here,
A0, B0, C0, D0 connected with MUX 0.
A1, B1, C1, D1 connected with MUX 1.
A2, B2, C2, D2 connected with MUX 2.
A3, B3, C3, D3 connected with MUX 3.

The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers. The
selection lines choose the four bits of one register and transfer them into the four-line common bus.

The following function table shows the register that is selected by the bus for each of the four possible
binary values of the Selection lines.

If the selection lines is 00 like S1=0 or S0=0 so all the multiplexers provides 0 output.

A0=0 (MUX 0) B0=0 (MUX 0)

A1=0 (MUX 1) B1=0 (MUX 1)

A2=0 (MUX 2) B2=0 (MUX 2)

A3=0 (MUX 3) B3=0 (MUX 3)

 If S1=0 and S0=0 then A0, A1, A2, A3 = 00 = 0 (Register A)

 If S1=0 and S0=1 then B0, B1, B2, B3 = 01 = 1 (Register B)
 If S1=1 and S0=0 then C0, C1, C2, C3 = 10 = 2 (Register C)
 If S1=1 and S0=1 then D0, D1, D2, D3 = 11 = 3 (Register D)

Extra Example: Explanation of 8×1 Multiplexer

If the register size is 8 Bit and there are four registers then a connection to the common bus is shown in
the following diagram.

As there are 4 registers. So, No. of inputs to each multiplexer is 4 and the total no of bits in each register
is 8. So, the total multiplexer will be 8. As there are four registers, two select lines (two bits) are enough
to represent these four registers.

No. of bits in a register is equal to no. of multiplexers.

For example:
 8 bit Register = 8 multiplexers
 16 bit register = 16 multiplexers
 4 bit register = 4 multiplexers

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

8×1 Multiplexer with Example

Let‟s suppose, when S1S0= 11 then Register D will activate and 1 output from each multiplexer of
Register D to the common bus is shown in the following diagram.

Question: How do registers communicate with each other through a common bus?
Answer: We connect all registers with a common bus through the multiplexers.

Note: If a common bus has 8 registers of 16 bits then it requires 16 multiplexers. Each multiplexer will
contain eight data input lines and three selection lines (S2, S1, and S0).

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

2. Using three states bus buffers

 It is a digital circuit that has 3 gates.

 The most commonly gate used in 3 state bus buffers is buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

Control Input C

 1st state is 1/0.

 2nd state is, if C = 1
 3rd state is, if C = 0, that is High Impedance, high impedance means it doesn‟t produce any output or no
circuit.
If C = 1 then Y = A
If C = 1 and A = 1 then Y = 1
If C = 0, then there is no output, high impedance.

One Line
Common Bus
System

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o In 2*4 decoder, 2 is the no. of selection inputs and 4 is the no. of outputs
o Formula of the Decoder is to select no. of input and output lines: N * 2N

For example:

2 * 22 = 2 * 4 means 2 selection inputs S1 S0 and 4 outputs

3 * 23 = 3 * 8 means 3 selection inputs S2 S1 S0 and 8 outputs
The following function table shows the register that is selected by the bus for each of the four
possible binary values of the Selection lines.
In case of 00 the state A will be active, and rest B C D is 0.
In case of 01 the state B will be active, and rest A C D is 0.
In case of 10 the state C will be active, and rest A B D is 0.
In case of 11 the state D will be active, and rest A B C is 0.

Q. Numerical based on 3 state buffers: Using Tri State buffer & decoder construct bus system to transfer
bus information from 4 register. Each register is of 4 bit wide.

Solution: Let‟s take four register A B C D of size 4 bits. Decoder = 2*22 = 2*4, 2 means 2 selection
inputs S1 S0 and 4 means no. of output lines.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 PROCESSOR ORGANIZATION

Also explain all the terms of the processor organization figure:

Like ALU, Registers, Control unit, System bus or BUS, Control Bus, Data Bus, Address bus.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 GENERAL REGISTER ORGANIZATION

A set of flip-flops forms a register. A register is a unique high-speed storage area in the CPU.

If a CPU includes some registers, therefore a common bus can link these registers. A general
organization of seven CPU registers is displayed in the figure.

The CPU bus system is managed by the control unit. The control unit explicit the data flow through the
ALU by choosing the function of the ALU and components of the system.

Consider R1 ← R2 + R3, the following are the functions implemented within the CPU −

MUX A Selector (SELA) − It can place R2 into bus A.

MUX B Selector (SELB) − It can place R3 into bus B.

ALU Operation Selector (OPR) − It can select the arithmetic addition (ADD).

Decoder Destination Selector (SELD) − It can transfers the result into R1.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

The 14-bit control word defines a micro-operation. The encoding of register selection fields is specified
in the table. Encoding of Register Selection Field

Binary Code SELA SELB SELD

000 Input Input None

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7

There are several micro-operations are implemented by the ALU. Few of the operations implemented
by the ALU are displayed in the table. Encoding of ALU Operations

OPR Select Operation Symbol

00000 Transfer A TSFA

00001 Increment A INCA

00010 Add A + B ADD

00101 Subtract A - B SUB

00110 Decrement A DECA

01000 AND A and B AND

01010 OR A and B OR

01100 XOR A and B XOR

01110 Complement A COMA

10000 Shift right A SHRA

11000 Shift left A SHLA

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

There are some ALU micro-operations are shown in the table.

ALU Micro-Operations

Micro-operation SELA SELB SELD OPR Control Word

R1 ← R2 – R3 R2 R3 R1 SUB 010 011 001 00101

R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010

R6 ← R6 + R1 R6 R1 R6 INCA 110 000 110 00001

R7 ← R1 R1 - R7 TSFA 001 000 111 00000

Output ← R2 R2 – None TSFA 010 000 000 00000

Output ← Input Input - None TSFA 000 000 000 00000

R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000

R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

 STACK ORGANIZATION

 Stack organization refers to a computer architecture where memory is managed in a Last-In-

First-Out (LIFO) structure.
 Stack organization is a fundamental concept in computer architecture and programming that
involves the management of memory using a Last-In-First-Out (LIFO) data structure.

Two operations of stack organization are:

 PUSH
 POP
SP
Stack's operations are:
SP
 Push: Adds an item to the top of the stack
 Pop: Removes one item from the stack's top

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

DR (Data
Register)
D,E,F DR (Data
Register)
SP C,D,E,F

SP

MEMORY STACK M[SP]

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

Here, in case of push

operation, stack is
continuously
decrementing. Ex.
4001, 4000, 3999
etc. So, SP <- SP-1

Here, in case of pop

operation, stack is
continuously
incrementing. Ex.
3999, 4000, 4001
etc. So, SP <- SP+1

 ADDRESSING MODES
Addressing modes shows the location of a required data or instructions. Output of addressing
mode is Effective Address (EA). Effective address is the actual address of the data or instructions.

 In opcode we get to know which operation has to perform like addition, subtraction,
multiplication, division, increment, and decrement.
 In operand we get to know about the data, in which operation is performed. We will get the
data in the memory, so the location of the data is given by addressing mode.

OPCODE OPERAND

Relative Address = Program counter (Next Instruction) + Address (Program counter stores next
instruction address)
Indexed Address = XR + Address

Direct/Absolute addressing mode

In this mode, the data is directly copied from the given address to the register. The address field of
the instructions contains effective address of the operand (data).
In this you will get the data (operand) of effective address.
Immediate addressing mode
Data is present in address field of the instruction. Whatever the address is given, the data is
present in that address only. We don‟t need to go anywhere to search the data. So we will get the
data immediately.

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

Indirect addressing mode

In this mode, the data is transferred from one register to another by using the address pointed by the
register.
The address field contains memory location which contains effective address.
In this you will get the data: address of the effective address.
Relative addressing mode
Effective address of the operand is obtained by adding the content of program counter with the address part
of the instruction.
Relative Address = Program counter (next instruction) + Address (Program counter stores next instruction
address)

Indexed addressing mode

Effective address of the operand is obtained by adding the content of Indexed register with the address part
of the instruction. Here Indexed Register is denoted as XR.
Indexed Address = XR + Address
Register direct addressing mode
 This addressing mode is similar to direct addressing mode.
 In this effective address is empty. Only contains name of the register for example – R1.
 Whatever the value of register we assume it is directly stored in the memory or accumulator.
 The only difference is address field of the instruction refers to a CPU register instead of main
memory.
Register indirect addressing mode
 This addressing mode is similar to indirect addressing mode.
 The only difference is address field of the instruction refers to a CPU register that contains the
effective address of the data or operand.
Auto Increment
In auto-increment addressing mode,
 First, the operand value is fetched.
 Then, the instruction register RAUTO value is incremented by 1.

Auto decrement
In auto-decrement addressing mode,
 First, the instruction register RAUTO value is decremented by 1.
 Then, the operand value is fetched.
Implied/Implicit addressing mode
 This mode doesn‟t require any operand (data); the data is specified by the opcode
itself. Implied addressing mode knows about their data itself. Here we don‟t need to
search the data, Implicit addressing mode already knows about their data.

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

 For example: CMP.

 In stack organized computer Zero address instruction are implied mode instruction. The
operands are specified implicitly in the instruction.
EXAMPLE OF ADDRESSING MODE:

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Q. Show the block diagram of hardware that implements the following register transfer
statement: yT2: R2 R1, R1 R2

Answer:
Ø Here we have used AND gate because in the equation we can see that both the input is in
multiplication (yT2) so we have to use the gate accordingly.

Ø The output from the AND gate is transferred to the register R1 & R2 the data is transferred from R1
to R2 and from R2 to R1.

Ø Both the register are connected to clock.

Explanation:

Q. Represent the following conditional control statement by two register transfer statements with

Control functions. If (P=1) then (R1 R2) else if (Q = 1) then (R1 R3)

Answer:
P: R1 R2
P‟Q: R1 R3

Q. A digital computer has a common bus system for 16 registers of 32 bits each. The bus is
constructed with multiplexers.
a. How many selection inputs are there in each multiplexer?
b. What size of multiplexers are needed?
c. How many multiplexers are there in the bus?

Answer:
a) 4 (since we have 16 registers, so, 2n, here n = no. of selection inputs lines, 24=16, hence there are 4
selection inputs.)
b) 16X1 (because there are 16 registers, so we get 16 inputs in multiplexer) or (size of multiplexers =
number of registers *1)
c) 32 (as we know, no. of bits of registers = no. of multiplexers, 32 bit register = 32 multiplexers).

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Q. The following transfer statements specify a memory. Explain the memory operation in each
case.
a. R2 M[AR]
b. M[AR] R3
c. R5 M[R5]
Answer:
a. This is read operation. It reads memory word specified by the address in the Address Register (AR),
and load it R2.
b. This statement writes the content of register R3 to memory word specified by the address in the
Address Register (AR).
c. This is a read operation where it reads memory word specified by the address in R5, and Override
the content of R5.

Q. Draw the block diagram for the hardware that implements the following statements: x+yz:
AR AR + BR, Where AR and BR are two n-bit registers and x, y and z are control variables.
Include the logic gates for the control functions.

Answer:

Ø Here we have used AND gate because in the equation we can see the input is in multiplication (yz)
but also we use OR gate because in the equation we see both the input is in addition also (x + yz) so we
have to use the gate accordingly.

Ø Both the register are connected to clock.

Y
CLOCK

AR
X
n n

ADDER

BR

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

Q. Register A holds the 8-bit binary 11011001. Determine the B operand

and the logic micro operation to be performed in order to change the
value in A to:
I. 01101101
II. 11111101

Answer:

To change the value in Register A to the desired values, we need to perform logic micro operations
using the B operand.
I. To change the value in Register A to 01101101, we can perform a bitwise XOR operation with the B
operand. The B operand should be the 8-bit binary 10110100. The XOR operation will flip the bits in A
where the corresponding bits in B are set to 1.
II. To change the value in Register A to 11111101, we can perform a bitwise OR operation with the B
operand. The B operand should be the 8-bit binary 00100100. The OR operation will set the bits in A to
1 where the corresponding bits in B are set to 1.
Here is a table showing the B operand and the logic micro operation for each case:
Desired Value B Operand Logic Micro operation

01101101 10110100 XOR

11111101 00100100 OR
Please note that the B operand is determined based on the desired value and the logic micro operation to
be performed.

 INFIX, PREFIX, POSTFIX

Operands = A, B, X, Y etc.

Operator = +, -, *, /, (, ) etc.

Infix = Infix means operator is present between two operands known as infix notation.

For example: A+ B etc.

Prefix = Prefix means operator is present before the operands.

For example: +AB etc.

Postfix = Postfix means operator is present after the operands. Postfix is also known as Reverse Polish
Notation (RPN).

For example: AB+ etc.

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

To perform Infix to RPN we need to remember some rules:

1. You need to know the priorities of the operator.

 Exponent is the highest priority
 Multiplication and division is having the next priority, both is having the same priority
 Addition and subtraction is having the lowest priority, both is having the same priority.
2. No two operators of same priority can stay together in a stack column.
3. Highest priority cannot tolerate the lowest priority. But lowest priority can tolerate the highest
priority.
4. If any closed parenthesis occurs so we have to pop that parenthesis and element.

Q. Convert the following expression from infix to reverse polish notation:

a) (A+B /C * (D + E) – F)

Answer:

Symbol Stack Postfix Explanation

( (
A ( A
+ (+ A
B (+ AB
/ (+/ AB Hence here + operator is having less priority and / divide is having
the highest priority. So lowest priority can tolerate the highest
priority
C (+/ ABC
* (+ / * ABC/ Hence no two operator of the same priority will stay together so
pop the divide operator.
( (+*( ABC/
D (+*( ABC/D
+ (+*(+ ABC/D
E (+*(+ ABC/DE
) (+*(+) ABC/DE+ If any closed parenthesis occurs so we have to pop that parenthesis
and element.

- (+*- ABC/DE+*+ Here * is having the highest priority but – is having the lowest
priority, so highest priority cannot tolerate the lowest priority.
Also + and – both have same priorities, so operator with same
priorities will not stay together.

F (- ABC/DE+*+F
) (-) ABC/DE+*+F- If any closed parenthesis occurs so we have to pop that parenthesis
and element.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Q. An instruction is stored at location 300 with its address field at location 301. The address field
has the value 400. A processor register R1 contains the number 200. Evaluate the effective
address if the addressing mode of the instruction is (a) direct; (b) immediate; (c) relative; (d)
register indirect; (e) index with R1 as the index register.

Solution:

(a) Direct addressing

Direct addressing means that the address field contains the address of memory location the instruction is
supposed to work with (where an operand "resides").
Effective address would therefore be 400.

(b) Immediate addressing

Immediate addressing means that the address field contains the operand itself.
Effective address would therefore be 301.

(c) Relative addressing

Relative addressing means that the address field contains offset to be added to the program counter to
address a memory location of the operand.
Effective address would therefore be 302 + 400 = 702.

(d) Register indirect addressing

Register indirect addressing means that the address of an operand is in the register. The address field in
this case contains just another operand.
Effective address would therefore be in R1 = 200.

(e) Indexed addressing with R1 as index register

There are several possible indexed addressing modes but in this case (there is an address field) it is co
called "indexed absolute" addressing.
In indexed absolute addressing the effective address is calculated by taking the contents of the address
field and adding the contents of the index register.
Effective address would therefore be 400 + R1 = 400 + 200 = 600.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Q.

Notes By Prof. Tanya Shrivastava