COA

Digital Systems
Functional Units & their
Interconnections
by
Upendra Mishra
CSE
KIET Group of Institutions
Delhi-NCR-Ghaziabad
Computer Organization
Computer Organization comes after the decide of Computer
Architecture first. Computer Organization is how operational attribute
are linked together and contribute to realize the architectural
specification. Computer Organization deals with structural relationship.

Organization describes how it does it.

Computer Architecture
Computer Architecture is a functional description of requirements
and design implementation for the various parts of computer. It
deals with functional behavior of computer system. It comes before
the computer organization while designing a computer.

Architecture describes what the computer does.

Computer Architecture Computer Organization

Architecture describes what the computer

Organization describes how it does it.
does.

Computer Architecture deals with Computer Organization deals with

functional behavior of computer system. structural relationship.

Its clear that it deals with high-level design its also clear that it deals with low-level
issue. design issue.

Where, Organization indicates its

Architecture indicates its hardware.
performance.

For designing a computer, its architecture For designing a computer, organization is

is fixed first. decided after its architecture.

Computer Architecture is also called as Computer Organization is frequently

instruction set architecture. called as micro architecture.

Computer Architecture comprises logical

Computer Organization consists of
functions such as instruction sets,
physical units like circuit designs,
registers, data types and addressing
peripherals and adders.
modes.

Architecture coordinates between the Computer Organization handles the

hardware and software of the system. segments of the network in a system.
 Functional Units & Interconnections
• A computer organization describes the functions and design
of the various units of a digital system.
• Functional units of a computer system are parts of the CPU
(Central Processing Unit) that performs the operations and
calculations called for by the computer program. A computer
consists of five main components namely, Input unit, Central
Processing Unit, Memory unit Arithmetic & logical unit,
Control unit and an Output unit.
Functional Units & Interconnections

Fig : Basic Functional Units of a Computer [1]

 Input Units
The most common input device is the keyboard.
Many other kinds of input devices for human-
computer interaction are available, including the
touchpad, mouse, joystick, and trackball.

Microphones

Cameras
 Output Units
The primary function of the output unit is to send the
processed results to the user. Output devices display
information in a way that the user can understand.
For example The most common example of an output device is
a monitor.
Some units, such as graphic displays, provide both an output
function, showing text and graphics, and an input function,
through touchscreen capability. The dual role of such units is
the reason for using the single name input/output (I/O) unit in
many cases.
 Arithmetic & Logic Unit
Most computer operations are executed in the
arithmetic and logic unit (ALU) of the processor.
Any arithmetic or logic operation, such as
addition, subtraction, multiplication, division, or
comparison of numbers, is initiated by bringing
the required operands into the processor, where
the operation is performed by the ALU.
 Control Unit
The memory, arithmetic and logic, and I/O
units store and process information and
perform input and output operations. The
operation of these units must be coordinated in
some way.
This is the responsibility of the control unit.
The control unit acts as the nerve center that
sends control signals to other units and senses
their states.
A large set of control lines (wires) carries the
signals used for timing and synchronization of
events in all units.
Control Unit
• The control unit is a component of a computer's central
processing unit that coordinates the operation of the
processor. It tells the computer's memory, arithmetic/logic
unit and input and output devices how to respond to a
program's instructions.
• The control unit is also known as the nerve center of a
computer system.
• Let's us consider an example of addition of two operands by
the instruction given as Add LOCA, RO. This instruction adds
the memory location LOCA to the operand in the register RO
and places the sum in the register RO. This instruction
internally performs several steps.
 Memory Unit

Registers

Cache

Siz
st

e
Co

d
Main Memory

ee
Sp
Secondary Memory

Auxiliary Memory

Fig : Memory Hierarchy

 The operation of a computer can be summarized as follows:

The computer accepts information in the form of programs

and data through an input unit and stores it in the memory.

Information stored in the memory is fetched under

program control into an arithmetic and logic unit, where it
is processed.

Processed information leaves the computer through an

output unit.

All activities in the computer are directed by the control

unit.
Reference:
[1] Hamacher, Carl et al., Computer Organization
and embedded Systems. 6th ed. McGrawHill.
Thank
You
 •

Upendra Mishra
COMPUTER ORGANISATION AND
ARCHITECTURE
BUS, ITS ARCHITECTURE, AND TYPES

12/21/2024 28
 BUS

• Bus is a communication system that helps data transfer between different

modules of the computer.
• Bus is a collection of wires that connects several devices.
• Buses are used to send control signals and data between the processor and other
components
• In computer system all the peripherals are connected to microprocessor through
Bus.
• A bus that connects major computer components like processor ,memory and
I/O is called system bus.

12/21/2024 29
• On any bus lines can be classified into three function groups:
i. Data Bus
ii. Address Bus
iii. Control Bus.

12/21/2024 30
12/21/2024 31
Data Bus:
1.Data bus carry the data.
2.Data lines provides path for moving data between components.
3.Width of databus is number of lines in databus.
4.Each line can carry only one bit at a time.
5.Data bus is a bidirectional bus.
6.Data bus fetch the instructions from memory.
7.Data bus used to store the result of an instruction into memory.
8.Data bus carry commands to an I/O device controller or port.
12/21/2024 32
Address lines
• These lines indicate the Location (e.g. in memory) that the data should
be either read from or written to.
• Address bus carry the memory address while reading from writing
into memory.
Control Bus
• The control bus holds the control and timing signals needed to
coordinate all of the computer’s activities.

12/21/2024 33
Different types of control signals are used in a bus:
1.Memory Read: This signal, is issued by the CPU or DMA
controller when performing a read operation with the memory.
2.Memory Write: This signal is issued by the CPU or DMA controller
when performing a write operation with the memory.
3.I/O Read: This signal is issued by the CPU when it is reading from
an input port.
4.I/O Write: This signal is issued by the CPU when writing into an
output port.

12/21/2024 34
• Following are the three components of a bus: –
• The address bus, a one-way pathway that allows
information to pass in one direction only, carries
information about where data is stored in memory.
• The data bus is a two-way pathway carrying the actual
data (information) to and from the main memory.
• The control bus holds the control and timing signals
needed to coordinate all of the computer’s activities.

12/21/2024 35
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12/21/2024 40
 TYPES OF BUSES
Dedicated and Multiplexed Bus
Types of Bus Dedicated Bus Multiplexed Bus
Explanation A dedicated bus is permanently Common bus used for both data and address
assigned either to a particular transmission. Address and data information may be
function or to a physical subset of transmitted over the same set of lines using an Address
computer components. Valid control lines.
Functional Dedication means a
separate bus for each different
function.
Physical Dedication means use of
separate buses connecting different
system components (same
functionality).

Advantages High Throughput and Less Waiting Use of fewer lines -> Less Cost and Space
Time
Disadvantages More Cost (Larger Bus Size) Reduced Performance-> More Complex Circuit

12/21/2024 41
12/21/2024 42
Computer Organization
and Architecture
Topic: Registers
by
Upendra Mishra
(M. Tech., Ph.D.*)
KIET Group of Institutions
Quick recap to Memory Hierarchy
Flip Smaller in size,
flops Faster in operation
and
Register costlier
Cache

Larger in size,
Main Memory Slower in operation
and
cheaper
Secondary Memory
 Introduction to Register
 Register is a digital device that is very fast memory unit that may
accept, store and transfer data or instruction.
 Registers is a group of flip-flops.
 Question: What is flip-flop?:
 Flip flop is able to store 1 bit of data/information.
 This means n-bit register have n-flip flops
Two broad categories of Register
Special Purpose Registers General purpose register
 Users do not access Special Purpose  General purpose register is used to
registers. These registers are for store data intermediate results
processor internal processing. during program execution. It can be
 Examples: Program Counter, accessed via assembly
Memory Address Register, programming.
Memory Data Register ,  Examples: Accumulator, Data Register
Instruction Register, Flag register
Computer components:
Top-Level View
Brief Description of Important Register
 PC(Program Counter): Contains the address of the next instruction to be fetched
from memory.
 MBR(Memory Buffer Register): Contains a word to be stored in memory or sent to
the I/O unit, or is used to receive a word from memory or from the I/O unit.
 MAR(Memory Address Register): Specifies the address in memory of the word to
be written from or read into the MBR.
 MDR(Memory Data Register ): It contains the data to be stored in the computer
storage (e.g. RAM), or the data after a fetch from the
computer storage.
Brief Description(contd.)
 IR(Instruction Register): Contains the instruction most recently fetched.
 Flag register: Depending upon the value of result after any arithmetic and logical operation
the flag bits become set (1) or reset (0).
 AC(Accumulator): Employed to hold temporarily operands and results of ALU operations.
 Data Register: A register used in microcomputers to temporarily store data being
transmitted to or from a peripheral device.
 Index Register: These are used for indexed addressing and may be
auto indexed
Topic: Register Transfer and
Memory Transfer
Register Recap
 Register is a digital device that is very fast memory unit that may
accept, store and transfer data or instruction.
 It is made of Flip flops.
Microoperations
 The operations executed on data stored in registers are called MICROOPERATIONS.
 A Microoperations is an elementary operation performed on the information stored
in one or more registers.
 The result of the operation may replace the previous binary information of a
register or may be transferred to another register.
 Example, Counter, increment and load, bidirectional shift
Register Transfer
Register Transfer Language
Register Transfer Language
implies the availability of hardware logic is borrowed from programmers, who
circuits that can perform a stated apply this term to programming
microoperation and transfer the result of languages.
the operation to the same or another
register.
Register Transfer Language
Expresses the symbolic form the
microoperation sequences among the
registers of a digital module.
Block representation of Register
Computer registers are designated by capital letters.
PC: Program Counter IR: Instruction Register
R1: Processor Register MAR: Memory Address Register
N – bit Register -> n number of flip flops
For Example: 8 - bit Register

R1 7 6 5 4 3 2 1 0

For Example: 16 - bit Register

15 0 15 8 7 0
PC PC(H) PC(L)
Information Transfer
• R2  R1 : denotes a transfer of the content of register R1 into register R2.
• Normally, we want the transfer to occur only under a predetermined control condition.
This can be shown by means of an if-then statement.
If (P = 1) then (R2  R1)
where, P is a control signal which results in Boolean value 0 or 1.

P: R2  R1
• It symbolizes the requirement that the transfer operation be
executed by the hardware only if P = 1 .
 P: R2  R1

Block Diagram
Clock pulse is
a time varying
voltage signal
applied to
control
operation of a
flip flop.
Timing Diagram
Memory Transfer
 The transfer of information from a memory word to the outside environment is called a
READ
operation.
 Read: DR  M[AR]
 The transfer of new information to be stored into the memory is called a WRITE
operation.
 Write: M[AR]  DR
 A memory word will be symbolized by the letter M.
 M[AR]: to specify the address of M when writing memory transfer
operations, address is enclosed in square brackets.(here, AR is
address register)
Arithmetic Microoperations
Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to

R3.
R2 ← R2' Complement the contents of R2 (1's
complement)
R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Thank
You
BUS ARBITRATION
Bus Arbitration
• Bus Arbitration is a process which decides among a number of
devices requesting to use the system bus ,which one to grant access
of bus.
• Bus Arbitration refers to the process by which the current bus master
accesses and then leaves the control of the bus and passes it to the
another bus requesting processor unit.
• Bus master :The controller that has access to a bus at an instance.
• Bus Arbiter decides who would become current bus master.
• There are two approaches to bus arbitration:

1.Centralized bus arbitration –

A single bus arbiter performs the required arbitration.

2.Distributed bus arbitration –

All devices participating in the selection of the next bus
master.
Daisy Chaining method

• In this method ,the device which is “physically closer” to the bus controller/arbitor
will be allowed to use the bus first.
• Three control signals are use here:
• i) Bus Request: Used by devices to make request for the bus.
• ii) Bus Busy: Used to show that bus is already used by other devices.
• iii)Bus Grant : Used to allow a device to grant access of bus.
• It is a simple and cheaper method where all the bus masters use the same line for
making bus requests. The bus grant signal serially propagates through each
master until it encounters the first one that is requesting access to the bus. This
master blocks the propagation of the bus grant signal, therefore any other
requesting module will not receive the grant signal and hence cannot access the
bus.
During any bus cycle, the bus master may be any device – the processor or any
DMA controller unit, connected to the bus.
Polling or Rotating Priority
method
• In this, the controller is used to generate the address for
the master(unique priority), the number of address lines
required depends on the number of masters connected in
the system. The controller generates a sequence of master
addresses. When the requesting master recognizes its
address, it activates the busy line and begins to use the
bus.

Polling count line =n

Max Number of connected Modules=
Fixed priority or Independent
Request method
• In this, each master has a separate pair of bus request
and bus grant lines and each pair has a priority
assigned to it.
• The built-in priority decoder within the controller
selects the highest priority request and asserts the
corresponding bus grant signal.
Procedure:
• Each device is given a 4-bit ID No, Suppose
• Device ID of A= 0101
• Device ID of B=0110
• Step1: Perform Logical OR of all the ID
• 0101
• 0110
• 0111 { Logical OR}
• Step2: Perform comparison of logical OR with first device ID.
• 0101
• 0111
• 0100
If result is same as Device ID ,then Device will get the Bus control otherwise
Again we perform logical OR with the result
0100 {Appear on Aribitration Line}
0110 {Logical OR with Device B}
0110  Same as Device ID, So device B will get the bus control.
Thank you
Computer Organization
and Architecture
Topic: Register Transfer and Memory
Transfer
by
Upendra Mishra
(M. Tech., Ph.D.*)
Register Recap
 Register is a digital device that is very fast memory unit that may
accept, store and transfer data or instruction.
 It is made of Flip flops.
Microoperations
 The operations executed on data stored in registers are called MICROOPERATIONS.
 A Microoperations is an elementary operation performed on the information stored
in one or more registers.
 The result of the operation may replace the previous binary information of a
register or may be transferred to another register.
 Example, Counter, increment and load, bidirectional shift
Register Transfer Language
Register Transfer Language
implies the availability of hardware logic is borrowed from programmers, who
circuits that can perform a stated apply this term to programming
microoperation and transfer the result of languages.
the operation to the same or another
register.
Register Transfer Language
Expresses the symbolic form the
microoperation sequences among the
registers of a digital module.
Block representation of Register
Computer registers are designated by capital letters.
PC: Program Counter IR: Instruction Register
R1: Processor Register MAR: Memory Address Register
N – bit Register -> n number of flip flops
For Example: 8 - bit Register

R1 7 6 5 4 3 2 1 0

For Example: 16 - bit Register

15 0 15 8 7 0
PC PC(H) PC(L)
Information Transfer
• R2  R1 : denotes a transfer of the content of register R1 into register R2.
• Normally, we want the transfer to occur only under a predetermined control condition. This
can be shown by means of an if-then statement.
If (P = 1) then (R2  R1)
where, P is a control signal which results in Boolean value 0 or 1.

P: R2  R1
• It symbolizes the requirement that the transfer operation be
executed by the hardware only if P = 1 .
 P: R2  R1

Block Diagram
Clock pulse is
a time varying
voltage signal
applied to
control
operation of a
flip flop.
Timing Diagram
P: R2  R1
Basic Symbols for Register Transfer
Memory Transfer
 The transfer of information from a memory word to the outside environment is called a READ
operation.
 Read: DR  M[AR]
 The transfer of new information to be stored into the memory is called a WRITE operation.
 Write: M[AR]  DR
 A memory word will be symbolized by the letter M.
 M[AR]: to specify the address of M when writing memory transfer
operations, address is enclosed in square brackets.(here, AR is address
register)
Arithmetic Microoperations
Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.

R2 ← R2' Complement the contents of R2 (1's complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Thank
You
Computer Organization
and Architecture
Topic: Register Transfer and Memory
Transfer
by
Upendra Mishra
(M. Tech., Ph.D.*)
Register Recap
 Register is a digital device that is very fast memory unit that may
accept, store and transfer data or instruction.
 It is made of Flip flops.
Microoperations
 The operations executed on data stored in registers are called MICROOPERATIONS.
 A Microoperations is an elementary operation performed on the information stored
in one or more registers.
 The result of the operation may replace the previous binary information of a
register or may be transferred to another register.
 Example, Counter, increment and load, bidirectional shift
Register Transfer Language
Register Transfer Language
implies the availability of hardware logic is borrowed from programmers, who
circuits that can perform a stated apply this term to programming
microoperation and transfer the result of languages.
the operation to the same or another
register.
Register Transfer Language
Expresses the symbolic form the
microoperation sequences among the
registers of a digital module.
Block representation of Register
Computer registers are designated by capital letters.
PC: Program Counter IR: Instruction Register
R1: Processor Register MAR: Memory Address Register
N – bit Register -> n number of flip flops
For Example: 8 - bit Register

R1 7 6 5 4 3 2 1 0

For Example: 16 - bit Register

15 0 15 8 7 0
PC PC(H) PC(L)
Information Transfer
• R2  R1 : denotes a transfer of the content of register R1 into register R2.
• Normally, we want the transfer to occur only under a predetermined control condition. This
can be shown by means of an if-then statement.
If (P = 1) then (R2  R1)
where, P is a control signal which results in Boolean value 0 or 1.

P: R2  R1
• It symbolizes the requirement that the transfer operation be
executed by the hardware only if P = 1 .
 P: R2  R1

Block Diagram
Clock pulse is
a time varying
voltage signal
applied to
control
operation of a
flip flop.
Timing Diagram
P: R2  R1
Basic Symbols for Register Transfer
Memory Transfer
 The transfer of information from a memory word to the outside environment is called a READ
operation.
 Read: DR  M[AR]
 The transfer of new information to be stored into the memory is called a WRITE operation.
 Write: M[AR]  DR
 A memory word will be symbolized by the letter M.
 M[AR]: to specify the address of M when writing memory transfer
operations, address is enclosed in square brackets.(here, AR is address
register)
Arithmetic Microoperations
Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.

R2 ← R2' Complement the contents of R2 (1's complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Thank
You
Computer Organization
and Architecture
Topic: General Register Organization
by
Upendra Mishra
(M. Tech., Ph.D.*)
KIET Group of Institutions
 Prerequisites
 Registers
 Register Transfer and Memory Transfer
Multiplexer
 Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection
Example: 8x1 Multiplexer
lines and single output line. Input: 8 -> pow(2,3)
 2x1 Multiplexer 4x1 Multiplexer 8x1 Multiplexer Selection lines: 3
Output: 1
16x1 Multiplexer …….
Inputs
8x1 Outputs
Mux
A Select
B
C lines
D

Block Diagram Truth Table

Decoder
 Decoder is a combinational circuit that has ‘n’ input lines and 2n data outputs out of which
only ONE output is activated based on ‘n’ inputs. Example: 3*8 Decoder
Input: 3
 2x4 Decoder 3x8 Decoder Output: 8 -> pow(2,3)
4x16 Decoder

Block Diagram Truth Table

GENERAL REGISTER ORGANIZATION Input
Clock

A bus organization
for seven CPU R1 A
R2
registers. R3

R1 R2+R3 R4
B
R5
1. MUX A selector (SELA): R6
to place the content of R2 R7
into bus A . Load
2 . MUX B selector (7 lines)
(SELB): to place the SELA { MUX MUX } SELB

content o f R 3 into bus B

3 . ALU operation selector 3x8
R2
A bus R3
B bus
decoder
(OPR): to provide the
arithmetic addition
A + B. SELD
OPR ALU
4. Decoder destination
selector (SELD): to OPR
transfer the content of
the output bus into R1 Result -> Register Output 108
Control Word
Examples of Microoperations
Symbolic Designation

Microoperation SEL A SEL B SEL D OPR Control Word

R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101

R4  R4  R5 R4 R5 R4 OR 100 101 100 01010

R6  R6 + 1 R6 - R6 INCA 110 000 110 00001

R7  R1 R1 - R7 TSFA 001 000 111 00000

Output  R2 R2 - NONE TSFA 010 000 000 00000

Output  Input INPUT - NONE TSFA 000 000 000 00000

R4  shl R4 R4 - R4 SHLA 100 000 100 11000

R5  0 R5 R5 R5 XOR 101 101 101 01100 118

Reference
1. Computer System Architecture - Morris Mano

119
Thank
You
 Computer
Organization and
Architecture
BUS SYSTEM USING
MULTIPLEXER
by
Upendra Mishra
(B.Tech., M.Tech. PhD.(P))
KIET Group of Institutions
 Contents

 MULTIPLEXER
 BUS SYSTEM USING MULTIPLEXER
 MULTIPLEXER(MUX)
•
Multiplexer
 Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection
Example: 8x1 Multiplexer
lines and single output line. Input: 8 -> pow(2,3)
 2x1 Multiplexer 4x1 Multiplexer 8x1 Multiplexer Selection lines: 3
Output: 1
16x1 Multiplexer …….
Inputs
8x1 Outputs
Mux
A Select
B
C lines
D

Block Diagram Truth Table

 4-TO-1-LINE MULTIPLEXER
Function Table for 4-to-1 Line Multiplexer

The multiplexer is also called a data selector,

since it selects one of many data inputs, and
steers the binary information to the output.
4-TO-1-LINE MULTIPLEXER
Decoder
 Decoder is a combinational circuit that has ‘n’ input lines and 2n data outputs out of which
only ONE output is activated based on ‘n’ inputs. Example: 3*8 Decoder
Input: 3
 2x4 Decoder 3x8 Decoder Output: 8 -> pow(2,3)
4x16 Decoder

Block Diagram Truth Table

BUS SYSTEM USING MULTIPLEXER

A typical digital computer has many registers, and paths must be provided
to transfer information from one register to another.
The number of wires will be excessive if separate lines are used between
each register and all other registers in the system.
A more efficient scheme for transferring information between registers in
a multiple-register configuration is a common bus system.
BUS SYSTEM USING MULTIPLEXER

A bus structure consists of a set of common lines, one for each bit of a
register, through which binary information is transferred one at a time.
Control signals determine which register is selected by the bus during
each particular register transfer.
One way of constructing a common bus system is with multiplexers.
The multiplexers select the source register whose binary information is
then placed on the bus.
Bus System for Four Registers
Bus System for Four
Registers
1.Number of Multiplexer Required= Number of bits in each register
2. Size of Multiplexer = Number of register used
 Bus System for Four Registers
Each register has four bits, numbered 0 through 3.
The bus consists of four 4X1 multiplexers each having four data inputs, 0
through 3, and two selection inputs, S1 and S0.
For example, output 1 of register A is connected to input 0 of Mux 1 because
this input is labelled A1.
The MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the
four 1 bits of the registers, and similarly for the other two bits.
 Bus System for Four Registers
The two selection lines S1 and S0 are connected to the selection inputs of all
four multiplexers.
The selection lines choose the four bits of one register and transfer them into
the four-line common bus. When S1S0=00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that form the bus.
This causes the bus lines to receive the content of register A since the outputs
of this register are connected to the 0 data inputs of the multiplexers. Similarly,
register B is selected if S1S0=01, and so on.
 Bus System for Four Registers

In general, a bus system will multiplex k registers of n bits each to produce an n-
line common bus.
The number of multiplexers needed to construct the bus is equal to n, the
number of bits in each register.
The size of each multiplexer must be k X 1 since it multiplexes k data lines.
 Bus System for Four Registers

The transfer of information from a bus into one of many destination registers
can be accomplished by connecting the bus lines to the inputs of all destination
registers and activating the load control of the particular destination register
selected.
GENERAL REGISTER ORGANIZATION Input
Clock

A bus organization
for seven CPU R1 A
R2
registers. R3

R1 R2+R3 R4
B
R5
1. MUX A selector (SELA): R6
to place the content of R2 R7
into bus A . Load
2 . MUX B selector (7 lines)
(SELB): to place the SELA { MUX MUX } SELB

content o f R 3 into bus B

3 . ALU operation selector 3x8
R2
A bus R3
B bus
decoder
(OPR): to provide the
arithmetic addition
A + B. SELD
OPR ALU
4. Decoder destination
selector (SELD): to OPR
transfer the content of
the output bus into R1 Result -> Register Output 140
Problem
Q1.A bus-organized CPU has 16 registers with 32 bits in each. an ALU, and a
destination decoder.
a) How many multiplexers are there In the A bus, and what is the size of each
multiplexer?
b) How many selection Inputs are needed for MUX A and MUXB?
c) How many inputs and outputs are there in the decoder?
d) How many inputs and outputs are there in the ALU for data, including
input and output carries?
e) Formulate a control word for the system if the ALU has 35
operations.
•
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vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
vgghhhhhhh

SEL A SEL B SEL D OPR

 References

 Computer System Architecture - M. Mano , 3rd Edition.

Thank
You
 Computer
Organization and
Architecture
BUS SYSTEM USING TRI-
STATE BUFFER
by
Upendra Mishra
(B.Tech., M.Tech., Ph.D.(P))
KIET Group of Institutions
 CONTENTS

 TRI-STATE BUS BUFFER

 BUS SYSTEM USING TRI-STATE
BUFFER
 TRI-STATE BUS BUFFER
A three-state gate is a digital circuit that exhibits three
states. Two of the states are signals equivalent to logic 1 and
0 as in a conventional gate.
The third state is a high-impedance state.
The high-impedance state behaves like an open circuit,
which means that the output is disconnected and does not
have a logic significance.
 Three-state gates may perform any conventional logic, such
as AND or NAND. However, the one most commonly used in
the design of a bus system is the buffer gate.
TRI-STATE BUS BUFFER
• A bus system that can be constructed with three state buffer gates is
called three-state bus buffer.
• Buffer gate has the property that what we gave input is considered as
output.
• Three-State Gates: A 3 state gate is a digital circuit that shows 3
states.i) state1 ii) state-0 iii) High impedence
 GRAPHIC SYMBOL OF A TRI-STATE
BUFFER
It is distinguished from a normal buffer by having both a normal input and a
control input. The control input determines the output state. When the control
input is equal to 1, the output is enabled and the gate behaves like any
conventional buffer, with the output equal to the normal input.
When the control input is 0, the output is disabled and the gate goes to a high-
impedance state, regardless of the value in the normal input.
Bus System with Tri-State Buffers
Bus System with Tri-State Buffers

The outputs of four buffers are connected together to form a single bus line.
(It must be realized that this type of connection cannot be done with gates
that don't have three-state outputs.)
The control inputs to the buffers determine which of the four normal inputs
will communicate with the bus line. No more than one buffer may be in the
active state at any given time. The connected buffers must be controlled so
that only one three-state buffer has access to the bus line while all other
buffers are maintained in a high-impedance state.
Bus System with Tri-State Buffers

One way to ensure that no more than one control input is active at any
given time is to use a decoder.
When the enable input of the decoder is 0, all of its four outputs are 0, and
the bus line is in a high-impedance state because all four buffers are
disabled.
When the enable input is active, one of the three-state buffers will be
active, depending on the binary value in the select inputs of the decoder.
Bus System with Tri-State Buffers

To construct a common bus for four registers of n bits each using three-state
buffers, we need n circuits with four buffers in each as shown in last figure .
Each group of four buffers receives one significant bit from the four
registers. Each common output produces one of the lines for the common
bus for a total of n lines. Only one decoder is necessary to select between
the four registers.
Points to Remember:
• In common to construct a common bus for 4 registers of n bits &
each using three state buffers, then we need n circuits with four
buffers.
• Each group of four buffers receives one significant bit from the four
registers.
• Each common output produces one of the lines for the common bus
for a total of n lines.
• Only one decoder is necessary to select between the four registers.
 References

Computer System Architecture - M. Mano , 3rd Edition.

Thank
You
 Processor
Organization
By
Upendra Mishra
KIET Group of Institutions, Delhi-NCR,
Ghaziabad
Processor Organization
 Components of the processor
• ALU (Arithmetic and Logic Unit) is a group of circuits that performs arithmetic
(addition, increment/decrement or complement) and logic (AND, OR, NOT, X-OR etc)
operations.
• The control unit controls the movement of data and instructions into and out of the
processor and controls the operation of the ALU. A control unit is a group of circuits
that provides timing and signals to all the operations in the computer and controls the
data flow.
• A minimal internal memory, consisting of a set of storage locations, called registers.

An internal processor bus is needed to transfer data

between the various registers and the ALU
because the ALU in fact operates only on data in the internal
processor memory.
Some mechanism that provides for communication
among the control unit, ALU, and registers
 Register organization
Register categories:
• User-visible registers
• Control and status registers

• User-visible registers: used by the machine language or assembly language

programmer.
• Control and status registers: Used by the control unit to control the operation
of the processor
 User-visible registers
• General-purpose registers can be assigned to a variety of
• General purpose functions by the programmer.
• Data • Data registers may be used only to hold data and cannot be
• Address employed in the calculation of an operand address.
• Condition codes • Address registers may themselves be somewhat general
purpose, or they may be devoted to a particular addressing
mode.
• A final category of registers, which is at least partially
visible to the user, holds condition codes (also referred to
as flags). Condition codes are bits set by the processor
hardware as the result of operations. For example, an
arithmetic operation may produce a positive, negative,
zero, or overflow result
 Examples of Address
Registers
Segment pointers: In a machine with segmented
• Examples include the addressing, a segment register holds the address of the
following: base of the segment. There may be multiple registers: for
example, one for the operating system and one for the
• Segment pointers current process.
• Index registers
• Stack pointer Index registers: These are used for indexed addressing and
may be auto-indexed.

Stack pointer: If there is user-visible stack addressing, then

typically there is dedicated register that points to the top
of the stack. This allows implicit addressing; that is, push,
pop, and other stack instructions need not contain an
explicit stack operand.
 Control and Status Registers
Control and status registers: Used by the Program counter (PC): Contains the
control unit to control the operation of address of an instruction to be fetched
the processor.
Instruction register (IR): Contains the
Four registers are essential to instruction instruction most recently fetched
execution:
Memory Address Register (MAR): Contains
Program counter the address of a location in memory
Instruction register where a word of data to be written to or
Memory Address read from.
Register
Memory buffer Memory buffer register (MBR) or
register Memory Data Register (MDR): Contains a
word of data to be written to memory or
the word most recently read.
 Program Status Word (PSW)
A register or set of registers, often known as the program • Sign Flag
status word (PSW) contain status information. • Zero Flag
The PSW typically contains condition codes plus other • Equal Flag
status information. • Overflow Flag
• Interrupt
Common fields or flags include the following: Enable/Disable Flag
• Supervisor Flag
 Program Status Word (PSW)
Sign: Contains the sign bit of the result of the last arithmetic operation.
Zero: Set when the result is 0.
Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction)
out of a high-order bit.
Equal: Set if a logical compare result is equality.
Overflow: Used to indicate arithmetic overflow.
Interrupt Enable/Disable: Used to enable or disable interrupts.

Supervisor: Indicates whether the processor is

executing in supervisor or user mode. Certain privileged
instructions can be executed only in supervisor mode,
and certain areas of memory can be accessed only in
Important points
• The basic operations are addition, shifting, and complement.

• The arithmetic operations such as subtractions, multiplication and

division are performed with the help of these basic operations.

• The number of registers and types of register in a processor depend

on the design of a processor
References
• COMPUTER ORGANIZATION AND ARCHITECTURE-DESIGNING FOR
PERFORMANCE, EIGHTH EDITION by William Stallings

• COMPUTER ORGANIZATION AND EMBEDDED SYSTEMS, SIXTH EDITION, by Carl

Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian
Thank
You
 Stack
Organization
by
Upendra Mishra
KIET Group of Institutions, Delhi-NCR,
Ghaziabad
 Contents
• Stack
• Operations on Stack
• Types of Stack
• Applications of Stack
What is Stack?
How to work with Stack?
• Operations on Stack
• Push: to insert an element into the stack
• Pop: To remove the top element from the stack

• A register is used to store the address of the topmost element of the stack
which is known as Stack pointer (SP).

• The stack pointer register SP contains a binary number whose value is equal to
the address of the word that is currently on top of the stack.
 Register Stack:
• A stack can be placed in a portion of a large
memory or it can be organized as a collection
of a finite number of memory words or
registers.

• Example: A register stack of 64 words or

registers
Initially:
FULL=0
EMPTY=1
SP=0
Register Stack (contd..)
 FULL=0 (Stack is not full) • FULL is a one-bit flag register for showing the
 FULL=1 (Stack is full) status of stack whether it is Full (containing all 64
elements) or not.

 EMPTY =0 (Stack is Not empty) • EMPTY is also a one-bit flag register for showing
the status of stack whether it is Empty
 EMPTY = 1 (Stack is Empty) (containing no element) or not

• DR is the data register that holds the binary data

to be written in to or read out of the stack.
 Register Stack (contd..)
PUSH Operation: • PUSH Operation: The push operation is
• SP ←SP + 1 (Increment stack pointer) implemented with the shown sequence
of micro-operation.
• M [SP] ← DR (Write item on top of the
stack)
• The stack pointer is incremented so that
it points to the address of the next-
• if (SP==0) then (Full ← 1) (Check if stack higher word.
is full)
• Empty ← 0 (Marked the stack not empty) • A memory write operation inserts the
word from DR into the top of the stack.
Note that SP holds the address of the top
 Add element A to the Stack
• Initially:
FULL=0
EMPTY=1
SP=0
Push an
element:
SP= SP+1 =
0+1 =1
M[SP] DR
( M[1]=A)
If (SP==0)
then (Full 1 )
 Add an element B to the Stack
• Given
FULL=0
EMPTY=0
SP=1

Push an
element:
SP= SP+1 =
1+1 =2
M[SP]
DR ( M[2]=B)
If (SP==0)
No
EMPTY=0
 Add an element C to the Stack
• Given
FULL=0
EMPTY=0
SP=2
Push an
element:
SP= SP+1 =
2+1 =3
M[SP] DR (
M[3]=C)
If (SP==0)
No
EMPTY=0
 Removing an element from the
stack
• POP operation: • The top item is read from the
• DR← M [SP] (Read item from the top of stack) stack into DR.
• SP ← SP-1 Decrement stack Pointer
• If ( SP==0) then (Empty ← 1) Check if stack • The stack pointer is then
is empty decremented.
• FULL ← 0 (Mark the stack not full)
• If its value reaches zero, the
stack is empty, so Empty is set to
1.
 Removing the top element from
the stack
Given
Full = 0
Empty= 0
SP=3

Pop an item
DR← M [SP]  DR=
M[3]= C
SP= SP-1  SP=3-1= 2
If (SP==0) then (Empty 1)
FULL=0
000000
- 1
111111
 Important Point
• The first item stored in the stack is at address 1.

• The second last (or prior to last) item stored in the stack is at
address 63.

• The last item is stored at address 0.

Stack Pointer Movement
Memory Stack:
 Memory Stack:
• Push Operation:
• A new item is inserted with the push operation
as follows.

• SP← SP-1 (Decrement stack Pointer)

• M [SP] ← DR (Write item on top of
the stack)
Memory Stack:
• A new item is deleted with a pop operation
as follows.

• DR← M [SP] (Read item from the top

of stack)

• SP←SP + 1 (increment stack

Pointer)
Applications of Stack
• Subroutines Call
• Zero-address Instruction Implementation
• Infix notation to Post-fix notation
• Evaluation of Arithmetic Expressions
Precedence and Associativity
Instruction
• Instruction: An Instruction is a command given to the computer to
perform a specific function.
• Instruction format:
• i) Operation Code(Opcode):Specifies Operation to be performed.
• ii) Specifies which addressing mode is used.
• iii) Specify a memory address or register address.

Operation Code(Opcode) Mode Field Address Field

• Evaluate the arithmetic statement
• X= (A+B)*(C+D)
• Assume that A,B,C,& D are Memory addresses.
Problem
Problem2
Thank
You
Addressing Modes
 Addressing Modes
• Specify different ways of determining (calculating) effective address of an
operand.
• The term addressing modes refers to the way in which the
operand of an instruction is specified. The addressing mode
specifies a rule for interpreting or modifying the address field
of the instruction before the operand is actually executed.
• The effective address is a term that describes the address
of an operand that is stored in memory.
• There are several methods to designate the effective address
of those operands or get them directly from the register.
These methods are known as addressing modes.
Types of Addressing Modes
• Direct address mode :The operand is located at the specified address given
• Indirect address mode: The address specifies the effective address of the operand
• Register mode: The operands are in registers.
• Register indirect mode: The instruction specifies a register that contains the address of the operand
• Relative address mode: The effective address is the summation of the address field and the content
of the PC.
• Immediate mode: The operand is specified in the instruction
• Implied mode: The operands are specified implicitly in the definition of the instruction –complement
accumulator or zero-address instructions
• Auto increment or auto decrement mode: Similar to the register indirect mode
• Indexed addressing mode: The effective address is the summation of an index register and the
address field
• Base register address mode: The effective address is the summation of a base register and the
address field
 Direct Addressing Mode

Direct address mode: the operand is located at the specified address given
Indirect address mode:
Register Addressing mode
Register Indirect Addressing
Relative Addressing Mode.
Immediate Addressing Mode
Index Register Addressing Mode
Base Register Addressing Mode
Implied Addressing Mode
Autoincrement Addressing Mode
Auto-decrement Addressing Mode
Problem
•An instruction is stored at location 300 with its address fields at location 301. The
address field has the value 400. A processor register RI contain the number 200.

• Evaluate the effective address if the addressing mode of the instruction is

(a) Direct (b) Immediate (c) Relative (d) Register Indirect
a) Direct Addressing:
Effective Address(EA)= Value of address field=400
b) Indirect Addressing
Effective Address(EA)= Memory content of address
field=M[400]
c) Immediate Addressing:
Effective Address(EA)= Address of the address field
d) Register Addressing :
Effective Address(EA)= Name of register= R1
e) Register Indirect Addressing :
Effective Address(EA)= Value of register =200
f) Relative Addressing:
Effective Address(EA)= Value of PC + value of
address field = 702
g) Index Addressing:
Effective Address(EA)= value of indexing + value
of address field
= 200 +400