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Exercise_II_Reportvhdl

vhdl exercise

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3 views

Exercise_II_Reportvhdl

vhdl exercise

Uploaded by

massinissaramdhane.belaidi.etd
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Exercise II Report

1. Detailed Circuit Design

This section presents the detailed circuit design for a 1-bit full adder implemented using multiplexers. In this design, the

multiplexer-based approach is used to select sum and carry outputs based on the inputs (A, B, and Cin). The design

implements the sum and carry functions of a full adder as follows:

- Sum = A XOR B XOR Cin

- Carry = (A AND B) OR (B AND Cin) OR (A AND Cin)

2. VHDL Code

The following VHDL code implements an N-bit full adder using the component-generate and generic statements. This

implementation allows for flexible bit-widths by specifying the bit-width using a generic parameter N.

```vhdl

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity N_bit_full_adder is

generic (N : integer := 4);

Port (A, B : in STD_LOGIC_VECTOR(N-1 downto 0);

Cin : in STD_LOGIC;

Sum : out STD_LOGIC_VECTOR(N-1 downto 0);

Cout : out STD_LOGIC);

end N_bit_full_adder;
architecture Behavioral of N_bit_full_adder is

signal carry : STD_LOGIC_VECTOR(N downto 0);

begin

carry(0) <= Cin;

gen_adder: for i in 0 to N-1 generate

sum(i) <= A(i) XOR B(i) XOR carry(i);

carry(i+1) <= (A(i) AND B(i)) OR (B(i) AND carry(i)) OR (A(i) AND carry(i));

end generate;

Cout <= carry(N);

end Behavioral;

```

3. VHDL Testbench Code

The following is the VHDL testbench code to verify the N-bit full adder implementation.

```vhdl

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity testbench is

end testbench;

architecture behavior of testbench is

signal A, B : STD_LOGIC_VECTOR(N-1 downto 0) := (others => '0');

signal Cin : STD_LOGIC := '0';

signal Sum : STD_LOGIC_VECTOR(N-1 downto 0);

signal Cout : STD_LOGIC;


begin

uut: entity work.N_bit_full_adder

generic map(N => 4)

port map (A => A, B => B, Cin => Cin, Sum => Sum, Cout => Cout);

stimulus: process

begin

-- Test cases

A <= "0001"; B <= "0010"; Cin <= '0'; wait for 10 ns;

A <= "0101"; B <= "0011"; Cin <= '1'; wait for 10 ns;

A <= "1111"; B <= "0001"; Cin <= '1'; wait for 10 ns;

wait;

end process;

end behavior;

```

4. Simulation Results

Simulation results were generated to verify the functionality of the N-bit full adder. The waveform outputs show the

expected results for the sum and carry bits based on various input cases applied through the testbench.

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