Laboratory Report Cover Sheet

UET ABBOTABAD CAMPUS

Faculty of Department of Electronics Engineering

ELE-408
FPGA BASED SYSTEM DESIGN
7th Semester fall 2020

Name:
Register No./C.NO :
Venue: Computer Laboratory # 1
Lab No. : 3
Lab Tile : Implement four bit full adder by instantiate 4, 1-bit full adder
using Spartan 3.

Date of Conduction:

Date of Submission:

Particulars Maximum Marks Marks Obtained

Pre –lab 20

lab simulations/codes 40

data analysis 40

Total 100

REPORT VERIFICATION
Date:

Instructor Name: Engr. Mehmoona Gul

Signature:
LAB #3
IMPLEMENT FOUR BIT FULL ADDER BY INSTANTIATE 4, 1-BIT FULL ADDER USING
SPARTAN 3.

1.1 AIM
The purpose of this lab is to introduce you to the Hierarchical method of complex digital design using
system FPGA and programming tools. For the purposes of this lab we will use nested module
instantiations to create a top-down design hierarchy for 4-bit binary adder.

1.2 OBJECTIVE

● Create a new design by Verilog coding.

● Verify the function of a design by behavioral simulation.

● Map a design to an FPGA device through placement and routing procedures.

● Estimate the performance of the design by timing analysis.

● Use the 1-bit full adder created in this tutorial to implement and simulate a 4-bit adder

3.3 THEORY
3.3.1 INTRODUCTION.

This is a step-by-step tutorial for building a 4-bit full adder in Xilinx ISE 8.2, a Design Suite software that
provides designers with the ability to code designs in a hardware description language such as VHDL or
Verilog. The ISE Design Suite also provides the ability to apply FPGA pin and timing constraints, analyze
for errors and violations, and synthesize to generate configuration bit file formats for FPGAs.

3.3.2 HALF ADDER

An adder is a digital logic circuit in electronics that implements addition of numbers. In many computers
and other types of processors, adders are used to calculate addresses, similar operations and table
indices in the ALU and also in other parts of the processors. These can be built for many numerical
representations like excess-3 or binary coded decimal. Adders are classified into two types: half adder
and full adder. The half adder circuit has two inputs: A and B, which add two input digits and generate a
carry and sum.

By using half adder, you can design simple addition with the help of logic gates.Let’s see an addition of
single bits.

0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10

HALF ADDER TRUTH TABLE

Now it has been cleared that 1-bit adder can be easily implemented with the help of the XOR Gate for
the output ‘SUM’ and an AND Gate for the ‘Carry’. When we need to add, two 8-bit bytes together, we
can be done with the help of a full-adder logic. The half-adder is useful when you want to add one
binary digit quantities. A way to develop a two-binary digit adders would be to make a truth table and
reduce it. When you want to make a three binary digit adder, do it again. When you decide to make a
four digit adder, do it again. The circuits would be fast, but development time is slow.

Half Adder Logic Circuit

The simplest expression uses the exclusive OR function: Sum=A xor B. An equivalent expression in terms
of the basic AND, OR, and NOT is: SUM=A’.B+A.B’.

VERILOG CODE FOR HALF ADDER

module xor1( a, b,s );

input a, b;
 output s;
xor (s, a, b);
endmodule

module and1(a, b, c);

input a, b;
output c;
and (c, a, b);
endmodule

module halfadder ( a, b, s, c);

input a, b;
output s, c;
xor1 u1(a, b, s);
and1 u2(a, b, c);
endmodule

3.3.3 FULL ADDER

This adder is difficult to implement than a half-adder. The difference between a half-adder and a full-
adder is that the full-adder has three inputs and two outputs, whereas half adder has only two inputs
and two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. When a
full-adder logic is designed, you string eight of them together to create a byte-wide adder and cascade
the carry bit from one adder to the next.

TRUTH TABLE
With the truth-table, the full adder logic can be implemented. You can see that the output S is an XOR
between the input A and the half-adder, SUM output with B and C-IN inputs. We take C-OUT will only be
true if any of the two inputs out of the three are HIGH.
So, we can implement a full adder circuit with the help of two half adder circuits. At first, half adder will
be used to add A and B to produce a partial Sum and a second half adder logic can be used to add C-IN
to the Sum produced by the first half adder to get the final S output.

If any of the half adder logic produces a carry, there will be an output carry. So, COUT will be an OR
function of the half-adder Carry outputs. Take a look at the implementation of the full adder circuit
shown below.
The implementation of larger logic diagrams is possible with the above full adder logic a simpler symbol
is mostly used to represent the operation. Given below is a simpler schematic representation of a one-
bit full adder.

With this type of symbol, we can add two bits together, taking a carry from the next lower order of
magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a multi-bit
operation, each bit must be represented by a full adder and must be added simultaneously. Thus, to add
two 8-bit numbers, you will need 8 full adders which can be formed by cascading two of the 4-bit blocks.
VERILOG CODE FOR FULL ADDER BY INSANTATING 2 HALF ADDER

module full_adder(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire s1,c1,c2;
halfadder ha1(a,b,s1,c1);
halfadder ha2(cin,s1,s,c2);
or(cout,c1,c2);
endmodule

3.3.4 FOUR BIT FULL ADDER

Binary adders are implemented to add two binary numbers. So in order to add two 4 bit binary numbers
we need to use 4 full-adders. The connection of full-adders to create binary adder circuit is discussed in
block diagram below.
In this implementation, carry of each full-adder is connected to previous carry.

VERILOG CODE FOR 4-BIT FULL ADDER

module four_bit_adder(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output[3:0] sum;
output cout;
wire c1,c2,c3;
full_adder fa1(a[0],b[0],cin,sum[0],c1);
full_adder fa2(a[1],b[1],c1,sum[1],c2);
full_adder fa3(a[2],b[2],c2,sum[2],c3);
full_adder fa4(a[3],b[3],c3,sum[3],cout);
 endmodule

3.4 PRE-LAB:
1. Write a truth table for 4-bit full adder.

3.5 SOFTWARE TOOLS REQUIREMENT

Equipment:
Computer with ISE Software
Specifications:
● HP Computer i7 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk

● Software: ISE
3.6 PROCEDURE:

1. Double click the project navigator and select the option File-New project.
2. Give the project name.
3. Select Verilog module.
4. Type your Verilog coding.(described in sec 2.3 for half adder and for full adder)
5. Check for syntax.
6. Choose behavioral simulation and simulate it by Xilinx ISE simulator.
7. Define UCF file.
8. Synthesize your design.
9. Implement your design
10. Generate programming file
11. Using JTAG cable configure your target device with .bit file
12. Verify the output on the fpga by giving different inputs.

PROGRESS RESULT
3.7 IN LAB-TASK
Verify the logic of four bit adder by configuring FPGA board / timing diagram by simulating in
software(covid-19).

3.7 POST-LAB TASK

1. Implement/simulate 4-bit binary subtractor.