Advanced Digital Design and

Synthesis
EC9040
Department of Computer Engineering,
Faculty of Engineering
University of Jaffna.
Digital Logic Gates & Family

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 Digital Logic Gates NOT
The electrical circuits which perform logical operations are called gates. A C
0 1 A
All data manipulation is based on logic 1 0
Logic follows well defined rules, producing predictable digital output from certain input.
Main Logic gates are AND, OR, NOT, NAND, NOR and XOR
AND OR NAND NOR XOR
AB C AB C AB C AB C AB C
0 0 0 0 0 0 0 0 1 0 0 1 0 0 0
0 1 0 0 1 1 0 1 1 0 1 0 0 1 1
1 0 0 1 0 1 1 0 1 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 0 1 1 0

A A A A A
B C B B B B

Digital logic gates NAND and NOR are called universal logic gate because we can construct
all other logic gates using NAND gate or NOR gate alone.

NAND gate can be built using 4 MOSFETs ( 2NMOS and 2PMOS). 3

NAND – A Universal Logic Gates
NAND
NOT AND
AB C invert output (invert NAND)
A C AB C
0 0 1 0 1 0 0 0
0 1 1 1 0 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
A
B NOR
AB C
0 0 1
OR 0 1 0
AB C 1 0 0
0 0 0 1 1 0
0 1 1
1 0 1
1 1 1
invert both inputs
invert inputs and output (invert OR)
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 NOR – A Universal Logic Gates

NOT
NOR
A C
AB C A
0 1
0 0 1 C 1 0
0 1 0
1 0 0 B
A A’
1 1 0

OR AND
AB C AB C A
0 0 0 A 0 0 0 C
0 1 1 C 0 1 0
1 0 1 B 1 0 0 B
1 1 1 1 1 1

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XOR –Logic Gates
A
B
C

• XOR = (A NAND B) AND (A OR B)

• And this you already know you can make from composite NAND gates
(though requiring 6 total)
• Then, obviously, XNOR is the inverse of XOR
– so just stick an inverter on the output of XOR

Exclusive OR operator: operating on two variables

A and B is true if A or B is a 1, but not when both A and B are 1, i.e. it excludes both
A and B being a 1; symbol ⊕

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Logic Family / Level Of Integration

Scheme # gates / chip

Small Scale Integration (SSI) <12
Medium Scale Integration (MSI) 12 - 99
Large Scale Integration (LSI) 1000
Very large Scale Integration (VLSI) 10k
Ultra large Scale Integration (ULSI) 100k
Giga Scale Integration (GSI) 1Meg

Note: Ratio gate count/transistor count is roughly 1/10

➢IC logic gates fall under SSI, combinational logic circuits fall under MSI, and
Microprocessor system come under LSI and VLSI.

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Digital Logic Family
Digital Logic Family
 Logic families can be classified broadly according to the
technologies they are built with

 There are various logic families namely –

 Diode logic (DL)

 Resistor-Transistor logic (RTL)
 Diode-Transistor logic (DTL)
 Emitter coupled logic (ECL)
 Transistor-Transistor logic (TTL)
 CMOS logic

 TTL and CMOS logic family is most widely used IC

technologies.

 Within each family, several subfamilies of logic types are

available, with different rating for speed, power consumption,
temperature range, voltage level and current level.
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Nomenclature of Logic family
The different manufacturers of digital logic ICs have standardized a numbering
scheme so that basic part number will be same regardless of the
manufacturer.

The prefix of the part number represents the manufacturer code and the suffix at
the middle denotes the subfamily of the ICs and suffix at the end denotes the
packaging type.

For example: If the part number is S74F08N. The 7408 is the basic number used
by all manufacturer for quad AND gate. The S prefix is the manufacture’s code for
Signetics, F stands for FAST TTL subfamily, and the N suffix at the end is used to
specify the plastic dual in line packaging

Suffix used for packaging: Suffix used for subfamily:

N - Plastic dual in line package 74H04 - High-speed
W - Ceramic flat pack 74L045- Low-Power
D - Surface mounted plastic package 74S04 - Uses a Schottky Diode
74ALS04 - Advanced low power Schottky
Prefix used for manufacturers:
S - Signetics
SN - Texas Instruments
DM - National Semiconductor 8
Diode Logic Family
In diode logic family, all the logic is implemented using diodes and resistors.
One basic thing about the diode, is that diode needs to be forward biased to conduct.

OR
XY Z
0 0 0
0 1 1
1 0 1
1 1 1

Diode Logic suffers from voltage degradation from one stage to the next.

Diode Logic only permits OR and AND functions, cannot perform a NOT function.

Diode Logic is used extensively but not in integrated circuits

How to build AND gate using Diode logic?

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 DL OR Gate
Schematic, and truth table DL OR gate

X Y Z
0 0 0
0 1 1
1 0 1
1 1 1
 TTL NOT Gate
Schematic of TTL NOT gate
Resistor Transistor Logic (RTL) Family
In RTL (resistor transistor logic), all the logic are implemented using resistors and
transistors. One basic thing about the transistor (NPN), is that HIGH at input causes
output to be LOW (i.e. like a inverter).

NOR
A
XY Z B
0 0 1
0 1 0
1 0 0
1 1 0

RTL draw a significant amount of current

from the power supply for each gate.
Another limitation is that RTL gates
cannot switch at the high speeds used by
today's computers, although they are still
useful in slower applications
NOR gate using RTL
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 RTL NOR Gate
Schematic, and truth table RTL NOR gate

X Y Z
0 0 1
0 1 0
1 0 0
1 1 0
Transistor Transistor Logic (TTL) Family
The idea of variable RC is accommodated by TTL IC. It uses another transistor Q3 in place of
RC to act like a varying resistance.
Q3 is cutoff (act like a high RC ) when output
transistor Q4 is saturated and Q3 is
saturated (act like a low RC ) when output
transistor Q4 is cutoff . Thus one transistor is
ON at one time.

The combination of Q3 and Q4 is called

totem pole arrangement.

Q1 is called input transistor, which is multi-

emitter transistor, that drive transistor Q2
which is used to control Q3 and Q4.

Diode D1 and D2 is used to protect Q1 from

unwanted negative voltages and diode D3
ensures when Q4 is ON, Q3 is OFF.

Multi-emitter input transistor is a striking feature of TTL logic family. 12

 CMOS Inverter
Schematic, truth table and logic symbol of CMOS Inverter.

OR VOUT

VIN Q1 Q2 VOUT
0.0 (L) OFF ON 5.0 (H)
5.0 (H) ON OFF 0.0 (L)
 CMOS NAND Gate

Schematic, truth table and logic symbol of CMOS NAND gate.

A B Q1 Q2 Q3 Q4 Z
L L OFF ON OFF ON H
L H OFF ON ON OFF H
H L ON OFF OFF ON H
H H ON OFF ON OFF L
 CMOS NOR Gate

Schematic, truth table and logic symbol of CMOS NOR gate.

A B Q1 Q2 Q3 Q4 Z
L L OFF ON OFF ON H
L H OFF ON ON OFF L
H L ON OFF OFF ON L
H H ON OFF ON OFF L
Transistor Transistor Logic (TTL) Family
One basic function of TTL IC is as a complimenting switch or inverter.

When Vin equals 1 (+5V), the transistor is turned on (saturation) and Vout equals 0 (0V).

When Vin equals 0 (0V), the transistor is turned off and Vout equals 1 (5V), assuming RL > RC

RL +5V
Vout  VCC
(R C  R L )
IC RC
Thus level 1 of inverter output is very much
dependent on RL , which can typically vary Vout
IB C
by factor of 10. Thus we need very small RC
B
compared to RL i.e. RL > > RC .
RB E
But when transistor is saturated (Vout = 0V), Vin IE RL
IC will be very large if RC is very small. RE

Thus we need large RC when transistor is in

satuaration and small RC when transistor is
off.
The idea of variable RC is accommodated by TTL IC. 11
Transistor Transistor Logic - Dual In Line Packaging (DIP)

IC 7400

Dual In Line package (DIP) is the most common pin layout for integrated circuits. The pins
are aligned in two straight lines, one on each side of the IC.

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Transistor Transistor Logic - Dual In Line Packaging (DIP)

IC 7408 IC 7402
IC 7404

Some common digital ICs used in labs are: IC7400 (Quad NAND gate), IC 7404 ( hex
inverter), IC 7408 (quad AND gate) and IC7402 (quad NOR gates).
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 NAND gate using TTL logic / Static analysis
NAND
AB C
0 0 1
0 1 1
1 0 1
1 1 0
A
B

When one or both inputs low (connected to When inputs high, base-emitter junction of
GND), base-emitter junction of Q1 is forward Q1 is reverse bias so Q1 OFF and output at
bias so Q1 ON (saturated) and output at collector will be high making Q2 ON.
collector will be low making Q2 off. Q4 ON and Q3 & D1 OFF so output is LOW.
• Q4 off and Q3 & D1 on making output HIGH. • Power dissipation in R1, Q1, R2, Q2, R3, Q4.
• Power dissipation in R1, Q1, R2, R4, Q3, D1 15
Performance Parameters of logic families

• Fan-out

• Input and Output Voltage level

• Noise Margin

• Rise and Fall time, and Propagation delay

•Power Dissipation.

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Fan In
• Fan in or gate is the number of inputs that can practically be supported
without degrading practically input voltage level.

Fan Out Fan in = 4

•The maximum number of digital input that the output of a single logic
gate can feed and the gate must be same logic family.

•Fan Out is calculated from the amount of current available in the output of
a gate and the amount of current needed in each input of the connecting
gate.

•It is specified by manufacturer and is provided in the data sheet.

•Exceeding the specified maximum load may cause a malfunction because

the circuit will not be able supply the demanded power.
Fanout = 4
VNH = HIGH-state noise margin
VNL = LOW-state noise margin
VIL = LOW-state input voltage
VIH = HIGH-state input voltage
VOL = LOW-state output voltage
VOH = HIGh-state output voltage
Where,
VNH = VOH -VIH
VNL = VIL – VOL

Manufacturers specify voltage limits to represent the logical 0 or 1. These limits are not
the same at the input and output sides. For example, a particular gate A may output a
voltage of 4.8V when it is supposed to output a HIGH but, at its input side, it can take a
voltage of 3V as HIGH. In this way, if any noise should corrupt the signal, there is some
margin for error.
Propagation Delay

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Comparison of a logic family
 Evolution of TTL Logic Family TTL 74H Series
TTL 74 Series High speed TTL logic – decrease the
resistance to lower the internal time
Standard TTL logic – saturated constant but increase in Pdis. Typical Pdis
BJT, Obsolete now, Don’t use in =22mW and t = 6ns
new designs

TTL 74S Series

TTL 74L Series
Schottky TTL logic – Deep saturation
Low Power TTL logic – Increase the
prevented by BC Schottky Diode. Reduced
resistance to lower the Pdis but increase
storage time delay. Practically obsolete.
in internal time constant . Typical Pdis
Typical Pdis =20mW and t = 3ns
=1mW and t = 35ns

TTL 74LS Series TTL 74ALS Series

Low power Schottky TTL. Low power, high speed Schottky TTL
Typical Pdis =2mW and t = 10ns logic-Innovations in IC design and
fabrication. Improvement in speed and
power dissipation. Popular.
 References

1. “Digital Design”, “Fifth edition”, M.Morris Mano, Michael D.

Ciletti.
2. https://web.stanford.edu/class/ee121/handouts/lect03.pdf
3. http://www.iitg.ac.in/apvajpeyi/ph218/Lec-28.pdf
4. http://www.asic-world.com/