DIGITAL LOGIC DESIGN

[EEng--2042 ]

Chapter Five:
Analysis and Synthesis of Combinational Logic
Circuits
Outline
 Introduction
 An Implementation of Combinational Logic
 The Universality of NAND and NOR Gates
 Implementation of Combinational Logic Using NAND and NOR Gates
 Design of Combinational Logic Circuits
Basic Adder
Comparator
Encoder and Decoder
Multiplexer and Demultiplexer
Parity generator/checker
2
 Introduction
 The digital system consists of two types of circuits, namely
1.Combinational circuits and
2.Sequential circuits

 A combinational circuits consists of logic gates, where outputs are at

any instant and are determined only by the present combination of
inputs without regard to previous inputs or previous state of outputs.

 A combinational circuits performs a specific information-processing

operation assigned logically by the set of Boolean functions.

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 Cont’d...
 Sequential circuits contains logic gates as well as memory cells.

 Their output depends on the present inputs and also on the states of
memory elements.

 Since the output of sequential circuits depends not only on the present
inputs but also on the past inputs, the circuit behavior must be specified by
a time sequence of inputs and memory states.

 The sequential circuit will be discussed later

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 Cont’d...
 In previous chapters we have discussed binary numbers, codes, Boolean
algebra and simplification of Boolean function, logic gates, and
economical gate implementation.

 Binary numbers and codes bear discrete quantities of information and the
binary variables are the representation of electric voltages or some other
signals.

 In this chapter formulation and analysis of various systematic design of

combinational circuits and application of information processing hardware
will be discussed.

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 A combinational circuit consists of input variables, logic gates and out
put variables.
 The logic gates accept signals from inputs and output signals are
generated according to the logic circuits employed in it.
 Binary information from the given data transforms to desire out put data in
this process.
 Both inputs an outputs are obviously
the binary signals, i.e., both the input
and output signals are of two possible
states, logic 1 and logic 0.
Figure 4-1 6
 Cont’d...
 Figure 4-1 shows a block diagram of a combinational logic circuits.
 There are n-number of input variables coming from an electric source and
m-number of output signals go to an external destination.
 The source and/or destination may consists of memory elements or
sequential logic circuits or shift registers, located either in the
vicinity/neighborhood of the combinational logic circuit or in a remote
external location.

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 Cont’d...
 But the external circuit does not interfere in the behavior of the
combinational circuit.
 For n-number of input variables to a combinational circuit, possible
combinations of binary input states are possible.
 For each possible combination, there is one and only one possible out put
combination.
 A combinational logic circuit can be described by ‘m’ Boolean functions
and each output can be expressed in terms of ‘n’ input variables.

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 Cont’d...
Types of Logic Circuits
 Combinational Logic
 Memoryless
Outputs are strictly dependent on the combination of input values that are being applied to
circuit right now.
 In some books called Combinatorial Logic
 Sequential Logic
 Has memory
Structure stores history Can ”store” data values
 Outputs are determined by previous (historical) and current values of inputs
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 Cont’d...
 Logic gates were discussed on an individual basis and in simple
combinations.

 SOP and POS implementations,

 which are basic forms of combinational logic.

 When logic gates are connected together to produce a specified output for
certain specified combinations of input variables, with no storage
involved,

 the resulting circuit is in the category of combinational logic.

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 Cont’d...
Basic Combinational Logic Circuits
 SOP expressions are implemented with an AND gate for each product
term and one OR gate for summing all of the product terms.
 As you know, this SOP implementation is called AND-OR logic and is the
basic form for realizing standard Boolean functions.
 In this section, the AND-OR and the AND-OR-Invert are examined;
 the exclusive-OR and exclusive-NOR
NOR gates, which are actually a form of
AND-OR logic, are also covered.

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 Cont’d...
AND-OR Logic

Figure 5.1 An example of AND-OR logic.

 Figure 5–1(a) shows an AND-OR circuit consisting
of two 2-input AND gates and one 2-input OR
gate;
 The Boolean expressions for the AND gate outputs
and the resulting SOP expression for the output X
are shown on the diagram.
 an AND-OR circuit can have any number of AND
gates, each with any number of inputs. 12
 Cont’d...
 An AND-OR circuit directly implements an SOP expression, assuming the
complements (if any) of the variables are available.

 The operation of the AND-OR circuit in Figure 5.1 is stated as follows:

 For a 4-input AND-OR logic circuit, the output X is HIGH (1)

if both input A and input B are HIGH (1) or

both input C and input D are HIGH (1).

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 Cont’d...
AND-OR-Invert Logic
 When the output of an AND-OR circuit is complemented (inverted), it
results in an AND-OR-Invert circuit.
circuit
 Recall that AND-OR logic directly implements SOP expressions.
 POS expressions can be implemented with AND-OR-Invert logic.
 This is illustrated as follows, starting with a POS expression and
developing the corresponding AND-OR
OR-Invert (AOI) expression.

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 Cont’d...

Figure 5.2 An AND-OR-Invert

Invert circuit produces a POS output.

 The operation of the AND-OR-Invert circuit in Figure 5–3 is stated as follows:

 For a 4-input AND-OR-Invert logic circuit, the output X is LOW (0)
 if both input A and input B are HIGH (1) or
 both input C and input D are HIGH (1)).
 A truth table can be developed from the AND-OR truth table in Table 5–1 by
simply changing all 1s to 0s and all 0s to 1s in the output column.
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Exclusive-OR Logic

 a combination of two AND gates, one OR gate, and two inverters, as shown in
Figure 5.3.

Figure 5.3 Exclusive-OR logic diagram

and symbols.
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 Cont’d...
 A special exclusive-OR operator is often used,
 so the expression X = AB + AB can be stated as “X is equal to A
exclusive-OR B” and can be written as

Exclusive-NOR Logic
 The complement of the exclusive--OR function is the exclusive-NOR,
which is derived as follows:

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 Cont’d...

Figure 5.4 Two equivalent ways of implementing the exclusive-NOR.

exclusive

 Notice that the output X is HIGH only when the two inputs, A and B, are at the same
level.

 The exclusive-NOR can be implemented by simply inverting the output of an

exclusive- OR, as shown in Figure 5.4(a),
(a), or by directly implementing the expression
AB + AB, as shown in part (b).
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 Implementing Combinational Logic
From a Boolean Expression to a Logic Circuit
 Let’s examine the following Boolean expression:
expression
X = AB + CDE
 This expression is composed of two terms, AB and CDE, with a domain of five
variables.
 The first term is formed by ANDing A with B, and the second term is formed by
ANDing C, D, and E. The two terms are then ORed to form the output X.
 These operations are indicated in the structure of the expression as follows:

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 Note that in this particular expression, the AND operations forming the two
individual terms, AB and CDE, must be performed before the terms can be
ORed.
 To implement this Boolean expression, a 2-input AND gate is required to form
the term AB, and a 3-input AND gate is needed to form the term CDE.
 A 2-input OR gate is then required to combine the two AND terms.

Figure 5.5 Logic circuit for X = AB + CDE.

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 Cont’d...
As another example, let’s implement the following expression:
X = AB(CD + EF) AB(CD + EF) = ABCD + ABEF

The logic gates required to implement X = AB(CD + EF) are as follows:

1.One inverter to form D
2.Two 2-input AND gates to form CD and EF
3.One 2-input OR gate to form CD + EF
4.One 3-input AND gate to form X

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Cont’d...
AB(CD + EF) = ABCD + ABEF

a. X=AB(CD + EF) b. Sum-of-products

Sum implementation of the circuit
in part (a)
Figure 5.6 Logic circuits for X = AB(CD + EF ) = ABCD + ABEF.

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From a Truth Table to a Logic Circuit
 We can write the SOP expression from the truth table and then implement the
logic circuit.
 The Boolean SOP expression obtained from the truth table by ORing the product
terms for which X = 1 is
X = ABC + AB C

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Cont’d...

 Figure 5.7 Logic circuit for X = ABC + AB C.

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 Cont’d...
Example Design a logic circuit to implement the operation specified in the truth
table of Table 5–4.

Notice that X=1 for only three of the input conditions. Therefore, the logic
expression is
X = ABC + ABC + ABC 25
Cont’d...

Figure 5.8 Logic circuit for X = ABC + ABC + ABC

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 The Universality of NAND and NOR Gates
 The universality of the NAND gate means that it can be used as an
inverter and that combinations of NAND gates can be used to implement
the AND, OR, and NOR operations..

 Similarly, the NOR gate can be used to implement the inverter (NOT),
AND, OR, and NAND operations.

The NAND Gate as a Universal Logic Element

 The NAND gate is a universal gate because it can be used to produce the
NOT, the AND, the OR, and the NOR functions.

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 Cont’d...
 An inverter can be made from a NAND gate by connecting all of the
inputs together and creating, in effect, a single input, as shown in Figure
5–18(a) for a 2-input gate.
 An AND function can be generated by the use of NAND gates alone, as
shown in Figure 5–18(b).
 An OR function can be produced with only NAND gates, as illustrated in
part (c).
 Finally, a NOR function is produced as shown in part (d).

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Cont’d...

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Cont’d...

Figure 5.9 Universal application of NAND gates.

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 Cont’d...
The NOR Gate as a Universal Logic Element
 Like the NAND gate, the NOR gate can be used to produce the NOT,
AND, OR, and NAND functions.

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Cont’d...

Figure 5.10 Universal application of NOR gates. 32

 Implementation of Combinational Logic Using
NAND and NOR Gates
 In this section, you will see how NAND and NOR gates can be used to
implement a logic function.
 The NAND gate also exhibits an equivalent operation called the negative-
OR and that the NOR gate exhibits an equivalent operation called the
negative-AND.
NAND Logic
 As you have learned, a NAND gate can function as either a NAND or a
negative-OR because, by DeMorgan’s theorem,

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 Cont’d...
 Consider the NAND logic in Figure 5–20. The output expression is
developed in the following steps:

Figure 5.11 NAND logic for X = AB + CD.

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Cont’d...

(b) Equivalent NAND/Negative-OR logic diagram

(a) Original NAND logic diagram showing

effective gate operation relative to the output
expression

(c) AND-OR equivalent

Figure 5.12 Development of the AND-OR

OR equivalent of the circuit in Figure 5.11.
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 Cont’d...
 As you can see in Figure 5.10, the output expression, AB + CD, is in the
form of two AND terms ORed together.
together
 This shows that gates G2 and G3 act as AND gates and that gate G1 acts
as an OR gate, as illustrated in Figure 5–21(a).
 This circuit is redrawn in part (b) with NAND symbols for gates G2 and
G3 and a negative-OR symbol for gate G1.

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 Cont’d...
NAND Logic Diagrams Using Dual Symbols
 All logic diagrams using NAND gates should be drawn with each gate
represented by either a NAND symbol or the equivalent negative-OR
symbol to reflect the operation of the gate within the logic circuit.
 The NAND symbol and the negative-OR
negative symbol are called dual
symbols.

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Cont’d...

(a) Several Boolean steps are required to arrive at final output expression.

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 Cont’d...

(b) Output expression can be obtained directly from the function of each gate symbol in
the diagram.

Figure 5.13 Illustration of the use of the appropriate dual symbols in a NAND logic diagram.
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 Cont’d...
Example Redraw the logic diagram and develop the output expression for the circuit in
Figure 5.14 using the appropriate dual symbols.
symbols

Writing the expression for X directly from the

indicated logic operation of each gate gives
X = (A + B)C + (D + E )F.

Redraw the logic diagram with

the use of equivalent negative-
OR symbols.
b
Figure 5.14 Illustration of the use of the appropriate dual symbols in a NAND logic diagram. 40
 Cont’d...
Example Implement each expression with NAND logic using appropriate dual
symbols:
(a) ABC + DE (b) ABC + D + E

a
b
Figure 5.15

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 Cont’d...
NOR Logic
 A NOR gate can function as either a NOR or a negative-AND, as shown
by DeMorgan’s theorem.

Consider the NOR logic in Figure 5.16.

The output expression is developed as
follows: Figure 5.16 NAND logic for X = AB + CD.

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 Cont’d...
 As you can see in Figure 5.16, the output expression (A + B)(C + D) consists of two OR terms
ANDed together.
 This shows that gates G2 and G3 act as OR gates and gate G1 acts as an AND gate, as
illustrated in Figure 5.17(a).
 This circuit is redrawn in part (b) with a negative-AND
negative symbol for gate G1.

a b

Figure 5.17 43
 Cont’d...
NOR Logic Diagram Using Dual Symbols
 As with NAND logic, the purpose for using the dual symbols is to make the logic diagram
easier to read and analyze, as illustrated in the NOR logic circuit in Figure 5.18.
 When the circuit in part (a) is redrawn with dual symbols in part (b), notice that all output-to-
input connections between gates are bubble-to--bubble or nonbubble-to-nonbubble.

a. Final output expression is obtained after several Boolean steps.

44
 Cont’d...
 Again, you can see that the shape of each gate symbol indicates the type of term (AND or OR)
that it produces in the output expression, thus making the output expression easier to determine
and the logic diagram easier to analyze.

(b) Output expression can be obtained directly from the function of each gate symbol in the diagram.

Figure 5.18 Illustration of the use of the appropriate dual symbols in a NOR logic diagram. 45
 Cont’d...
Example Using appropriate dual symbols, redraw the logic diagram and develop the output
expression for the circuit in Figure 5.20.
 Redraw the logic diagram with the equivalent
negative-AND symbols as shown in Figure 5.20..
 Writing the expression for X directly from the
indicated operation of each gate,
X = (A B + C)(D E + F)

Figure 5.20. Illustration of the use of the appropriate dual symbols in a NOR logic diagram. 46
 Design of Combinational Logic Circuits
 A combinational circuit can be designed by the following steps of design
procedure.
1. The problem is stated
2. Identify the input variables and output functions
3. The input and output variables are assigned letter symbols
4. The truth table is prepared that completely defines the relationship
between the input variables and output functions
5. The simplified Boolean expression is obtained by any method of
minimization
6. A logic diagram is realized from the simplified expression using logic
gate
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 Cont’d...
 A practical design approach should consider constraints like:
 Minimum number of gates
 Minimum number of output
 Minimum propagation time of the signal through the circuit
 Minimum number of interconnections
 Limitations of the driving capabilities of each logic gates
 Since the importance of each constraints is dictated by the particular application, it is
difficult to make all these criteria satisfied simultaneously and also difficult to make a
general statement on the process of achieving an acceptable simplification.
 In most cases, first simplified Boolean expression at standard form is derived and then
other constraints are taken care of as far as possible for a particular application.
48
 Cont’d...
Basic Adder
 Various information processing jobs are carried out by digital computers.
 Arithmetic operations are among basic functions of a digital computer.
 Addition of two binary digits is the most basic arithmetic operation.
 The simple addition consists of four elementary operations which are:
TABLE 5.1 Rule Sum (+) Carry
Rule 1 0+0=0
Rule 2 0+1=1
Rule 3 1+0=1
Rule 4 1+1=0 and carry 1 = 10
+ symbol means add 49
 Cont’d...
 The first three operations produce a sum of one digit, but the fourth
operation produces a sum consisting of two digits.
 The higher significant bit of this result is called the carry.
 A combinational circuit that performs the addition of two bits as described
above is called half-adder.
 When the augend and addend numbers contain more significant digits, the
carry obtained from the addition of two bits is added to the next higher-
order pair of significant bits.
 Here the addition operation involves three bits-the augend bit, addend bit,
and the carry bit and produces a sum result as well as carry.
50
 Cont’d...
 The combinational circuit performing this type of addition operation is
called a full-adder.
 In circuit development two half adders can be employed to form a full-
adder.
 Two sample binary addition problems are shown below.

51
 Cont’d...
Design of Half Adder
 As described above, a half-adder has two inputs and two out puts.
 Let the input variables: augend and addend be designated as A and B, and
output functions be designated as S for sum and C for carry.
 A half-adder is represented by the logic symbol in Figure 5.21.

Figure 5.21. Logic symbol for a half-adder.

half
52
 Cont’d...
 The truth table for functions as beside.
beside TABLE 5.2
Half-adder truth table.
 From the truth table, it can be seen that
the outputs S and C functions are similar
to Exclusive-OR and AND functions
respectively.
Cout =
AB

A and B = input variables

(operands)
Figure 5.22. Half-adder logic diagram. 53
 Cont’d...
The Full-Adder
 The second category of adder is the full-adder.
full

 The full-adder accepts two input bits and an input carry and generates a
sum output and an output carry.

Figure 5.23. Logic symbol for a full-adder.

full
54
 Cont’d...
 The basic difference between a TABLE 5.3
Full
Full-adder truth table.
full-adder and a half-adder is
that the full-adder accepts an
input carry.
 A logic symbol for a full-adder
is shown in Figure 5.23, and the
truth table in Table 5.3 shows
the operation of a full-adder.

55
 Cont’d...
Full-Adder Logic
 The full-adder must add the two input bits and the input carry.
 From the half-adder you know that the sum of the input bits A and B is the
exclusive-OR of those two variables, A ⊕ B.
 For the input carry (Cin) to be added to the input bits, it must be exclusive-
Ored with A ⊕ B, yielding the equation for the sum output of the full-
adder.
Equation 5-4

56
 Cont’d...

(a) Logic required to form the sum of three bits

Figure 5.24. Full-adder logic.

(b) Complete logic circuit for a full-adder

adder (each half-adder
half is enclosed by a shaded area) 57
 Cont’d...
 The output carry is a 1 when both inputs to the first XOR gate are 1s or
when both inputs to the second XOR gate are 1s.
 You can verify this fact by studying Table 5.3.
 The output carry of the full-adder is therefore produced by input A ANDed
with input B and A ⊕ B ANDed with Cin.
 These two terms are ORed, as expressed in Equation 6–4.
 This function is implemented and combined with the sum logic to form a
complete full-adder circuit, as shown in Figure 6–4(b).
Cout = AB + (A ⊕ B)Cin

58
Cont’d...

(b) Full-adder logic symbol

(a) Arrangement of two half-adders

adders to form a full-adder
full

Figure 5.25. Full-adder

adder implemented with half-adders.
half 59
 Cont’d...
 Example For each of the three full-adders
full in Figure 6–6, determine the
outputs for the inputs shown.

Figure 5.26.
 (a) The input bits are A = 1, B = 0, and C in = 0.
1 + 0 + 0 = 1 with no carry
Therefore, 1 and Cout = 0.
60
 Cont’d...
(b) The input bits are A = 1, B = 1, and C in = 0.
1 + 1 + 0 = 0 with a carry of 1
Therefore, 0 and Cout = 1.
(c) The input bits are A = 1, B = 0, and C in = 1.
1 + 0 + 1 = 0 with a carry of 1
Therefore, 0 and Cout = 1.

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 Cont’d...
Parallel Binary Adders
 Two or more full-adders are connected to form parallel binary adders.
 A single full-adder is capable of adding two 1-bit numbers and an input
carry.
 To add binary numbers with more than one bit, you must use additional
full-adders.
 When one binary number is added to another, each column generates a
sum bit and a 1 or 0 carry bit to the next column to the left, as illustrated
here with 2-bit numbers.

62
Cont’d...

Figure 5.27. Block diagram of a basic 2-bit

2 parallel adder using two full-adders.

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 Cont’d...
 To add two binary numbers, a full-adder
adder (FA) is required for each bit in
the numbers.
 So for 2-bit numbers, two adders are needed; for 4-bit numbers, four
adders are used; and so on.
 The carry output of each adder is connected to the carry input of the next
higher-order adder, as shown in Figure 5.27 for a 2-bit adder.
 Notice that either a half-adder can be used for the least significant position
or the carry input of a full-adder can be made 0 (grounded) because there
is no carry input to the least significant bit position.

64
 Cont’d...
 In Figure 6–7 the least significant bits (LSB) of the two numbers are
represented by A1 and B1. The next higher-order bits are represented by
A2 and B2.
 The three sum bits are 1, © 2, and © 3. Notice that the output carry from
the left-most full-adder becomes the most significant bit (MSB) in the
sum, © 3.

65
 Cont’d...
 Example Determine the sum generated by the 3-bit parallel adder in
Figure 6–8 and show the intermediate carries when the binary numbers
101 and 011 are being added.

Figure 5.28

66
 Cont’d...
Four-Bit Parallel Adders
 A group of four bits is called a nibble.
nibble
 A basic 4-bit parallel adder is implemented with four full-adder stages as
shown in Figure 5.30.

Figure 5.30 A 4-bit parallel adder. 67

 Cont’d...
Again, the LSBs (A1 and B1) in each number being added go into the right-
most full-adder; the higher-order bits are applied as shown to the
successively higher-order adders, with the MSBs (A4 and B4) in each
number being applied to the left-most full-adder.
full

68
 Cont’d...

 In terms of the method used to handle

carries in a parallel adder, there are
two types:
 the ripple carry adder and
 the carry look-ahead adder.
TABLE 6–3
Truth table for each stage of a 4-bit parallel
adder.

(b) Logic symbol

Figure 5.30 A 4-bit parallel adder. 69

 Cont’d...
Adder Expansion
 The 4-bit parallel adder can be expanded to handle the addition of two 8-
bit numbers by using two 4-bit adders.
adders

Figure 5.31 Cascading of two 4-bit

bit adders to form an 8-bit
8 adder. 70
 Cont’d...
Ripple Carry and Look-Ahead Carry Adders
 As mentioned in the last section, parallel adders can be placed into two
categories based on the way in which internal carries from stage to stage
are handled.
 Those categories are ripple carry and look-ahead carry.
 Externally, both types of adders are the same in terms of inputs and
outputs.
 The difference is the speed at which they can add numbers. The look-
ahead carry adder is much faster than the ripple carry adder.

71
 Cont’d...
The Ripple Carry Adder
 A ripple carry adder is one in which the carry output of each full-adder is
connected to the carry input of the next higher-order stage (a stage is one
full-adder).

Figure 5.32 Cascading of two 4-bit

4 adders to form an 8-bit adder. 72
 Cont’d...
The Look-Ahead Carry Adder
 A ripple carry adder is one in which the carry output of each full-adder is
connected to the carry input of the next higher-order stage (a stage is one
full-adder).

73
 Cont’d...
Comparators
 The basic function of a comparator is to compare the magnitudes of two
binary quantities to determine the relationship of those quantities.
 In its simplest form, a comparator circuit determines whether two numbers
are equal.
Equality
 The exclusive-NOR gate can be used as a basic comparator because its
output is a 0 if the two input bits are not equal and a 1 if the input bits are
equal.
 Figure 6–18 shows the exclusive-NOR
NOR gate as a 2-bit comparator.
74
Cont’d...

1 The input bits are equal. 0 The input bits are not equal.

0 The input bits are not equal. 1 The input bits are equal.

Figure 5.33 Basic comparator operation.

 In order to compare binary numbers containing two
bits each, an additional exclusive-NOR gate is
necessary
necessary.
A=B  General format: Binary number

HIGH indicates equality.

A → A1A0
B → B1B0
Figure 5.34. Logic diagram for equality
comparison of two 2-bit numbers. 75
 Cont’d...
Inequality
 Comparators can indicate which of the two binary numbers being
compared is the larger.
 To determine an inequality of binary numbers A and B,
you first examine the highest-order bit in each number.
The following conditions are possible:
1.If A3 = 1 and B3 = 0, number A is greater than
number B.
2.If A3 = 0 and B3 = 1, number A is less than number
B.
3.If A3 = B3, then you must examine the next lower bit
position for an inequality. Figure 5.35. Logic symbol for a 4-bit
76
comparator with inequality indication.
 Cont’d...
Decoders
 A decoder is a digital circuit that detects the presence of a specified
combination of bits (code) on its inputs and indicates the presence of
that code by a specified output level.
level
 In its general form, a decoder has n input lines to handle n bits and from
one to 2n output lines to indicate the presence of one or more n-bit
combinations.
 In this section, three fixed-function IC decoders are introduced.
 The basic principles can be extended to other types of decoders.

77
 Cont’d...
The Basic Binary Decoder
 Suppose you need to determine when a binary 1001 occurs on the inputs of
a digital circuit.
 An AND gate can be used as the basic decoding element because it
produces a HIGH output only when all of its inputs are HIGH.
 Therefore, you must make sure that all of the inputs to the AND gate are
HIGH when the binary number 1001 occurs;
this can be done by inverting the two middle bits (the 0s), as shown in
Figure 6–26.

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 Cont’d...

Figure 5.35. Decoding logic for the binary code 1001 with an active-HIGH
active output.

Example Determine the logic required to decode the binary number 1011 by producing a
HIGH level on the output.

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The 4-Bit Decoder
 In order to decode all possible combinations of four bits, sixteen decoding
gates are required (24 = 16).
 This type of decoder is commonly called either a 4-line-to-16-line decoder
because there are four inputs and sixteen outputs or a 1-of-16 decoder
because for any given code on the inputs, one of the sixteen outputs is
activated.
 A list of the sixteen binary codes and their corresponding decoding
functions is given in Table 6–4.

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TABLE 6–4
Decoding functions and truth table for a 4-line-to-16
16-line (1-of-16) decoder with active-LOW outputs.

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 If an active-LOW output is required for each decoded number, the entire
decoder can be implemented with NAND gates and inverters.
 In order to decode each of the sixteen binary codes, sixteen NAND gates are
required (AND gates can be used to produce active-HIGH outputs).

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Figure 5.36. Logic symbol for a 4-line-to-16-line
4 (1-of-16) decoder.
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Encoders
 An encoder is a combinational logic circuit that essentially performs a
“reverse” decoder function.
 An encoder accepts an active level on one of its inputs representing a digit,
such as a decimal or octal digit, and converts it to a coded output, such as
BCD or binary.
 Encoders can also be devised to encode various symbols and alphabetic
characters.
 The process of converting from familiar symbols or numbers to a coded
format is called encoding.
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The Decimal-to-BCD Encoder
 This type of encoder has ten inputs one for each decimal digit and four
outputs corresponding to the BCD code, as shown in Figure 6–36.
 This is a basic 10-line-to-4-line encoder.
encoder

Figure 5.37. Logic symbol for a decimal-to-BCD

decimal encoder. 84
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Multiplexers (Data Selectors)
 A multiplexer (MUX) is a device that allows digital information from
several sources to be routed onto a single line for transmission over that
line to a common destination.
 The basic multiplexer has several data-input
data lines and a single output line.
 It also has data-select inputs, which permit digital data on any one of the
inputs to be switched to the output line.
line
 Multiplexers are also known as data selectors.
selectors

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Multiplexers (Data Selectors)

Figure 5.38. Logic symbol for a 1-of-4 data

selector/multiplexer.

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Demultiplexers
 A demultiplexer (DEMUX) basically reverses the multiplexing function. It
takes digital information from one line and distributes it to a given number
of output lines.
 For this reason, the demultiplexer is also known as a data distributor. As
you will learn, decoders can also be used as demultiplexers.

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Parity Generators/Checkers
 Errors can occur as digital codes are being transferred from one point to
another within a digital system or while codes are being transmitted from one
system to another.
 The errors take the form of undesired changes in the bits that make up the
coded information; that is, a 1 can change to a 0, or a 0 to a 1, because of
component malfunctions or electrical noise.
noise
 In most digital systems, the probability that even a single bit error will occur
is very small, and the likelihood that more than one will occur is even
smaller.
 Nevertheless, when an error occurs undetected, it can cause serious problems
in a digital system.
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Basic Parity Logic
 In order to check for or to generate the proper parity in a given code, a
basic principle can be used:
 The sum (disregarding carries) of an even number of 1s is always 0, and
the sum of an odd number of 1s is always 1.
 Therefore, to determine if a given code has even parity or odd parity, all
the bits in that code are summed.

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Thank You !

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