MM54HC02/MM74HC02 Quad 2-Input NOR Gate

January 1988

MM54HC02/MM74HC02 Quad 2-Input

NOR Gate
General Description Features
These NOR gates utilize advanced silicon-gate CMOS tech- Y Typical propagation delay: 8 ns
nology to achieve operating speeds similar to LS-TTL gates Y Wide power supply range: 2 – 6V
with the low power consumption of standard CMOS inte- Y Low quiescent supply current: 20 mA maximum
grated circuits. All gates have buffered outputs, providing (74HC Series)
high noise immunity and the ability to drive 10 LS-TTL loads. Y Low input current: 1 mA maximum
The 54HC/74HC logic family is functionally as well as pin- Y High output current: 4 mA minimum
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground.

Connection and Logic Diagrams

Dual-In-Line Package

TL/F/5294 – 1
Top View

Order Number MM54HC02 or MM74HC02

TL/F/5294 – 2

C1995 National Semiconductor Corporation TL/F/5294 RRD-B30M105/Printed in U. S. A.

 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions
If Military/Aerospace specified devices are required, Min Max Units
please contact the National Semiconductor Sales Supply Voltage (VCC) 2 6 V
Office/Distributors for availability and specifications.
DC Input or Output Voltage 0 VCC V
Supply Voltage (VCC) b 0.5 to a 7.0V
(VIN, VOUT)
DC Input Voltage (VIN) b 1.5 to VCC a 1.5V
Operating Temp. Range (TA)
DC Output Voltage (VOUT) b 0.5 to VCC a 0.5V
MM74HC b 40 a 85 §C
Clamp Diode Current (IIK, IOK) g 20 mA
MM54HC b 55 a 125 §C
DC Output Current, per pin (IOUT) g 25 mA
Input Rise or Fall Times
DC VCC or GND Current, per pin (ICC) g 50 mA
(tr, tf) VCC e 2.0V 1000 ns
Storage Temperature Range (TSTG) b 65§ C to a 150§ C VCC e 4.5V 500 ns
Power Dissipation (PD) VCC e 6.0V 400 ns
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (TL) (Soldering 10 seconds) 260§ C

DC Electrical Characteristics (Note 4)

74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
VIH Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum High Level VIN e VIL
Output Voltage lIOUTl s20 mA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN e VIL
lIOUTl s4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
lIOUTl s5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum Low Level VIN e VIH or VIL
Output Voltage lIOUTl s20 mA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN e VIH or VIL
lIOUTl s4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
lIOUTl s5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA
Current
ICC Maximum Quiescent VIN e VCC or GND 6.0V 2.0 20 40 mA
Supply Current IOUT e 0 mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,
ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.

2
 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Guaranteed
Symbol Parameter Conditions Typ Units
Limit
tPHL, tPLH Maximum Propagation 8 15 ns
Delay

AC Electrical Characteristics VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)

74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
tPHL, tPLH Maximum Propagation 2.0V 45 90 113 134 ns
Delay 4.5V 9 18 23 27 ns
6.0V 8 15 19 23 ns
tTLH, tTHL Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
6.0V 7 13 16 19 ns
CPD Power Dissipation (per gate) 20 pF
Capacitance (Note 5)
CIN Maximum Input 5 10 10 10 pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.

3
MM54HC02/MM74HC02 Quad 2-Input NOR Gate
Physical Dimensions inches (millimeters)

Order Number MM54HC02J or MM74HC02J

NS Package J14A

Order Number MM74HC02N

NS Package N14A
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