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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY

COMPUTER ENGINEERING DEPARTMENT
COURSE INFORMATION SHEET
(For Theory Based Course)
Session: Fall-2024
Course Title: Digital Logic Design
Course Code: CE-215T
Credit Hours: 3+0
Semester: 3rd .
Pre-Requisites: Nil
Instructor Name: Mahjabeen Tahir, Jawaid Shabir, Yarsir
Zaheen, Jahangir Ahsan And Bushra Shabih
Email and Contact Information: matahir@ssuet.edu.pk (Room BS-02)
jshabir@ssuet.edu.pk (Room AS-08)
myasir@ssuetkhi.onmicrosoft.com
(Room AS-01)
jahsan@ssuet.edu.pk (Room BS-02)
bshabik@ssuetkhi.onmicrosoft.com
(Room AG-06)
WhatsApp Group CE-2023 FALL A, B C & D
Office Hours: 8:30am to 5:00pm

Synchronous/Asynchronous/Hybrid/Blended

Course Objective

Computer Engineering is applied reasoning which requires the ability to implement ideas through Software
and Hardware technology.
The Course is concerned with software and hardware. The course is designed in such a way to facilitate young
Computer Engineers to be able to work in the field confidently or take advanced studies and research work in
the related fields. The course is also supplemented through laboratory work and seminars. Ample computing
facilities with modern computers are available.

Course Outline

Basic understanding of Digital Systems and Binary Numbers, use of binary numbers and their manipulation.
Explanation of various number systems and conversion from and to different number systems. Introduction and
basic definitions of Boolean Algebra and Logic Gates with different types of logic gates. Axiomatic Definition of
Boolean Algebra, Basic Theorems and Properties of Boolean Algebra. Logic operations being performed by the
various logic gates. Introduction to Gate‐Level Minimization and explanation of multiple methods of Gate-Level
Minimization. Overview of Hardware Description Language and its implementation. Introduction to
Combinational Logic and combinational circuits along with their analysis and design procedures. Working of
 (SSUET/QR/111)
SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
COMPUTER ENGINEERING DEPARTMENT
adders, multipliers, comparators, encoders, decoders, and multiplexers demultiplexers. Understanding of
Synchronous Sequential Logic designs, storage elements like flip flops and latches.

Analysis of clocked sequential circuits and Synthesizable HDL Models of Sequential Circuits. Introduction to
Registers and Counters along with their different types like shift registers, ripple counters and Synchronous
counters. Details description of Memory and Programmable Logic. Analysis of memory decoding, error detection
and correction and programmable logic arrays. Introduction of Designing at the Register Transfer Level and
algorithmic state machines (ASMs).

COURSE LEARNING OUTCOMES (CLOS) AND ITS MAPPING WITH PROGRAM LEARNING
OUTCOMES(PLOS):

CLO Bloom’s
Course Learning Outcomes (CLOs) (PLOs)
No. Taxonomy
Describe binary arithmetic and its operations,
PLO_1
other radices, radix conversions, Boolean logic, C2
1 (Engineering
logic gates, their characteristics, and applications (Understanding)
knowledge)
and their timing response.
To apply knowledge of the course to solve
PLO_2
2 problems of designing variety of logic circuits C3 (Applying)
(Problem Analysis)
from digital integrated circuits.
To analyze a given gate network and obtain a
PLO_2
3 reduced or simplified switching expression for its C4 (Analyzing)
outputs and to generate its truth table. (Problem Analysis)

COMPLEX ENGINEERING PROBLEM:

Complex Engineering problem Included: No

Details

RELATIONSHIP BETWEEN ASSESSMENT TOOLS AND CLOS:

Assessment Tools CLO_1 (26) CLO_2(36) CLO_3(38)

Quizzes 12 % (3) 8% (3) 11% (4)

Assignments 12 % (3) 8% (3) 11% (4)

Midterm Exam 38 % (10) 28% (10) 26% (10)

Final Exam 38 % (10) 56% (20) 52% (20)

Total 100% 100% 100%
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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY
COMPUTER ENGINEERING DEPARTMENT

GRADING POLICY:

Assessment Tools Percentage

Quizzes 10%
Assignments 10%
Midterm Exam 30%
Final Exam 50%
TOTAL 100%

RECOMMENDED BOOKS:
1. Thomas L. Floyd “Digital Fundamentals”, Pearson, 10th Edition March 29, 2008, ISBN: 978-
0132359238
HTTPS://DRIVE.GOOGLE.COM/FILE/D/13G4PN2OZNSWP1W8LS3LRNV4VS61-3Q0W/VIEW?USP=SHARING

2. Digital Design, 4-th edition, M. Morris Mano, Michael D. Ciletti, Prentice Hall, ASIN:
011DBXA7E
https://drive.google.com/file/d/1HuCfGWxLr3svB9-BrGIvP22LUkHLaA2f/view?usp=sharing

REFERENCE BOOKS:
1. Digital Principals & Applications (Seventh Edition) by Donald P. Leech & Albert Paul Malvino
https://drive.google.com/file/d/1AktG2QkZ4ERf6WZc-lSnZ3NbzequFZPo/view?usp=sharing
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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY

COMPUTER ENGINEERING DEPARTMENT

LECTURE PLAN

Course Title: D i g i t a l L o g i c D e s i g n
Course Code: CE-215T

Week Lesson Required

Topics Key Date
No. Date Reading
8-10-2024 Basic understanding of Digital Systems Page 1-
to Assignment#1
1 and Binary Numbers, use of binary 08,18,
Quiz # 1
13-10-2024 numbers and their manipulation. 78-105
Explanation of various number systems
and conversion from and to different
number systems.
14-10-2024
Introduction and basic definitions of Boolean Page 18-
2 to Quiz # 1
20-10-2024 Algebra and Logic Gates with different types of 22,42-45
logic gates
21-10-2024 Axiomatic Definition of Boolean Algebra,
to Basic Theorems and Properties of Boolean Page 118-
3 27-10-2024 Algebra Quiz # 1
143

28-10-2024 Logic operations being performed by the various Page 118-

4 to logic gates. Introduction to Gate‐Level 143, 184- Assignment#1
03-11-2024 Minimization and explanation of multiple 190
methods of Gate-Level Minimization
04-11-2024 Introduction to Combinational Logic and
5 to combinational circuits along with their analysis Page 26-38 Quiz#2
10-11-2024 and design procedures
11-11-2024
Working of Adders, Multipliers, Comparators,
6 to Page 51-60 Quiz #2
17-11-2024 Encoders and Decoders
18-11-2024
Overview of Hardware Description Language and Page 144-
7 to Quiz #2
24-11-2024 its implementation. 150

25-11-2024 Quiz #2
Working of Multiplexer and De-Multiplexer Page 151-
8 to
1-12-2024 161
Mid Term Examination
9 (2-12-2024 To 7-12-2024)
9-12-2024 Page 208-
Understanding of Synchronous Sequential Logic
10 to 214, Assignment#2
15-12-2024 designs, storage elements like flip flops and 109,110
latches
16-12-2024
Analysis of clocked sequential circuits and Page 238-
11 to
246
Assignment#2
22-12-2024 Synthesizable HDL Models of Sequential
Circuits.

Page 4 of 5
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SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY

COMPUTER ENGINEERING DEPARTMENT

23-12-2024 Introduction to Registers like shift registers,

to Page 222-
12 SISO, SIPO, PISO, PIPO Assignment#3
29-012- 230, 247
2024
30-12-2024 Page 231-
to Introduction to Counters like Ripple Counters,
235,
05-01-2025 Synchronous Counters
13 394, Morris Assignment#3
Mano Page
167-172
06-01-2025 Details description of Memory and
to Programmable Logic. Analysis of memory
12-01-2025 decoding, error detection and correction and Page 266-
14 Quiz #3
290
programmable logic arrays.

13-01-2025 Introduction of Designing at the Register Page 266-

to Transfer Level and algorithmic state machines 290
15 19-01-2025 (ASMs). Page 305-
Quiz #3

310
16 20-01-2025 Revision
To
24-01-2025

Final Examination
(28-01-2025 to 8-02-2025)

Page 5 of 5