KIIT, Deemed to be University

School of Electronics Engineering

Digital System Design Laboratory [EC 29005]
EXPERIMENT - 6
Aim:
Design and simulation of modulo counter using Verilog behavioral modeling.
Design modulo counter using JK flip-flops.
Component/Software Used:
Component/Software Specification
ICs 7476, 7408, 7490, 7447

Bread Board, Power supply, LEDs, As per requirement

Resistors,Switches, Connecting wires
Software(s) Used Vivado 2016.1

Theory:
Flip-flop:
A counter is one of the most beneficial and adaptable components of a digital system .
The number of clock cycles can be counted using a counter that is powered by a clock.
The function of a counter is to count the number of clock pulses. Since the clock
pulses occur at known intervals, the counter can be used as an instrument for
measuring time and, therefore, period or frequency. It can be used to keep track of the
number of events that have occurred, such as the number of times a button has been
pressed or the number of pulses received from a sensor. Flip-flops are the basic
building blocks of a counter. There are basically two different types of counters
synchronous and asynchronous.
An asynchronous binary counter is also called a serial or ripple counter. The ripple
counter is simple and straightforward in operation and its construction requires a
minimum amount of hardware. It does, however, have a speed limit. Each flip-flop is
triggered by the previous flip-flop, and thus the counter has a cumulative settling time.
A synchronous binary counter is also called a parallel counter. An increase in the
speed of operation can be achieved by use of a parallel or synchronous counter. Here,
every flip-flop is triggered by the clock (synchronism), and thus the settling time is
simply equal to the delay time of a single flip-flop. Usually, the additional hardware is
required to get the speed improvement.
Counters can also be designed to count up or down, and the number of bits used to
represent the count will determine the maximum number of counts that can be
recorded. For example, a 4-bit counter can count from 0 to 15, while an 8-bit counter
can count from 0 to 255.

A digital counter is designed using a set of flip-flops (FFs) whose states change in
response to pulses applied at the input to the counter. A counter can be used as a
frequency divider to obtain waveform with frequencies that are specific fractions of
the clock frequency. They are also used to perform the timing function as in digital
watches, to create time delays, to produce non-sequential binary counts, to generate
pulse trains, and to act as frequency counters, etc.

The number of states or counting sequences through which a particular counter

advances before returning once again back to its original first state is called
the modulus (MOD). Modulus Counters, or simply MOD counters, are defined based
on the number of states that the counter will sequence through before returning back to
its original value. For example, a counter that counts from 002 to 112 in binary, that is
0 to 3 in decimal, has a modulus value of 4 ( 00 → 1 → 10 → 11, and return back to
00 ) so would therefore be called a modulo-4, or mod-4, counter. Note also that it has
taken four clock pulses to get from 00 to 11.

Design Procedure of a synchronous Counter:

1. Find the number of FFs (flip-flop) required.

The number of Flip-flops required can be determined by using the equation:
M ≤ 2N where, M is the MOD number and N is the number of required flip-flops.
2. Draw a state diagram for a given sequence.
3. Draw the FF transition table (excitation table).
4. Use K-map to derive the logic expressions of inputs of FFs.
5. Implemention using FFs and required combinational logic(gates).

Design of Mod-6 Counter using JK flip-flops:

To design the Mod-6 synchronous counter, contain six counter states (i.e from 0 to 5).
No of FFs required = 3 given by QA,QB and QC where QC is the MSB and QA is LSB to
design this counter.

Figure 6.1: State Diagram of MOD-6 synchronous counter

 Clock Present state Next State Inputs of the FFs
Sl. No. QC QB QA
pulse
QC QB QA QC QB QA JC KC JB KB JA KA
1 0 0 0 0
0 0 0 0 0 1 0 X 0 X 1 X
2 1 0 0 1
0 0 1 0 1 0 0 X 1 X X 1
3 2 0 1 0
0 1 0 0 1 1 0 X X 0 1 X
4 3 0 1 1
0 1 1 1 0 0 1 X X 1 X 1
5 4 1 0 0 1 0 0 1 0 1 X 0 0 X 1 X
6 5 1 0 1 1 0 1 0 0 0 X 1 0 X X 1

Table 6.1: Count table of MOD-6 counter Table 6.2: Excitation table of MOD-6 counter

K-map and logic expressions of inputs of FFs.

Note: The counts “110” and “111” need to be consider as Don’t care (X) in all K-maps.

JA QC , QB , QA KA QC , QB , QA
= (0,2,4) + d(1,3,5,6,7) = 1 = (0,2,4) + d(1,3,5,6,7) = 1

JB QC , QB , QA = 1 + d(2,3,6,7) KB QC , QB , QA = 3 + d(0,1,4,5,6,7)
= QC QA = QA
JC QC , QB , QA = 3 + d(4,5,6,7) KC QC , QB , QA = 5 + d(0,1,2,3,6,7)

= QB QA = QA

CLK 0

QA QB QC
Figure 6.2 Logic Diagram of synchronous binary MOD-6 counter
Outputs

+5V
13 15 11 5 +5V
13 15 5
GND QA QA QB QB Vcc GND
GND QC QQCC Vcc
Vcc

7476 (IC1) 7476 (IC2)

+5V JA KA JB KB JC KC +5V

4 16 9 12 1 6 1 4 16

+5V TTL +5V

3 6
14 7
GND
VCC

+5V 7408
1 2 4 5

Figure 6.3: Logic Diagram of synchronous binary MOD-6 counter using IC 7476 and IC 7408
 Procedure
For Software Simulation:
a) Create a module with required number of variables and mention it’s input/output.
b) Write the description of given Boolean function using operators or by using the
built in primitive gates.
c) Synthesize to create RTL Schematic.
d) Create another module referred as test bench to verify the functionality and to
obtain the waveform of input and output.
e) Follow the steps required to simulate the design and compare the obtained output
with the corresponding truth table.
f) Take the screenshots of the RTL schematic and simulated waveforms.

Note: Students need to write the Verilog HDL code by their own for which they can refer
Appendix - A if required.

For Hardware implementation:

a) Turn off the power of the Trainer Kit before constructing any circuit.
b) Connect power supply (+ 5 V DC) pin and ground pin to the respective pins of
the trainer kit.
c) Place the ICs properly on the bread board in the Trainer Kit.
d) Connect VCC and GND pins of each chip to the power supply and ground bus
strips on the bread board.
e) Connect the input and output pins of chips to the input switches and output LEDs
respectively in the Trainer Kit.
f) Check the connections before you turn on the power.
g) Apply various combinations of inputs according to truth tables and observe outputs
of LEDs.

Observation:
To be written by students
 Design Problem
Design and Simulation of decade counter using Verilog HDL.
Hardware implementation of a decade counter to display the digits 0 to 9 using IC 7490
(decade counter), IC 7447 (BCD to decimal decoder) and seven segment display.
Solution:
IC 7490 :The IC 7490 is 4-bit ripple type Decade Counter. It consists of four
master/slave flip-flops which are internally connected to provide a divide-by-two
section and a divide-by-five section. Each section has a separate clock input which
initiates state changes of the counter on the HIGH-to-LOW clock transition. State
changes of the Q outputs do not occur simultaneously because of internal ripple delays.
Therefore, decoded output signals are subject to decoding spikes and should not be
used for clocks or strobes.
A gated NAND asynchronous Master Reset (MR1 , MR2 ) is provided which overrides
clocks and resets (clears) all the flip-flops. A gated NAND asynchronous Master Set
(MS1 , MS2 ) .
Since the output from the divide-by-two section is not internally connected to the
succeeding stages, the devices may be operated in various counting modes.
BCD Decade (8421) Counter : The CLKB input must be externally connected to the QA
output. The CLKA input receives the incoming count producing a BCD count sequence.
Symmetrical Biquinary Divide-By-Ten Counter: The QC output must be externally
connected to the CLKA input. The input count is then applied to the CLKA input and a
divide-by ten square wave is obtained at output Q0.
Divide-By-Two and Divide-By-Five Counter: No external interconnections are
required. The first flip-flop is used as a binary element for the divide-by-two function
( CLKA as the input and QA as the output). The CLKB input is used to obtain binary
divide-by-five operation at the QC output.
The pin diagram and the logic symbol are given in Figure 6.4 and Figure 6.5
respectively. The count table is shown in Table 6.3. In Figure 6.5, QD (MSB) ,
QC ,QB andQA (LSB) are the outputs of the Decade Counter.

CLKB CLKA MS
CLKA
CLKA
MR1 NC
7490
CLKB
MR2 QA
7490 MR QA QB Qc QD
74
NC QD

Vcc GND
MS1 QB

MS2 QC

Figure 6.4: Pin diagram of IC 7490 Figure 6.5: Logic symbol of IC 7490
 Reset/Set inputs Outputs Outputs

MR1 MR2 MS1 MS2 QD QC QB QA Count QD QC QB QA

1 1 0 X 0 0 0 0 0 0 0 0 0

1 1 X 0 0 0 0 0 1 0 0 0 1

X X 1 1 1 0 0 1 2 0 0 1 0

X 0 X 1 Count 3 0 0 1 1

0 X 0 X Count 4 0 1 0 0

0 X X 0 Count 5 0 1 0 1

X 0 0 X Count 6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Table 6.3: Mode selection and Count table of 7490 (Decade counter)

IC 7447 :
The IC 7447 BCD-to-Seven segment decoder. The IC is stand-alone and requires no
external components other than the LED current limiting resistors. The output of the
IC has complete ripple blanking and requires no external driver transistors. It
incorporates automatic leading/or trailing-edge, zero blanking control (RBI and RBO).
A Lamp test of these devices may be performed at any time when the BI/RBO mode is
at a high logic level.

The 7447 decodes the input data in the pattern indicated in the Table 6.4 and the
segment identification illustration. If the input data is decimal zero, a LOW signal
applied to the RBI blanks the display and causes a multi digit display. For example, by
grounding the RBI of the highest order decoder and connecting itsBI/RBO to RBI of
the next lowest order decoder, etc., leading zeros will be suppressed. Similarly, by
grounding RBI of the lowest order decoder and connecting its BI/RBO to RBI of the
next highest order decoder, etc., trailing zeros will be suppressed. Leading and trailing
zeros can be suppressed simultaneously by using external gates, i.e.: by driving RBI of
a intermediate decoder from an OR gate whose inputs are BI/RBO of the next highest
and lowest order decoders. BI/RBO also serves as an unconditional blanking input.
The internal NAND gate that generates the RBO signal has a resistive pull-up, as
opposed to a totem pole, and thus BI/RBO can be forced LOW by external means,
using wired collector logic. A LOW signal thus applied to BI/RBO turns off all
segment outputs. This blanking feature can be used to control display intensity by
varying the duty cycle of the blanking signal. A LOW signal applied to LT turns on all
segment outputs, provided that BI/RBO is not forced LOW
 7447

Figure 6.4: Pin diagram of IC 7447

Decimal Inputs BI/ Outputs

or RBO Note
function LT RBI D C B A a b c d e f g

0 1 1 0 0 0 0 1 0 0 0 0 0 0 1
1 1 X 0 0 0 1 1 1 0 0 1 1 1 1
2 1 X 0 0 1 0 1 0 0 1 0 0 1 0
3 1 X 0 0 1 1 1 0 0 0 0 1 1 0
4 1 X 0 1 0 0 1 1 0 0 1 1 0 0
5 1 X 0 1 0 1 1 0 1 0 0 1 0 0
6 1 X 0 1 1 0 1 1 1 0 0 0 0 0
7 1 X 0 1 1 1 1 0 0 0 1 1 1 1
8 1 X 1 0 0 0 1 0 0 0 0 0 0 0
9 1 X 1 0 0 1 1 0 0 0 1 1 0 0 (1)

10 1 X 1 0 1 0 1 1 1 1 0 0 1 0
11 1 X 1 0 1 1 1 1 1 0 0 1 1 0
12 1 X 1 1 0 0 1 1 0 1 1 1 0 0
13 1 X 1 1 0 1 1 0 1 1 0 1 0 0
14 1 X 1 1 1 0 1 1 1 1 0 0 0 0
15 1 X 1 1 1 1 1 1 1 1 1 1 1 1
BI X X X X X X 0 1 1 1 1 1 1 1 (2)

RBI 1 0 0 0 0 0 0 1 1 1 1 1 1 1 ( 3)
LT 0 X X X X X 1 0 0 0 1 0 0 0 (4)

Table 6.4: Function table for IC 7447.

 Note (1): The blanking input (BI) must be open or held at a high logic level when output functions 0
through 15 are desired. The ripple-blanking input ( RBI ) must be open or high if blanking of
a decimal zero is not desired.
Note (2): When a low logic level is applied directly to the blanking input ( BI ), all segment outputs
are high regardless of the level of any other input.
Note (3): When ripple-blanking input ( RBI ) and inputs A, B, C, and D are at a low level with the
lamp test input high, all segment outputs go high and the ripple- blanking output (RBO) goes to
a low level (response condition).
Note (4): When the blanking-output ( BI/RBO ) is open or held high and a low is applied to the
lamp-test input, all segment outputs are low. Input (BI/RBO) is awire-AND logic serving as a
blanking input (BI) and /or ripple blanking output (RBO).

7447

Figure 6.5: Logic diagram of Decade counter using IC 7490 and IC 7447

Conclusion:
To be written by students.
Sample viva-voice questions

1. What is a counter?
2. What are the applications of counters?
3. What do you mean by presetting the counter?
4. What is the difference between asynchronous and synchronous counter?

5. What is the modulus of a counter?

6. What is the maximum modulus of a counter with 5 nos. of flip-flop?
7. In mod-20 counter, how many flip-flops are there?
8. What is a BCD counter?