Module – 2 : Assembly

Language Programming
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• CO2 Develop simple Assembly Language Programs(ALP) for
8051.
• M2.01 : Explain the structure of Assembly Language
programming. - Understanding
• M2.02 : Explain various addressing modes and types
of instructions. - Understanding
• M2.03 : Describe Jump, Loop, Call and single bit level
instructions. - Understanding
• M2.04 : Develop Assembly language programs for 8051.
- Applying

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• Contents:

• Introduction to Assembly Language programming of 8051 –

Structure, addressing modes, Types of instructions: -Data transfer,
arithmetic, logical, Compare, Rotate and swap instructions.
• Describe jump instruction- conditional and unconditional, call
instructions, calling subroutines. machine cycle, Delay generation.
• Single-Bit level instructions, Data serialization.

• Simple programs: - 8-bit Addition, 8-bit subtraction, multiplication,

division, ASCII to packed BCD, packed BCD to ASCII, BCD to
hex and hex to BCD, port reading and writing.

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 Assembly Language
• Provides ‘English like’ words called ‘mnemonics’
for the machine codes.
• For e.g.
– 0010 1111 (2FH), is a 8-bit instruction in
Machine language of 8051 to add two numbers
– ADD A, R7 is an Assembly language instruction
of 8051 to add two numbers

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 High-level Languages
• These languages are machine-independent
• Programmer may not know the internal details
of the CPU
• For e.g. Embedded C, Embedded Java etc.
• High-level language programs are translated to
machine code using a program called ‘Compiler’

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 Programming using ‘Assembly’
• A program called ‘Assembler’ is needed to
translate an Assembly Language program to
machine language
• Assembly language is ‘machine dependent’,
i.e. a low-level programming language
• A programmer must know the
– Internal details of CPU
– Instruction set

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 Programming Model of 8051
A • 8-bit Registers of 8051
B • These CPU Registers are used to
R0 store data temporarily
R1 • The Accumulator, register A, is
R2 used for all Arithmetic & Logic
operations.
R3
• Registers R0 – R7 are for general
R4
use
R5
R6
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 Assembly Language program
• Consists of a series of Assembly language
instructions
• Structure of Assembly Language
– Has four fields

[label:] mnemonic [operands] [;comments]

start: MOV R5, #25H ;load 25H in R5

MOV A, #5 ;load 5 in A
ADD A, R5 ;add A & R5
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 Assembler Directives

• are instructions to the Assembler program

• For e.g.
ORG 0H ;start at location 0
begin: MOV R2, #5 ;load 5 in R2
MOV R3, #6 ;load 6 in R3
MOV A, R2 ;copy R2 in A
ADD A, R3 ;add A & R3
MOV R4, A ;store result in R4
END ;end of asm source file
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 Assembler Directives Cont.
• ORG tells Assembler to place the following
opcodes starting at memory location 0
• END indicates to the Assembler the end of
the source code
• Assembler directives are also called pseudo-
instructions
• No opcodes are generated by assembler for
assembler directives

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 Assembling & Running a 8051 program

Editor Program

Assembler Program

Linker Program

OH Program

Hex file
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 CPU timing
• Most 8051 instructions are executed in one cycle.
• MUL (multiply) and DIV (divide) are the only
• instructions that take more than two cycles to complete
(four cycles)
• Normally two code bytes are fetched from the program
memory during every machine cycle.
• The only exception to this is when a MOVX instruction
is executed. MOVX is a one-byte, 2-cycle instruction
that accesses external data memory.
• During a MOVX, the two fetches in the second cycle
are skipped while the external data memory is being
addressed and strobed.
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 8051 Programming using
Assembly

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 Addressing modes

• The CPU can access data in

various ways, which are called
addressing modes
• The different ways in which a
source operand in an instruction
are known as the addressing
modes.
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 Types of Addressing Modes
• The 8051 provides a total of 5 distinct
addressing modes.
• Immediate
• Register
• Direct
• Register Indirect
• Indexed
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 Immediate Addressing Mode
• The source operand is a constant
– The immediate data must be preceded by the pound
sign, “#”
– Can load information into any registers, including
16-bit DPTR register

4521H

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 Immediate Addressing Mode (cont.)

• DPTR can also be accessed as two 8-bit

registers
– The high byte DPH and low byte DPL

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 Immediate Addressing Mode (cont.)

• We can use EQU directive to access

immediate data

• We can also use immediate addressing

mode to send data to 8051 ports
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 Register Addressing Mode
• Use registers to hold the data to be manipulated

• The source and destination registers must match

in size
– MOV DPTR,A will give an error
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 Register Addressing Mode (cont.)

• The movement of data between Rn registers is

not allowed
– MOV R4, R7 is invalid

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 Direct Addressing Mode
• It is most often used the direct addressing
mode to access RAM locations 30 – 7FH
– The entire 128 bytes of RAM can be accessed

– The register bank locations are accessed by the

register names

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 Direct Addressing Mode (cont.)

• Contrast this with immediate addressing mode

– There is no “#” sign in the operand

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 SFR Registers and Their Addresses
• The SFR (Special Function Register) can be
accessed by their names or by their addresses
– The SFR registers have addresses between 80H and
FFH
• Not all the address space of 80 to FF is used by SFR
• The unused locations 80H to FFH are reserved and must
not be used by the 8051 programmer

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 SFR Registers and Their Addresses
(cont.)

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 SFR Registers and Their Addresses
(cont.)

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 SFR Registers and Their Addresses
(cont.)

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 SFR Registers and Their Addresses
(cont.)

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 Stack and Direct Addressing
Mode
• Only direct addressing mode is allowed for
pushing or popping the stack
– PUSH A is invalid
• Pushing the accumulator onto the stack must be
coded as PUSH 0E0H

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 Register Indirect Addressing Mode
• A register is used as a pointer to the data
– Only register R0 and R1 are used for this purpose
– R2 – R7 cannot be used to hold the address of an
operand located in RAM
• When R0 and R1 hold the addresses of RAM locations,
they must be preceded by the “@” sign

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 44H

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 Register Indirect Addressing Mode
(cont.)
• The advantage is that it makes accessing data
dynamic rather than static as in direct addressing
mode
– Looping is not possible in direct addressing mode

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 Register Indirect Addressing Mode
(cont.)

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 Register Indirect Addressing Mode
(cont.)
• R0 and R1 are the only registers that can be used
for pointers in register indirect addressing mode
– Since R0 and R1 are 8 bits wide, their use is limited
to access any information in the internal RAM
• Whether accessing externally connected RAM or
on-chip ROM, we need 16-bit pointer
– In such case, the DPTR register is used

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 Indexed Addressing Mode and On-
chip ROM Access
• Indexed addressing mode is widely used in
accessing data elements of look-up table
entries located in the program ROM
– The instruction used for this purpose is
MOVC A,@A+DPTR
• Use instruction MOVC,
– “C” means code
• The contents of A are added to the 16-bit register
DPTR to form the 16-bit address of the needed
data
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 The 8051 Instruction Set

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 Instruction Groups
• The 8051 has 255 instructions
– Every 8-bit opcode from 00 to FF is used except for
A5.

• The instructions are grouped into 5 groups

– Arithmetic
– Logic
– Data Transfer
– Boolean
39 – Branching
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 Arithmetic Instructions
• ADD
– 8-bit addition between the accumulator (A) and a
second operand.
• The result is always in the accumulator.
• The CY flag is set/reset appropriately.

• ADDC
– 8-bit addition between the accumulator, a second
operand and the previous value of the CY flag.
• Useful for 16-bit addition in two steps.
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• The CY flag is set/reset appropriately.
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 Example – 16-bit Addition
Add 1E44H to 56CAH

CLR C ; Clear the CY flag

MOV A, #44H ; The lower 8-bits of the 1st number
ADD A, #CAH ; The lower 8-bits of the 2nd number
MOV R1, A ; The result 0EH will be in R1. CY = 1.
MOV A, #1EH ; The upper 8-bits of the 1st number
ADDC A, #56H ; The upper 8-bits of the 2nd number
MOV R2, A ; The result of the addition is 75H

The overall result: 750EH will be in R2:R1. CY = 0.

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 Arithmetic Instructions
• DA
– Decimal adjust the accumulator.
• Format the accumulator into a proper 2 digit packed BCD
number.
• Operates only on the accumulator.
• Works only after the ADD instruction.

• SUBB
– Subtract with Borrow.
• Subtract an operand and the previous value of the borrow
(carry) flag from the accumulator.
– A  A - <operand> - CY.
– The result is always saved in the accumulator.
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– The CY flag is set/reset appropriately.
 Example – BCD addition
Add 34 to 49 BCD

CLR C ; Clear the CY flag

MOV A, #34H ; Place 1st number in A
ADD A, #49H ; Add the 2nd number.
; A = 7DH
DA A ; A = 83H

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 Arithmetic Instructions
• INC
– Increment the operand by one.
• The operand can be a register, a direct address, an indirect
address, the data pointer.

• DEC
– Decrement the operand by one.
• The operand can be a register, a direct address, an indirect
address.

• MUL AB / DIV AB
– Multiply A by B and place result in A:B.
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– Divide A by B and place
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 Logical Operations
• ANL / ORL
– Work on byte sized operands or the CY flag.
• ANL A, Rn
• ANL A, direct
• ANL A, @Ri
• ANL A, #data
• ANL direct, A
• ANL direct, #data

• ANL C, bit
• ANL C, /bit
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 Logical Operations
• XRL
– Works on bytes only.

• CPL / CLR
– Complement / Clear.
– Work on the accumulator or a bit.
• CLR P1.2

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 Logical Operations
• RL / RLC / RR / RRC
– Rotate the accumulator.
• RL and RR without the carry
• RLC and RRC rotate through the carry.

• SWAP A
– Swap the upper and lower nibbles of the
accumulator.

• No compare instruction.
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– Built into conditional Baiju
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GS
instructions.
 Data Transfer Instructions
• MOV
– 8-bit data transfer for internal RAM and the SFR.
• MOV A, Rn
• MOV A, direct
• MOV A, @Ri
• MOV A, #data
• MOV Rn, A
• MOV Rn, direct
• MOV Rn, #data
• MOV direct, A
• MOV direct, Rn
• MOV direct, direct
• MOV direct, @Ri
• MOV direct, #data
• MOV @Ri, A
• MOV @Ri, direct
• MOV @Ri, #data
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 Data Transfer Operations
• MOV
– 1-bit data transfer involving the CY flag
• MOV C, bit
• MOV bit, C

• MOV
– 16-bit data transfer involving the DPTR
• MOV DPTR, #data

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 Data Transfer Instructions
• MOVC
– Move Code Byte
• Load the accumulator with a byte from program memory.
• Must use indexed addressing

• MOVC A, @A+DPTR
• MOVC A, @A+PC

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 Data Transfer Instructions
• MOVX
– Data transfer between the accumulator and a byte
from external data memory.
• MOVX A, @Ri
• MOVX A, @DPTR
• MOVX @Ri, A
• MOVX @DPTR, A

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 Data Transfer Instructions
• PUSH / POP
– Push and Pop a data byte onto the stack.
– The data byte is identified by a direct address from
the internal RAM locations.

• PUSH DPL
• POP 40H

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 Data Transfer Instructions
• XCH
– Exchange accumulator and a byte variable
• XCH A, Rn
• XCH A, direct
• XCH A, @Ri

• XCHD
– Exchange lower digit of accumulator with the lower digit of the
memory location specified.
• XCHD A, @Ri

• The lower 4-bits of the accumulator are exchanged with the lower 4-bits
of the internal memory location identified indirectly by the index
register.
• The upper 4-bits of each are not modified.
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 Boolean Operations
• This group of instructions is associated with the
single-bit operations of the 8051.
• This group allows manipulating the individual
bits of bit addressable registers and memory
locations as well as the CY flag.
– The P, OV, and AC flags cannot be directly altered.

• This group includes:

– Set, clear, and, or complement, move.
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– Conditional jumps. Baiju G S
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 Boolean Operations
• CLR
– Clear a bit or the CY flag.
• CLR P1.1
• CLR C

• SETB
– Set a bit or the CY flag.
• SETB A.2
• SETB C

• CPL
– Complement a bit or the CY flag.
• CPL 40H ; Complement bit 40 of the bit
addressable memory
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 Boolean Operations
• ORL / ANL
– OR / AND a bit with the CY flag.
• ORL C, 20H ; OR bit 20 of bit addressable
memory with the CY flag
• ANL C, /34H ; AND complement of bit 34 of
bit addressable memory with the CY
flag.

• MOV
– Data transfer between a bit and the CY flag.
• MOV C, 3FH ; Copy the CY flag to bit 3F of the
bit addressable memory.
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• MOV P1.2, C ; Copy the CY flag to bit 2 of P1.
 Boolean Operations
• JC / JNC
– Jump to a relative address if CY is set / cleared.

• JB / JNB
– Jump to a relative address if a bit is set / cleared.
• JB ACC.2, <label>

• JBC
– Jump to a relative address if a bit is set and clear the
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 Branching Instructions
• The 8051 provides four different types of
unconditional jump instructions:
– Short Jump – SJMP
• Uses an 8-bit signed offset relative to the 1st byte
of the next instruction.
– Long Jump – LJMP
• Uses a 16-bit address.
• 3 byte instruction capable of referencing any
location in the entire 64K of program memory.
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 Branching Instructions
– Absolute Jump – AJMP
• Uses an 11-bit address.
• 2 byte instruction
– The upper 3-bits of the address combine with the 5-bit opcode to
form the 1st byte and the lower 8-bits of the address form the 2nd
byte.
• The 11-bit address is substituted for the lower 11-
bits of the PC to calculate the 16-bit address of the
target.
– The location referenced must be within the 2K Byte memory page
containing the AJMP instruction.
– Indirect Jump – JMP
• JMP @A + DPTR
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 Branching Instructions
• The 8051 provides 2 forms for the CALL
instruction:
– Absolute Call – ACALL
• Uses an 11-bit address similar to AJMP
• The subroutine must be within the same 2K page.
– Long Call – LCALL
• Uses a 16-bit address similar to LJMP
• The subroutine can be anywhere.

– Both forms push the 16-bit address of the next

instruction on the stack and update the stack pointer.
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 Branching Instructions
• The 8051 provides 2 forms for the return
instruction:
– Return from subroutine – RET
• Pop the return address from the stack and continue
execution there.
– Return from ISV – RETI
• Pop the return address from the stack.
• Restore the interrupt logic to accept additional interrupts at
the same priority level as the one just processed.
• Continue execution at the address retrieved from the stack.
• The PSW is not automatically restored.
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 Branching Instructions
• The 8051 supports 5 different conditional jump
instructions.
– ALL conditional jump instructions use an 8-bit
signed offset.

– Jump on Zero – JZ / JNZ

• Jump if the A == 0 / A != 0
– The check is done at the time of the instruction execution.

– Jump on Carry – JC / JNC

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• Jump if the C flag is set / cleared.
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 Branching Instructions
– Jump on Bit – JB / JNB
• Jump if the specified bit is set / cleared.
• Any addressable bit can be specified.

– Jump if the Bit is set then Clear the bit – JBC

• Jump if the specified bit is set.
• Then clear the bit.

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 Branching Instructions
• Compare and Jump if Not Equal – CJNE
– Compare the magnitude of the two operands and
jump if they are not equal.
• The values are considered to be unsigned.
• The Carry flag is set / cleared appropriately.

• CJNE A, direct, rel

• CJNE A, #data, rel
• CJNE Rn, #data, rel
• CJNE @Ri, #data, rel
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 Branching Instructions
• Decrement and Jump if Not Zero – DJNZ
– Decrement the first operand by 1 and jump to the
location identified by the second operand if the
resulting value is not zero.

• DJNZ Rn, rel

• DJNZ direct, rel

• No Operation
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– NOP
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 Thank You

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