Editor, Compiler, Assembler, Linker & Loader

Editor Compiler / Assembler

L Library
Source Object
I
a
Higher Level
File File

d
Language Complier
N
n
Executable File
(Program)

u
Loader Memory
K
Assembly
Source
File
Object

g E F
in
File
Language Assembler
(Program)

er R

n
 In Editor we write programs for Microcontroller.

i e  Linker : It is linking all the object files of compiler

and assembler with the use of library.

g
 Programs may be written in Assembly Language or Higher Level

n
Language {C Language}.  It will generate executable files.

E
 By writing program we generate source file.  Loader: It is used to load executable files into the
 Assembler : It is used to convert Assembly language into memory of microcontroller.
machine code or object file. It also shows errors if any syntax  Once program is loaded into memory,
error is there in program. microcontroller can execute it as per the
 Complier : It is used to convert Higher Level language into requirement of USER.
machine code or object file. It also shows errors if any syntax
error is there in program. It also gives warnings if it is there
with programs.
 Data Types & Assembler Directives of 8051 𝝁𝝁C
 Data Types of 8051 microcontroller  END {Terminate}
 8051 Microcontroller supports Binary, Decimal and Hexadecimal  It is used to END source file {.asm file}.

a
data formats.  Anything after END directive will be ignored by assembler.

d
Example:  EQU {Equate}

n
MOV A,#00110110B ; A ← 00110110, Binary 00110110 is loaded  It is used to define constant without occupying a memory

MOV A,#15
in A which is equivalent of 36H. location.

F u
; A ← 15, Decimal 15 is loaded in A which is  It is used for constant values in program.

g
equivalent of 0FH. pp EQU 25H ;constant with pp label

i n
MOV A,#15H ; A ← 15H, Hexadecimal 15H is loaded in A. MOV R1, #pp ;constant loaded in R1
 Assembler Directives of 8051 microcontroller

er  DB {Define Byte}

e
 Assembler directives are also referred as pseudo Opcodes.  It is used to define byte data.

in
Assembler directives are not instructions, so they are not  Here, 8 bits {Byte} number can be decimal, Hexadecimal, Binary

g
executed by MPU, it is used to give directions to assembler. or ASCII number.

n
ORG 1000H
 ORG {Origin}

E
data1: DB 25 ;data 1 is defined by 25 decimal no.
ORG 1000H
data2: DB 25H ;data 2 is defined by 25H Hex no.
 ORG directives is used indicate beginning address.
data3: DB 00110011B ;data 3 is defined by 33H binary no.
 After writing ORG 1000H, program or data will be stored at
data4: DB ‘A’ ;data 4 is defined by ASCII of A.
1000H memory location.
data5: DB “EF” ;data 5 is defined by string of ASCII.
 Some assembler may use .ORG, so you need check that as well.
 If you don’t write H after number then it will consider decimal
address with ORG.
Engineering Funda Android App 8051 YT Playlist
 Addressing Modes of 8051 𝝁𝝁C
 Addressing mode: The Various formats of specifying the  Indirect Addressing Mode
operands are called addressing modes.  In this Addressing mode, address of operand will be given by
 Immediate Addressing Mode register.

a
 In this Addressing mode, data (1byte/2bytes) specified in  Internal and External RAM can be accessed by this mode.

d
instruction itself.  Internal RAM with 8bits of addressing, “@” is used here

n
 Data is specified by ‘#’ symbol before data in the instruction. MOV A,@R1 ; A ← [R1]

u
Example: MOV @R2,A ; [R2] ← A

F
MOV A,#15H ; A ← 15H  External RAM with 16bits of addressing by DPTR, “X” is used here

g
MOV DPTR,#1000H ; DPTR ← 1000H MOVX A,@DPTR ; A ← [DPTR]

in
 Register Addressing Mode MOVX @DPTR,A ; [DPTR] ← A

r
 In this Addressing mode, data is specified by registers in  External RAM with 8bits of addressing by R0 or R1

e
instruction. MOVX A,@R1 ; A ← [R1], If R1 is 25H then

e
 The permitted registers are A, R7, R6, … , R0. [R1] = [0025H]

i n
Example: MOVX @R0,A ; [R0] ← A, If R0 is 35H then

g
MOV A,R2 ; A ← R2 [R0] = [0035H]

n
MOV R2,A ; R2 ← A
 Indexed Addressing Mode

E
MOV R1,R2 ; Not Allowed with 8051,  This addressing mode is used to access data from code memory
 Direct Addressing Mode {Internal ROM or External ROM}.
 In this Addressing mode, address of operand is given in  In instruction, we use ‘C’ to operate with Indexed Addressing
instruction. mode.
 Only Internal RAM and SFR address are allowed. Example:
Example: MOVC A,@A+DPTR ; A ← [A+DPTR]
MOV A,35H ; A ← [35H] MOVC A,@A+PC ; A ← [A+PC]
MOV A,80H ; A ← [80H], Content of port 0 is [80H]
MOV 30H, 35H ; [30H] ← [35H]
 Arithmetic Instructions of 8051 𝝁𝝁C
 Addition instructions  Increment instructions
 ADD – It will Add Accumulator data with 8 bits & stores result  INC – It will increment Register, Pointer or data of memory

a
into A. locations.

d
ADD A, #50H ; A ← A + 50H INC A ;A←A+1

n
ADD A, R1 ; A ← A + R1 INC R1 ; R1 ← R1 + 1

u
ADD A, 17H ; A ← A + [17H] INC 25H ; [25H] ← [25H] + 1

F
ADD A, @R1 ; A ← A + [R1] INC @R1 ; [R1] ← [R1] + 1

g
 ADDC – It will Add Accumulator data with 8 bits along with INC DPTR; DPTR ← DPTR + 1

i n  Decrement instructions
Carry & stores result into A.
ADDC A, #50H ; A ← A + 50H + Carry

er  DEC – It will decrement Register, Pointer or data of memory

e
ADDC A, R1 ; A ← A + R1 + Carry locations.

in
ADDC A, 17H ; A ← A + [17H] + Carry DEC A ;A←A-1

g
ADDC A, @R1 ; A ← A + [R1] + Carry DEC R1 ; R1 ← R1 - 1
 Subtraction instructions
E n
 SUBB – It will Sub Accumulator data with 8 bits along with
Carry & stores result into A.
DEC 25H ; [25H] ← [25H] - 1
DEC @R1 ; [R1] ← [R1] - 1
DEC DPTR ; Does not exists
SUBB A, #50H ; A ← A - 50H - Carry
SUBB A, R1 ; A ← A - R1 - Carry
SUBB A, 17H ; A ← A - [17H] - Carry
SUBB A, @R1 ; A ← A - [R1] - Carry
Engineering Funda Android App 8051 YT Playlist
 Arithmetic Instructions of 8051 𝝁𝝁C
 Multiplication instruction Example:
 MUL AB – It will Multiply A and B and Answer will be stored in ADD A, R1 ; A ← A + R1

a
BA where B hold higher Byte and A hold Lower Byte. DA A ; BCD Addition Adjustment

d
MUL AB ; (𝑩𝑩𝑯𝑯𝑯𝑯𝑯𝑯𝑯𝑯𝑯𝑯𝑯𝑯 𝑩𝑩𝑩𝑩𝑩𝑩𝑩𝑩 𝑨𝑨𝑳𝑳𝑳𝑳𝑳𝑳𝑳𝑳𝑳𝑳 𝑩𝑩𝑩𝑩𝑩𝑩𝑩𝑩 ) ← A X B

n
AC = 1
 Division instruction
u
A = 56H A = 36H A = 38H

F
 DIV AB – It will Divide A by B and Answer remainder will be R1 = 23H R1 = 29H R1 = 29H

g
stored in B & Quotient will be stored in A. A = 79H A = 5FH A = 61H

in
DIV AB ; (𝑩𝑩𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹𝑹 𝑨𝑨𝑸𝑸𝑸𝑸𝑸𝑸𝑸𝑸𝑸𝑸𝑸𝑸𝑸𝑸𝑸𝑸 ) ← A / B 06H 06H
 Decimal Adjustment instruction
er A = 65H A = 67H

e
 DA A – It will be used after ADD instruction.

i n
 It is used to convert that given Hex addition in BCD addition. 11

g
 Normal Addition is done by ADD that is Binary or Hex Addition. A = 60H A = 99H

n
 After when you use DA A, it adjust that addition in BCD form. R1 = 70H R1 = 99H

E
 DA A performs following adjustments to show given addition in
A = D0H A = 32H
BCD addition.
60H 06H
 If Lower Nibble > 9 or Auxiliary Carry is 1 then Add 06H with A
 If Higher Nibble > 9 or Carry is 1 then Add 60H with A 60H
A = 30H
Carry = 1 AL = 98H
Carry = 1
 Logical Instructions of 8051 𝝁𝝁C
 Logic AND instructions  Logic XOR instructions
 ANL – It will perform logic AND in between two 8 bits numbers.  XRL – It will perform logic XOR in between two 8 bits numbers.
ANL A, #50H ; A ← A AND 50H XRL A, #50H

d a ; A ← A XOR 50H

n
ANL A, R1 ; A ← A AND R1 XRL A, R1 ; A ← A XOR R1

u
ANL A, 17H ; A ← A AND [17H] XRL A, 17H ; A ← A XOR [17H]

F
ANL A, @R1 ; A ← A AND [R1] XRL A, @R1 ; A ← A XOR [R1]

g
ANL 25H, A ; [25H] ← [25H] AND A XRL 25H, A ; [25H] ← [25H] XOR A

r in
ANL 25H, #50H ; [25H] ← [25H] AND 50H XRL 25H, #50H ; [25H] ← [25H] XOR 50H

e
 Logic OR instructions  Other Logical instructions

i n e
 ORL – It will perform logic OR in between two 8 bits numbers.  CPL A – It will perform 1’s compliment of A, meant NOT
operation of A.

g
ORL A, #50H ; A ← A OR 50H

n
ORL A, R1 ; A ← A OR R1  CLR A – It will Clear Accumulator. So A = 00H after instruction.

E
ORL A, 17H ; A ← A OR [17H]  SWAP A – It will swap lower Nibble and higher nibble of A,
ORL A, @R1 ; A ← A OR [R1] means if A = 78H after instruction A = 87H.
ORL 25H, A ; [25H] ← [25H] OR A  NOP – It will do nothing, it is used to generate delay only. NOP
ORL 25H, #50H ; [25H] ← [25H] OR 50H means No Operation performed.
 Rotate Instructions of 8051 𝝁𝝁C
 Rotate without Carry instructions  Rotate with Carry instructions
 RR A – It will perform rotate Right of A without carry by 1 bit.  RRC A – It will perform rotate Right of A with carry by 1 bit.
 If initially A = 46H & Carry = 1  If initially A = 46H & Carry = 1

1 0 1 0 0 0 1 1 0 1

d
0
a 1 0 0 0 1 1 0
Carry Carry

un
F
 After Instruction  After Instruction

0 0 0 1 0 0 0 1 1

in g 0 1 0 1 0 0 0 1 1

r
Carry Carry

e
 After Instruction, A = 23H and Carry = 0  After Instruction, A = A3H and Carry = 0

i n e
 RL A – It will perform rotate Left of A without carry by 1 bit.  RLC A – It will perform rotate Left of A with carry by 1 bit.

g
 If initially A = 46H & Carry = 1  If initially A = 46H & Carry = 1

1
Carry
 After Instruction
0 1 0 0

E n 0 1 1 0 1
Carry
 After Instruction
0 1 0 0 0 1 1 0

0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1
Carry Carry
 After Instruction, A = 8CH and Carry = 0  After Instruction, A = 8DH and Carry = 0
 Boolean Instructions of 8051 𝝁𝝁C
 Set, Clear & Complement Carry instructions  Logic AND & OR Bit instructions
 SETB C – It will make Carry Flag = 1  ANL C, b – It will do logic AND between Carry flag and bit b and
 CLR C – It will make Carry Flag = 0 result will be stored into Carry flag.
 CPL C – It will Complement Carry Flag ANL C,P0.2

d a
; C ← C AND P0.2

n
 Set, Clear & Complement Bit instructions ANL C,07H ; C ← C AND [07H] bit in RAM

u
 ANL C, /b – It will do logic AND between Carry flag and

F
 SETB – It will make given bit = Logic ‘1’
complemented bit b and result will be stored into Carry flag.
SETB P0.2 ; P0.2 ← 1

g
ANL C,/P0.2 ; C ← C AND {NOT} P0.2

in
SETB 07H ; 07H bit location in RAM ← 1 ANL C,/07H ; C ← C AND {NOT} [07H] bit in RAM

r
 CLR – It will make given bit = Logic ‘0’

e
 ORL C, b – It will do logic OR between Carry flag and bit b and

e
CLR P0.2 ; P0.2 ← 0 result will be stored into Carry flag.

n
ORL C,P0.2 ; C ← C OR P0.2

i
CLR 07H ; 07H bit location in RAM ← 0

g
 CPL – It will make given bit = complement of initial value ORL C,07H ; C ← C OR [07H] bit in RAM

n
CPL P0.2 ; P0.2 will get complemented  ORL C, /b – It will do logic OR between Carry flag and

E
complemented bit b and result will be stored into Carry flag.
CPL 07H ; 07H bit location in RAM will
ORL C,/P0.2 ; C ← C OR {NOT} P0.2
get complemented
ORL C,/07H ; C ← C OR {NOT} [07H] bit in RAM
 Move Bit instructions
MOV C,P0.2 ; Carry Flag ← P0.2
MOV P0.2,C ; P0.2 ← Carry Flag
MOV 07H,C ; [07H] bit in RAM ← Carry Flag
 Data Transfer Instructions of 8051 𝝁𝝁C
 Move instructions  Stack instructions
 MOV – It will move data from one location to another location.  PUSH – It will store data on stack

a
MOV A, #50H ; A ← 50H  In PUSH, 1st SP will increment by 1, then it will store data on stack.

d
MOV A, R1 ; A ← R1  POP – It will load data from stack

n
MOV A, 50H ; A ← [50H]  In POP, 1st load data from stack, then it will decrement SP by 1.

u
MOV A, @R1 ; A ← [R1] PUSH R1 ; R1 will be stored on stack

F
MOV R1, A ; R1 ← A PUSH 25H ; [25H] will be stored on stack

g
MOV R1, #50H ; R1 ← 50H POP R1 ; R1 will be loaded from stack

in
MOV R1, 50H ; R1 ← [50H] POP 25H ; [25H] will be loaded from stack
MOV 50H, R1 ; [50H] ← R1

er  Exchange instructions

e
MOV 50H, 40H ; [50H] ← [40H]  XCH – It will exchange the mentioned two data.

n
MOV 50H, @R1 ; [50H] ← [R1]

i
XCH A, R0 ; A ←→ R0

g
MOV @R1, A ; [R1] ← A
XCH A, 25H ; A ←→ [25H]

n
MOV @R1, #25H ; [R1] ← 25H
XCH A, @R1 ; A ←→ [R1]

E
MOV @R1, 25H ; [R1] ← [25H]
MOV DPTR,#2525H; DPTR ← 2525H  XCHD A, @Rx – It will exchange lower Nibble of the mentioned
MOVX A, @R1 ; A ← [00-R1] from External RAM two data.
MOVX A, @DPTR ; A ← [DPTR] from External RAM XCHD A, @R1 ; A ←→ [R1] only Lower Nibble.
MOVX @R1, A ; [00-R1] ← A for External RAM
MOVX @DPTR, A ; [DPTR] ← A for External RAM
MOVC A,@A+DPTR; A ← [A+DPTR] for ROM
MOVC A,@A+PC ; A ← [A+PC] for ROM
 Brach Operations of 8051 𝝁𝝁C
{SJMP, AJMP & LJMP}
Parameters SJMP AJMP
d a LJMP
Name  SJMP – Short Jump

un
 AJMP – Absolute Jump  LJMP – Long Jump
Syntax  SJMP Label1  AJMP Label2

g F  LJMP Label3

in
Range  -128 to +127 locations, because  Maximum range is 2KB.  Maximum range is 64KB.

r
of Label1 is 8 bits signed No.
Size  2 Bytes {1 Opcode + 1 Label}

e e
 2 Bytes {1 Opcode + 1 Label}  3 Bytes {1 Opcode + 2 Label}

i n
Address  PC = PC of Next instruction +  PC = 1st 5 bits same of PC +  PC = 16 bits Label3

g
calculation Label1 3bits of AJMP + 8 bits of Label2
Instructions

Usage
 SJMP

E n
 All conditional Jump available
 Generally, we use it in same
 AJMP
 ACALL
 LJMP
 LCALL
 We use it for jump within same  We use it to jump anywhere
program jump with many page of 2KB. in 64KB of 8051 𝝁𝝁C.
conditions and unconditional.  64Kb is bisected into 32 pages
of 2KB
 JMP and CALL of 8051 𝝁𝝁C
Program Program

d a PUSH PC ; PA on stack
PC ← L1

n
PC ← L1

u
LJMP L1 L1: Address LCALL L1 L1: Address

F
Physical

g
Address of Next

in
instruction in PC.

r
POP PC ; PA on PC RET
JMP

e e CALL

given program.

g i n
 Here, we just jump to new location and then we move on with  Here, we jump to new location for subroutine, after subroutine
we come back to that location again.

E
 JMP doesn’t stores branch location.
n
 No need of retrieve back to branch location.  By RET at the end of subroutine, it will retrieve back to branch
location.
 CALL stores branch location on Stack.
 In 8051, JMP is of three types:  In 8051, CALL is of two types:
 SJMP, AJMP and LJMP  ACALL and LCALL
 In 8051, SJMP can be conditional and unconditional.  In 8051, we have only unconditional CALL instructions.
 JMP is used for program logic only.  CALL is used for function execution in main program.
 RET & RETI Instructions of 8051 𝝁𝝁C
RET RETI
Used with normal subroutine.
d a
Used with ISR – Interrupt Service
Routine
un
With RET, 8051 just return back to
F
With RETI, 8051 return back to main
g
main program from subroutine.

erin
program + It will Enable Interrupt by
making EA = 1.
Operation:
i n e Operation:
POP PC ; PCH ← [SP]
n g POP PC ; PCH ← [SP]
E
; PCL ← [SP-1]
; SP ← SP - 2
; PCL ← [SP-1]
; SP ← SP – 2
EA ← 1
 Branch Instructions of 8051 𝝁𝝁C
 Unconditional Jump instructions  Conditional Jump instructions {All are SJMP}
 SJMP Label – It jump to location with respect to Label {8 bits}.  DJNZ R3, Label – It will decrement R3, and jump to the Label

a
 Range of SJMP is -128 to +127 locations. only if R3 is not Zero.

d
 Final Address will be PC = PC + Label  DJNZ 25H, Label – It will decrement [25H], and jump to the

n
 AJMP Label – It jump to location with respect to Label {8 bits}. Label only if [25H] is not Zero.

u
 Range of AJMP is 2KB.  CJNE A, #25H, Label – It will compare A with #25H and jump to

F
 Final Address will be PC = 1st 5 bits of PC + 3 bits of AJMP + Label. the Label only if A and #25H are not equal.

g
 LJMP Label – It jump to location at Label {16 bits}.  CJNE A, 25H, Label – It will compare A with [25H] and jump to

in
 It can jump anywhere in 64KB memory of 8051. the Label only if A and [25H] are not equal.

r
 Final Address will be PC = Label  CJNE R2, #25H, Label – It will compare R2 with #25H and jump

e
 JMP @A+DPTR – It will jump to the location A + DPTR. to the Label only if R2 and #25H are not equal.

e
 CJNE @R2, #25H, Label – It will compare [R2] with #25H and
 Boolean Conditional Jump instructions

i n
jump to the Label only if [R2] and #25H are not equal.
{All are SJMP}
g
 JC Label – It will jump to Label if with previous instruction, carry

n
 JB P0.0, Label – Jump to Label Only if P0.0 = 1 flag is 1.

E
 JNB P0.0, Label – Jump to Label Only if P0.0 = 0  JNC Label – It will jump to Label if with previous instruction,
 JBC P0.0, Label – Jump to Label Only if P0.0 = 1 and also make carry flag is 0.
P0.0 = 0  JZ Label – It will jump to Label if with previous instruction, Zero
flag is 1.
 JNZ Label – It will jump to Label if with previous instruction,
Zero flag is 0.