EVALUATION KIT AVAILABLE

MAX1452 Low-Cost Precision Sensor

Signal Conditioner

General Description Benefits and Features

The MAX1452 is a highly integrated analog-sensor sig- ●● Single-Chip, Integrated Analog Signal Path Reduces
nal processor optimized for industrial and process con- Design Time and Saves Space in a Complete
trol applications utilizing resistive element sensors. The Precision Sensor Solution
MAX1452 provides amplification, calibration, and temper- • Provides Amplification, Calibration, and
ature compensation that enables an overall performance Temperature Compensation
approaching the inherent repeatability of the sensor. The • Fully Analog Signal Path
fully analog signal path introduces no quantization noise • Accommodates Sensor Output Sensitivities from
in the output signal while enabling digitally controlled trim- 4mV/V to 60mV/V
ming with the integrated 16-bit DACs. Offset and span are • Single-Pin Digital Programming
calibrated using 16-bit DACs, allowing sensor products to • No External Trim Components Required
be truly interchangeable. • 16-Bit Offset and Span Calibration Resolution
The MAX1452 architecture includes a programmable • Supports Both Current and Voltage Bridge Excitation
sensor excitation, a 16-step programmable-gain ampli- • Fast 150μs Step Response
fier (PGA), a 768-byte (6144 bits) internal EEPROM, four • On-Chip Uncommitted Op Amp
16-bit DACs, an uncommitted op amp, and an on-chip ●● On-Chip Lookup Table Supports Multipoint
temperature sensor. In addition to offset and span com- Calibration Temperature Correction Improving
pensation, the MAX1452 provides a unique temperature System Performance
compensation strategy for offset TC and FSOTC that was ●● Secure-Lock™ Prevents Data Corruption
developed to provide a remarkable degree of flexibility
while minimizing testing costs. ●● Low 2mA Current Consumption Simplifies Power-
Supply Design in 4–20mA Applications
The MAX1452 is packaged for the commercial, industrial,
and automotive temperature ranges in 16-pin SSOP/
TSSOP and 24-pin TQFN packages.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
Customization
MAX1452CAE+ 0°C to +70°C 16 SSOP
Maxim can customize the MAX1452 for high-volume
dedicated applications. Using our dedicated cell library MAX1452EAE+ -40°C to +85°C 16 SSOP
of more than 2000 sensor-specific functional blocks, MAX1452AAE+ -40°C to +125°C 16 SSOP
Maxim can quickly provide a modified MAX1452 solution. MAX1452AUE+ -40°C to +125°C 16 TSSOP
Contact Maxim for further information.
MAX1452ATG+ -40°C to +125°C 24 TQFN-EP*
Applications MAX1452C/D 0°C to +70°C Dice**
●● Pressure Sensors
+Denotes a lead(Pb)-free/RoHS-compliant package.
●● Transducers and Transmitters
*EP = Exposed pad.
●● Strain Gauges **Dice are tested at TA = +25°C, DC parameters only.
●● Pressure Calibrators and Controllers
●● Resistive Elements Sensors Detailed Block Diagram and Pin Configurations appear at
●● Accelerometers the end of data sheet.
●● Humidity Sensors
Outputs Supported
●● 4–20mA
●● 0 to +5V (Rail-to-Rail)
●● +0.5V to +4.5V Ratiometric Secure-Lock is a trademark of Maxim Integrated Products, Inc.
●● +2.5V to ±2.5V

19-1829; Rev 5; 4/15

MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Absolute Maximum Ratings

Supply Voltage, VDD to VSS.........................................-0.3V, +6V Operating Temperature:
Supply Voltage, VDD to VDDF................................-0.5V to +0.5V MAX1452CAE+/MAX1452C/D.............................0°C to +70°C
All Other Pins...................................(VSS - 0.3V) to (VDD + 0.3V) MAX1452EAE+.................................................-40°C to +85°C
Short-Circuit Duration, FSOTC, OUT, BDR, MAX1452AAE+...............................................-40°C to +125°C
AMPOUT................................................................Continuous MAX1452AUE+..............................................-40°C to +125°C
Continuous Power Dissipation (TA = +70°C) MAX1452ATG+...............................................-40°C to +125°C
16-Pin SSOP/TSSOP (derate 8.00mW/°C above +70°C)..640mW Junction Temperature.......................................................+150°C
24-Pin TQFN (derate 20.8mW/°C above +70°C).................1.67W Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Electrical Characteristics
(VDD = VDDF = +5V, VSS = 0V, TA = +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GENERAL CHARACTERISTICS
Supply Voltage VDD 4.5 5.0 5.5 V
EEPROM Supply Voltage VDDF 4.5 5.0 5.5 V
Supply Current IDD (Note 1) 2.0 2.5 mA
Maximum EEPROM Erase/
IDDFW 30 mA
Write Current
Maximum EEPROM Read
IDDFR 12 mA
Current
Oscillator Frequency fOSC 0.85 1 1.15 MHz
ANALOG INPUT
Input Impedance RIN 1 MI
Input-Referred Offset Tempco (Notes 2, 3) P1 µV/°C
Input-Referred Adjustable
Offset TC = 0 at minimum gain (Note 4) P150 mV
Offset Range
Percent of +4V span, VOUT = +0.5V to
Amplifier Gain Nonlinearity 0.01 %
4.5V
Specified for common-mode voltages
Common-Mode Rejection Ratio CMRR 90 dB
between VSS and VDD (Note 2)
Input Referred Adjustable 4 to
(Note 5) mV/V
FSO Range 60
ANALOG OUTPUT
Differential Signal-Gain Range Selectable in 16 steps 39 to 234 V/V
Configuration [5:2] 0000bin 34 39 46
Configuration [5:2] 0001bin 47 52 59
Differential Signal Gain Configuration [5:2] 0010bin 58 65 74 V/V
Configuration [5:2] 0100bin 82 91 102
Configuration [5:2] 1000bin 133 143 157
Maximum Output-Voltage Swing No load from each supply 0.02 V

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Signal Conditioner

Electrical Characteristics (continued)

(VDD = VDDF = +5V, VSS = 0V, TA = +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output-Voltage Low IOUT = 1mA sinking, TA = TMIN to TMAX 0.100 0.20 V
Output-Voltage High IOUT = 1mA sourcing, TA = TMIN to TMAX 4.75 4.87 V
Output Impedance at DC 0.1 Ω
ΔVOUT/
Output Offset Ratio 0.90 1.05 1.20 V/V
ΔOffset
ΔVOUT/
Output Offset TC Ratio 0.9 1 1.2 V/V
ΔOffset TC
Step Response and IC
150 µs
(63% Final Value)
Maximum Capacitive Load 1 µF
DC to 1kHz (gain = minimum, source
Output Noise 0.5 mVRMS
impedance = 5kΩ VDDF filter)
BRIDGE DRIVE
Bridge Current IBDR RL = 1.7kΩ 0.1 0.5 2 mA
Current Mirror Ratio AA RISOURCE = internal 10 12 14 A/A
VSPAN Range (Span Code) TA = TMIN to TMAX 4000 C000 hex
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution 16 Bits
ΔVOUT/
ODAC Bit Weight DAC reference = VDD = +5.0V 76 µV/bit
ΔCode
ΔVOUT/
OTCDAC Bit Weight DAC reference = VBDR = +2.5V 38 µV/bit
ΔCode
ΔVOUT/
FSODAC Bit Weight DAC reference = VDD = +5.0V 76 µV/bit
ΔCode
ΔVOUT/
FSOTCDAC Bit Weight DAC reference = VBDR = +2.5V 38 µV/bit
ΔCode
COARSE OFFSET DAC
IRODAC Resolution Including sign 4 Bits
ΔVOUT/ Input referred, DAC reference =
IRODAC Bit Weight 9 mV/bit
ΔCode VDD = +5.0V (Note 6)
FSOTC BUFFER
VSS
Minimum Output-Voltage Swing No load V
+ 0.1
Maximum Output-Voltage
No load VDD - 1.0 V
Swing
Current Drive VFSOTC = +2.5V -40 +40 µA
INTERNAL RESISTORS
Current-Source Reference
RISRC 75 kΩ
Resistor

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Electrical Characteristics (continued)

(VDD = VDDF = +5V, VSS = 0V, TA = +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Current-Source Reference
ΔRISRC 1300 ppm/°C
Resistor Temperature Coefficient
FSOTC Resistor RFTC 75 kΩ
FSOTC Resistor Temperature
ΔRFTC 1300 ppm/°C
Coefficient
TEMPERATURE-TO-DIGITAL CONVERTER
Temperature ADC Resolution 8 Bits
Offset P3 LSB
Gain 1.45 °C/bit
Nonlinearity P0.5 LSB
Lowest Digital Output 00 hex
Highest Digital Output AF hex
UNCOMMITTED OP AMP
Open-Loop Gain RL = 100kΩ 90 dB
Input Common-Mode Range VSS VDD V
VSS + VDD -
Output Swing No load, TA = TMIN to TMAX V
0.02 0.02
Output-Voltage High 1mA source, TA = TMIN to TMAX 4.85 4.90 V
Output-Voltage Low 1mA sink, TA = TMIN to TMAX 0.05 0.15 V
Offset VIN+ = +2.5V, unity-gain buffer -20 +20 mV
Unity-Gain Bandwidth 2 MHz
EEPROM
Maximum Erase/Write Cycles (Note 7) 10k Cycles
Minimum Erase Time (Note 8) 6 ms
Minimum Write Time 100 µs
Note 1:
Excludes sensor or load current.
Note 2:
All electronics temperature errors are compensated together with sensors errors.
Note 3:
The sensor and the MAX1452 must be at the same temperature during calibration and use.
Note 4:
This is the maximum allowable sensor offset.
Note 5:
This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full span output of +4V and a bridge volt-
age range of +1.7V to +4.25V.
Note 6: Bit weight is ratiometric to VDD.
Note 7: Programming of the EEPROM at room temperature is recommended.
Note 8: Allow a minimum of 6ms elapsed time before sending any command.

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Typical Operating Characteristics

(VDD = +5V, TA = +25°C, unless otherwise noted.)

OFFSET DAC DNL AMPLIFIER GAIN NONLINEARITY

5.0 5.0

OUTPUT ERROR FROM STRAIGHT LINE (mV)

MAX1452 toc01

MAX1452 toc02
ODAC = 6250hex
OTCDAC = 0
FSODAC = 4000hex
2.5 2.5 FSOTCDAC = 8000hex
PGA INDEX = 0
IRO = 2
DNL (mV)

0 0

-2.5 -2.5

-5.0 -5.0
0 10k 20k 30k 40k 50k 60k 70k -50 -40 -30 -20 -10 0 10 20 30 40 50
DAC CODE INPUT VOLTAGE [INP - INM] (mV)

OUTPUT NOISE
MAX1452 toc03

OUT
10mV/div

400µs/div
C = 4.7µF, RLOAD = 1kΩ

Pin Description
PIN
NAME FUNCTION
SSOP/TSSOP TQFN-EP
1 1 ISRC Bridge Drive Current Mode Setting
High ESD and Scan Path Output Signal. May need a 0.1µF capacitor, in
2 2 OUT
noisy environments. OUT may be parallel connected to DIO.
3 3 VSS Negative Supply Voltage
4 4 INM Bridge Negative Input. Can be swapped to INP by configuration register.
5 5 BDR Bridge Drive
6 6 INP Bridge Positive Input. Can be swapped to INM by configuration register.
7 7 VDD Positive Supply Voltage. Connect a 0.1µF capacitor from VDD to VSS.
8, 9, 13, 16, 20, 22, No Connection. Not internally connected; leave unconnected (TQFN
— N.C.
23, 24 package only).
8 10 TEST Internally Connected. Connect to VSS.

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Signal Conditioner

Pin Description (continued)

PIN
NAME FUNCTION
SSOP/TSSOP TQFN-EP
Positive Supply Voltage for EEPROM. Connect a 1µF capacitor from
9 11 VDDF VDDF to VSS. Connect VDDF to VDD or for improved noise performance
connect a 30Ω resistor to VDD.
10 12 UNLOCK Secure-Lock Disable. Allows communication to the device.
11 14 DIO Digital Input Output. DIO allows communication with the device.
12 15 CLK1M 1MHz Clock Output. The output can be controlled by a configuration bit.
13 17 AMPOUT Uncommitted Amplifier Output
14 18 AMP- Uncommitted Amplifier Negative Input
15 19 AMP+ Uncommitted Amplifier Positive Input
16 21 FSOTC Full Span TC Buffered Output
— — EP Exposed Pad (TQFN Only). Internally connected; connect to VSS.

Detailed Description The single pin, serial Digital Input-Output (DIO) communi-
The MAX1452 provides amplification, calibration, and cation architecture and the ability to timeshare its activity
temperature compensation to enable an overall perfor- with the sensor’s output signal enables output sensing
mance approaching the inherent repeatability of the sen- and calibration programming on a single line by paral-
sor. The fully analog signal-path introduces no quantiza- lel connecting OUT and DIO. The MAX1452 provides a
tion noise in the output signal while enabling digitally con- Secure-Lock feature that allows the customer to prevent
trolled trimming with the integrated 16-bit DACs. Offset modification of sensor coefficients and the 52-byte user
and span can be calibrated to within ±0.02% of span. definable EEPROM data after the sensor has been
calibrated. The Secure-Lock feature also provides a hard-
The MAX1452 architecture includes a programmable ware override to enable factory rework and recalibration
sensor excitation, a 16-step programmable-gain ampli- by assertion of logic high on the UNLOCK pin.
fier (PGA), a 768-byte (6144 bits) internal EEPROM,
four 16-bit DACs, an uncommitted op amp, and an on- The MAX1452 allows complete calibration and sensor
chip temperature sensor. The MAX1452 also provides a verification to be performed at a single test station. Once
unique temperature compensation strategy for offset TC calibration coefficients have been stored in the MAX1452,
and FSOTC that was developed to provide a remarkable the customer can choose to retest in order to verify per-
degree of flexibility while minimizing testing costs. formance as part of a regular QA audit or to generate final
test data on individual sensors.
The customer can select from one to 114 temperature
points to compensate their sensor. This allows the The MAX1452’s low current consumption and the integrat-
latitude to compensate a sensor with a simple first order ed uncommitted op amp enables a 4–20mA output signal
linear correction or match an unusual temperature curve. format in a sensor that is completely powered from a 2-wire
Programming up to 114 independent 16-bit EEPROM current loop. Frequency response can be user-adjusted
locations corrects performance in 1.5°C temperature to values lower than the 3.2kHz bandwidth by using the
increments over a range of -40°C to +125°C. For sensors uncommitted op amp and simple passive components.
that exhibit a characteristic temperature performance, The MAX1452 (Figure 1) provides an analog amplification
a select number of calibration points can be used with path for the sensor signal. It also uses an analog architec-
a number of preset values that define the temperature ture for first-order temperature correction. A digitally con-
curve. In cases where the sensor is at a different tempera- trolled analog path is then used for nonlinear temperature
ture than the MAX1452, the MAX1452 uses the sensor correction. Calibration and correction is achieved by vary-
bridge itself to provide additional temperature correction. ing the offset and gain of a programmable-gain-amplifier
(PGA) and by varying the sensor bridge excitation current

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Offset Correction
VDD
Initial offset correction is accomplished at the input stage
of the signal gain amplifiers by a coarse offset setting.
VDD BIAS Final offset correction occurs through the use of a tem-
GENERATOR perature indexed lookup table with 176 16-bit entries.
IRO MAX1452
DAC CLK1M The on-chip temperature sensor provides a unique 16-bit
OSCILLATOR
TEST offset trim value from the table with an indexing resolu-
INP tion of approximately 1.5°C from -40°C to +125°C. Every
∑ PGA OUT millisecond, the on-chip temperature sensor provides
INM indexing into the offset lookup table in EEPROM and
the resulting value transferred to the offset DAC register.
CURRENT ANAMUX
ISRC
SOURCE The resulting voltage is fed into a summing junction at
the PGA output, compensating the sensor offset with a
BDR A=1 FSOTC
resolution of ±76μV (±0.0019% FSO). If the offset TC
16 BIT DAC - FSO (176) POINT

TEMP
DAC is set to zero then the maximum temperature error
16 BIT DAC - OFFSET (176)

SENSOR
16 BIT DAC - OFFSET TC

176
is equivalent to one degree of temperature drift of the
16 BIT DAC - FSO TC

8-BIT ADC TEMPERATURE sensor, given the Offset DAC has corrected the sensor
LOOK UP at every 1.5°C. The temperature indexing boundaries
POINTS FOR
VDDF INTERNAL OFFSET AND
are outside of the specified Absolute Maximum Ratings.
DIO EEPROM SPAN. The minimum indexing value is 00hex corresponding to
UNLOCK 6144 BITS
approximately -69°C. All temperatures below this value
416 BITS
output the coefficient value at index 00hex. The maximum
FOR USER VDD
BDR OP-AMP indexing value is AFhex, which is the highest lookup table
AMP+
AMPOUT entry. All temperatures higher than approximately 184°C
AMP-
output the highest lookup table index value. No indexing
VSS wraparound errors are produced.
FSO Correction
Figure 1. Functional Diagram
Two functional blocks control the FSO gain calibration.
or voltage. The PGA utilizes a switched capacitor CMOS First, a coarse gain is set by digitally selecting the gain
technology, with an input-referred offset trimming range of of the PGA. Second, FSO DAC sets the sensor bridge
more than ±150mV with an approximate 3μV resolution current or voltage with the digital input obtained from a
(16 bits). The PGA provides gain values from 39V/V to temperature-indexed reference to the FSO lookup table
234V/V in 16 steps. in EEPROM. FSO correction occurs through the use of a
The MAX1452 uses four 16-bit DACs with calibration temperature indexed lookup table with 176 16-bit entries.
coefficients stored by the user in an internal 768 x 8 The on-chip temperature sensor provides a unique FSO
EEPROM (6144 bits). This memory contains the following trim from the table with an indexing resolution approach-
information, as 16-bit wide words: ing one 16-bit value at every 1.5°C from -40°C to +125°C.
The temperature indexing boundaries are outside of the
● Configuration Register specified Absolute Maximum Ratings. The minimum
● Offset Calibration Coefficient Table indexing value is 00hex corresponding to approximately
● Offset Temperature Coefficient Register -69°C. All temperatures below this value output the coef-
ficient value at index 00hex. The maximum indexing
● FSO (Full-Span Output) Calibration Table value is AFhex, which is the highest lookup table entry.
● FSO Temperature Error Correction Coefficient Register All temperatures higher than approximately 184°C output
● 52 bytes (416 bits) uncommitted for customer pro- the highest lookup table index value. No indexing wrap-
gramming of manufacturing data (e.g., serial number around errors are produced.
and date)

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Linear and Nonlinear For high-accuracy applications (errors less than 0.25%),
Temperature Compensation the first-order offset and FSO TC error should be com-
Writing 16-bit calibration coefficients into the offset TC pensated with the offset TC and FSOTC DACs, and the
and FSOTC registers compensates first-order tempera- residual higher order terms with the lookup table. The
ture errors. The piezoresistive sensor is powered by a offset and FSO compensation DACs provide unique
current source resulting in a temperature-dependent compensation values for approximately 1.5°C of tem-
bridge voltage due to the sensor’s temperature resistance perature change as the temperature indexes the address
coefficient (TCR). The reference inputs of the offset TC pointer through the coefficient lookup table. Changing the
DAC and FSOTC DAC are connected to the bridge volt- offset does not effect the FSO, however changing the
age. The DAC output voltages track the bridge voltage as FSO affects the offset due to nature of the bridge. The
it varies with temperature, and by varying the offset TC temperature is measured on both the MAX1452 die and
and FSOTC digital code a portion of the bridge voltage, at the bridge sensor. It is recommended to compensate
which is temperature dependent, is used to compensate the first-order temperature errors using the bridge sensor
the first-order temperature errors. temperature.
The internal feedback resistors (RISRC and RSTC) for Typical Ratiometric Operating Circuit
FSO temperature compensation are optimized to 75kΩ
Ratiometric output configuration provides an output that is
for silicon piezoresistive sensors. However, since the
proportional to the power supply voltage. This output can
required feedback resistor values are sensor dependent,
then be applied to a ratiometric ADC to produce a digital
external resistors may also be used. The internal resistors
value independent of supply voltage. Ratiometricity is an
selection bit in the configuration register selects between
important consideration for battery-operated instruments
internal and external feedback resistors.
and some industrial applications.
To calculate the required offset TC and FSOTC compen-
The MAX1452 provides a high-performance ratiometric
sation coefficients, two test-temperatures are needed.
output with a minimum number of external components
After taking at least two measurements at each tempera-
(Figure 2). These external components include the fol-
ture, calibration software (in a host computer) calculates
lowing:
the correction coefficients and writes them to the internal
EEPROM. ● One supply bypass capacitor.
With coefficients ranging from 0000hex to FFFFhex and a ● One optional output EMI suppression capacitor.
+5V reference, each DAC has a resolution of 76μV. Two ● Two optional resistors, RISRC and RSTC, for special
of the DACs (offset TC and FSOTC) utilize the sensor sensor bridge types.
bridge voltage as a reference. Since the sensor bridge
voltage is approximately set to +2.5V the FSOTC and
offset TC exhibit a step size of less than 38μV.

+5V VDD
7
VDD
5 9
BDR VDDF
6
INP OUT 2
OUT
MAX1452
16
FSOTC

SENSOR 4
INM RSTC
1
ISRC
0.1µF 0.1µF
TEST VSS RISRC
8 3
GND

Figure 2. Basic Ratiometric Output Configuration

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Signal Conditioner

G 2N4392

1
IN VPWR
S D
+12V TO +40V
MAX15006B

8
OUT
GND

7 30Ω 5

5 VDD
9
BDR VDDF
6
INP OUT 2
OUT
MAX1452
16
FSOTC

SENSOR 4
INM RSTC
1
ISRC
1.0µF 2.2µF 0.1µF 0.1µF
TEST VSS RISRC
8 3
GND

Figure 3. Basic Nonratiometric Output Configuration

Typical Nonratiometric Internal Calibration Registers (ICRs)

Operating Circuit The MAX1452 has five 16-bit internal calibration registers
that are loaded from EEPROM, or loaded from the serial
(12VDC < VPWR < 40VDC) digital interface.
Nonratiometric output configuration enables the sensor
power to vary over a wide range. A high-performance volt- Data can be loaded into the internal calibration registers
age reference, such as the MAX15006B, is incorporated under three different circumstances.
in the circuit to provide a stable supply and reference for Normal Operation, Power-On Initialization Sequence
MAX1452 operation. A typical example is shown in Figure ● The MAX1452 has been calibrated, the Secure-Lock
3. Nonratiometric operation is valuable when wide ranges byte is set (CL[7:0] = FFhex) and UNLOCK is low.
of input voltage are to be expected and the system A/D
● Power is applied to the device.
or readout device does not enable ratiometric operation.
● The power-on-reset functions have completed.
Typical 2-Wire, Loop-Powered, ● Registers CONFIG, OTCDAC, and FSOTCDAC are
4–20mA Operating Circuit refreshed from EEPROM.
Process Control systems benefit from a 4–20mA current ● Registers ODAC, and FSODAC are refreshed from the
loop output format for noise immunity, long cable runs, temperature indexed EEPROM locations.
and 2-wire sensor operation. The loop voltages can range Normal Operation, Continuous Refresh
from 12VDC to 40VDC and are inherently nonratiometric.
The low current consumption of the MAX1452 allows it ● The MAX1452 has been calibrated, the Secure-Lock
to operate from loop power with a simple 4–20mA drive byte has been set (CL[7:0] = FFhex) and UNLOCK is
circuit efficiently generated using the integrated uncom- low.
mitted op amp (Figure 4). ● Power is applied to the device.
● The power-on-reset functions have completed.
● The temperature index timer reaches a 1ms time
period.

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

2N4392 VIN+
G D 100Ω +12V TO +40V

S
1
IN
Z1

MAX15006B

8
OUT
GND

7 5
30Ω
VDD
5 9
BDR VDDF
6 16
INP FSOTC
1.0µF
MAX1452 RSTC
1
ISRC 2.2µF 0.1µF
4
SENSOR INM
RISRC 4.99MΩ
499kΩ
2
OUT 0.1µF
13
AMPOUT 2N2222A
14 4.99kΩ
AMP-
15 0.1µF
AMP+

TEST VSS 100kΩ

8 3

100kΩ 47Ω

VIN-

Figure 4. Basic 4–20mA Output, Loop-Powered Configuration

● Registers CONFIG, OTCDAC, and FSOTCDAC are page. Each page can be individually erased. The memory
refreshed from EEPROM. structure is arranged as shown in Table 1. The lookup
● Registers ODAC and FSODAC are refreshed from the tables for ODAC and FSODAC are also shown, with the
temperature indexed EEPROM locations. respective temp-index pointer. Note that the ODAC table
occupies a continuous segment, from address 000hex to
Calibration Operation, Registers Updated by Serial address 15Fhex, whereas the FSODAC table is divided
Communications in two parts, from 200hex to 2FFhex, and from 1A0hex to
● The MAX1452 has not had the Secure-Lock byte set 1FFhex. With the exception of the general-purpose user
(CL[7:0] = 00hex) or UNLOCK is high. bytes, all values are 16-bit wide words formed by two
● Power is applied to the device. adjacent byte locations (high byte and low byte).
● The power-on-reset functions have completed. The MAX1452 compensates for sensor offset, FSO, and
temperature errors by loading the internal calibration
● The registers can then be loaded from the serial digital
registers with the compensation values. These compen-
interface by use of serial commands. See the section
sation values can be loaded to registers directly through
on Serial Interface Command Format.
the serial digital interface during calibration or loaded
Internal EEPROM automatically from EEPROM at power-on. In this way the
The internal EEPROM is organized as a 768 by 8-bit device can be tested and configured during calibration
memory. It is divided into 12 pages, with 64 bytes per and test and the appropriate compensation values stored

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Table 1. EEPROM Memory Address Map

LOW-BYTE HIGH-BYTE ADDRESS TEMP-INDEX[7:0]
PAGE CONTENTS
ADDRESS (hex) (hex) (hex)
000 001 00
0
03E 03F 1F
040 041 20
1
07E 07F 3F
080 081 40
2
0BE 0BF 5F
ODAC
0C0 0C1 60 Lookup Table
3
0FE 0FF 7F
100 101 80
4
13E 13F 9F
140 141 A0
15E 15F AF to FF
160 161 Configuration
162 163 Reserved
164 165 OTCDAC
5 166 167 Reserved
168 169 FSOTCDAC
16A 16B Control Location
16C 16D
17E 17F
52 General-Purpose
180 181 User Bytes
19E 19F
6 1A0 1A1 80
1BE 1BF 8F
1C0 1C1 90
7
1FE 1FF AF to FF
200 201 00
8
23E 23F 1F FSODAC
240 241 20 Lookup Table
9
27E 27F 3F
280 281 40
A
2BE 2BF 5F
2C0 2C1 60
B
2FE 2FF 7F

in internal EEPROM. The device auto-loads the registers is stored as two 8-bit quantities. The configuration register,
from EEPROM and be ready for use without further con- FSOTCDAC and OTCDAC registers are loaded from the
figuration after each power-up. The EEPROM is config- pre-assigned locations in the EEPROM.
ured as an 8-bit wide array so each of the 16-bit registers

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

The ODAC and FSODAC are loaded from the EEPROM and the DIO pin to be configured by Secure-Lock or the
lookup tables using an index pointer that is a function of UNLOCK pin.
temperature. An ADC converts the integrated temperature
sensor output to an 8-bit value every 1ms. This digitized Reinitialization Sequence
value is then transferred into the temp-index register. The MAX1452 allows for relearning the baud rate. The
reinitialization sequence is one byte transmission of
The typical transfer function for the temp-index is as fol-
FFhex, as follows:
lows:
11111111011111111111111111
temp-index = 0.6879 Temperature (°C) + 44.0
When a serial reinitialization sequence is received, the
where temp-index is truncated to an 8-bit integer value.
receive logic resets itself to its power-up state and waits
Typical values for the temp-index register are given in
for the initialization sequence. The initialization sequence
Table 6.
must follow the reinitialization sequence in order to re-
Note that the EEPROM is byte wide and the registers that establish the baud rate.
are loaded from EEPROM are 16 bits wide. Thus each
index value points to two bytes in the EEPROM. Serial Interface Command Format
Maxim programs all EEPROM locations to FFhex with the All communication commands into the MAX1452 follow a
exception of the oscillator frequency setting and Secure- defined format utilizing an interface register set (IRS). The
Lock byte. OSC[2:0] is in the Configuration Register (Table IRS is an 8-bit command that contains both an interface
3). These bits should be maintained at the factory preset register set data (IRSD) nibble (4-bit) and an interface
values. Programming 00hex in the Secure-Lock byte register set address (IRSA) nibble (4-bit). All internal cali-
(CL[7:0] = 00hex), configures the DIO as an asynchronous bration registers and EEPROM locations are accessed for
serial input for calibration and test purposes. read and write through this interface register set. The IRS
byte command is structured as follows:
Communication Protocol IRS[7:0] = IRSD[3:0], IRSA[3:0]
The DIO serial interface is used for asynchronous serial
Where:
data communications between the MAX1452 and a host
calibration test system or computer. The MAX1452 auto- ● IRSA[3:0] is the 4-bit interface register set address
matically detects the baud rate of the host computer when and indicates which register receives the data nibble
the host transmits the initialization sequence. Baud rates IRSD[3:0].
between 4800bps and 38,400bps can be detected and ● IRSA[0] is the first bit on the serial interface after the
used regardless of the internal oscillator frequency setting. start bit.
Data format is always 1 start bit, 8 data bits, 1 stop bit and
● IRSD[3:0] is the 4-bit interface register set data.
no parity. Communications are only allowed when Secure-
Lock is disabled (i.e., CL[7:0] = 00hex) or the UNLOCK ● IRSD[0] is the fifth bit received on the serial interface
pin is held high. after the start bit.
The IRS address decoding is shown in Table 10.
Initialization Sequence
Sending the initialization sequence shown below enables Special Command Sequences
the MAX1452 to establish the baud rate that initializes the A special command register to internal logic (CRIL[3:0])
serial port. The initialization sequence is one byte trans- causes execution of special command sequences within
mission of 01hex, as follows: the MAX1452. These command sequences are listed as
1111111101000000011111111 CRIL command codes as shown in Table 11.
The first start bit 0 initiates the baud rate synchronization Write Examples
sequence. The 8 data bits 01hex (LSB first) follow this A 16-bit write to any of the internal calibration registers is
and then the stop bit, which is indicated above as a 1, performed as follows:
terminates the baud rate synchronization sequence. This
1) Write the 16 data bits to DHR[15:0] using four byte
initialization sequence on DIO should occur after a period
accesses into the interface register set.
of 1ms after stable power is applied to the device. This
allows time for the power-on-reset function to complete 2) Write the address of the target internal calibration reg-
ister to ICRA[3:0].

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

THREE-STATE THREE-STATE
NEED WEAK NEED WEAK
DRIVEN BY TESTER PULLUP DRIVEN BY MAX1452 PULLUP

DIO 11111 0 1 0 0 11 0 1 0 11 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 111111 1 1 1 11

START-BIT
LSB

STOP-BIT

START-BIT
LSB

MSB
STOP-BIT
MSB
Figure 5. DIO Output Data Format

3) Write the load internal calibration register (LdICR) com- Serial Digital Output
mand to CRIL[3:0]. When a RdIRS command is written to CRIL[3:0], DIO
When a LdICR command is issued to the CRIL register, is configured as a digital output and the contents of the
the calibration register loaded depends on the address in register designated by IRSP[3:0] are sent out as a byte
the internal calibration register address (ICRA). Table 12 framed by a start bit and a stop bit.
specifies which calibration register is decoded. Once the tester finishes sending the RdIRS command,
Erasing and Writing the EEPROM it must three-state its connection to DIO to allow the
MAX1452 to drive the DIO line. The MAX1452 three-
The internal EEPROM needs to be erased (bytes set
states DIO high for 1 byte time and then drive with the
to FFhex) prior to programming the desired contents.
start bit in the next bit period followed by the data byte and
Remember to save the 3 MSBs of byte 161 hex (high byte
stop bit. The sequence is shown in Figure 5.
of the configuration register) and restore it when program-
ming its contents to prevent modification of the trimmed The data returned on a RdIRS command depends on the
oscillator frequency. address in IRSP. Table 13 defines what is returned for the
various addresses.
The internal EEPROM can be entirely erased with the
ERASE command, or partially erased with the PageErase Multiplexed Analog Output
command (see Table 11, CRIL command). It is necessary When a RdAlg command is written to CRIL[3:0] the ana-
to wait 6ms after issuing the ERASE or PageErase com- log signal designated by ALOC[3:0] is asserted on the
mand. OUT pin. The duration of the analog signal is determined
After the EEPROM bytes have been erased (value of by ATIM[3:0] after which the pin reverts to three-state.
every byte = FFhex), the user can program its contents, While the analog signal is asserted in the OUT pin, DIO
following the procedure below: is simultaneously three-stated, enabling a parallel wiring
1) Write the 8 data bits to DHR[7:0] using two byte of DIO and OUT. When DIO and OUT are connected in
accesses into the interface register set. parallel, the host computer or calibration system must
three-state its connection to DIO after asserting the stop
2) Write the address of the target internal EEPROM loca- bit. Do not load the OUT line when reading internal
tion to IEEA[9:0] using three byte accesses into the signals, such as BDR, FSOTC...etc.
interface register set.
The analog output sequence with DIO and OUT is shown
3) Write the EEPROM write command (EEPW) to in Figure 6.
CRIL[3:0].
The duration of the analog signal is controlled by ATIM[3:0]
as given in Table 14.

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

THREE-STATE THREE-STATE THREE-STATE

NEED WEAK 2ATIM +1 BYTE NEED WEAK
DRIVEN BY TESTER PULLUP TIMES PULLUP

DIO 11111 0 1 0 0 11 0 1 0 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11
START-BIT
LSB

MSB
STOP-BIT
HIGH IMPEDANCE
OUT VALID OUT

Figure 6. Analog Output Timing

The analog signal driven onto the OUT pin is determined ● Calibrate the output offset and FSO of the transducer
by the value in the ALOC register. The signals are speci- using the ODAC and FSODAC, respectively.
fied in Table 15. ● Store calibration data in the test computer or MAX1452
Test System Configuration EEPROM user memory.
The MAX1452 is designed to support an automated Set next test temperature:
production test system with integrated calibration and ● Calibrate offset and FSO using the ODAC and
temperature compensation. Figure 7 shows the imple- FSODAC, respectively.
mentation concept for a low-cost test system capable of
● Store calibration data in the test computer or MAX1452
testing many transducer modules connected in parallel.
EEPROM user memory.
The MAX1452 allows for a high degree of flexibility in
system calibration design. This is achieved by use of ● Calculate the correction coefficients.
single-wire digital communication and three-state output ● Download correction coefficients to EEPROM.
nodes. Depending upon specific calibration requirements ● Perform a final test.
one may connect all the OUTs in parallel or connect DIO
and OUT on each individual module. Sensor Calibration and
Compensation Example
Sensor Compensation Overview
The MAX1452 temperature compensation design corrects
Compensation requires an examination of the sensor per- both sensor and IC temperature errors. This enables the
formance over the operating pressure and temperature MAX1452 to provide temperature compensation approach-
range. Use a minimum of two test pressures (e.g., zero ing the inherent repeatability of the sensor. An example of
and full-span) and two temperatures. More test pressures the MAX1452’s capabilities is shown in Figure 8.
and temperatures result in greater accuracy. A typical
compensation procedure can be summarized as follows: A repeatable piezoresistive sensor with an initial offset of
16.4mV and a span of 55.8mV was converted into a com-
Set reference temperature (e.g., +25°C): pensated transducer (utilizing the piezoresistive sensor
● Initialize each transducer by loading their respective with the MAX1452) with an offset of 0.5000V and a span
registers with default coefficients (e.g., based on mean of 4.0000V. Nonlinear sensor offset and FSO temperature
values of offset, FSO and bridge resistance) to prevent errors, which were on the order of 20% to 30% FSO, were
overload of the MAX1452. reduced to under ±0.1% FSO. The following graphs show
● Set the initial bridge voltage (with the FSODAC) to the output of the uncompensated sensor and the output of
half of the supply voltage. Measure the bridge voltage the compensated transducer. Six temperature points were
using the BDR or OUT pins, or calculate based on used to obtain this result.
measurements.

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

DIO[1:N]
DIGITAL
MULTIPLEXER DIO1 DIO2 DION

MODULE 1 MODULE 2 MODULE N

MAX1452

MAX1452

MAX1452
DATA DATA

VOUT VOUT VOUT

VDD VSS VDD VSS VDD VSS
+5V

VOUT
DVM

TEST OVEN

Figure 7. Automated Test System Concept

MAX1452 Evaluation Kit 2) Design/Applications Manual, which describes

To expedite the development of MAX1452-based trans- in detail the architecture and functionality of the
ducers and test systems, Maxim has produced the MAX1452. This manual was developed for test engi-
MAX1452 evaluation kit (EV kit). First-time users of the neers familiar with data acquisition of sensor data and
MAX1452 are strongly encouraged to use this kit. provides sensor compensation algorithms and test
procedures.
The EV kit is designed to facilitate manual programming
of the MAX1452 with a sensor. It includes the following: 3) MAX1452 Communication Software, which enables
programming of the MAX1452 from a computer key-
1) Evaluation Board with or without a silicon pressure board (IBM compatible), one module at a time.
sensor, ready for customer evaluation.
4) Interface Adapter, which allows the connection of the
evaluation board to a PC serial port.

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

RAW SENSOR OUTPUT UNCOMPENSATED SENSOR

TA = +25ºC TEMPERATURE ERROR
80 30.0
FSO OFFSET
20.0

ERROR (% FSO)
60
VOUT (mV)

10.0
40
0.0
6 -10.0
0 -20.0
0 20 40 60 80 100 -50 0 50 100 150
PRESSURE (kPs) TEMPERATURE (ºC)

COMPENSATED TRANSDUCER
COMPENSATED TRANSDUCER ERROR TA = +25ºC
0.15 5.0
FSO OFFSET
0.1 4.0
ERROR (% FSO)

0.05

VOUT (V)
3.0
0
-0.05 2.0

-0.1 1.0
-0.15 0
-50 0 50 100 150 0 20 40 60 80 100
TEMPERATURE (ºC) PRESSURE (kPs)

Figure 8. Comparison of an Uncalibrated Sensor and a Calibrated Transducer

Table 2. Registers
REGISTER DESCRIPTION
CONFIG Configuration Register
ODAC Offset DAC Register
OTCDAC Offset Temperature Coefficient DAC Register
FSODAC Full Span Output DAC Register
FSOTCDAC Full Span Output Temperature Coefficient DAC Register

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MAX1452 Low-Cost Precision Sensor
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Table 3. Configuration Register (CONFIG[15:0])

FIELD NAME DESCRIPTION
15:13 OSC[2:0] Oscillator frequency setting. Factory preset, do not change.
12 REXT Logic ‘1’ selects external RISRC and RSTC.
11 CLK1M EN Logic ‘1’ enables CLK1M output driver.
10 PGA Sign Logic ‘1’ inverts INM and INP polarity.
9 IRO Sign Logic ‘1’ for positive input-referred offset (IRO). Logic ‘0’ for negative input-referred offset (IRO).
8:6 IRO[2:0] Input-referred coarse offset adjustment.
5:2 PGA[3:0] Programmable gain amplifier setting.
1 ODAC Sign Logic ‘1’ for positive offset DAC output. Logic ‘0’ for negative offset DAC output.
0 OTCDAC Sign Logic ‘1’ for positive offset TC DAC output. Logic ‘0’ for negative offset TC DAC output.

Table 4. Input Referred Offset (IRO[2:0])

INPUT-REFERRED OFFSET INPUT-REFERRED OFFSET, CORRECTION
IRO SIGN, IRO[2:0]
CORRECTION AS % OF VDD AT VDD = 5VDC IN mV
1,111 +1.25 +63
1,110 +1.08 +54
1,101 +0.90 +45
1,100 +0.72 +36
1,011 +0.54 +27
1,010 +0.36 +18
1,001 +0.18 +9
1,000 0 0
0,000 0 0
0,001 -0.18 -9
0,010 -0.36 -18
0,011 -0.54 -27
0,100 -0.72 -36
0,101 -0.90 -45
0,110 -1.08 -54
0,111 -1.25 -63

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MAX1452 Low-Cost Precision Sensor
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Table 5. PGA Gain Setting (PGA[3:0]) Table 6. Temp-Index Typical Values

PGA[3:0] PGA GAIN (V/V) TEMPERATURE TEMP-INDEX[7:0]
0000 39 (°C) DECIMAL HEXADECIMAL
0001 52 -40 20 14
0010 65 25 65 41
0011 78 85 106 6A
0100 91 125 134 86
0101 104
0110 117 Table 7. Oscillator Frequency Setting
0111 130 OSC[2:0] OSCILLATOR FREQUENCY
1000 143 100 -37.5%
1001 156 101 -28.1%
1010 169 110 -18.8%
1011 182 111 -9.4%
1100 195 000 1MHz (nominal)
1101 208 001 +9.4%
1110 221 010 +18.8%
1111 234 011 +28.1%

Table 8. EEPROM ODAC and FSODAC Lookup Table Memory Map

EEPROM ADDRESS ODAC EEPROM ADDRESS FSODAC
TEMP-INDEX[7:0]
LOW BYTE AND HIGH BYTE LOW BYTE AND HIGH BYTE
00hex 000hex and 001hex 200hex and 201hex
to to to
7Fhex 0FEhex and 0FFhex 2FEhex and 2FFhex
80hex 100hex and 101hex 1A0hex and 1A1hex
to to to
AFhex 15Ehex and 15Fhex 1FEhex and 1FFhex

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Table 9. Control Location (CL[15:0])

FIELD NAME DESCRIPTION
15:8 CL[15:8] Reserved
Control Location. Secure-Lock is activated by setting this to FFhex which disables DIO serial
7:0 CL[7:0]
communications and connects OUT to PGA output.

Table 10. IRSA Decoding

IRSA[3:0] DESCRIPTION
0000 Write IRSD[3:0] to DHR[3:0] (data hold register)
0001 Write IRSD[3:0] to DHR[7:4] (data hold register)
0010 Write IRSD[3:0] to DHR[11:8] (data hold register)
0011 Write IRSD[3:0] to DHR[15:12] (data hold register)
0100 Reserved
0101 Reserved
Write IRSD[3:0] to ICRA[3:0] or IEEA[3:0], (internal calibration register address or internal EEPROM address
0110
nibble 0)
0111 Write IRSD[3:0] to IEEA[7:4] (internal EEPROM address, nibble 1)
1000 Write IRSD[3:0] to IRSP[3:0] or IEEA[9:8], (interface register set pointer where IRSP[1:0] is IEEA[9:8])
1001 Write IRSD[3:0] to CRIL[3:0] (command register to internal logic)
1010 Write IRSD[3:0] to ATIM[3:0] (analog timeout value on read)
1011 Write IRSD[3:0] to ALOC[3:0] (analog location)
1100 to 1110 Reserved
1111 Write IRSD[3:0] = 1111bin to relearn the baud rate

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MAX1452 Low-Cost Precision Sensor
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Table 11. CRIL Command Codes

CRIL[3:0] NAME DESCRIPTION
0000 LdICR Load internal calibration register at address given in ICRA with data from DHR[15:0].
0001 EEPW EEPROM write of 8 data bits from DHR[7:0] to address location pointed by IEEA[9:0].
0010 ERASE Erase all of EEPROM (all bytes equal FFhex).
0011 RdICR Read internal calibration register as pointed to by ICRA and load data into DHR[15:0].
0100 RdEEP Read internal EEPROM location and load data into DHR[7:0] pointed by IEEA[9:0].
0101 RdIRS Read interface register set pointer IRSP[3:0]. See Table 13.
Output the multiplexed analog signal onto OUT. The analog location is specified in ALOC[3:0] (Table
0110 RdAlg 15) and the duration (in byte times) that the signal is asserted onto the pin is specified in ATIM[3:0]
(Table 14).
Erases the page of the EEPROM as pointed by IEEA[9:6]. There are 64 bytes per page and thus 12
0111 PageErase
pages in the EEPROM.
1000 to
Reserved Reserved.
1111

Table 12. ICRA[3:0] Decode

ICRA[3:0] NAME DESCRIPTION
0000 CONFIG Configuration Register
0001 ODAC Offset DAC Register
0010 OTCDAC Offset Temperature Coefficient DAC Register
0011 FSODAC Full Scale Output DAC Register
0100 FSOTCDAC Full Scale Output Temperature Coefficient DAC Register
0101 Reserved. Do not write to this location (EEPROM test).
0110 to
Reserved. Do not write to this location.
1111

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MAX1452 Low-Cost Precision Sensor
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Table 13. IRSP Decode

IRSP[3:0] RETURNED VALUE
0000 DHR[7:0]
0001 DHR[15:8]
0010 IEEA[7:4], ICRA[3:0] concatenated
0011 CRIL[3:0], IRSP[3:0] concatenated
0100 ALOC[3:0], ATIM[3:0] concatenated
0101 IEEA[7:0] EEPROM address byte
0110 IEED[7:0] EEPROM data byte
0111 TEMP-Index[7:0]
1000 BitClock[7:0]
1001 Reserved. Internal flash test data.
1010-1111 11001010 (CAhex). This can be used to test communication.

Table 14. ATIM Definition

ATIM[3:0] DURATION OF ANALOG SIGNAL SPECIFIED IN BYTE TIMES (8-BIT TIME)
0000 20 + 1 = 2 byte times i.e. (2 x 8)/baud rate
0001 21 + 1 = 3 byte times
0010 22 + 1 = 5 byte times
0011 23 + 1 = 9 byte times
0100 24 + 1 = 17 byte times
0101 25 + 1 = 33 byte times
0110 26 + 1 = 65 byte times
0111 27 + 1 = 129 byte times
1000 28 + 1 = 257 byte times
1001 29 + 1 = 513 byte times
1010 210 + 1 = 1025 byte times
1011 211 + 1 = 2049 byte times
1100 212 + 1 = 4097 byte times
1101 213 + 1 = 8193 byte times
1110 214 + 1 = 16,385 byte times
In this mode OUT is continuous, however DIO accepts commands after 32,769 byte times. Do not parallel
1111
connect DIO to OUT.

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Table 15. ALOC Definition

ALOC[3:0] ANALOG SIGNAL DESCRIPTION
0000 OUT PGA Output
0001 BDR Bridge Drive
0010 ISRC Bridge Drive Current Setting
0011 VDD Internal Positive Supply
0100 VSS Internal Ground
0101 BIAS5U Internal Test Node
0110 AGND Internal Analog Ground. Approximately half of VDD.
0111 FSODAC Full Scale Output DAC
1000 FSOTCDAC Full Scale Output TC DAC
1001 ODAC Offset DAC
1010 OTCDAC Offset TC DAC
1011 VREF Bandgap Reference Voltage (nominally 1.25V)
1100 VPTATP Internal Test Node
1101 VPTATM Internal Test Node
1110 INP Sensor’s Positive Input
1111 INM Sensor’s Negative Input

Table 16. Effects of Compensation

TYPICAL UNCOMPENSATED INPUT (SENSOR) TYPICAL COMPENSATED TRANSDUCER OUTPUT

Offset........................................................................ ±100% FSO OUT................................................... Ratiometric to VDD at 5.0V

FSO................................................................. 4mV/V to 60mV/V Offset at +25°C.................................................... 0.500V ±200μV
Offset TC...................................................................... 20% FSO FSO at +25°C...................................................... 4.000V ±200μV
Offset TC Nonlinearity.................................................... 4% FSO Offset accuracy over temp. range.................±4mV (±0.1% FSO)
FSOTC........................................................................ -20% FSO FSO accuracy over temp. range...................±4mV (±0.1% FSO)
FSOTC Nonlinearity....................................................... 5% FSO
Temperature Range........................................... -40°C to +125°C

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Detailed Block Diagram

EEPROM
(LOOKUP PLUS CONFIGURATION DATA)
VDD
EEPROM ADDRESS USAGE
VDD 000H + 001H OFFSET DAC LOOKUP TABLE
(176 x 16-BITS)
:
16-BIT
FSO 15EH + 15FH
DAC 160H + 161H CONFIGURATION REGISTER SHADOW VDD
162H + 163H RESERVED
ISRC VSS
164H + 165H OFFSET TC REGISTER SHADOW VSS
166H + 167H RESERVED
168H + 169H FSOTC REGISTER SHADOW TEST
VDD
16AH + 16BH CONTROL LOCATION REGISTER
16-BIT
OFFSET 16CH + 16DH USER STORAGE (52 BYTES)
CLK1M
DAC :
RISRC RSTC
75kΩ 75kΩ 19EH + 19FH
VSS VDDF
1A0H + 1A1H FSO DAC LOOKUP TABLE
VSS : (176 x 16-BITS)

2FEH + 2FFH
VDD

8-BIT
BANDGAP LOOKUP
±1 TEMP ADDRESS
FSOTC 16-BIT
SENSOR ∑∆
BDR FSOTC UNLOCK
DAC DIGITAL
INTERFACE
VSS DIO
INP PHASE VSS FSOTC REGISTER
REVERSAL
MUX PGA BANDWIDTH
3kHz 10%

MUX ∑ x 26 PGA ∑ MUX OUT

INM

INPUT REFERRED OFFSET AMP-

(COARSE OFFSET) PROGRAMMABLE GAIN STAGE
VSS
IRO (3, 2:0) OFFSET mV ±1 PGA (3:0) PGA GAIN TOTAL GAIN
1,111 63 0000 1.5 39 AMPOUT
1,110 54 0001 2.0 52
1,101 45 0010 2.5 65
16-BIT
1,100 36 0011 3.0 78
OFFSET AMP+
1,011 27 TC DAC 0100 3.5 91
1,010 18 0101 4.0 104
1,001 9 VSS 0110 4.5 117
OTC REGISTER
1,000 0 0111 5.0 130
0,000 0 1000 5.5 143 UNCOMMITTED OP AMP
0,001 -9 * INPUT REFERRED 1001 6.0 156 PARAMETER VALUE
0,010 -18 OFFSET VALUE IS 1010 6.5 169
PROPORTIONAL TO VDD. I/P RANGE VSS TO VDD
0,011 -27 1011 7.0 182 I/P OFFSET ±20mV
VALUES GIVEN ARE FOR
0,100 -36 VDD = 5V. 1100 7.5 195 O/P RANGE
0,101 -45 1101 8.0 208 NO LOAD VSS, VDD ±0.01V
0,110 -54 1110 8.5 221 1mA LOAD VSS, VDD ±0.25V
0,111 -63 1111 9.0 234 UNITY GBW 10MHz TYPICAL
PGA BANDWIDTH 3kHz ± 10%

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Pin Configurations

FSOTC
TOP VIEW

AMP+
N.C.

N.C.

N.C.

N.C.
+ 24 23 22 21 20 19
ISRC 1 16 FSOTC
ISRC 1 18 AMP-
OUT 2 15 AMP+ +
VSS 3 14 AMP- OUT 2 17 AMPOUT

INM 4 13 AMPOUT VSS 3 16 N.C.

MAX1452
BDR 5 12 CLK1M MAX1452
INM 4 15 CLK1M
INP 6 11 DIO
BDR 5 14 DIO
VDD 7 10 UNLOCK

TEST 8 9 VDDF INP 6 13 N.C.

7 8 9 10 11 12
SSOP/TSSOP

VDD

N.C.

N.C.

TEST

VDDF

UNLOCK
TQFN

Chip Information Package Information

SUBSTRATE CONNECTED TO: VSS For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.

PACKAGE PACKAGE OUTLINE LAND

TYPE CODE NO. PATTERN NO.
16 SSOP A16+2 21-0056 90-0106
16 TSSOP U16+2 21-0066 90-0117
24 TQFN-EP T2444+4 21-0139 90-0022

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MAX1452 Low-Cost Precision Sensor
Signal Conditioner

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED

Added TQFN and TSSOP package information, changed packages to lead free,
changed all occurrences of ASIC to MAX1452, changed VDDF RC filter values,
1–7, 9, 10, 12,
2 4/09 recommended a more suitable voltage reference for non-ratiometric application
18, 22, 24
circuits, corrected MAX1452 input range, and added typical EEPROM current
requirements to EC table, and added gain nonlinearity graph.

3 11/13 Updated Package Information section 24

4 10/14 Deleted automotive reference 8
5 4/15 Updated Benefits and Features section 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. │ 25