18-100 Introduction to ECE

L03 Notes: Binary and Adders

Tom Zajdel, Carnegie Mellon University

1 Why Digital?
We are living in the Information Age. Data is swirling all around us, and
nearly all of it is stored in the form of bits, 1s and 0s, the fundamental
units of information. Ultimately, a bit answers a simple question: “High
or Low?” From this innocuous question flows the foundations of digital
information processing.
Because computers are physical circuits, they ultimately need to work
with binary 1s and 0s in a physical form. Bits are most often represented
as two voltage levels: High (1) and Low (0). A computer system sourced
with a +5V supply might use +5V for High and 0V for Low. Why just
two values? Why not divide the supply into more, smaller levels?
Computers exist in the real world, and the real world contains noise,
unwanted variations in voltage and current caused by interference or nat-
ural processes. Noise degrades a signal and makes it more difficult to
interpret. If there are only two voltage levels, the signal is more resistant
to noise than would be the case for multiple intermediate levels.

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2 Binary Number Systems
The number system you are most familiar with is base-10. A base-10
number uses the ten digits 0-9, so each digit in a number represents a
power of 10. Consider the number 18100. There are 5 digits, each with
a different place-value (ones, tens, hundreds, etc.). The most significant
digit is the one farthest to the left (ten-thousands in this case), while the
least significant digit is the one farthest on the right (ones).
1 8 1 0 0
1 × 104 8 × 103 1 × 102 0 × 101 0 × 100
ten-thousands thousands hundreds tens ones
Rewritten as a sum of these powers of 10, 18000 = 10000 + 8000 + 100.

2.1 Base-2
Binary numbers use a base-2 system so there are only two choices for
each digit: 0 or 1. Every place-value represents a power of 2. Here’s an
8-bit example: 100010102. The subscript 2 indicates that this should be
interpreted as a base-2 number.
1 0 0 0 1 0 1 0
1 × 2 7 0 × 26 0 × 2 5 0 × 2 4 1 × 2 3 0 × 2 2 1 × 2 1 0 × 20
1 × 128 0 × 64 0 × 32 0 × 16 1 × 8 0 × 4 1 × 2 0 × 1
b7(MSB) b6 b5 b4 b3 b2 b1 b0(LSB)
b7 is the most significant bit (MSB) in this example. A flip of
this bit (0 → 1 or 1 → 0) would affect the total value of the number the
most. b0 is the least significant bit (LSB). A flip of this bit results
in a change of value of 1. This number is written in base-10 as this sum:
1 × 27 + 1 × 23 + 1 × 21 = 128 + 8 + 2 = 138
You may write the result as 13810, but usually a number is assumed
to be in base-10 unless marked otherwise.

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 Most data storage systems describe capacity in Bytes. 1 Byte (B) =
8 bits (b). The maximum number that can be represented by 8 bits is
28 − 1 = 255. This maximum value would be represented by 1’s in each of
the n digits (like having all 9 digits in a base-10 number). In general, an
n-bit number can have a maximum value of 2n − 1 (what is the maximum
value of a 3-digit base-10 number? 103 − 1 = 999).

2.2 Hexadecimal (Base-16)

Base-16, or hexadecimal (hex) uses 16 possibilities for each digit. Be-
cause we run out of numeric digits after the first ten (0-9), the numbers
10-15 are represented by the letters A-F. Therefore, the first 16 hex num-
bers are:
hex binary decimal
016 00002 0
116 00012 1
216 00102 2
316 00112 3
416 01002 4
516 01012 5
616 01102 6
716 01112 7
816 10002 8
916 10012 9
A16 10102 10
B16 10112 11
C16 11002 12
D16 11012 13
E16 11102 14
F16 11112 15

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 In software, the prefix 0x is used instead of the subscript 16 because it
is more convenient to type. An example: 0xD7 = D716. Because each hex
digit represents one of 16 possibilities, each hex digit represents a 4-bit
number. This leads to a more compact representation of binary numbers.
Consider the 8-bit representation of 138 once again:

138 = 100010102 = 8A16

The first four bits of the binary representation are grouped into the
first hex digit (10002 = 816), and the last four bits are grouped into the
second hex digit (10102 = A16). Each hex digit represents 4 bits, so one
Byte can be represented by just two hex digits.

2.3 Addition
Adding two bits has only 4 possible outcomes. All of these results are
presented below. Notice that in the case where both bits are 1, the result
is a 0 with a carry of 1.

1
0 0 1 1
+ 0 + 1 + 0 + 1
0 1 1 1 0
The following is an example of adding 100010112 + 11012 (decimal
139 + 13). Notice how the carries propagate through the calculation. The
result 100110002 = 152.

1 1 1 1
1 0 0 0 1 0 1 1
+ 1 1 0 1
1 0 0 1 1 0 0 0

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2.4 Two’s Complement
Two’s complement is a way to represent negative numbers in binary. Con-
version between a binary number and its two’s complement is a two-step
process:
1. Invert all the bits
2. Add 1
For example, take the 5 represented as an 8-bit number 000001012.
The conversion to −5 in two’s complement would proceed as follows:
Original number 0 0 0 0 0 1 0 1
Invert all the bits 1 1 1 1 1 0 1 0
Add 1 1 1 1 1 1 0 1 1
Therefore, the two’s complement of 000001012 is 111110112. When
these numbers are added together, it’s the same as adding 5 + (−5) = 0.
Let’s verify that this would be the case:
1 1 1 1 1 1 1 1
0 0 0 0 0 1 0 1
+ 1 1 1 1 1 0 1 1
0 0 0 0 0 0 0 0
The final carry out (marked in red) is not included in the final result,
because there is not a 9th bit to store it in. This is known as a carry out
or an overflow. Therefore, the result of the sum is 000000002 = 0. If you
want to perform x − y in binary, take the two’s complement of y, then
add x to the result. This is the binary equivalent of x + (−y).
Note that the leftmost bit of a two’s complement number is always 1.
We interpret the most significant bit (MSB) as the sign bit, where 0 =
positive and 1 = negative. This changes the range of numbers that can be
represented in two’s complement form. For an 8-bit number, this range
shifts to −128 to +127 (from 0 to 255).

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 How does 2’s complement work? It is a clever way of assigning meaning
to the binary numbers that includes negative numbers, so that addition
may represent subtraction. If we have three bits, there are 8 possible
numbers to work with (23 = 8). When we interpret a binary number as
an unsigned value, we simply use the values 0 to 7. If however we want to
interpret a number as an integer with a positive or negative value, we use
the signed values -4 to +3.

b2 b1 b0 unsigned signed
0 0 0 0 0
0 0 1 1 1
0 1 0 2 2
0 1 1 3 3
1 0 0 4 −4
1 0 1 5 −3
1 1 0 6 −2
1 1 1 7 −1

What is 0 + 2? You can interpret that as starting in the first row of

the table above, then stepping down the table by 2 rows. If you were
adding two unsigned variables, then your result is 2. If you were adding
two signed variables, then your result is also 2.
What if you started with the binary number 1012 and added 0102 to
it? If you were working with an unsigned interpretation, then you have
5 + 2, and the result is 1112 = 7. If you were working with the signed
interpretation, than you have −3 + 2 = −1. You still end up in the same
row of the table, but your interpretation changes. When the sum gets to
an overflow, the carry out is ignored and the position wraps back to the
first row, 0. Notice how each of the negative numbers in the signed column
are all exactly the correct number of steps from 0. This is the magic of
two’s complement notation!

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3 Boolean Algebra
Boolean algebra is the set of operations based on comparisons between
binary bits. In boolean algebra, variables are typically denoted by capital
letters (e.g. A or Z), and they may have one of two values: 0 or 1 (‘false’
or ‘true’, ‘high’ or ‘low’).
The fundamental operations of boolean algebra: NOT, AND, OR, are
used to derive more complex operations. Each of these can be physically
realized as switching digital circuits known as logic gates, which inter-
pret low and high voltages as 0s and 1s. At the heart of these circuits
are voltage-controlled switches known as transistors, which may be
switched on or off. Like diodes, transistors are made from semiconductor
materials and they can be used to control the flow of current.
For now, we will focus on the higher-level applications of these digital
circuits, presenting the truth table and schematic symbols for the fun-
damental gates. In a few lectures, we will talk about how transistors are
wired together to create these logic gates.

3.1 NOT
The output Z is the inversion or complement of the input A.

A Z

A Z
0 1
1 0

Algebraic form: Z = A

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3.2 AND
The output Z is true only if both inputs A and B are true.

A Z
B

A B Z
0 0 0
1 0 0
0 1 0
1 1 1

Algebraic form: Z = A · B

3.3 OR
The output Z is true if either input A or B is true. If both A and B are
true, then Z is also true.

A Z
B

A B Z
0 0 0
1 0 1
0 1 1
1 1 1

Algebraic form: Z = A + B

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3.4 XOR
XOR is the exclusive-or operation. Z is true if either input A or B
exclusively is true. If both A and B are true, then Z is false.

A Z
B

A B Z
0 0 0
1 0 1
0 1 1
1 1 0

Algebraic form: Z = A ⊕ B

If you’ve ever flipped a light switch at either the top or the bottom of
a stairwell, you’ve interacted with XOR logic. When the switches at each
end of the stairwell are both in the same position, the light is off off. You
can flip one of the switches to turn the light on, walk across the stairs,
then flip the switch on the other side to turn the light off.
XOR is also useful for arithmetic operations. Consider summing two
binary bits X and Y . If X and Y are both 0, then the sum S will be
0. If either X or Y is 0 and the other is 1, then S = 1. If X and Y
are both 1, then the result is S = 0 with a bit carried over to the next
digit. Therefore, the addition of two binary bits can be represented as
S = X ⊕ Y . Some additional logic is required to keep track of any carries,
but basic 1-bit summation uses XOR.
Do you need to complement a bit for something (perhaps a two’s com-
plement representation of a number)? See if you can prove to yourself why
A ⊕ 1 = A.

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 XOR can be derived from the set of fundamental logic operations
(NOT, AND, OR). The output A ⊕ B is only true under two conditions:

(A is true AND B is false) OR (A is false AND B is true)

A ⊕ B = (A · B) + (A · B)

Therefore, an XOR gate can be built this way out of NOT, AND, and
OR gates:

A⊕B

B
Figure 1: One of many possible realizations of XOR. As is custom for
digital circuits, wires that cross over each other are not connected unless
indicated by a black circle.

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3.5 NAND and NOR
Complementary gates NAND and NOR are equivalent to putting a NOT
gate at the output of the AND and OR, respectively. The output of NAND
is 1 if either input A or B is 0. The output of NOR is 0 if either input
A or B is 1. Their logic gates and truth tables are presented below for
reference. Notice an open circle (or “bubble”) at the output of each gate
represents the logical inversion.

NAND NOR

A Z A Z
B B

A Z A Z
B B

A B Z A B Z
0 0 1 0 0 1
1 0 1 1 0 0
0 1 1 0 1 0
1 1 0 1 1 0

Z = (A · B) Z = (A + B)

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4 Arithmetic Logic Circuits
Think about doing arithmetic by hand. You know how to add 1067394 +
20988992. The process is automatic and repetitive because you have been
adding numbers together since elementary school. You just need to follow
a few simple rules, and the sum will eventually pop out.
Computers free us from the drudgery of calculating sums by hand
by implementing digital circuits that follow the simple rules of addition,
subtraction, multiplication, etc. These numbers are ultimately represented
in the computer as binary bits that are passed through arithmetic logic
circuits that compute the results. In 18-100, you will build the most
fundamental of these arithmetic circuits: the adder.

4.1 Half Adder

The sum of two bits a0 + b0 will only have four possible outcomes, which
can be fully represented by a sum bit s0 and a carry out cout. Here is
the truth table for a Half Adder, which adds two 1-bit binary numbers
without considering any carry-ins. This is suitable for adding the LSBs of
two binary numbers.

a0 b0 s0 cout
0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1

Inspection of the truth table, one may conclude that s0 = a0 ⊕ b0 and

cout = a0 · b0. This means that this operation has the following logic gate
representation:

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 a0 s0
b0

cout

Figure 2: The Half Adder’s logic gate representation.

4.2 Full Adder

The Full Adder steps things up by one bit. It considers the sum between
two binary numbers, while also considering a third bit, representing a carry
in from the previous sum cin. The Full Adder essentially adds three bits,
so there are 8 possible outputs. You will complete the truth table for the
Full Adder as an exercise in Lab 2. Here is its logic gate representation:
an
bn sn
cin

cout

Figure 3: The Full Adder’s logic gate representation.

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5 The Logical Laws of Computers
How does a computer access a particular variable in memory? How does
a computer display graphics on a monitor? How does a computer add
two numbers together? Every task that a computer does boils down to
manipulating bits.
We need to make sense of the laws of boolean algebra if we are to
understand the digital circuits and logic structures that make a computer
tick. The organized, hierarchical implementation of these structures is
the subject of computer architecture, and over the course of the next
few lectures, we will build up our understanding towards a basic 4-bit
computer architecture. All the tools that the computer has to control bits
derive from the rules of boolean algebra.

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6 Boolean Algebra
When you studied algebra in school, you learned about a number of rules
and identities you now use to simplify equations. Boolean algebra has
its own set of logical rules that will simplify complex logical expressions.
Every logic gate takes up space and uses power, so the most efficient
implementation of digital logic (i.e. the fewest gates) is preferred.
There are a number of basic laws to simplify boolean algebra and they
are presented in Tables 1 and 2. Of particular note are the Identity and
Dominance laws. We take advantage of these laws to control the flow and
selection of bits in a computer.

Law AND OR
Identity A·1=A A+0=A
Dominance A·0=0 A+1=1
Complementary A·A=0 A+A=1
De Morgan’s A·B =A+B A+B =A·B
Idempotent A·A=A A+A=A
Commutative A·B =B·A A+B = B+A
A · (B · C) = A + (B + C) =
Associative
(A · B) · C (A + B) + C
A + (B · C) = A · (B + C) =
Distributive
(A+B)·(A+C) (A · B) + (A · C)
Absorptive A · (A + B) = A A + (A · B) = A

Table 1: Laws for Boolean algebra involving AND and OR.

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 Law Expression
Double negative
A=A
(involution)
XOR Identity A⊕0=A
XOR Inequality A⊕1=A
XOR Self-Inverse A⊕A=0
XOR
A⊕A=1
Complement

Table 2: Other useful laws for Boolean algebra, mostly involving XOR.

Imagine you had to design a logic circuit to pass the bit X to output
Z when desired, but pass 0 otherwise. A control gate might use a second
pass bit P to dictate when to pass X on to Z. If P = 1, then Z = X. If
P = 0, then Z = 0. The Identity of AND states that X · 1 = X, and the
Dominance Law of AND states that X · 0 = 0, so we could implement the
following logic:
X ·P =Z

X Z
P
Figure 4: A digital control gate. The bit at X is passed to the output Z
if the pass bit P = 1. Otherwise, Z = 0. P is the “gatekeeper.”

From the simple decoder to the arithmetic logic unit (ALU),

every decision that the computer makes is controlled by manipulating bits
in this way.

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6.1 De Morgan’s Laws
De Morgan’s Laws deserve special mention. They are two laws that
involve the complements of AND and OR. You can think of it like the
complement operation is being distributed across the operation. Both
inputs invert, but notice that the operation changes (from AND to OR or
vice versa).

(A · B) = A + B
(A + B) = A · B
The truth tables below show how each of the two pairs are equiva-
lent. The first table pertrains to NAND equivalence, and the second table
pertains to NOR equivalence.

A B (A · B) A B A + B
0 0 1 1 1 1
1 0 1 0 1 1
0 1 1 1 0 1
1 1 0 0 0 0

A B (A + B) A B A · B
0 0 1 1 1 1
1 0 0 0 1 0
0 1 0 1 0 0
1 1 0 0 0 0

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6.2 Everything is NAND
Inverting logic (NOT, NAND, NOR) is the most prevalent form of logic
in use because the inverting gates have very efficient implementations in
CMOS (complementary MOS, more details in the next lecture). One
handy thing to remember is that any of the logic gates we’ve discussed so
far can be fully implemented using only NAND gates: (A · B). Let’s step
through the main three gates: NOT, AND, and OR.

6.2.1 NOT from one NAND

We have a problem: NOT has one input while NAND has two inputs. It’s
not a major problem. We can just tie the NAND gate’s inputs together,
so that they’re both connected to the same node. We can call this input
A, so both inputs to the NAND gate will always be the same.

A Z A Z

Figure 5: Building a NOT gate from a NAND gate.

The output of the NAND gate will be 0 when A = 1, because (1 · 1) =

0. Similarly, the output will be 1 when A = 0, because (0 · 0) = 1. This
is an inverter, a NOT gate!

6.2.2 AND from two NANDs

How do you make an AND gate? You could start with NAND, then invert
its output! That is,
(A · B) = A · B
Since you now know how to build a NOT gate, you could build AND
from two NAND gates in the following way:

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 A Z A Z
B B
Figure 6: Building an AND gate from two NAND gates.

6.2.3 OR from three NANDs

How do you get an OR from NAND? De Morgan’s Law says that there’s
an OR hiding in every NAND:

(A · B) = A + B

To fully recover OR from NAND, we simply need to invert each input

first:
(A · B) = A + B = A + B
This requires three NAND gates: one to invert each of the two inputs
before the third, final NAND gate.

Z A Z
B

Figure 7: Building an OR gate from three NAND gates.

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7 Digital Circuits
Digital circuits physically implement boolean algebra. They represent bits
as high and low voltage levels, and use logic gates to process the bits. We’ve
already discussed an arithmetic circuit: the Adder. For the remainder of
this lecture, we will cover some useful logic structures that we will use to
work towards building a (simple) working computer.

7.1 Decoder
An n-to-2n decoder has n inputs and 2n outputs. The decoder takes
at its n inputs a binary-encoded number, then “decodes” this and drives
one of its 2n output wires to a logical high (1), while the rest are set to a
logical low (0).
Consider a 3:8 decoder. There are three select bits representing a 3-bit
binary number S2S1S0, and there are eight output lines (wires) (D0-D7).
The decoder allows 3 bits to control which of the output lines is high. For
example, each of these lines could be connected to one of 8 LEDs, so 3-bits
could control which one turns on. Thus the decoder is our first structure
for digital control.

S2
S1
S0
000 001 010 011 100 101 110 111

D0 D1 D2 D3 D4 D5 D6 D7
Figure 8: Symbol for a 3-bit (3:8) binary decoder. Only one of the output
lines D0-D7 will be driven high.

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 Here is the truth table for the 3:8 decoder:
S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

The logic for constructing a decoder requires the inputs to be connected

such that only one combination of S2S1S0 will result in a true expression
for each output. Take D3 for example, which decodes 0112 to 3. We want
D3 to be high only when S2S1S0 = 011, so D3 = S2S1S0 (= S2 · S1 · S0).
The logic gate implementation (note that we are using a 3-input AND
gate, whose output is only true when all 3 inputs are true):

S2

S1 D3

S0
Figure 9: The connections for D3, one output line from the 3-bit (3:8)
binary decoder. This is one-eighth of the complete decoder circuit. Each
of the output lines gets a different set of complements of the input bits
S2S1S0.

Another use for the decoder is the selection between bits stored in a
memory array. With two decoders, one decoder could select a row and
another decoder could select a column. In this way, two 3-bit decoders
could select between 8 × 8 = 64 individual bits with 6 total control bits.

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7.2 Multiplexer
A 2n-to-1 multiplexer (mux) selects which of the 2n data lines is con-
nected to the sole output. There are n select bits which determine which
of the 2n data lines to output. It can be thought of as a many-to-one
switch. Unlike the decoder, the output could be true or false, depending
on the value of the data in.
Here is the symbol and truth table for a 4-to-1 multiplexer:

4-to-1 MUX
D3

D2
F
D1

D0
S1 S0

Figure 10: Symbol for a 4-to-1 mux. Only one of the input data lines
D0-D3 will be connected to the output. The two select bits S1S0 control
the multiplexer, specifying which data line makes it to the output.

S1 S0 F
0 0 D0
0 1 D1
1 0 D2
1 1 D3

The output F could be high or low. It all depends on the data on the
selected line.

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 Recall that a 2-input AND gate can be used to “gatekeep” one bit
(Figure 1), so you could begin to implement this 4-to-1 mux with four
AND gates, one for each data line. Then, a 2-to-4 decoder could select
which of these 4 gates is “open” to pass its data line to the output. The
decoder passes a 1 to one of these AND gates and a 0 to the rest, effectively
passing the desired data bit. Then, the output from the four AND gates
have to be combined down to 1 output. Since A + 0 = A, we can use a
4-input OR gate to accomplish this (only one of the AND gate outputs at
a time may be high - the rest will be low).

D0

D1
F
D2

D3

0 1 2 3

S1 S0
Figure 11: A complete 4-to-1 multiplexer. There are 4 AND gates, each
gatekeeping one of the input data lines D0 to D3. The bit passed to F
is selected by a 2-to-4 decoder, selected by S1S0. Remember, wires that
cross over each other are not connected unless indicated by a black dot.

Multiplexers can facilitate many connections to a shared wire (or bus).

Think of them like air traffic controllers presiding over an airport with only
one runway. They decide which planes (bits) get to use the runway (bus)
and when they get to use them.

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8 Glossary
• Bit: The fundamental unit of digital information. A 0 or a 1, false
or true, low or high. Represented as a ‘b’ suffix (e.g. 100Mb = 100
megabits = 100 × 106 bits)

• Byte: A unit of memory. 8 bits = 1 byte. Represented as a ‘B’

suffix (e.g. 100MB = 100 megabytes = 800 × 106 bits)

• Noise: Unwanted variations in voltage caused by interference or

natural processes.

• Decimal: Base-10 number system. Uses the ten numeric digits 0-9.

• Binary: Base-2 number system. Uses the digits 0 and 1.

• Hexadecimal (hex): Base-16 number system. Uses the sixteen

digits 0-F. Sometimes noted by the prefix 0x.

• Most significant bit (MSB): The leftmost bit in a binary num-

ber. A change in this bit would cause the greatest change in the
overall value of the number.

• Least significant bit (MSB): The right bit in a binary number.

A change in this bit would cause the smallest change in the overall
value of the number, a change of ±1.

• Two’s Complement: A binary representation of negative num-

bers. The MSB is reserved as the sign bit. 0 = positive, 1 =
negative.

• Boolean Algebra: A set of mathematical operations and laws

that works with bits.

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• De Morgan’s Laws: Two logical transformation rules regarding
the complements of AND and OR:

(A · B) = A + B

(A + B) = A · B

• Decoder: Converts a binary input (n bits) to a logical high level

on one of its output wires (2n). Some decoders, like a 7-segment
display decoder, will have multiple output levels high.

• Arithmetic Logic Unit (ALU): A digital system that special-

izes in carrying out calculations: addition, subtraction, multiplica-
tion, division, and so on.

• Multiplexer (mux): Selects which of several data input lines is

connected to the output line.

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