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DSD Lab Final Question paper.

The document outlines the course structure for 'Digital System Design' (Course Code: 20CS37L), including practical lab work with a focus on combinational circuits, logic gates, and flip-flops. It details the course outcomes, which include demonstrating truth tables, designing various circuits, and constructing flip-flops and counters. Additionally, it provides a list of reference books and web resources for further study.

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32 views

DSD Lab Final Question paper.

The document outlines the course structure for 'Digital System Design' (Course Code: 20CS37L), including practical lab work with a focus on combinational circuits, logic gates, and flip-flops. It details the course outcomes, which include demonstrating truth tables, designing various circuits, and constructing flip-flops and counters. Additionally, it provides a list of reference books and web resources for further study.

Uploaded by

vibhavspaerk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Course Title: Digital System Design Course Code: 20CS37L

Lab
Credits (L: T:P): 0:0:1.5 Contact Hours (L: T: P): 0:0:39
Type of Course: Practical Category: Professional Core Course
CIE Marks: 50 SEE Marks: 50

Pre-requisite: NIL

Course Outcomes: After completing this course, students should be able to:

CO-1 Demonstrate the truth table of various expressions and combinational circuits using
logic gates.
CO-2 Design various combinational circuits such as adders, subtractors, comparators,
multiplexers and demultiplexers.
CO-3 Construct flips-flops, counters and shift registers.

Weeks Programs
1. Simplify the given expression and realize it using logic gates. (Any one)
a. f(a,b,c,d) = ∑(0,1,2,3,6,10,14) + dc(4,8,12)
b. f(a,b,c,d) = ∑(5,6,7,8,9) + dc(10,11,12,13,14,15)
c. f(a,b,c,d) = π(1,2,5,6,9) + dc(10,11,12,13,14,15)
d f(a,b,c,d) = π(0,5,6,7,8) + dc(10,11,12,13,14,15)
2. Design and realize Half Adder and Full Adder using NAND gates only.

3. Design and realize Half Subtractor and Full Subtractor using logic gates.

4. Design and set up the following circuit using IC 7483.


a. A 4-bit binary parallel adder and subtractor
b. BCD to Excess- 3 and vice versa
5. Design and realize BCD to Excess- 3 Code using logic gates.

6. Design and realize Excess- 3 to BCD to Code using logic gates.

7. a. Design and implement 4:1 Multiplexer (MUX) using only NAND gates.
b. Design and implement half adder and Half subtractor using dual 4:1 Multiplexer
(IC 74153).

8. Full Adder and Full Subtractor using dual 4:1 Multiplexer (IC 74153).
Design and implement Two-Bit Magnitude Comparator using logic gates.
9. Design and implement the following Boolean function using 8:1 multiplexer. (Any
one)
a. f(a,b,c,d) = ∑(0,3,5,8,10,11,13,14,15) consider b,c,d as selection lines
b. f(w,x,y,z) = ∑(1,2,4,5,7,8,9,11,12,13,15) consider w,y,z as selection lines
10. Design and implement Full Adder and Full Subtractor using 3:8 Decoder (IC
74LS138)
11. a. Design and implement 3-bit parity generator and verify using Parity
Checker.
b. Design and implement one-bit comparator using logic gates
12. Implementation and verification of truth table for
a. J-K flip-flop
b. Master-slave J-K flip-flop using NAND gates
c. D flip-flop
d. T flip-flop.
13. Design and implement Mod-8 synchronous counter using J-K flip-flops.

14. Design and implementation of shift register to function as i) SISO, ii) SIPO,
iii) PISO, iv) PIPO, v) shift left and vi) shift right operation.
15. Design and implementation of i) Ring counter and ii) Johnson counter using 4-bit
shift register.

16. Design and implementation of Asynchronous Up-Counter using JK flip flops.

17. Design and implementation of Decade Counters using IC 7490 (N=1 to 9)

Reference Books:

Sl.
Author/s Title Publisher Details
No.
1 Donald P Leach, Albert Paul Digital Principles and 8th Edition, Tata
Malvino& Goutam Saha Applications McGraw Hill, 2015
2 M. Morris Mano Digital Design 7th Edition, Pearson
Prentice Hall, 2016
3 D. P. Kothari and J. S Dhillon Digital Circuits and Pearson, 2016
Design
4 Charles H Roth Jr., Larry L. Fundamentals of Logic Cengage Learning,
Kinney Design 7thEdition.

Web References:
Sl. No. Web link
1 https://nptel.ac.in/courses/108/106/108106177/
2 https://nptel.ac.in/courses/117/105/117105080/

Course Program Outcomes PSO’s


Outcomes PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 P012 PSO1 PSO2 PSO3 PSO4
CO-1 3 3 3 1 3 1 1 1 3 2 2 2 3 1 1 1
CO-2 3 3 3 3 3 2 1 2 2 1 1 2 2 3 1 1
CO-3 3 3 3 3 3 1 1 2 2 2 2 2 3 3 1 1

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