Department of Computer Science and Engineering

NITK, Surathkal
CO204 – Design of Digital Systems Lab [B. Tech, 3rd Semester]
(Syllabus and Assessment)

Semester: III [S1 & S2] Academic Year: 2017-18 Credits: (0-0-3) 4

A. Syllabus

Module I (Venue: Computer Lab)

(Number Systems Using C Programming)
1. Write a C program to perform (input)x to (output)y.
2. Write a C program to find ‘x’ and ‘y’ with respect to (number1)x = (number2)y, where, number1
and number2 are the inputs.
3. Write a C program to perform addition, subtraction, multiplication and division on (number1) x
and (number2)x.
4. Write a C program to perform ‘x’ and ‘x-1’complemention of (number)x.
5. Write a C program to prove the self-complementing property a weighted number system.

Module II (Venue: Digital Lab)

(Combinational and Sequential Circuits Using Hardware)

1. Verify the truth table for Basic (AND, OR, NOT), Universal (NAND, NOR) and Advanced logic
gates (EXOR, EXNOR) using a digital IC trainer kit.
2. Implement – (i) Basic gates using universal gates. (ii) NAND gate using NOR gate and (iii)
NOR gate using NAND gate.
3. Implement to find r’s and (r-1)’s complement of a given number using Universal gates only.
4. Implement a given Boolean function using (i) 1 or 2 input basic gates (ii) universal gates, after
simplification using Boolean algebra, K-map.
5. Implement
(i) Grey code to Binary code and vice versa.
(ii) Excess-3 to BCD code and vice versa.
(iii) Output binary number equal to the square of the input number.
(iv) 9’s complement of decimal equivalent of BCD.
and so on.

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6. Implement – (i) Half Adder (ii) Half Subtractor (iii) Full Adder (iv) Full Subtractor
7. Implement, (i) 4-bit adder using decoder
(ii) 4-bit adder using multiplexer
(iii) 4-bit subtractor using decoder
(iv) 4-bit subtractor using multiplexer
and so on.

8. Flip-flops truth table verification.

9. Implement, (i) synchronous and asynchronous counter
(ii) Johnson counter
(iii) Ripple counter
(iv) Register

10. Hardware implementation for the given statements.

Module III (Venue: Computer Lab)

(Combinational and Sequential Circuits Design using Logisim and Verilog)

1. Verify the truth table for Basic (AND, OR, NOT), Universal (NAND, NOR) and Advanced logic
gates (EXOR, EXNOR) using a digital IC trainer kit.
2. Implement – (i) Basic gates using universal gates. (ii) NAND gate using NOR gate and (iii)
NOR gate using NAND gate.
3. Implement to find r’s and (r-1)’s complement of a given number using Universal gates only.

4. Implement a given Boolean function using (i) 1 or 2 input basic gates (ii) universal gates, after
simplification using Boolean algebra, K-map.
5. Implement
(i) Grey code to Binary code and vice versa.
(ii) Excess-3 to BCD code and vice versa.
(iii) Output binary number equal to the square of the input number.
(iv) 9’s complement of decimal equivalent of BCD.
and so on.

6. Implement – (i) Half Adder (ii) Half Subtractor (iii) Full Adder (iv) Full Subtractor
7. Implement, (i) 4-bit adder using decoder
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 (ii) 4-bit adder using multiplexer
(iii) 4-bit subtractor using decoder
(iv) 4-bit subtractor using multiplexer
and so on.

8. Flip-flops truth table verification.

9. Implement, (i) synchronous and asynchronous counter
(ii) Johnson counter
(iii) Ripple counter
(iv) Register
10. Hardware implementation for the given statements.

B. Weekly Planning

Sl. No./
Dates To be Completed Remarks
Week No.
1 July 31 – Aug 04 Module I (C Program) -
2 Aug 07 – Aug 11 Module I (C Program) Lab Record
3 Aug 14 – Aug 18 Module II ( 1, 2 & 3) -
4 Aug 21 – Aug 25 Module II (4 & 5) Lab Record
5 Aug 28 – Sep 01 Module II (6 & 7) Lab Record
6 Sep 04 – Sep 08 Module II (8 & 9) Lab Record
7 Sep 11 – Sep 15 Theory Mid-Sem Examination -
8 Sep 18 – Sep 22 Module II (10) Lab Record
9 Sep 25 – Sep 29 Laboratory Mid-Sem Examination Max. Marks: 25
10 Oct 02 – Oct 06 Module III (1, 2, 3 & 4) -
11 Oct 09 – Oct 13 Module III (5, 6 & 7) Lab Record
12 Oct 16 – Oct 20 Module III (8 & 9) Lab Record
13 Oct 23 – Oct 27 Module III (10) Lab Record
14 Oct 30 – Nov 03 Mini-Project Progress 1
15 Nov 06 – Nov 10 Mini-Project Progress 2
16 Nov 13 – Nov 16 Laboratory End-Sem Examination Exam & Mini-Project
Demo
Note:
1. Module I, lab record should contain handwritten flowchart, program and output.
2. Module II, lab record should contain hand drawn circuit diagram.
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3. Module III, lab record should contain handwritten code.
4. Irrespective of holidays, students should strictly follow the weekly plan with the extra
laboratories.

C. Assessment Scheme

Sl. No. Item % of Marks Remarks

Viva – 10 %
1 End-Sem Examination 50 Question 1 – 20 %
Question 2 – 20%
Viva – 5 %
2 Mid-Sem Examination 25
Question 1 – 20 %
Viva – 5 %
3 Surprise Test (2 Test) 15
Question 1 – 10 %
4 Regular Lab Activity 10 Best 5 Marks

Course Instructor DUGC H.O.D

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