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Efficient Signal Filtering: Integrating Polyphase

Structure with Distributed Arithmetic in FIR Filters
Jai Surya S Sharon Sthuthi E Sarabojirajan B
2 Electronics and Communication Eng., Electronics and Communication Eng., Electronics and Communication Eng.,
SRM Institute of Science and SRM Institute of Science and SRM Institute of Science and
Technology, Kattankulathur, Chennai, Technology, Kattankulathur, Chennai, Technology, Kattankulathur, Chennai,
js7841@srmist.edu.in se6363@srmist.edu.in sb4746@srmist.edu.in

Sudhanya P*
8 SRM Institute of Science and
Technology, Kattankulathur, Chennai,
sudhanyp@srmist.edu.in
Corresponding Author: Sudhanya P

Abstract— This paper presents an approach to FIR filter lowering power consumption, making DA-based FIR filters
design using polyphase decomposition and pipelining techniques ideal for power-sensitive applications.
to enhance both speed and power efficiency. By utilizing a
polyphase structure, the FIR filter is divided (decomposed) into
multiple sub-filters that operate in parallel, significantly This research proposes a novel polyphase FIR filter design
reducing the computational load. Pipelining ensures that the integrating polyphase decomposition, pipelining, and
critical path delay is minimized, allowing higher operating Distributed Arithmetic. The goal is to enhance performance
frequencies and reduced power consumption. Performance and reduce power consumption, particularly for real-time
evaluations on FPGA implementations demonstrate notable DSP applications on FPGA platforms. The results
improvements in processing speed and reduced power demonstrate notable improvements in speed and energy
consumption compared to conventional FIR filters. efficiency, offering a practical solution to the demands of
modern DSP systems.
Keywords—(FIR) Finite Impulse Response, (DA) Distributed
Arithmetic Algorithm, (DSP) Digital Signal Processing, (LUT)
Look Up Table. II. BACKGROUND RESEARCH

1 I. INTRODUCTION
FIR filters are fundamental components in digital signal
processing, utilized across various applications including
Finite Impulse Response (FIR) filters are essential telecommunications and biomedical engineering due to
components in digital signal processing (DSP), playing a theirstability and linear phase characteristics. However,
critical role in applications like telecommunications, audio traditional FIR filter implementations face challenges in
processing, and biomedical signal analysis. Known for their efficiency and power consumption, especially as the
1 stability and phase linearity, FIR filters can, however, face filter order increases. Amit Rai (2024) explored FIR
challenges as the filter order increases. A higher number of filter modeling using the distributed arithmetic (DA)
taps leads to more computations, resulting in increased power algorithm on FPGA platforms, demonstrating how DA
consumption and slower processing speeds. This is can optimize FIR filter performance by replacing
particularly significant in real-time systems where efficiency multipliers with lookup tables (LUTs) to lower power
and speed are paramount. usage [1].

To address these challenges, polyphase decomposition can be Zheng and Wei (2018) demonstrated that FPGA-based
employed, breaking the FIR filter into several smaller sub- implementations of FIR filters using DA algorithms are
filters, each corresponding to a specific phase. This approach effective for achieving lower power consumption while
enables parallel processing, allowing multiple phases of the maintaining performance integrity. Their research
signal to be handled simultaneously without increasing underscores how hardware-efficient methods like DA are
computational complexity. Polyphase FIR filters are suitable for FIR filter designs on FPGAs [5]. Further,
12 particularly advantageous in Field-Programmable Gate Nguyen and Nhi (2018) presented a hardware-efficient
Arrays (FPGAs), where their parallel processing capabilities implementation of polyphase FIR filters on FPGA,
can be fully exploited. Additionally, pipelining enhances confirming the utility of the polyphase method in
performance by dividing the filtering process into smaller, optimizingperformance and power consumption in real-
sequential stages that can be processed simultaneously. This time digital processing environments. [2]
increases clock rates without extending critical path delays,
resulting in faster processing times. Polyphase structures are used to decompose FIR filters
into sub-filters, allowing for parallel processing that
Moreover, Distributed Arithmetic (DA) further optimizes the significantly reduces computational complexity. Datta
design by replacing traditional multiplication with and Dutta (2021) investigated polyphase digital down
precomputed values stored in lookup tables (LUTs). This converters on FPGA, highlighting the advantages of
significantly reduces the need for complex multipliers, thus using polyphase decomposition for enhancing signal
processing efficiency in real-time systems. This

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approach minimizes processing latency and optimizes (2019), whose methods to reduce computational load are
resource utilization, making it suitable for high-speed essential for enhancing the responsiveness of DA-based
applications. Similarly, Yang and Li (2015) emphasized filters. Supporting this, Sinhmar and Rai (2012) provide
the efficient design of polyphase filter banks for multi- insights on filter behavior across time and frequency
rate systems, showcasing the technique’s ability to domains, aiding in the calibration of our design for stable
improve performance through parallelism. [3][4][5] performance.[11][12]

Research into power-efficient FIR filter designs continues Naveen and Kiran's (2015) work on reconfigurable DA FIR
to be a focus, especially in the context of real-time filters highlights real-time flexibility without performance
applications. Bhavya et al. (2021) examined distributed loss, guiding our adaptable design. Power efficiency is
arithmeticcombined with offset binary coding algorithms to addressed by Vinay et al. (2020), who apply DA techniques
optimize FIR filter performance, highlighting to create energy-saving filters—a strategy that aligns well
improvements in speed and power efficiency through low- with our low-power focus. Muktesh et al. (2022) further
complexity hardware configurations [6]. contribute by showing how optimization algorithms can
enhance filter detail processing, an approach adaptable to
Power consumption and efficiency have been critical areas improve DA filter precision in high-detail applications.
of research. Rai (2023) presents an optimized 4-bit These studies together form a comprehensive foundation
programmable FIR filter using adiabatic techniques, for an adaptable, power-efficient polyphase DA FIR filter
focusingon minimizing power consumption in digital signal tailored for advanced DSP.[13][14][15]
processing systems. This approach effectively reduces
dynamic power dissipation by employing energy-recovery III. FIR FILTER DESIGN
mechanisms, resulting in significantly lower power usage.
While Rai’s work addresses the need for low-power
solutions, it focuses on adiabatic logic rather than structural 3.1 FIR Filter
11 optimizations like polyphase decomposition. Our research The serial 4-tap Finite Impulse Response (FIR) filter is a
builds upon this background by leveraging polyphase FIR fundamental structure in digital signal processing,
filter architecture, aimed at reducing computational characterized by its use of four discrete stages to process an
complexity and power consumption while maintaining high input signal. The term "4-tap" denotes that the filter employs
performance in digital filtering tasks. This comparison four coefficients, or taps, which are essential for generating
highlights different strategies to achieve low-power, high- the desired output through convolution with the input signal.
efficiency designs.[7][8]

The design of an efficient polyphase distributed arithmetic

(DA) FIR filter is informed by foundational studies on
polyphase and DA filters for optimized digital signal
processing. Kuo and Wang (2014) emphasize the
computational benefits of polyphase FIR filters in reducing
processing complexity for multi-rate systems, an approach
well-suited to our efficiency goals. Chen and Xu (2017)
extend this by demonstrating high-speed polyphase filter Fig 1 FIR Filter Architecture
implementations, crucial for the rapid processing
requirements in our design.[9][10] The architecture of a serial 4-tap FIR filter consists of several
key components:
Optimization for real-time applications is explored by Doe

Fig.2 DA Algorithm Flow Diagram

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Input Sampling: The filter operates on an input signal, simultaneous computation and enhances throughput.
typically represented as an 8-bit data stream. This signal is Additionally, various functional modules are designed,
sampled at consistent intervals, with each sample being including the shift register, lookup tables, adder/subtractor,
processed sequentially through the filter stages. and accumulator. These modules are orchestrated to work in
Shift Register: A shift register is utilized to temporarily store conjunction with the polyphase design, allowing for an
the most recent input samples. As new samples are received, effective filtering operation while minimizing resource
the older samples are shifted through the register, ensuring usage. The entire system is implemented in Verilog, ensuring
that the filter has access to the latest data necessary for a scalable and modular design suitable for hardware
convolution with the filter coefficients. implementation.
Filter Coefficients: The coefficients that define the filter's
frequency response are stored in a Look-Up Table (LUT). 4.1 Design Overview
Each coefficient corresponds to a specific tap, allowing for the
scaling of the shifted input samples during processing. The polyphase FIR filter design proposed in this paper
Weighted Summation: The output of the filter is computed divides the input signal into multiple phases, each processed
by taking the product of each sample held in the shift register by independent FIR sections. Each phase operates on distinct
and its associated filter coefficient. This operation is executed segments of the input data, allowing the computations to
serially, simplifying the overall design and reducing the need occur in parallel. By employing a demultiplexing stage, the
for complex multipliers. input samples are separated and fed into different FIR
Accumulation: The results from the weighted summation are sections corresponding to different phases.[8]
then accumulated to produce the final output of the filter. An
accumulator is employed to sum the contributions from each In addition to polyphase decomposition, pipelining is
tap, yielding the filtered signal after processing all four taps. incorporated at various stages of the design, reducing the
5 The equation governing the filter's output can be written as: critical path delay. Each stage of the FIR filter – including the
shift register, distributed arithmetic (DA) lookup table,
{M−1} adder/subtractor, accumulator, and feedback unit – is
y[n] = ∑ ℎ[𝑘] ⋅ x[n − k] [1] pipelined to enhance throughput without significantly
{k=0} increasing resource utilization.[9][1]

The modular design allows for easy scalability, enabling the

3.2 Overview of the DA Algorithm filter to handle more taps or phases if needed. The
combination of pipelining and parallelism from the polyphase
decomposition results in improved speed and reduced power
The Distributed Arithmetic (DA) algorithm is an consumption.
efficient computational technique widely employed for
2 implementing linear filtering operations, particularly in the
context of Finite Impulse Response (FIR) filters. This
algorithm is particularly advantageous in applications that
demand low power consumption and optimal hardware
utilization, making it a preferred choice in digital signal
processing and embedded systems. The DA algorithm
exploits the binary representation of numbers to perform
multiplications and additions in a parallel manner,
significantly enhancing computational efficiency. Unlike
traditional methods that rely on dedicated multipliers for each
multiplication operation, the DA algorithm utilizes pre-
computed values stored in Look-Up Tables (LUTs). This
approach minimizes the need for complex hardware resources,
7 making it especially beneficial for implementation in Field
Programmable Gate Arrays (FPGAs) and Application-
Specific Integrated Circuits (ASICs), where power and area
constraints are critical considerations.
Fig.3 Polyphase Filter Flow Diagram

IV. METHODOLOGY
4.2 LUT Configuration
1 The proposed methodology for implementing a 4-tap FIR
filter using the Distributed Arithmetic (DA) algorithm
encompasses several key components, each playing a critical The LUT is configured to contain pre-computed values
corresponding to the filter coefficients and the various
role in achieving efficient signal processing. This combinations of input samples. In this design, the LUT has a
methodology involves the design of a digital filter that width of 8 bits to accommodate the filter coefficients,
integrates the polyphase structure, allowing for efficient allowing it to handle a wide range of values. The LUT is
parallel processing of input signals. The polyphase approach indexed using a 4-bit input derived from the shift register,
divides the filter's taps into multiple phases, which enables which represents the binary form of the input samples.

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Each entry in the LUT corresponds to a specific combination minimize the propagation delay across the filter. This allows
of input bits, derived from the outputs of the shift register. the filter to operate at higher clock frequencies.

• The weights 𝑤0, 𝑤1, 𝑤2, w3 represent the filter coefficients Pipelining also helps reduce power consumption, as each
and are pre-defined to achieve the desired filtering stage consumes power only when it is active. The reduced
characteristics. delay per stage means the clock frequency can be lowered
while maintaining the same throughput, leading to lower
dynamic power consumption. Additionally, the use of DA
LUTs eliminates the need for power-hungry multipliers,
further optimizing the design for low-power operation.
Feedback processing is simplified, minimizing unnecessary
operations.
V. RESULTS

1 The implementation of the 4-tap FIR filter using the

Distributed Arithmetic (DA) algorithm and polyphaser filter
2 implementation was evaluated through simulation and
performance analysis. The results demonstrate the
effectiveness of the proposed design in processing digital
signals with high accuracy and efficiency.

Fig 4 LUT Case Values

The design of the LUT also allows for easy modifications to

filter coefficients without extensive hardware redesign. This
flexibility is advantageous for adapting the filter
characteristics to meet specific application requirements.
Furthermore, the pre-computation of values within the LUT
enhances operational speed, allowing the FIR filter to process
incoming data samples with minimal latency.[1][3]
4.3 Polyphase Filter Theory and Implementation

Polyphase decomposition is a technique used to split the FIR

14 filter into sub-filters, each of which processes a fraction of the
input data. Mathematically, the impulse response of the filter
is divided into multiple phases, each corresponding to one Fig.5 Polyphase FIR Simulated Waveform
sub-filter. These sub-filters, operating in parallel,
significantly reduce the overall computational load.
The simulation waveform in Figure 5 confirms the successful
In this design, a two-phase polyphase FIR filter is implementation and functionality of the proposed polyphase
implemented. The input signal is demultiplexed, and the FIR filter. The clk and reset signals are operating correctly,
lower and upper halves of the signal are fed into two distinct and the 4-bit data_in is appropriately processed by the filter.
FIR sections. Each FIR section processes its corresponding The output signal [filter_out] , dynamically changes in
portion of the input, and the results are combined to form the response to the input, demonstrating the filter's real-time
final filtered output. The shift register stages store input performance. Key filter parameters, such as NUM_TAPS,
samples for each phase, while distributed arithmetic (DA) is WIDTH, and PHASES, are configured and reflected in the
employed to perform efficient multiply-accumulate (MAC) testbench, ensuring accurate operation.
operations. [3][4]

The DA LUT reduces the complexity of multiplications by

using precomputed values, further contributing to power
savings. The outputs of each phase are accumulated, and
feedback is applied to maintain filter stability.[1]

4.4 Pipeline and Power Optimization

The proposed design implements pipelining to maximize

operating speed by breaking down each stage of the FIR filter
into smaller sub-tasks. By adding pipeline registers between
each stage (such as between the shift register and the DA
Fig.6 Simulated DA Alg.Waveform
LUT, and between the DA LUT and the accumulator), we

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The simulation validates the designed polyphase structure, The computational efficiency of the polyphase FIR filter is
confirming its capability for efficient filtering while notable , especially when compared to conventional FIR filter
maintaining synchronization with the clock, highlighting its designs. By utilizing a polyphase architecture, the filter
suitability for high-speed digital signal processing effectively splits the input signal into multiple phases,
applications. allowing for concurrent processing.
Table 2 Comparison results of existing architectures and proposed FIR Implimentation

No. of Clock LUTs DSP Total Max Frequency

Architecture Delay (ns)
Taps Cycles Used Slices Power (W) (MHz)

1 per
Standard FIR 6 200 2 9.551 130 7.692
sample
Proposed
6 1 per phase 160 2 0.253 150 6.667
Polyphased FIR
1 per
Direct Form FIR 4 160 2 0.300 100 10.000
sample
Distributed 1 per bit-
8 220 3 1.200 140 8.333
Arithmetic FIR level
Our Solution
6 1 per phase 160 2 0.253 150 6.667
(Polyphased DA)

The simulation waveform in Figure 6 demonstrates the This parallelism not only increases throughput but also
functionality and behavior of individual modules within the minimizes the latency associated with filter operations. The
FIR filter, including the shift register, DA LUT, accumulator, implementation statistics reflect a total on-chip power
adder-subtractor, and feedback components. The clk and consumption of only 0.254 W, indicating a well-optimized
reset signals are functioning as expected, and the data_in is design that balances performance and power efficiency. The
accurately processed by the FIR structure. The intermediate design's use of 160 LUTs and 23 flip-flops demonstrates
outputs, such as siso_out, da_out, add_sub_out, acc_out, and effective resource utilization, allowing it to process multiple
feedback_out, show correct data propagation through each data streams simultaneously without significant overhead.
stage of the filtering process.
Table.1 Utilization Hierarchy

Polyphase Fir Slice Slice F7 Muxes

Tap No. LUTs Registers
Tap 0 78 11 10
Tap 1 81 12 8
Total 160 23 10

Fig.7 RTL Polyphase Schematic

The correct behavior of these signals confirms that the Consequently, the combination of reduced power
designed FIR filter operates as intended, with synchronized consumption, minimal delay, and enhanced data handling
input and output data. This validates the use of distributed capabilities establishes this polyphase FIR filter as a highly
arithmetic in efficiently computing the filter response, efficient solution for applications requiring high-speed signal
ensuring proper real-time filtering operations suitable for processing while maintaining energy efficiency.
power-constrained applications.
The implemented polyphase FIR filter design demonstrates
enhanced efficiency compared to traditional FIR filter
implementations. By utilizing input demultiplexing, it
processes data across multiple phases concurrently, leading
to reduced resource utilization and lower power
consumption. This design allows for targeted optimizations
in each filter section, resulting in significant decreases in both
dynamic and static power usage.
Fig.8 RTL DA FIR Schematic
The total on-chip power measured at 0.254 W highlights its
efficiency, particularly in I/O operations. Overall, the

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1 polyphase FIR filter effectively balances high performance 2. Zheng J and Wei Z (2018) FIR filter design based on FPGA, 2018 10th
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