Combinational Logic Circuits

 Remember logic gates are the building blocks of the digital circuits.
 In combinational logic gates we can notice that we are free to use any
gate to express a logic operation.
 Restricting our choice of gates to one type has the advantage of
simplicity – of avoiding using a range of gates – but this advantage is
apparently offset by the major disadvantage that more gates are being
used.
 Combinational Logic Circuits are memoryless digital logic circuits whose
output at any instant in time depends only on the combination of its
input.
 Combinational logic circuits do not have an internal stored state, i.e.,
they have no memory. Consequently the output is solely a function of
the current inputs.
 Unlike Sequential Logic Circuits whose outputs are dependent on both
their present inputs and their previous output state giving them some
form of Memory.
 The outputs of Combinational Logic Circuits are only determined by
the logical function of their current input state, logic “0” or logic
“1”, at any given instant in time.
 The result is that combinational logic circuits have no feedback, and
any changes to the signals being applied to their inputs will
immediately have an effect at the output. In other words, in a
Combinational Logic Circuit, the output is dependent at all times on
the combination of its inputs.
 Combinational Logic Circuits are made up from basic logic gates
that are “combined” or connected together to produce more
complicated switching circuits.
 These logic gates are the building blocks of combinational logic
circuits.
 An example of a combinational circuit is a decoder, which
converts the binary code data present at its input into a number
of different output lines, one at a time producing an equivalent
decimal code at its output.
 Combinational logic circuits can be very simple or very
complicated and any combinational circuit can be implemented by
using“universal” gates.
 As combinational logic circuits are made up from individual
logic gates only, they can also be considered as “decision
making circuits”.
 Combinational logic is about combining logic gates together
to process two or more signals in order to produce at least
one output signal according to the logical function of each
logic gate.
 Common combinational circuits made up from individual
logic gates that carry out a desired application include
Multiplexers, De-multiplexers, Encoders, Decoders, Full
and Half Adders etc.
Classification of Combinational Logic
 One of the most common uses of combinational logic is in Multiplexer
and De-multiplexer type circuits.
 Here, multiple inputs or outputs are connected to a common signal
line and logic gates are used to decode an address to select a single
data input or output switch.
 A multiplexer consist of two separate components, a logic decoder
and some solid state switches.
 AND-OR Logic
 Fig.(a) shows an AND-OR circuit consisting of two 2-input AND gates and one 2-
input OR gate; Fig.(b) is the ANSI standard rectangular outline symbol. The
Boolean expressions for the AND gate outputs and the resulting SOP expression
for the output X are shown in the diagram. In general, all AND-OR circuit can
have any number of AND gates each with any number of inputs.

For a 4-input AND-OR logic circuit, the output X is HIGH (1) if both input
A and input B are HIGH (1) or both input C and input D are HIGH (1).
UNIVERSAL PROPERTY OF NAND AND NOR
GATES
 The NAND gate is a universal gate because it can be used to produce the NOT, the
AND, the OR, and the NOR functions.
 An inverter can be made from a NAND gate by connecting all of the inputs
together and creating, in effect, a single input, as shown in Fig.(a) for a 2-input
gate.
 An AND function can be generated by the use of NAND gates alone, as shown in
Fig.(b).
 An OR function can be produced with only NAND gates, as illustrated in part (c).
 Finally. a NOR function is produced as shown in part (d).
The NOR Gate as a Universal Logic Element

 Like the NAND gate, the NOR gate can be used to produce the NOT, AND.
OR and NAND functions.
 A NOT circuit, or inverter, can be made from a NOR gate by connecting
all of the inputs together to effectively create a single input, as shown
in Fig.(a) with a 2-input example.
 Also, an OR gate can be produced from NOR gates, as illustrated in
Fig.(b). An AND gate can be constructed by the use of NOR gates, as
shown in Fig.(c).
 Basic Adders
 Half Adder
 A half-adder adds two bits and produces a sum and a carry output.
Adders are important in computers and also in other types of digital
systems in which numerical data are processed.

Recall Basic Rules for Binary:

The operations are performed by a logic circuit called a half-adder.

 The half-adder accepts two binary digits on its inputs and produces two
binary digits on its outputs, a sum bit and a carry bit.
 A half-adder is represented by the logic symbol in Fig.(1.1). Table.(1.1):Truth table for a half-adder

 Half-Adder Logic: From the operation of the half-adder as stated in

Table 1-1, expressions can be derived for the sum and the output carry
as functions of the inputs. Notice that the output Carry (Cout) is a 1
only when both A and B are 1s: therefore. Cout can be expressed
Cout = AB
 Now observe that the sum output ( Σ ) is a 1 only if the input variables A
and B, are not equal. The sum can therefore be expressed as the
Exclusive-OR of the input variables.

Fig.(1.1):Logic symbol for a half-adder. Fig.(1.2):Logic circuit diagram for a half-adder

The Full-Adder
 The second category of adder is the full-adder. The full-adder accepts
two input bits and an input carry, and generates a sum output and an
output carry.
 The basic difference between a full-adder and a half-adder is that the
full-adder accepts an input carry. A logic symbol for a full-adder is
shown in Fig.(1-3), and the truth table in Table 1-2 shows the operation
of a full-adder.

Fig.(1-3): Full adder symbol

Fig(1-4): Arrangement of two half adders

to form a full adder symbol
Table.(1-2):Truth table for Full adder

Fig.(1-5): Complete logic circuit for a Full adder

To do
 Determine the outputs of the inputs shown;
 The 74LS283 4-BIT Parallel Adder
 An example of a 4-bit parallel adder that is available in IC form shown below.
 Vcc is the pin 16 and ground is the pin 8 which is a standard configuration.
The pin diagram and logic symbol for this device are shown. The device may
be available in other TTL or CMOS families.
Subtractors
 Half Subtractors
 Half subtractor is a combination circuit with two inputs and two outputs (difference
and borrow). It produces the difference between the two binary bits at the input and
also produces an output (Borrow) to indicate if a 1 has been borrowed. In the
subtraction (X-Y), X is called as Minuend bit and Y is called as Subtrahend bit.
 If we compare the Boolean expressions of the half subtractor with a half adder, we
can see that the two expressions for the SUM (adder) and DIFFERENCE (subtractor)
are exactly the same and so they should be because of the Exclusive-OR gate
function. The two Boolean expressions for the binary subtractor BORROW is also very
similar to that for the adders CARRY. Then all that is needed to convert a half adder
to a half subtractor is the inversion of the minuend input X.

 One major disadvantage of the Half Subtractor circuit when used as a binary
subtractor, is that there is no provision for a “Borrow-in” from the previous circuit
when subtracting multiple data bits from each other. Then we need to produce what
is called a “full binary subtractor” circuit to take into account this borrow-in input
from a previous circuit.
Full Subtractors
 The disadvantage of a half subtractor is overcome by full
subtractor.
 The full subtractor is a combinational circuit with three
inputs X, Y, Bin and two output D for difference and Bout.
X is the 'minuend’, Y is 'subtrahend’, Bin is the 'borrow'
produced by the previous stage, D is the difference output
and Bout is the borrow output.

Full Subtractor Block Diagram

Full Subtractor Logic Diagram
As the full subtractor circuit below represents two half
subtractors cascaded together, the truth table for the full
subtractor will have eight different input combinations as there
are three input variables, the data bits and the Borrow-in, BIN
input. Also includes the difference output, D and the Borrow-out,
BOUT bit.
COMPARATORS
 The basic function of a comparator is to compare the magnitudes of two
binary quantities to determine the relationship of those quantities. In its
simplest form, a comparator circuit determines whether two numbers are
equal.

Equality
 The exclusive-OR gate can be used as a basic comparator because its output
is a 1 if the two input bits are not equal and a 0 if the input bits are equal.
The figure below shows the exclusive-OR gate as a 2-bit comparator
 In order to compare binary numbers containing two bits each, an additional
exclusive- OR gate is necessary. The two least significant bits (LSBs) of the two
numbers are compared by gate G1. and the two most significant bits (MSBs) are
compared by gate G2, as shown in Fig.(7-12). If the two numbers are equal,
their corresponding bits are the same, and the output of each exclusive-OR
gate is a 0. If the corresponding sets of bits are not equal, a 1 occurs on that
exclusive-OR gate output.

Logic diagram for equality comparison of two 2-bit numbers.

Example
 Inequality
 In addition to the equality output, many IC comparators provide additional
outputs that indicate which of the two binary numbers being compared is the
larger. That is, there is an output that indicates when number A is greater than
number B (A > B) and an output that indicates when number A is less than
number B (A < B), as shown in the logic symbol for a 4-bit comparator in Fig.
below.
To determine an inequality of binary numbers A and B, you first
examine the highest-order bit in each number. The following
conditions are possible:
1. If A3 = 1 and B3 = 0, number A is greater than number B.
2. If A3 = 0 and B3 = 1 number A is less than number B.
3. If A3 = B3, then you must examine the next lower bit position for an
inequality
 These three operations are valid for each bit position in the
numbers.
 The general procedure used in a comparator is to check for an
inequality in a bit position starting with the highest-order bits
(MSBs).
 When such an inequality is found, the relationship of the two
numbers is established and any other inequalities in lower order
bit position must be ignored because it is possible for an opposite
indication to occur: the highest order indication must take
precedence.
Example
 Determine the A=B, A>B and A<B outs for the input numbers shown on the
comparator below.

 What are the comparator outputs when A3A2A1A0 =1001 and B3B2B1B0=1010?
 Pin diagram and logic symbol for 74HC85