Solution:

a.) Full adder using two half adders

b.)

C.)
d.)

e.)
Step-1: Construct the characteristic table of T flip-flop and excitation table of the J-K flip-flop.

Step 2: Using the K map, find the Boolean expression for J and K in terms of T.

J=T
K=T
Step 3: Construct the circuit diagram for converting the J-K flip-flop into a T flip-flop.

f.)
Synchronous Circuit Asynchronous Circuit

The State Variables are not

All the State Variable changes are synchronized to change simultaneously
synchronized with a universal clock and may change at any time irrespective
signal. of each other to achieve the next Steady
Internal State

Since all the Internal State changes are in Since there is no such universal clock
the strict control of a master clock source, source, the internal state changes as
they are less prone to failure or to a race soon as any of the inputs change and
condition and hence are more reliable. hence is more prone to a race condition.

The changes in the internal state of an

Timings of the internal state changes are
asynchronous circuit are not in our
in our control.
control.

g.)

The contents of the register after each shift are:

1. 1101
2. 0110
3. 1011
4. 1101
5. 1110
6. 1111

Thus, after six shifts, the final register content is 1111

h.)

Moore and Mealy are two types of Finite State Machines (FSMs) used in digital circuits and
automation. The key difference lies in how they generate outputs.

1. Moore FSM

• Output depends only on the current state.

• More stable output since it changes only when the state changes.
• Easier to design and debug because the output is not affected by sudden input changes.
• Requires more states compared to a Mealy machine for the same functionality.
Output equation:

Output=f(State) Output = f(State) Output=f(State)

2. Mealy FSM

• Output depends on both the current state and input.

• Faster response since the output can change immediately with input.
• Fewer states compared to a Moore machine for the same function.
• More complex to design due to output dependency on input.

Output equation:

Output=f (State, Input) Output = f (State, Input) Output=f (State, Input)

i)
Modulus of a Counter
The modulus (MOD) of a counter refers to the number of unique states it cycles through before
resetting to its initial state.
• A counter with modulus N counts from 0 to N-1 before resetting to 0.
• It is also called a MOD-N counter.
• The number of flip-flops (FFs) required to implement a counter is determined by the
number of flip-flops≥ Log2(N)
j.)
Address Lines Calculation
• The memory size is 8K, meaning it has 8 × 1024 = 8192 memory locations.
• To address 8192 locations, we need a certain number of address lines (N).
• The formula for the number of address lines is: 2N=Total memory location
• 2N= 8192
• N=log2(8192) =13
• Number of address lines required = 13
2. Data Lines Calculation
• Each memory location stores 12 bits.
• The number of data lines is equal to the word size (i.e., the number of bits stored per
location).
Number of data lines required = 12
 SECTION B
b)
What is a Bidirectional Shift Register?
A Bidirectional shift register is a circuit which shifts data in both left and right directions. It
stores the data using a number of flip-flops to shift in accordance with the control signal. Its
ability to also perform wide-range data motion makes it extremely useful in environments
where robust adaptability is needed, such as serialization to parallelism conversion and
arithmetic. A bidirectional shift register is a sequential circuit that can shift data both leftwards
and rightwards. It consists of a series of flip-flops connected in a chain, allowing the data to be
shifted in either direction. The number of flip-flops used determines the size of the shift register
and its data storage capacity.
Bidirectional Shift Register Circuit Diagram
A bidirectional shift register is a versatile circuit used for shifting data either to the right or left
based on an input signal. It can be implemented using D flip-flops and logic gates, enabling the
transfer of data from one stage to the next stage in the desired direction determined by a mode
control signal. This flexible functionality makes bidirectional shift registers an essential
component in various digital systems.

Working Principle of Bidirectional Shift Register

The bidirectional shift register operates based on clock pulses and control signals. It has two
modes of operation: shift right and shift left. Let’s explore these modes in detail:
Shift Right: In the shift right mode, the data is shifted from the leftmost bit to the rightmost
bit. Each clock pulse triggers the transfer of data to the adjacent flip-flop on the right. The
rightmost bit receives the input data, while the leftmost bit is discarded.
Shift Left: In the shift left mode, the data is shifted from the rightmost bit to the leftmost bit.
Each clock pulse triggers the transfer of data to the adjacent flip-flop on the left. The leftmost
bit receives the input data, while the rightmost bit is discarded.
C)
The state reduction technique generally prevents the addition of duplicate states. The reduction
in redundant states reduces the number of flip-flops and logic gates, reducing the cost of the
final circuit. Two states are said to be equivalent if every possible set of inputs generates the
same output and the same next state. When two states are equal, one of them can be eliminated
without changing the input-output relationship. The state reduction algorithm is applied in the
state table to reduce equivalent states.

States g and e both go to states a and f and have outputs of 0 and 1 for x = 0 and x = 1,
respectively.
Thus, the row with present state g is removed and stage g is replaced by state e each time it
occurs in the next state columns. Present state f now has next states e and f and outputs 0 and
1 for x = 0 and x = 1. The same next states and outputs appear in the row with the present state
d. Therefore, states f and d are equivalent and can be removed and replaced with d.
Final reduced state

d)

e.)
4 to 2 Priority Encoder
This is also referred to as 4- bit priority, which consists of 4 inputs and 2 output lines. Since an
encoder contains 2^n input lines and n output lines. The third output is ‘V’, which is considered
as a valid but indicator and it is set to 1 when more than one input line is high or active (1).

If the valid bit is equal to ‘0’, then all the inputs are ‘0’. In this case, the other 2 output lines
are considered as don’t care conditions denoted by ‘X
The truth table of a 4 to 2 priority encoder is shown below.

D3 D2 D1 D0 A B V

0 0 0 0 X X 0

1 0 0 0 0 0 1

X 1 0 0 0 1 1

X X 1 0 1 0 1

X X X 1 1 1 1

From the above truth table, we can observe that D3, D2, D1, D0 are the inputs; A and B are the
outputs and V is the valid bit indicator. Here D3 input is the highest priority input and D0 is
the lowest priority input. When the input D3 is active high (1), which has the highest priority
irrespective of all other input lines, then the output of the 4-bit priority encoder is 11.When the
D3 input is active low and the D2 is active high that has the next highest priority irrespective
of all other input lines, then the output is BA=10. When D3, D2 inputs are active low, and the
D1 is active high and has the next highest priority regardless of the remaining input line, then
the output will be BA = 01. The output expression can be determined for a 4-bit encoder with
the help of a karnaugh map (K-map) as shown below.

A = D3 + D1D2′
B= D2 + D3
V = D0 + D1 + D2 + D3
From the above K-map, the simplified expressions for the outputs A and B are obtained. From
these output expressions, the 4 to 2 priority encoder circuit diagram is illustrated with logic
gates as shown below.
The circuit diagram of 4 to 2 priority encoder is drawn with 2 OR gates, and the combination
of AND gate and the NOT gate represent the valid bit, which is used when more than one input
is logic high (1). Thus, four inputs with two outputs are encoded based on the assigned priority
to the inputs.
SECTION C
Ques. 3
b.) A "magnitude comparator" is a digital circuit that compares two binary numbers and
outputs whether one is greater than, less than, or equal to the other; a 4-bit magnitude
comparator specifically compares two 4-bit binary numbers, meaning it can compare
numbers up to 15 (in decimal) with three output signals indicating "greater than", "less
than", and "equal to". A circuit diagram with two sets of 4 inputs labeled A3, A2, A1,
A0 (representing the first 4-bit number) and B3, B2, B1, B0 (representing the second
4-bit number), connected to multiple logic gates (including AND, OR, NOT) with three
outputs labeled A>B, A=B, and A<B]
Explanation:
• Inputs:
• A3, A2, A1, A0: The four bits of the first binary number (A) where A3 is the
most significant bit.
• B3, B2, B1, B0: The four bits of the second binary number (B).
• Outputs:
• A>B: High logic level if number A is greater than B.
• A=B: High logic level if A is equal to B.
• A<B: High logic level if A is less than B.
Ques 4.
a.)
The primary limitation of a JK flip flop is the "race around condition" which occurs when both
J and K inputs are set to logic '1' and the clock pulse is held high for a long duration, causing
the output to toggle rapidly and become unstable; this can be eliminated by using a "Master-
Slave" flip flop configuration, where one flip flop acts as the "master" latching the input during
the clock high period, and another "slave" flip flop updates the output only on the falling edge
of the clock, effectively preventing the race around condition.
Race Around Condition:
When J=K=1 and the clock is high for a significant time, the output continuously toggles
between states due to the internal logic loop, leading to unpredictable behavior.
Master-Slave J-K FF
b.)
A BCD counter is a 4-bit binary counter that counts from 0 to a predetermined count using a
clock signal. When the count reaches the predetermined value, it resets all of the flip-flops and
begins counting again from 0. This type of counter is built with four JK flip-flops and counts
from 0 to 9, with the result represented digitally. It resets and restarts after reaching the count
of 9 (1001).

Clock
QD QC QB QA
Pulses

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1
Ques5.
a. The general steps to be followed for the design of asynchronous sequential circuits are as
follows:
1. Create a state table or state diagram from the given problem statement.
2. Create a new reduced state table by removing all the redundant states.
3. Create the transition table.
4. Write the excitation and output Boolean equations and simplify them.
5. Draw the logic diagram.
b. A universal shift register is a type of digital circuit that can load and retrieve data in both
serial and parallel modes, allowing it to shift data either left or right, making it versatile for
various data manipulation operations depending on the selected control signals; essentially, it
combines the functionality of different shift register types into one unit by utilizing
multiplexers to choose the desired operation mode - like parallel load, shift left, or shift right -
based on control inputs.