Datapath Components-Part II

Jia Chen
jiac@ucr.edu
Datapath components
Multiplexer Decoder

Adder Subtractor

Register Encoder

Shifter Counter

Multiplier Divider

Comparator …
Registers

3
 Registers
• Register: logic unit used to store multiple bits in a sequential
logic circuit

➢ A basic register can be built simply by using multiple D-FFs

➢ Two common types of registers:

Parallel load register

Shift register

4
 Parallel load register
• Parallel load register: individual bit values in the register
are loaded simultaneously.
Register
Output 1 Output 2 Output 3 Output 4 Output 5 Output 6

D D D D D D
Flip- Flip- Flip- Flip- Flip- Flip-
DflopQ DflopQ DflopQ DflopQ DflopQ DflopQ

Clk
Input 1 Input 2 Input 3 Input 4 Input 5 Input 6

5
 Shift register
• Shift register: a register that provides the ability to shift its contents

➢ The D-FFs share a single clock signal, which causes the data stored in
the system to shift from one location to the next
For example,
Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop flop flop flop
Input 1 D Q D Q D Q D Q

Clk
6
 What will we output 4 cycles later?
Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop flop flop flop
Input 1 D Q D Q D Q D Q

Clk

Input 1 Input 2 Input 3 Input 4

• For the above D-FF organization, what are we expecting to see in (O1,O2,O3,O4)
in the beginning of the 5th cycle after receiving (1,0,1,1)?

7
 1 cycle later?
Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop flop flop flop
Input 1 D Q
1 D Q D Q D Q

Clk

• For the aboveInput

D-FF1 organization,
Input 2 what areInput 3
we expecting Input
to see4 in (O1,O2,O3,O4)
in the beginning of the 5th cycle after receiving (1,0,1,1)?

8
 2 cycles later?
Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop flop flop flop
Input 1 0 1
D Q D Q D Q D Q

Clk

Input 1 Input 2 Input 3 Input 4

• For the above D-FF organization, what are we expecting to see in (O1,O2,O3,O4)
in the beginning of the 5th cycle after receiving (1,0,1,1)?

9
 3 cycles later?
Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop flop
Input 1
1 flop 0 1 flop
D Q D Q D Q D Q

Clk

Input 1 Input 2 Input 3 Input 4

• For the above D-FF organization, what are we expecting to see in (O1,O2,O3,O4)
in the beginning of the 5th cycle after receiving (1,0,1,1)?

10
4 cycles later (aka the beginning of the 5 th cycle)?
Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop flop flop flop
Input 1
1 1 0 1
D Q D Q D Q D Q

Clk

Input 1 Input 2 Input 3 Input 4

• For the above D-FF organization, what are we expecting to see in (O1,O2,O3,O4)
in the beginning of the 5th cycle after receiving (1,0,1,1)?

11
 What will we output 4 cycles later?
Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop flop flop flop
Input 1
1 1 0 1
D Q D Q D Q D Q

Clk

• For the above D-FF organization, what are we expecting to see in (O1,O2,O3,O4)
in the beginning of the 5th cycle after receiving (1,0,1,1)?

(1,1,0,1)

12
 Let’s play with the shift register more…
• For the extended shift register, what sequence of input will
circuit output “1” after 4 clock cycles?
A. (1, 1, 1, 1)
B. (0, 1, 0, 1) output
C. (1, 0, 1, 0)
D. (0, 1, 1, 0)
E. (1, 0, 0, 1)

13
 Let’s play with the shift register more…
• For the extended shift register, what sequence of input will
the circuit output “1” after 4 clock cycles?
A. (1, 1, 1, 1)
B. (0, 1, 0, 1) output
C. (1, 0, 1, 0)
D. (0, 1, 1, 0)
E. (1, 0, 0, 1)

1 0 0 1

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 4-bit up-counter
Expectation:
Outputs Q3Q2Q1Q0 count in the sequence 0, 1, 2, . . . , 14, 15, 0, and so on

Clock

Q0

Q1

Q2

Q3

Count

Timing diagram
 4-bit up-counter
clock cycle Q3 Q2 Q1 Q0
Clock 0 0 0 0 0
Q0 1 0 0 0 1
2 0 0 1 0
Q1 3 0 0 1 1
4 0 1 0 0
Q2
5 0 1 0 1
Q3 6 0 1 1 0
7 0 1 1 1
Count
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
Q0 always changes 11 1 0 1 1
Q1 changes only when Q0 = 1 12 1 1 0 0
Q2 changes only when Q1 = Q0 = 1 13 1 1 0 1
Q3 changes only when Q2 = Q1 = Q0 = 1 14 1 1 1 0
15 1 1 1 1
 Up-counter
D0 Counter counts the clock pulses only if Enable = 1.

Q0(t+1) = Q0(t) if Enable = 1

( )
D1 ( )
( )

Q0 always changes
D2
Q1 changes only when Q0 = 1
Q2 changes only when Q1 = Q0 = 1
Q3 changes only when Q2 = Q1 = Q0 = 1
D3
Z:
1)Status indicator, all 1s
2)Makes it easy for concatenating
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 Counters
• Sequences through a fixed set of patterns
• Note: definition is general
• For example, the one in the figure is a type of counter called Linear Feedback
Shift Register (LFSR)
Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop flop flop flop
D Q D Q D Q D Q

Clk

18
 Counters
• Assume that initially, O1 = 1, O2 = 0, O3 = 0, O4 = 1

Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop flop flop flop
1 0 0 1
D Q D Q D Q D Q

Clk

19
 After one clock cycle
• Assume that initially, O1 = 1, O2 = 0, O3 = 0, O4 = 1

Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop 0 flop
1 flop
0 flop
0
D Q D Q D Q D Q

Clk

20
 After two clock cycles
• Assume that initially, O1 = 1, O2 = 0, O3 = 0, O4 = 1

Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop 1 flop 0 flop
1 flop
0
D Q D Q D Q D Q

Clk

21
 After three clock cycles
• Assume that initially, O1 = 1, O2 = 0, O3 = 0, O4 = 1

Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop
1 flop 1 flop 0 flop
1
D Q D Q D Q D Q

Clk

22
 After four clock cycles
• Assume that initially, O1 = 1, O2 = 0, O3 = 0, O4 = 1

Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop
0 flop 1 flop 1 flop 0
D Q D Q D Q D Q

Clk

23
 After five clock cycles
• Assume that initially, O1 = 1, O2 = 0, O3 = 0, O4 = 1

Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop 1 flop 0 flop
1 flop 1
D Q D Q D Q D Q

Clk

24
 After six clock cycles
• Assume that initially, O1 = 1, O2 = 0, O3 = 0, O4 = 1

Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop 0 flop 1 flop
0 flop 1
D Q D Q D Q D Q

Clk

25
 After seven clock cycles
• Assume that initially, O1 = 1, O2 = 0, O3 = 0, O4 = 1

Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop 0 flop 0 flop 1 flop 0
D Q D Q D Q D Q

Clk

26
 After eight clock cycles
• Assume that initially, O1 = 1, O2 = 0, O3 = 0, O4 = 1
Back to the
initial status!!
Output 1 Output 2 Output 3 Output 4

D Flip- D Flip- D Flip- D Flip-

flop
1 flop 0 flop 0 flop 1
D Q D Q D Q D Q

Clk

27
Shifters

28
 Shifters
• Logical shifter: shifts value to left or right and fills empty spaces with 0’s
• 11001 >> 2 = 00110 (right)
• 11001 << 2 = 00100 (left)
• Arithmetic shifter: same as logical shifter, but on right shift, fills empty
spaces with the old most significant bit
• Ex: 11001 >>> 2 = 11110 (right)
• Ex: 11001 <<< 2 = 00100 (left)
• Rotator: rotates bits in a circle, such that bits shifted off one end are
shifted into the other end
• Ex: 11001 ROR 2 = 01110 (right)
• Ex: 11001 ROL 2 = 00111 (left)

https://en.wikipedia.org/wiki/Circular_shift
29
 Shift “Right”
0 A3 A2 A1 A0 Example: Example:
if S = 11 if S = 10
then then
Y3 = 0 Y3 = 0
Y2 = 0 Y2 = 0
Y1 = 0 Y1 = A3
Y0 = A3 Y0 = A2
The “chain” of multiplexers
11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00
shamt MUX determines how many bits to
MUX MUX MUX
2 shift
Y3 Y2 Y1 Y0
A3A2A1A0
Based on the value of the selection
input (shamt = shift amount) If S=11, shift right by 3 bits 0 0 0 A3
30
Y YYY
 Shift “left"
0 A0 A1 A2 A3 Example: Example: Example:
if S = 01 if S = 10 if S = 11
then then then
Y3 = A2 Y3 = A1 Y3 = A0
Y2 = A1 Y2 = A0 Y2 = 0
Y1 = A0 Y1 = 0 Y1 = 0
Y0 = 0 Y0 = 0 Y0 = 0
The “chain” of multiplexers
11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00
shamt MUX determines how many bits to
MUX MUX MUX
2 shift
Y0 Y1 Y2 Y3 We don’t need to modify the
circuit, just change the orders
Based on the value of the selection of inputs and outputs!
input (shamt = shift amount) 31
 Generic Shifter
0 A0 A1 A2 A3

1 0 1 0 1 0 1 0

MUX MUX MUX MUX SHR ?

11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00

shamt MUX MUX MUX MUX

2

1 0 1 0 1 0 1 0
MUX MUX MUX MUX

Y3 Y2 Y1 Y0
32
Encoder

33
 Binary Encoders

w0
y0
2n n
inputs outputs
yn – 1
w2 n – 1

A 2n-to-n binary encoder.

Exactly one of input signals should have a value of 1 ( one-hot coded), and
the outputs present the binary number that identifies which input is equal to 1.
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 Binary Encoders
w3 w2 w1 w0 y1 y0
0 0 0 1 0 0 Incompletely specified function
0 0 1 0 0 1
0 1 0 0
1 0 0 0
1
1
0
1
(12 don’t care conditions)
(a) Truth table (partial)

w1 y0
w2 K-maps for y1 and y0
w3 y1

(b) Circuit

4-to-2 binary encoder

Encoders can be used for efficient data communication and storage, since
2n bits are compressed to n bits in the process.
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Comparator

36
 Comparator
➢ A comparator compares the relative values of two binary numbers.
➢ If we design a comparator comparing two 4-bit unsigned numbers
using a truth table, we need 28 = 256 rows.
➢ We actually can compare the two numbers bit by bit.
A = a3a2a1a0 unsigned
B = b3b2b1b0 unsigned
Define ik=(bkak)’ ------ ik gives a 1 if bk = ak Note that we can
compare the bits of A
Then and B at the same
position from left to
A=B AeqB = i3i2i1i0 right. When we found
a difference, the
A>B AgtB = a3b3’ + i3a2b2’ + i3i2a1b1’ + i3i2i1a0b0’ comparison is done.
A<B AltB = (AgtB + AeqB)’
 A =actually
We a3a2a1can
a0 compare
unsigned
the two num
Comparator A = a3a2a1a0 unsigned
B = b3b2b1b0 unsigned
a3a 3 i3 i3
B = b3b2b1b0 unsigned
b3b 3 Define ik=(bkÅak)’ ------ ik giv
a2a 2 i Define ik=(bkÅak)’ ------ ik
A comparator compares the relative sizes of two binary numbers.
i2 2 Then
If we design a comparator comparing two 4-bit unsigned numbers
b2b 2 table, we need 2^8 rows. Then
i AeqB
AeqB A = B AeqB = i3i2i1i0
a1a 1 i1 1
We actually can compareAthe AeqB
= Btwo = i3bit
numbers i2iby
1 i0bit.
b1b 1 A > B AgtB = a3b3’ + i3a2b2’ + i3i2a1
A = a3a2a1a0 unsigned
a0a 0 i0i 0 A > B AgtB = a3b3’ + i3a2b2’ + i3Ni2
A < B AltB = (AgtB + AeqB)’ co
b0b 0 B = b3AltB
bAltB
2b1b0 unsigned
A < B AltB = (AgtB + AeqB)’ of
sa
Define ik=(bkÅak)’ ------ ik gives a 1 if bk == ak fr
W
Then di
co
A=B AeqBAgtB
=AgtB
i3i2i1i0 do

A>B AgtB = a3b3’ + i3a2b2’ + i3i2a1b1’ + i3i2i1a0b0’

A<B AltB = (AgtB + AeqB)’
38
Multiplier

39
 0000a3a2a1a0 0 Definition 0:=[00000000]

8 8
0 1 0
b0
8
8-bit Adder
MUX
Shift and add
Sum1
8-bit Shifter SHR = 0
8 0
1 0
MUX b1
0 0 0 0
8-bit Adder 0 0 0
Sum2 SHR = 0 0 0
8-bit Shifter 0
8
1 0
0 p7 p6 p5 p4 p3 p2 p1 p0
MUX b2 Sum4
8-bit Adder
Sum3
8
8-bit Shifter SHR = 0
0
1 0
MUX b3
8-bit Adder 40
8
Sum4 pppppppp