M74HC273
M74HC273
■ HIGH SPEED :
fMAX = 66 MHz (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
VNIH = V NIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE: DIP SOP TSSOP
|IOH| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL ORDER CODES
■ WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T&R
VCC (OPR) = 2V to 6V
DIP M74HC273B1R
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273 SOP M74HC273M1R M74HC273RM13TR
TSSOP M74HC273TTR
DESCRIPTION
The M74HC273 is an high speed CMOS OCTAL When the CLEAR input is held low, the Q output
D TYPE FLIP FLOP WITH CLEAR fabricated with are in the low logic level independent of the other
silicon gate C2MOS technology. inputs.
Information signals applied to D inputs are All inputs are equipped with protection circuits
transferred to the Q outputs on the positive-going against static discharge and transient excess
edge of the clock pulse. voltage.
TRUTH TABLE
INPUTS OUTPUTS
FUNCTION
CLEAR CLOCK D Q
L X X L CLEAR
H L L
H H H
H X Qn NO CHANGE
X : Don’t Care
LOGIC DIAGRAM
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M74HC273
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M74HC273
DC SPECIFICATIONS
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M74HC273
CAPACITIVE CHARACTERISTICS
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M74HC273
TEST CIRCUIT
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
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M74HC273
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M74HC273
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.254 0.010
b 0.45 0.018
b1 0.25 0.010
D 25.4 1.000
E 8.5 0.335
e 2.54 0.100
e3 22.86 0.900
F 7.1 0.280
I 3.93 0.155
L 3.3 0.130
Z 1.34 0.053
P001J
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M74HC273
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.1 0.2 0.004 0.008
a2 2.45 0.096
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.012
C 0.5 0.020
c1 45° (typ.)
D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 11.43 0.450
F 7.40 7.60 0.291 0.300
L 0.50 1.27 0.020 0.050
M 0.75 0.029
S 8° (max.)
PO13L
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M74HC273
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
K 0° 8° 0° 8°
A A2
K L
A1 b e
c E
E1
PIN 1 IDENTIFICATION
1
0087225C
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M74HC273
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