Ethernet Subsystem Registers www.ti.

com

14.5.2.4 RX_IDVER Register (offset = 10h) [reset = C0107h]

RX_IDVER is shown in Figure 14-32 and described in Table 14-43.
CPDMA_REGS RX IDENTIFICATION AND VERSION REGISTER

Figure 14-32. RX_IDVER Register

31 30 29 28 27 26 25 24
RX_IDENT

R-Ch

23 22 21 20 19 18 17 16
RX_IDENT

R-Ch

15 14 13 12 11 10 9 8
RX_MAJOR_VER

R-1h

7 6 5 4 3 2 1 0
RX_MINOR_VER

R-7h

LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset

Table 14-43. RX_IDVER Register Field Descriptions

Bit Field Type Reset Description
31-16 RX_IDENT R Ch RX Identification Value
15-8 RX_MAJOR_VER R 1h RX Major Version Value
7-0 RX_MINOR_VER R 7h RX Minor Version Value

1260 Ethernet Subsystem SPRUH73H – October 2011 – Revised April 2013

Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
www.ti.com Ethernet Subsystem Registers

14.5.2.5 RX_CONTROL Register (offset = 14h) [reset = 0h]

RX_CONTROL is shown in Figure 14-33 and described in Table 14-44.
CPDMA_REGS RX CONTROL REGISTER

Figure 14-33. RX_CONTROL Register

31 30 29 28 27 26 25 24
Reserved

R-0h

23 22 21 20 19 18 17 16
Reserved

R-0h

15 14 13 12 11 10 9 8
Reserved

R-0h

7 6 5 4 3 2 1 0
Reserved RX_EN

R-0h R/W-0h

LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset

Table 14-44. RX_CONTROL Register Field Descriptions

Bit Field Type Reset Description
31-1 Reserved R 0h
0 RX_EN R/W 0h RX DMA Enable
0 - Disabled
1 - Enabled

SPRUH73H – October 2011 – Revised April 2013 Ethernet Subsystem 1261

Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Ethernet Subsystem Registers www.ti.com

14.5.2.6 RX_TEARDOWN Register (offset = 18h) [reset = 0h]

RX_TEARDOWN is shown in Figure 14-34 and described in Table 14-45.
CPDMA_REGS RX TEARDOWN REGISTER

Figure 14-34. RX_TEARDOWN Register

31 30 29 28 27 26 25 24
RX_TDN_RDY Reserved

R-0h R-0h

23 22 21 20 19 18 17 16
Reserved

R-0h

15 14 13 12 11 10 9 8
Reserved

R-0h

7 6 5 4 3 2 1 0
Reserved RX_TDN_CH

R-0h R/W-0h

LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset

Table 14-45. RX_TEARDOWN Register Field Descriptions

Bit Field Type Reset Description
31 RX_TDN_RDY R 0h Teardown Ready - read as zero, but is always assumed to be one
(unused).
30-3 Reserved R 0h
2-0 RX_TDN_CH R/W 0h Rx Teardown Channel -Receive channel teardown is commanded by
writing the encoded value of the receive channel to be torn down.
The teardown register is read as zero.
000 - teardown receive channel 0 ...
111 - teardown receive channel 7

1262 Ethernet Subsystem SPRUH73H – October 2011 – Revised April 2013

Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
www.ti.com Ethernet Subsystem Registers

14.5.2.7 CPDMA_SOFT_RESET Register (offset = 1Ch) [reset = 0h]

CPDMA_SOFT_RESET is shown in Figure 14-35 and described in Table 14-46.
CPDMA_REGS SOFT RESET REGISTER

Figure 14-35. CPDMA_SOFT_RESET Register

31 30 29 28 27 26 25 24
Reserved

R-0h

23 22 21 20 19 18 17 16
Reserved

R-0h

15 14 13 12 11 10 9 8
Reserved

R-0h

7 6 5 4 3 2 1 0
Reserved SOFT_RESET

R-0h R/W-0h

LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset

Table 14-46. CPDMA_SOFT_RESET Register Field Descriptions

Bit Field Type Reset Description
31-1 Reserved R 0h
0 SOFT_RESET R/W 0h Software reset - Writing a one to this bit causes the CPDMA logic to
be reset.
Software reset occurs when the RX and TX DMA Controllers are in
an idle state to avoid locking up the VBUSP bus.
After writing a one to this bit, it may be polled to determine if the
reset has occurred.
If a one is read, the reset has not yet occurred.
If a zero is read then reset has occurred.

SPRUH73H – October 2011 – Revised April 2013 Ethernet Subsystem 1263

Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Ethernet Subsystem Registers www.ti.com

14.5.2.8 DMACONTROL Register (offset = 20h) [reset = 0h]

DMACONTROL is shown in Figure 14-36 and described in Table 14-47.
CPDMA_REGS CPDMA CONTROL REGISTER

Figure 14-36. DMACONTROL Register

31 30 29 28 27 26 25 24
Reserved

R-0h

23 22 21 20 19 18 17 16
Reserved

R-0h

15 14 13 12 11 10 9 8
TX_RLIM

R/W-0h

7 6 5 4 3 2 1 0
Reserved RX_CEF CMD_IDLE RX_OFFLEN_BLOCK RX_OWNERSHIP TX_PTYPE

R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset

Table 14-47. DMACONTROL Register Field Descriptions

Bit Field Type Reset Description
31-16 Reserved R 0h
15-8 TX_RLIM R/W 0h Transmit Rate Limit Channel Bus
00000000 - no rate-limited channels
10000000 - channel 7 is rate-limited
11000000 - channels 7 downto 6 are rate-limited
11100000 - channels 7 downto 5 are rate-limited
11110000 - channels 7 downto 4 are rate-limited
11111000 - channels 7 downto 3 are rate-limited
11111100 - channels 7 downto 2 are rate-limited
11111110 - channels 7 downto 1 are rate-limited
11111111 - channels 7 downto 0 are rate-limited all others invalid -
this bus must be set msb towards lsb.
tx_ptype must be set if any tx_rlim bit is set for fixed priority.
7-5 Reserved R 0h
4 RX_CEF R/W 0h RX Copy Error Frames Enable - Enables DMA overrun frames to be
transferred to memory (up to the point of overrun).
The overrun error bit will be set in the frame EOP buffer descriptor.
Overrun frame data will be filtered when rx_cef is not set.
Frames coming from the receive FIFO with other error bits set are
not effected by this bit.
0 - Frames containing overrun errors are filtered.
1 - Frames containing overrun errors are transferred to memory.
3 CMD_IDLE R/W 0h Command Idle
0 - Idle not commanded
1 - Idle Commanded (read idle in DMAStatus)
2 RX_OFFLEN_BLOCK R/W 0h Receive Offset/Length word write block.
0 - Do not block the DMA writes to the receive buffer descriptor
offset/buffer length word.
The offset/buffer length word is written as specified in CPPI 3.0.
1 - Block all CPDMA DMA controller writes to the receive buffer
descriptor offset/buffer length words during CPPI packet processing.
when this bit is set, the CPDMA will never write the third word to any
receive buffer descriptor.

1264 Ethernet Subsystem SPRUH73H – October 2011 – Revised April 2013

Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
www.ti.com Ethernet Subsystem Registers

Table 14-47. DMACONTROL Register Field Descriptions (continued)

Bit Field Type Reset Description
1 RX_OWNERSHIP R/W 0h Receive Ownership Write Bit Value.
0 - The CPDMA writes the receive ownership bit to zero at the end
of packet processing as specified in CPPI 3.0.
1 - The CPDMA writes the receive ownership bit to one at the end of
packet processing.
Users who do not use the ownership mechanism can use this mode
to preclude the necessity of software having to set this bit each time
the buffer descriptor is used.
0 TX_PTYPE R/W 0h Transmit Queue Priority Type
0 - The queue uses a round robin scheme to select the next channel
for transmission.
1 - The queue uses a fixed (channel 7 highest priority) priority
scheme to select the next channel for transmission

SPRUH73H – October 2011 – Revised April 2013 Ethernet Subsystem 1265

Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated