Section number Title Page

55.2.10 SDMA Initialization...................................................................................................................................4683

55.2.10.1 Hardware Reset-SDMA.........................................................................................................4683

55.2.10.2 Standard Boot Sequence........................................................................................................4683

55.2.10.3 User-Defined Boot Sequence.................................................................................................4684

55.2.10.4 Script Loading and Context Initialization..............................................................................4684

55.2.11 Instruction Description...............................................................................................................................4685

55.2.11.1 Scheduling Instructions..........................................................................................................4685

55.2.11.2 Conditional Branch Instructions............................................................................................4685

55.2.11.3 Unconditional Jump Instructions...........................................................................................4686

55.2.11.4 Subroutine Return Instructions..............................................................................................4686

55.2.11.5 Loop Instruction.....................................................................................................................4686

55.2.11.6 Miscellaneous Instructions.....................................................................................................4687

55.2.11.7 Logic Instructions..................................................................................................................4687

55.2.11.8 Arithmetic Instructions..........................................................................................................4687

55.2.11.9 Compare Instructions.............................................................................................................4688

55.2.11.10 Test Instructions.....................................................................................................................4688

55.2.11.11 Byte Permutation Instructions................................................................................................4688

55.2.11.12 Bit Shift Instructions..............................................................................................................4689

55.2.11.13 Bit Manipulation Instructions................................................................................................4689

55.2.11.14 SDMA Memory Access Instructions.....................................................................................4689

55.2.11.15 Functional Unit Instructions...................................................................................................4690

55.2.11.16 Illegal Instructions..................................................................................................................4690

55.2.11.17 Debug Instructions.................................................................................................................4690

55.2.12 Functional Units Programming Model......................................................................................................4691

55.2.12.1 Burst DMA Unit Programming..............................................................................................4692

55.2.12.1.1 Memory Source Address Register (MSA)......................................................4692

55.2.12.1.2 Memory Destination Address Register (MDA)..............................................4693

55.2.12.1.3 Memory Data Buffer Register (MD)..............................................................4693

55.2.12.1.4 State Register (MS).........................................................................................4694

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55.2.12.1.5 Burst DMA Write (stf)....................................................................................4695

55.2.12.1.6 Burst DMA Read (ldf)....................................................................................4698

55.2.12.1.7 Prefetch/Flush and Auto-Flush Management-Burst DMA Unit.....................4699

55.2.12.1.8 Data Alignment and Endianness-Burst DMA Unit........................................4701

55.2.12.1.8.1 Burst DMA in Read Mode.....................................................4701

55.2.12.1.8.2 Burst DMA in Write Mode.....................................................4702

55.2.12.1.8.3 Endianness-Burst DMA Unit.................................................4704

55.2.12.1.9 Burst DMA Unit Copy Mode.........................................................................4704

55.2.12.1.10 Burst DMA Unit Error Management..............................................................4705

55.2.12.1.11 Conditional Yielding-Burst DMA Unit..........................................................4707

55.2.12.2 Peripheral DMA Unit Programming......................................................................................4708

55.2.12.2.1 Peripheral Source Address Register (PSA).....................................................4709

55.2.12.2.2 Peripheral Destination Address Register (PDA).............................................4709

55.2.12.2.3 Peripheral Data Register (PD)........................................................................4710

55.2.12.2.4 Peripheral State Register (PS).........................................................................4710

55.2.12.2.5 Peripheral DMA Write (stf)-Write Mode.......................................................4712

55.2.12.2.6 Peripheral DMA Read (ldf)-Read Mode.........................................................4715

55.2.12.2.7 Peripheral DMA Unit Copy Mode..................................................................4716

55.2.12.2.8 Error Management..........................................................................................4716

55.2.12.2.8.1 Immediate Errors....................................................................4716

55.2.12.2.8.2 Data Transfer Errors...............................................................4717

55.2.12.2.8.3 Read Error (First Phase).........................................................4717

55.2.12.2.8.4 Write Error and Read Error (Second Phase)..........................4718

55.2.12.2.8.5 Copy Mode Errors..................................................................4719

55.2.12.2.8.6 Error Check Example.............................................................4719

55.2.12.2.9 Peripheral DMA Unit Prefetch/Flush Management.......................................4720

55.2.12.3 OnCE and Real-Time Debug.................................................................................................4720

55.2.12.3.1 Memory and Register Access.........................................................................4720

55.2.12.3.2 Hardware Breakpoints....................................................................................4720

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55.2.12.3.3 Watchpoints....................................................................................................4721

55.2.12.3.4 Software Breakpoints......................................................................................4721

55.2.12.3.5 Core Control....................................................................................................4721

55.2.13 The OnCE Controller.................................................................................................................................4721

55.2.13.1 OnCE Commands..................................................................................................................4721

55.2.13.2 Sending Commands to the OnCE Controller.........................................................................4722

55.2.13.2.1 Using the JTAG Interface...............................................................................4722

55.2.13.2.2 Using the ARM platform................................................................................4723

55.2.13.2.3 Conflicts Between the JTAG and the ARM platform Accesses.....................4724

55.2.13.3 Executing a Command from the OnCE.................................................................................4725

55.2.13.3.1 Nature of the Commands................................................................................4725

55.2.13.3.2 Execution Request..........................................................................................4725

55.2.13.3.3 Command Execution.......................................................................................4726

55.2.13.4 Registers Descriptions............................................................................................................4728

55.2.13.4.1 Event Cell Counter Register (ECOUNT).......................................................4728

55.2.13.4.2 Event Cell Address Registers (EAA or EAB)................................................4728

55.2.13.4.3 Event Cell Address Mask Register (EAM).....................................................4728

55.2.13.4.4 Event Cell Data Register (ED)........................................................................4729

55.2.13.4.5 Event Cell Data Mask Register (EDM)..........................................................4729

55.2.13.4.6 Real Time Buffer Register (RTB)...................................................................4729

55.2.13.4.7 Event Control Register (ECTL)......................................................................4729

55.2.13.4.8 Trace Buffer (TB)...........................................................................................4730

55.2.13.4.9 OnCE Status Register (OSTAT).....................................................................4730

55.2.13.5 JTAG Interface Requirements...............................................................................................4730

55.2.13.5.1 TCK Speed Limitation....................................................................................4731

55.2.13.5.2 Synchronization Implementation....................................................................4731

55.2.13.5.3 JTAG Controller Start-Up Recommended Procedure....................................4733

55.2.14 Using the OnCE.........................................................................................................................................4733

55.2.14.1 Activating Clocks in Debug Mode.........................................................................................4733

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55.2.14.2 Getting the Current Status......................................................................................................4733

55.2.14.3 Methods of Entering Debug Mode.........................................................................................4734

55.2.14.3.1 External Debug Request During Reset...........................................................4734

55.2.14.3.2 Debug Request During Normal Activity........................................................4734

55.2.14.3.3 Software Breakpoint Instruction.....................................................................4734

55.2.14.3.4 Event Detection Unit Matching Condition.....................................................4734

55.2.14.4 Executing Instructions in Debug Mode.................................................................................4735

55.2.14.5 Command Sequences Examples............................................................................................4735

55.2.14.5.1 Getting the SDMA Status...............................................................................4735

55.2.14.5.2 Saving the Context..........................................................................................4736

55.2.14.5.3 Restoring the Context.....................................................................................4737

55.2.14.5.4 Accessing the Memory...................................................................................4738

55.2.14.5.5 Resuming Program Execution........................................................................4739

55.2.14.5.6 Single Stepping in RAM.................................................................................4739

55.2.14.5.7 Single Stepping in ROM.................................................................................4740

55.2.14.6 OnCE Event Detection Unit...................................................................................................4740

55.2.14.7 Clock Gating and Reset..........................................................................................................4741

55.2.14.7.1 Clocks.............................................................................................................4741

55.2.14.7.2 Resets..............................................................................................................4742

55.2.14.8 Real Time Features................................................................................................................4742

55.2.14.8.1 Trace Buffer....................................................................................................4742

55.2.14.8.2 Real Time Buffer............................................................................................4744

55.2.14.8.3 Emulation Pin.................................................................................................4744

55.2.14.8.4 Real-Time Debug Outputs..............................................................................4744

55.3 Instruction Set...............................................................................................................................................................4748

55.3.1 Instruction Encoding..................................................................................................................................4748

55.3.2 SDMA Instruction Set................................................................................................................................4750

55.3.2.1 ADD (Addition).....................................................................................................................4752

55.3.2.2 ADDI (Add with Immediate Value)......................................................................................4753

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55.3.2.3 AND (Logical AND).............................................................................................................4754

55.3.2.4 ANDI (Logical AND with Immediate Value).......................................................................4755

55.3.2.5 ANDN (Logical AND NOT).................................................................................................4756

55.3.2.6 ANDNI (Logical AND with Negated Immediate Value)......................................................4757

55.3.2.7 ASR1 (Arithmetic Shift Right by 1 Bit)................................................................................4758

55.3.2.8 BCLRI1 (Bit Clear Immediate)..............................................................................................4759

55.3.2.9 BDF (Conditional Branch if Destination Fault).....................................................................4760

55.3.2.10 BF (Conditional Branch if False)...........................................................................................4761

55.3.2.11 BSETI (Bit Set Immediate)....................................................................................................4762

55.3.2.12 BSF (Conditional Branch if Source Fault).............................................................................4763

55.3.2.13 BT (Conditional Branch if True)...........................................................................................4764

55.3.2.14 BTSTI (Bit Test immediate)..................................................................................................4765

55.3.2.15 CLRF (Clear ARM platform flags)........................................................................................4766

55.3.2.16 CMPEQ (Compare for Equal)................................................................................................4767

55.3.2.17 CMPEQI (Compare with Immediate for Equal)....................................................................4768

55.3.2.18 CMPHS (Compare for Higher or Same)................................................................................4769

55.3.2.19 CMPLT (Compare for Less Than).........................................................................................4770

55.3.2.20 cpShReg (Update Context of PCU Registers and Flag)........................................................4771

55.3.2.21 DONE (DONE, Yield) ..........................................................................................................4771

55.3.2.22 ILLEGAL (ILLEGAL Instruction)........................................................................................4773

55.3.2.23 JMP (Unconditional Jump Immediate)..................................................................................4774

55.3.2.24 JMPR (Unconditional Jump).................................................................................................4774

55.3.2.25 JSR (Unconditional Jump to Subroutine Immediate)............................................................4775

55.3.2.26 JSRR (Unconditional Jump to Subroutine)............................................................................4776

55.3.2.27 LD (Load Register)................................................................................................................4777

55.3.2.28 LDF (Load Register from Functional Unit)...........................................................................4778

55.3.2.29 LDI (Load Register with Immediate Value)..........................................................................4780

55.3.2.30 LDRPC (Load from RPC to Register)...................................................................................4781

55.3.2.31 LOOP (Hardware Loop)........................................................................................................4782

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55.3.2.32 LSL1 (Logical Shift Left by 1 Bit)........................................................................................4784

55.3.2.33 LSR1 (Logical Shift Right by 1 Bit)......................................................................................4785

55.3.2.34 MOV (Logical Move)............................................................................................................4786

55.3.2.35 NOTIFY (Notify to ARM platform)......................................................................................4787

55.3.2.36 OR (Logical OR)....................................................................................................................4788

55.3.2.37 ORI (Logical OR with Immediate Value)..............................................................................4789

55.3.2.38 RET (Return from Subroutine)..............................................................................................4790

55.3.2.39 REVB (Reverse Byte Order)..................................................................................................4791

55.3.2.40 Reverse Low Order Bytes(REVBLO)...................................................................................4791

55.3.2.41 ROR1 (Rotate Right by 1 Bit)................................................................................................4792

55.3.2.42 RORB (Rotate Right by 1 Byte)............................................................................................4793

55.3.2.43 SOFTBKPT (Software Breakpoint).......................................................................................4794

55.3.2.44 ST (Store Register).................................................................................................................4794

55.3.2.45 STF (Store Register in Functional Unit)................................................................................4796

55.3.2.46 SUB (Subtract).......................................................................................................................4799

55.3.2.47 SUBI (Subtract with Immediate)...........................................................................................4800

55.3.2.48 TST (Test with Zero).............................................................................................................4801

55.3.2.49 TSTI (Test Immediate)...........................................................................................................4802

55.3.2.50 XOR (Logical Exclusive OR)................................................................................................4803

55.3.2.51 XORI (Exclusive OR with Immediate)..................................................................................4804

55.3.2.52 YIELD, YIELDGE (DONE, Yield).......................................................................................4805

55.4 Software Restrictions....................................................................................................................................................4805

55.4.1 Unsupported Burst DMA Access Sequence..............................................................................................4805

55.5 Application Notes.........................................................................................................................................................4806

55.5.1 Data Structures for Boot Code and Channel Scripts..................................................................................4806

55.5.1.1 Buffer Descriptor Format.......................................................................................................4807

55.5.1.2 Buffer Descriptor Commands for Bootload scripts...............................................................4810

55.5.1.3 Example of Buffer Descriptors for Channel 0.......................................................................4811

55.5.1.4 Channel Context.....................................................................................................................4814

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