Review of scanning electron

microscope-based overlay
measurement beyond 3-nm node
device

Osamu Inoue
Kazuhisa Hasumi

Osamu Inoue, Kazuhisa Hasumi, “Review of scanning electron microscope-based overlay measurement
beyond 3-nm node device,” J. Micro/Nanolith. MEMS MOEMS 18(2), 021206 (2019),
doi: 10.1117/1.JMM.18.2.021206.
J. Micro/Nanolith. MEMS MOEMS 18(2), 021206 (Apr–Jun 2019)
REVIEW

Review of scanning electron microscope-based overlay

measurement beyond 3-nm node device
Osamu Inoue* and Kazuhisa Hasumi
Hitachi High-Technologies, Hitachinaka-shi, Ibaraki-ken, Japan

Abstract. Overlay control has been one of the most critical issues for manufacturing of leading edge semicon-
ductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional
optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay dis-
crepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers
within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay
(SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures
on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of
Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows
insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated
SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have
been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM
but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns.
One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material con-
trast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or
even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface
depending on the material properties of underneath structure. SEM-OL measurement using transient voltage
contrast has been developed and its capability of overlay measurement has been proven. An overlay meas-
urement algorithm using template matching method has been developed and was applied to dynamic random
access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond
3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement
precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.
© 2019 Society of Photo-Optical Instrumentation Engineers (SPIE) [DOI: 10.1117/1.JMM.18.2.021206]
Keywords: overlay; high-voltage scanning electron microscope (SEM); critical dimension SEM; accuracy.
Paper 18138SSV received Nov. 13, 2018; accepted for publication May 23, 2019; published online Jun. 13, 2019.

1 Introduction On the other hand, DBO instrument measures diffraction

Optical overlay (Opt-OL) instruments are most commonly efficiencies of the diffracted orders from specially designed
used for overlay metrology in semiconductor manufacturing. stacked gratings that are set as overlay targets.4 The mea-
Two Opt-OL metrology techniques, image-based overlay sured data are a function of the overlay. Diffraction from the
(IBO) and diffraction-based overlay (DBO) are applied in overlay target is simulated with rigorous coupled wave
advanced semiconductor manufacturing. IBO instrument is approach,5 and it depends on the optics and sample condi-
bright field microscopy, which uses the standard method tion. It requires time for optimization of the target and recipe
of optical microscopy systems. Dedicated targets for IBO, creation.6 One of the standard dedicated targets for DBO
like box in box, have been adopted as the IC manufacturing metrology is μDBO target.7 μDBO target translates a lateral
overlay standard target for years.1 In 2003, advanced imag- position difference between two layer gratings in a stack into
ing metrology (AIM) mark was optimized using overlay an asymmetry in the angle-resolved diffraction. The relative
mark fidelity (OMF) as metrics.2,3 OMF is an estimate of merits of optical IBO and DBO in manufacturing environ-
overlay measurement variability due to process robustness ment are still being debated especially considering robust-
of the overlay target and the overlay metrology process. ness and accuracy issues on wafers with target asymmetry
AIM mark consists of grating targets that are patterned on and variations. Process- and target-specific wavelength opti-
the reference and current layer. Both target types are mirror mization, measurement quality metrics, and calibration to
symmetric with 0 baseline (same centerline). AIM mark scanning electron microscope-based overlay (SEM-OL)
has longer pattern edge than in SEMI Standard box in box measurements are being pursued.8–10
targets,1 and it also uses edge-based symmetry detection for Tool-induced shift (TIS) is evaluated to estimate the
the grating targets. Periodic patterns are useful for many impact of tool asymmetry on measurement error.11 TIS can
methodologies. be obtained by measuring overlay at 0 deg and 180 deg of
wafer rotation and the difference of the two divided by 2.
Once an estimate of TIS is available, this error can be
removed from OL measurement, improving overlay metrol-
ogy accuracy and tool-to-tool matching. TIS evaluation,
*Address all correspondence to Osamu Inoue, E-mail: osamu.inoue.ek@
hitachi-hightech.com optimization, and calibration have been automated on all

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

commercial Opt-OL tools. Testing for TIS is also useful in (iPQ), was developed for process monitor in manu-
alignment applications.12 Pattern size of the Opt-OL target is facturing.36
typically from 100 to 1000 nm, and target size is typically Since 2014, we have studied the SEM-OL in collabora-
from 7 × 7 μm through 30 × 30 μm.13 Opt-OL metrology tion with imec. We designed and evaluated dedicated targets
has a technical challenge in measuring smaller marks placed for SEM-OL metrology. With arrival of three-dimensional
in large numbers within field and segmented pattern in the structure devices and shrinking of device size, the overlay
mark.14 Conventional Opt-OL metrology uses a dedicated measurement between surface pattern and buried pattern
target with larger size and different structures than device by insulator film, namely see-through-overlay measurement,
patterns. The Opt-OL measurement results at after-develop became indispensable in manufacturing of memory devices,
inspection (ADI) were shifted due to scanner lens aberration especially DRAM. Then high-voltage SEM was developed
depending on the pattern sizes of optical metrology targets, to fulfill these requirements.37,38 SEM-OL measurements
which are significantly larger than device patterns.15–19 made it possible to feedback to mask or scanner linear
Wafer-induced shift (WIS) is introduced to account for the overlay 10 correctable terms. It was applied for improve-
errors due to pattern asymmetry of the overlay targets.20 ment in R&D, Technology Ramp and for process monitor
It is induced by process steps such as etch21 or chemical- in manufacturing.39,40 We will review SEM-OL metrology
mechanical polishing (CMP).22–24 Asymmetric etch causes applied in current CD-SEM and high-voltage SEM
shift of where the pattern centerline is at its top versus its (HV-SEM).
bottom and the target asymmetry, leading to error of conven- For logic devices (and not only memory devices), see-
tional OL metrology. CMP causes an asymmetric profile at through-overlay measurement enables high-order overlay
the top of the target, leading to asymmetric optical image, correction with scanner because SEM-OL can measure the
and OL measurement error. Nonzero overlay correction in small dedicated target within 2 × 2 μm, which is easy to
lithography, taking into account pre- and postprocessing, be laid out in large numbers within a die. For beyond 3-nm
was evaluated to improve final pattern and yield.21 node and cutting-edge DRAM device process, it is required
SEM such as critical dimension SEM (CD-SEM) is to control the overlay within 2.8 nm41 and to measure the
generally used for measurement of CD in semiconductor pro- precision within 0.3 nm. HV-SEM and small measurement
duction. SEM-OL metrology had been discussed for target have been used for high-order overlay correction.
decades.25–28 It can directly detect edges of device pattern As outlined above, over the years, conventional Opt-OL
metrology has been putting much effort into both basic
or device like pattern with high spatial resolution and measure
technology development and specific applications learning,
overlay using the edge positions. SEM-OL metrology is com-
managing to improve its accuracy and repeatability as
pletely different from Opt-OL metrology interaction with the
required. As the result, Opt-OL continued to be viable as pri-
sample and measurement error mechanisms. It is an image-
mary overlay metrology in production. Although SEM-OL
based technique and therefore has many things in common
metrology showed a great deal of promise, recently becom-
with the optical IBO metrology. In many critical applications
ing the main supplemental technology and the reference met-
cases, where optical OL metrology may suffer from process- rology for Opt-OL, especially when it comes to measurement
ing related signal variability and measurement inaccuracy. accuracy in the presence of target asymmetry and manufac-
SEM-OL metrology can be used for reference metrology and turing process variations, better representing device overlay,
optimization of Opt-OL measurement conditions. up to now it did not become the main process monitor.
Since around 2008 when double patterning technique was In this paper, we will review and illustrate significant recent
introduced to enable further pattern size shrinkage, overlay advancement in SEM-OL metrology technology and in
control has been one of the most critical issues for semicon- SEM-OL applications for advanced nodes. We will also con-
ductor device manufacturing. To improve residual error after sider one additional barrier to technology entry, the slower
correction, higher-order correction to compensate the nonlin- throughput of SEM-OL metrology tools.
ear overlay errors, correction per exposure (CPE) to correct
overlay errors in each individual field have been applied in
addition to linear correction to correct the intrafield and inter- 2 Dedicated Mark and Algorithm of SEM-OL
field overlay errors.29,30 For the overlay corrections, small metrology
OL mark has been needed to be laid out in large numbers Figure 1 shows a schematic diagram of SEM contrast.
within die. Topography and material contrast are the most typical con-
The requirements for overlay measurements became rap- trasts in conventional CD-SEM or HV-SEM. SEM at low
idly stringent; measurement discrepancy between Opt-OL accelerating voltage (<2 kV) measures the secondary elec-
mark and device pattern became a serious issue to be man- tron (SE) image. SE emission especially increases on speci-
aged in semiconductor processes. To solve this issue, Hitachi men tilt area like pattern edge. Contrast provides information
High-Technologies began developing SEM-OL techniques of the surface topography. When reference pattern at ADI is
to measure actual device patterns directly or device-like tar- covered by blanket film, it is not detected by low-energy
get at after-etch inspection (AEI).31,32 For initial optimization electron beam. CD-SEM is used for overlay measurement
of Opt-OL metrology, SEM-OL metrology has been used as at AEI in this paper. SEM-OL metrology by CD-SEM will
a reference.33 be discussed in Secs. 3–5. HV-SEM measures the SE image
In around 2012, the demand of layer-to-layer overlay and/or back scattering electron (BSE) image. Contrast
measurements between surface patterns in device area at mainly provides information of surface profile and surface
AEI using SEM-OL has increased.34,35 To detect reference or buried composition by material contrast. It can be used
patterns partially covered by the current layer pattern, over- for overlay measurement at ADI and AEI. SEM-OL metrol-
lay measurement algorithm, inspection and process qualifier ogy by HV-SEM will be discussed in Sec. 6.1.

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Topography Voltage contrast (VC)

Material contrast
contrast Steady charging state Transient charging state

BSEs BSEs Accumulated charge

SEs SEs SEs SEs SEs SEs
SEs
Model High C Low C
Metal
Metal Low R High R

Factor Edge Atomic mass Resistance Capacitance

Fig. 1 Typical SEM contrasts and their physical mechanisms for overlay measurement. Schematic
explaining mechanisms and the factors are shown.

On the other hand, voltage contrast is caused by charging Current pattern is 96-nm pitch and 24-nm trench patterned
under electron beam irradiation. At steady state, image con- M1A exposure. Reference pattern is 24 × 32 nm hole pat-
trast depends on the difference in resistance of specimen, terned by V0A. Scan direction of SEM is normally left to
because the emitted SEs result from the stable currents flow- right with respect to wafer notch. Pattern layout between the
ing into the resistor.28 At transient state, emitted SE is current and reference layer is like a part of AIM mark for
affected by the accumulation of charge. So transient voltage optical IBO. The current patterns are dense trenches (grating)
contrast depends on capacitance between the surface and the in the metal layer and reference patterns are dense holes in
substrate including buried structures.42,43 Buried pattern via layer, respectively. It was selected to prevent current and
detection by transient voltage contrast will be discussed in reference patterns from overlapping when large overlay error
Sec. 6.2. occurs for the evaluation. Each layer pattern is of the same
For SEM-OL, in collaboration with imec, imec N10 back size as dense pattern under the layout rule. The dedicated
end of line (BEOL) short loop to create metal 1 (M1) and via target for overlay Y, which rotates counterclockwise 90 deg
0 (V0) logic and static random access memory (SRAM) with respect to the target for overlay X, is located in the vicin-
devices was used. The M1 patterns are split into three images ity of the target for overlay X. Scan direction of SEM for
placed in three different plates (M1A, M1B, and M1C) and overlay Y is normally top to bottom with respect to wafer
V0 patterns are split into two images placed in two different notch. Overlay Y is measured by the same procedure for
plates (V0A and V0B). The exposures are performed on overlay X in consideration of image rotation. Although, addi-
NXT1950i scanner from ASML. The lithography process tional dedicated marks for overlays X and Y, which rotates
is using a negative tone development resist. We will review counterclockwise 180 deg and 270 deg, respectively, should
the evaluation results in Secs. 3, 4, and 6. be laid out for mark symmetry44 like AIM, they were not
Figure 2(a) shows an example of the dedicated SEM-OL evaluated at this time. Alternatively, interlace pattern as a
target between the metal layer and via layer for overlay X. dedicated SEM-OL mark between M1A and M1B, which

100%
SE signal

1 2
Threshold 50%
0% Left edge
Right edge
Beam position Pattern center
(c) of current layer
1 2

Overlay X
Pattern
center Pattern center
of reference layer

(a) (b) (d)

Fig. 2 Example of dedicated SEM-OL mark for explanation of the measurement algorithm for overlay X
(a) dedicated OL target for SEM-OL metrology whose reference and current layer is V0A and M1A,
respectively in this example, (b) detected pattern edges of trench and hole pattern, and the pattern center
calculated as the mean of pattern edge coordinates, (c) pattern edge method with threshold of 50%,
and (d) pattern center of reference and current patterns calculated as the mean of each pattern center
coordinate. Enlarged view of two pattern centers shows calculation method of overlay X .

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

has pattern symmetry, was evaluated in Sec. 4. Also line and When layout of overlay mark is symmetric and concentric,
space patterns by single exposure were laid out for evaluating like in SEMI Standard marks,1 measurement error due to
influence of pattern size and image rotation. image rotation and magnification error should be negligible.
Figure 2 shows SEM-OL measurement algorithm. An Third is tilt of primary electron beam axis. The TIS by
example of a dedicated target for overlay X measurement the tilt is proportional to the tangent of the tilt angle and
is shown in Fig. 2(a). Scan direction of SEM for overlay difference in height between the reference and current layer
X is left-to-right with respect to wafer notch. The pattern theoretically. Tilt is calibrated precisely using inverted pyra-
edge is detected for each pattern using conventional thresh- mid Si substrate, which is obtained via anisotropic etching of
old method.44 It is found with the cursor box [white and crystalline silicon.48
yellow boxes to check the pattern area in Fig. 2(a)]. In the Although SEM-OL metrology can measure device pattern
automatic measuring system, the position of the cursor box is directly, measurement of dedicated SEM-OL mark should be
decided by template matching with the registered image. selected in some cases. Current pattern edge on device pat-
Figure 2(b) shows each pattern edge and the pattern tern layout is close to the reference pattern edge as via in the
center. Right and left edges of the trench are detected 36 trench in the dual damascene (DD) process. Then the edges
points, respectively. Edges of the hole are detected at 48 overlap with each other and degrade the OL measurement
points. Pattern center is calculated as the mean of edge coor- accuracy, especially linearity when overlay error is large.
dinates. The threshold for edge detection is set to 50% Hotta et al.31 had developed SEM-OL metrology for double
[Fig. 2(c)]. Pattern centers for current and reference layers patterning of complex 2-D holes as well as dense lines.
are calculated as the average of all the patterns position coor- Again, high-voltage electron beam may have potential to
dinates for each layer [Fig. 2(d)]. Then the overlay vector is damage device property. In that case, a dedicated mark is
determined as the difference of coordinates of pattern centers laid out at a distance from the device area. When a large
for each layer [Fig. 2(e)]. For this case, overlay X is x com- number for measurements in the field is needed for high-
ponent of the overlay vector, which is as-designed zero offset order correction and device patterns within the measurement
in horizontal direction. Offset Y in Fig. 2(e) is not used for point is not proper for SEM-OL, dedicated mark is needed
overlay measurement. For overlay Y, which rotates counter- around the measurement points. In collaboration with imec,
clockwise 90 deg with respect to the target for overlay X, dedicated mark was designed for 10-nm node BEOL proc-
the target is located in vicinity of the target for overlay X. ess. It is important for design of dedicated SEM-OL mark
TIS in SEM-OL measurements had been evaluated.25,45 to be symmetric with zero baseline like SEMI Standard1
Rosenfield et al. have optimized the SEM accelerating volt- Opt-OL mark, Box in Box, AIM mark, and μDBO target to
keep high measurement accuracy.
age, detector design, and scanning technique to reduce TIS.
Developed techniques and applications for reducing TIS
In this paper, three factors are mainly considered to improve
and the optimized SEM-OL target are effective in improving
TIS in SEM-OL. First is charging caused by the interaction
the repeatability of SEM-OL measurement.
of the electrons with the specimen. Asymmetry of the signal
Current move–acquire–measure (MAM) time of SEM-
profile is increased in some cases, And it causes a shift of
OL measurement by CD-SEM is below 2 s. To ensure high
overlay measurement value. It depends on specimen struc-
precision, MAM time of HV-SEM is currently about 10 s for
ture and accelerating voltage of electron beam and scan con- low S∕N signal BSE images evaluated in Sec. 6.1. In order to
ditions, direction, and scan speed. To reduce the asymmetry, extend SEM-OL technique to beyond 3-nm node logic,
a method using multidirection scans for imaging has been improved measurement precision of detecting buried pat-
evaluated in Sec. 5.1. When left-to-right scan causes asym- terns and higher measurement throughput are required for
metry between left and right signal profile at pattern edge, more stringent overlay control. Measurement throughput
measurement using additional right-to-left scan can be is being improved through an image processing technique
applied. At ADI, resist shrink is caused by electron beam for low S∕N images and application for sequence before
irradiation. Normally, resist is shrunk symmetrical in imag- image acquisition.
ing when the resist pattern layout is symmetrical. Therefore, CD-SEM images were acquired using Hitachi CG5000,
influence of resist shrink to overlay accuracy should be operated at low accelerating voltage of 800 V. At the low
negligible. voltage, collected signal is mainly SE. CD-SEM on this con-
Second is SEM image distortion, rotation, and magnifica- dition cannot detect buried pattern, which includes reference
tion. It influences measured pattern edge distribution. It pattern at ADI. This condition is selected for higher yield of
mainly depends on electron-scanning uniformity in speed SE and needed for high-resolution measurement. CD-SEM
within the scan line and on relative displacement of the scan can detect pattern edge for SEM-OL measurement at AEI.
line by magnetic and electric noise. Measurement method In some case, to detect edge signal of current and reference
and correction method of image distortion have been patterns simultaneously or edge signal of the trench or hole
evaluated.46,47 Dedicated SEM-OL mark in Fig. 2 is for over- bottom, higher accelerating voltage from 1 to 5 kV is applied.
lay X measurement. As for the layout, there is a designed It will be discussed in Sec. 5.
offset Y between pattern centers of the reference and current
layer, which is about 800 nm. Image rotation should affect
overlay X as measurement error. Image rotation of SEM tool 3 Evaluation of SEM-OL Metrology Using Pattern
is calibrated. Overlay shift caused by image rotation cannot by Single Exposure
be measured by method using measurements at 0 deg and We evaluated the SEM-OL target patterned by single expo-
180 deg of wafer rotation. The measurement error will be sure (M1A).39 The overlay between grating patterns with
discussed in Sec. 3. If offset Y in Fig. 2(e) was measured, design rule pitch and relaxed pitch was measured at AEI
Y magnification error in SEM image would be unacceptable. using CD-SEM. In Fig. 3, the details of SEM-OL modules

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Conditions: Vacc = 800 V, Current = 8 pA, 512 pixel, 16 Frame

1.8nm/pixel 2.2nm/pixel 2.6nm/pixel 2.9nm/pixel 2.9nm/pixel 2.9nm/pixel 2.9nm/pixel

Mag. :150k 150k 100k 90k 90k 90k 90k

W24 / P96nm W60 / P120nm W100 / P200nm W150 / P300nm W200 / P400nm W250 / P500nm W300 / P600nm
(a) (b) (c) (d) (e) (f) (g)

Fig. 3 Images of SEM-OL module using HV-SEM. All patterns are patterned by single exposure. Overlay
was evaluated using upper and lower grating in each image, which was defined as current and reference
pattern, respectively. Size of current grating in each image is 24-nm width and 96-nm pitch. Width and
pitch of reference grating are described under each image. They increase from (a) to (g).

designed for the evaluation are shown. Upper and lower half length in the current layer for measurement is shorter and
patterns of each image are defined as the reference and cur- pixel size is about 3 nm at magnification 90k and 512 pixel
rent layer, respectively, in this section. Dimensions of refer- imaging. Measurement results of each site in field are aver-
ence and current grating in a group of targets are different. age of measurement in nine chips (points). Therefore, repeat-
Pattern size of reference grating in each target is a design rule ability pofffiffiffiaveraged result is estimated to be about 0.1 nm
of M1A in common (width = 24 nm and pitch = 96 nm). (¼0.3∕ 9). TIS of overlay X for reference grating pattern
Pattern size of the current grating in each target is from the size: 24,100 and 250 nm is −0.01, 0.12, and 0.16 nm,
device pitch 96 to 600 nm. Grating pitch of optical AIM respectively.
mark and μDBO target is typically from 200 to 2000 nm.7 Overlay shift within intrafield on six locations through the
Every target in Fig. 3 is for overlay X measurement and field is measured as shown in Fig. 5. Six measurement areas
as-designed zero offset between the reference and current are located on upper left (UL) and right corner (UR), and
pattern in horizontal direction. Scan direction of SEM for lower left (LL) and right corner (LR), and upper center (UC)
overlay X is left-to-right with respect to wafer notch. The and lower center (LC) end in the field. The graph shows the
dedicated target for overlay Y, which rotates counterclock- overlay between grating in design rule pitch (96 nm) and gra-
wise 90 deg with respect to the target for overlay X, is located ting in various pitches. In the X coordinate, Wxxx indicates
in the vicinity. Scan direction of SEM for overlay Y is top to the line width of current grating. The field is 26 × 16 mm. To
bottom with respect to wafer notch. The sampling plan was evaluate overlay variation in the field with respect to each
two targets at each site for both overlays X and Y, 6 sites in a target, averaged overlay of 54 measurements is subtracted
chip, and 9 chips in a wafer (54 measurement points in total). from measured overlay at each point. Every point is the aver-
The target for 24-nm current patterns in Fig. 3(a) consists age of nine fields over the wafer. Shape in the graph shows
of long-trench patterns through the top and bottom of the horizontal position in the field (circles are on the rightmost,
FOV (without line tip). Averages of 54 measurements of both squares are on the leftmost, and triangles are on the center).
overlays X and Y are not zero but 0.03 and −0.07 nm, The results show that larger grating size gives larger over-
respectively. One of the reasons for nonzero value is image lay range in the intrafield fingerprint (the maximum range is
rotation. It is very small because it is calibrated in advance. In
this paper, TIS was measured without image rotation factor.
Intra-field position
Figure 4 shows repeatability, which is 3σ of measure-
UL UC UR
ments repeated 10 times with wafer load and unload.
Repeatability of overlays X and Y for 24-nm current patterns UL UC UR
Overlay between different pitch

in Fig. 3(a) is 0.14 and 0.17 nm. Repeatability of image rota- LL LC LR

1.0 LL LC LR
within single exposure (nm)

tion will be estimated based on symmetry pattern results in 0.8

Sec. 3. The repeatability of the target including wider current 0.6 Right side
in field
pattern is degraded from 0.2 to 0.3 nm because total line 0.4
0.2
1.0nm
0.0
0.4
Overlay X Overlay Y –0.2
–0.4
Left side
Repeatability (nm)

0.3 –0.6
–0.8 in field
–1.0 Overlay X Overlay Y
0.2
W24
W60

W24
W60
W100
W150
W200
W250
W300

W100
W150
W200
W250
W300

0.1 Small Large Small Large

Reference grating pattern size (nm)
0.0
W24 W60 W100 W150 W200 W250 W300 Fig. 5 Overlay between device pitch and other pitches, which are pat-
Reference grating pattern size (nm) terned by single exposure. Intrafield positions, UL, UR, LL, and LR
correspond to upper left and right corner and lower left and right cor-
Fig. 4 Repeatability of SEM-OL measurement for the target shown in ner in field, respectively. UC and LC correspond to upper and lower
Fig. 3. Repeatability is defined as 3σ of 10 repeated measurements. center end in field.

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

1.0 nm on overlay X). The effect seems to be mainly a slit Table 1 SEM-OL performance in multiple patterning layers (M1B to
size and pitch issue. This is widely known to be related to M1A and V0B to V0A) and in layer-to-layer in DD process (V0A to
M1A) at AEI.
coma aberration fingerprint of the i-ArF scanner16,17 but has
not been simulated. Overlay error was caused by scanner
aberration depending on a variability from tools and the illu- Repeat. TIS
mination condition of the scanner, which is decided from the Current to
typical pattern feature. Therefore, in-die overlay using larger reference 3σ (nm) Ave. (nm) 3σ (nm)
size pattern has potential for having discrepancy from the
M1B to M1A OL X 0.11 −0.01 0.10
actual device pattern. Overlay measurement using device
pattern size is effective to reduce the discrepancy. OL Y 0.11 −0.01 0.07

4 SEM-OL for Dedicated Mark using CD-SEM V0B to V0A OL X 0.14 0.13 0.17
In Fig. 6, the details of CD-SEM overlay modules are shown.
There are three types of targets. The first and second modules OL Y 0.17 0.11 0.18
are designed for overlay measurement in the multiple pat-
M1A to V0A OL X 0.25 0.01 0.29
terning layer (M1B to M1A and V0B to V0A, respectively)
after hard mask (HM) etch. Dimensions patterned are the
OL Y 0.30 0.05 0.28
same in both layers. Third module is designed for overlay
measurement in layer-to-layer in DD process (M1A to V0A)
at AEI. In the imec N10 process, metal-first and self-align
process were applied. Therefore, large trench in the metal
measurement in Fig. 3(a) with asymmetry condition, 0.14
layer should be patterned over via area to detect via pattern
and 0.17 nm. It is caused by variation of image rotation
edges precisely in AEI. The trench size should be optimized
and less total measured line length on the measurement in
to prevent WIS for overlay in manufacturing, because etch-
Fig. 3(a).
ing conditions on large trench area may be not the same as in
the device area, and via pattern in the mark have potential to Results of overlay for V0B to V0A and M1A to V0A at
be degraded in edge contrast. Dedicated SEM-OL mark can AEI are not sufficient for overlay metrology for 3-nm node.
be designed within 2 × 2 μm, the size easily allows its place- Especially, repeatability of overlay for M1A to V0A is
ment in many locations for in-die overlay. Every target in degraded by low contrast on V0A hole pattern edge in
Fig. 6 is for overlay X measurement and as-designed zero Fig. 3(c). The edge seems to be rounded off at M1A HM
offset between reference and current pattern in horizontal etching. It will be improved by optimizing scan conditions
direction. The dedicated target for overlay Y, which rotates (scan speed and accelerating voltage, etc.), using well-
counterclockwise 90 deg with respect to the target for over- designed dedicated mark. Repeatability for overlay measure-
lay X, is located in vicinity. Scan direction of SEM is the ment is improved by higher resolution imaging (smaller pixel
same as evaluation in Sec. 2. The sampling plan was two size or larger frame number) and by increasing the number
targets at each site for both overlays X and Y, 1 site in a chip, of measurement points (edge length).49,50 The relationship
and 10 chips in a wafer (20 measurement points in total). between repeatability and throughput should be taken into
The repeatability, average of TIS and TIS variation over account when SEM-OL is considered as an alternative for
the wafer for the three evaluations are presented in Table 1. Opt-OL measurements.
Repeatability and TIS variation are 3σ of measurements Figure 7 shows CD-SEM imaging for SRAM pattern
repeated 10 times with wafer load and unload. Overlay mark after DD etching.37 This layout has via-in-trench with large
between M1B and M1A is interlace pattern with symmetry. metal trench region. CD-SEM can measure overlay in
Measurement points for each layer are selected so that the SRAM region between V0 and M1 directly. The repeatability
pattern centers of M1A and M1B are as-designed zero offset. of overlays X and Y is 0.31 and 0.47 nm, respectively. They
The results are sufficient for overlay metrology for 3-nm are larger than the dedicated target because it depends on
node. The repeatability, 0.11 nm, is improved from that of number of via and trench length.30

Conditions: Vacc = 800 V, Current = 8 pA, 1024 pixel, 16 Frame

0.73nm/pixel 1.3nm/pixel 1.3nm/pixel Current
V0B layer Reference
M1A layer
Trench
. Via
V0A
V0A

0.75μ m 1.35μ m 1.35μ m

(a) M1A M1B (b) (c) (d)

Fig. 6 Images of SEM-OL module using CD-SEM at AEI: (a) M1B to M1A after M1 HM etch, (b) V0B to
V0A after V0B HM etch, (c) M1A to V0A after DD etch, and (d) schematic cross section for overlay for
M1A to V0A.

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Conditions: Vacc = 800 V, Current = 8 pA, 1024 pixel, Table 2 Correlation between SEM-OL and optical IBO at AEI. Linear
pffiffiffi
1.1nm/pixel 16 Frame regression (slope, offset, and R 2 ) and NRE which defined as 3∕ 2 of
difference between two techniques.

Current to Offset NRE

reference Slope (nm) R2 (nm)

M1B to M1A X 0.97 −0.17 0.95 1.0

Y 1.03 0.16 0.95 1.0

V0B to V0A X 0.99 0.55 0.97 2.1

Fig. 7 CD-SEM imaging for SRAM pattern after DD metal etching Y 0.98 −0.77 0.97 2.1
and the schematic cross section.
M1A to V0A X 1.02 0.35 0.98 1.6

Results of the correlation of SEM-OL at AEI and optical Y 1.00 −0.80 0.98 1.6
IBO are shown in Fig. 8. IBO measurements are performed
using Archer 200 tool from KLA-Tencor with standard AIM
marks. The sampling plan was two targets at each site for
both overlays X and Y, 1 site in a chip, and 150 chips in for intralayer (V0B to V0A) and interlayer (M1A to
interfield. We checked the linearity with Opt-OL using a V0A).39,40 The differences are not significant. Six parameters
program-shifted wafer. In the correlation, both the slope and of CPE were compared between SEM-OL and optical IBO.
R-square are close to 1, indicating good correlation shown The sampling plan and SEM-OL and optical IBO conditions
in Table 2. Offset of overlay between M1B and M1A is are the same as correlation of evaluation in Fig. 7.
within 0.17 nm with symmetry of SEM-OL mark. On the In Fig. 9(a), six parameters of CPE are extracted for
other hand, offset of overlay between V0B and V0A and SEM-OL and optical IBO between V0B to V0A after HM
between M1A and V0A is lager. It was caused by asymmetry etching. Translations X and Y at overlay between V0B to
of SEM-OL mark and overlay discrepancy between the V0A have some programed trends in the vertical direction
hole of SEM-OL mark, which is the same size as the device, by a scanner offset. The distributions show the same ten-
and large width line ofpOpt-OL
ffiffiffi mark. Net residual error dency. The difference of each 3σ in interfield between
(NRE) is defined as 3σ∕ 2 of difference between two tech- SEM-OL and optical IBO is small, although each NRE is
niques. NREs are within 2.1 nm for overlays X and Y, which large (2.1 nm) in Table 2. In Fig. 9(b), the six parameters
include measurement uncertainty and CD-SEM overlay, pre- of CPE are extracted for SEM-OL and optical IBO between
cision of Opt-OL, sample variations of both optical and SEM M1A to V0A after DD etching. Distributions of translations
targets, and overlay variation due to distance of the Opt-OL X and Y for SEM-OL and optical IBO are similar to each
and SEM-OL marks. The distance is from 200 to 700 μm. other. The 3σ s of optical IBO is larger than SEM-OL.
Hotta et al.32 have evaluated NRE between overlays at two Four parameters (asymmetry magnification, asymmetry
sites as a function of the distance, which begins to increase rotation, symmetry magnification, and symmetry rotation)
at about 1000 μm. It should be considered for the evalua- are similar to each other, respectively. However, there are
tion. Measurement uncertainty of CD-SEM overlay will be several large differences (>0.08 nm∕mm) in CPE parameter
improved by optimized mark design regarding symmetry between SEM-OL and optical IBO on some shots of wafer
pattern and increasing edge length. center or wafer edge. The maximum difference in the field is
We have compared values of correction parameter estimated about 1 nm because the field size is 26 × 16 mm
between SEM-OL and Opt-OL in linear 10 correctable terms and the 3σ s of optical IBO is larger than SEM-OL by

12 12 12
SEM-OL (nm)
SEM-OL (nm)
SEM-OL (nm)

Overlay X 84
8
Overlay X 4 Overlay X84
0 0 0
-12 -8 -4 -4 0 4 8 12 -12 -8 -4 -4 0 4 8 12 -12 -8 -4 -4 0 4 8 12
-8 -8 -8
-12 -12 -12
Optical IBO (nm) Optical IBO (nm) Optical IBO (nm)
12 12 12
SEM-OL (nm)
SEM-OL (nm)

SEM-OL (nm)

Overlay Y 8 Overlay Y 8 Overlay Y8

4 4 4
0 0 0
-12 -8 -4 -4 0 4 8 12 -12 -8 -4 -4 0 4 8 12 -12 -8 -4 -4 0 4 8 12
-8 -8 -8
-12 -12 -12
(a) Optical IBO (nm) (b) Optical IBO (nm) (c) Optical IBO (nm)

Fig. 8 Correlation between SEM-OL and optical IBO at AEI: (a) M1B to M1A, (b) V0B to V0A, and
(c) M1A to V0A.

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Asymmetry Asymmetry Symmetry Symmetry

Translation X Translation Y magnification rotation magnification rotation

3σ =10.62 nm 3σ =11.67 nm 3σ =0.05 nm/mm 3σ =0.06 nm/mm 3σ =0.07 nm/mm 3σ =0.06 nm/mm

+/- 0.1nm/mm
+/- 0.1nm/mm

+/- 0.1nm/mm
+/- 0.1nm/mm
+/- 12nm
+/- 12nm
SEM
at AEI

3σ =10.71 nm 3σ =11.64 nm 3σ =0.08 nm/mm 3σ =0.08 nm/mm 3σ =0.08 nm/mm 3σ =0.07 nm/mm

+/- 0.1nm/mm
+/- 0.1nm/mm

+/- 0.1nm/mm
+/- 0.1nm/mm
+/- 12nm
+/- 12nm

IBO
at AEI

(a)

Asymmetry Asymmetry Symmetry Symmetry

Translation X Translation Y magnification rotation magnification rotation
3σ =2.23 nm 3σ =2.92 nm 3σ =0.11 nm/mm +/- 0.1nm/mm 3σ =0.10 nm/mm 3σ =0.11 nm/mm 3σ =0.09 nm/mm

+/- 0.1nm/mm
+/- 0.1nm/mm

+/- 0.1nm/mm
+/- 3nm
+/- 3nm

SEM
at AEI

3σ =2.89 nm 3σ =3.67 nm 3σ =0.17 nm/mm 3σ =0.13 nm/mm 3σ =0.16 nm/mm 3σ =0.13 nm/mm

+/- 0.1nm/mm
+/- 0.1nm/mm

+/- 0.1nm/mm

+/- 0.1nm/mm
+/- 3nm
+/- 3nm

IBO
at AEI

(b) : Large difference of CPE correctable between SEM and IBO (>0.08nm/mm)

Fig. 9 Wafer maps of six parameters for CPE which are extracted for SEM-OL and optical IBO
(a) between V0B to V0A after HM etching (b) between M1A and V0A after DD etching.

differences from 0.03 to 0.06 nm/mm. Discrepancy between Table 3 Overlay residual after CPE correction.
SEM-OL and optical IBO is larger for overlay between M1A
and V0A. The reasons include the difference of measurement 3σ of residual after CPE (nm)
patterns (trench and hole) and illumination condition of Current to
i-ArF scanner between M1A and V0A.31 reference SEM-OL Opt-OL IBO
CPE correction is effective in reducing overlay residual.
It is expected to reduce overlay error after the correction V0B to V0A X 2.0 2.8
when the correction is ideally fed back to the scanner. 3σ
Y 2.1 2.8
of overlay residual is a metric commonly used to evaluate the
overlay correction in semiconductor manufacturing. Table 3 M1A to V0A X 3.4 3.9
shows the 3σ of residuals after CPE correction. Each residual
is smaller with SEM-OL. It shows CPE by SEM-OL has the Y 6.4 6.8
possibility to improve overlay error more than optical IBO.
However, throughput of current SEM-OL is slower than
Opt-OL. Therefore, hybrid overlay metrology using SEM-
OL and Opt-OL may be a candidate for effective overlay 5 Overlay for Actual Device Pattern
monitor. Hotta et al. have evaluated hybrid overlay metrol-
ogy using optical linear correction (10 terms), which is 5.1 Overlay Using Edge-to-Edge Overlay
measured at four corners of chips and SEM-OL high-order Charley et al.51 have evaluated SEM-OL measurement using
correction in the intrafield, which is measured at four chips actual logic device area directly. Fig. 10(a) shows an example
on double patterning process for dense line patterns.31 of CD-SEM enables one to measure overlay between SiN

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Le edge Right edge

of 1st SAQP line of 6th SAQP line
structures of the CD-SEM-based methodology. The factor
of discrepancy between the two techniques in Fig. 10(b) may
EEL EER
Block length involve fluctuation of the tip edge position of block line pat-
tern, which is not robust to process variation (mask pattern,
Block paerns lithography, and etch). The average of the edge detection is
10pixel = 1 line in FOV not enough to be used, only averaged measurement results of
SAQP paerns 10 images using 10 pixels width per image.
= 6 lines
1st 2nd 3rd 4th 5th 6th
EEL, EER : Le and right edge to edge overlay 5.2 Overlay Using Comparison with Reference
Overlay = ( EEL - EER ) /2 Image
For a case where patterns for overlay measurement exist on
measurements of EEL and EER (nm)

the surface of an actual device, iPQ using comparison to

reference image had been developed.36 The iPQ enables
SEM-OL calculated from

overlay measurements even when the reference pattern edge

is partially covered by the current layer pattern or the pattern
is too complicated to detect the pattern edge. It expanded the
Slope = 0.95
range of application of SEM-OL technique, which has been
Offset = 0.11nm applied on high throughput review SEM or high-voltage
R 2 =0.91 SEM and was used as continuous monitoring of overlay
for memory device. The iPQ enables image collection at
predetermined points. The proposed overlay measurement
Opcal IBO (nm) algorithm is characterized by comparing test images with
a golden image, which has an ideal zero overlay. The golden
Fig. 10 Overlay between SAQP and EUV block pattern using CD- image is selected by the user from the collected images.
SEM: (a) SEM imaging and overlay calculation from left and right Figure 11 shows the process flow of the proposed algorithm.
EE overlays and (b) correlation between calculated SEM-OL and Two pattern regions, first current pattern region (#1 in this
optical IBO.
figure) and second reference pattern region (#2 in this figure)
are recognized from golden and test image automatically
by utilizing a “graph cut” technique.53,54
dense line patterned by self-aligned quadrupole patterning The placement error of the current patterns (dX c ; dY c ) and
(SAQP) process and SiO block patterned by extreme ultra- the placement error of the reference patterns (dX r ; dY r ) are
violet (EUV) exposure.52 Edge-to-edge (EE) overlay4 be- calculated using a template matching method.55 Based on
tween SAQP line edge and EUV block pattern tip should the technique, the placement error of the segmented pattern
be controlled. is obtained as a difference between the two images. This
It mainly depends on line width of SAQP, length of Block developed matching method extracts the position of each pat-
pattern, and overlay between SAQP and EUV block. In the tern contained in two images. Finally, the overlay (ex ; ey ) is
case illustrated in Fig. 10, there are six lines patterned by calculated from each pattern placement error.
SAQP process. Three parameters (identified: EEL , EER , and It is not necessary to set up the measurement cursors. This
the block length) were measured by CD-SEM. EEL is is one of the advantages of the proposed method from a
defined as distance between left edge of first SAQP line and usability point of view. The position of second pattern (layer
left tip end of block line. EER is defined as the distance #2 in Fig. 11) is measured automatically although the edge is
between the right edge of sixth SAQP line and right tip end partially covered by current pattern. It should be mentioned
of block line. Two line edges and two tips of EEL and EER that the calculated overlay is a relative value based on the
are detected using averaged SE signal profile for 10 scan golden image.
lines (of 10 pixel width).44 The basic performance of the proposed method was
Overlay between SAQP and EUV block is calculated evaluated with an advanced DRAM device. The target layers,
from EEL and EER Metal0, and contact are shown in Fig. 12(a). In this experi-
ment, we use a Hitachi High-Technologies Review SEM
overlay ¼ ðEEL − EER Þ∕2:
EQ-TARGET;temp:intralink-;sec5.1;63;227

RS6000 with iPQ for imaging. Overlays between metals in

current patterns and contact holes in reference patterns were
Acceleration voltage is optimized to 5 kV to enhance tip con- measured about 2700 points for wafer distribution. Contact
trast of block line pattern on SAQP. To reduce the asymmetry hole is partially covered by metal. Figure 12(b) shows a
of SEM signal between the left and right tips, a method using wafer map of the overlay, where the lengths and directions
multidirection scans for imaging has been applied. of the vectors correspond to the measurement results. There
Figure 10(b) shows the correlation plot between SEM-OL are differences in the overlay trend at the left side and the
and optical IBO. IBO measurements are performed using right side on the map. It is observed that the boundaries of
Archer 200 tool with standard AIM marks. Each data point the shot regions correspond to the discontinuous portion of
corresponds to 1 die on the wafer. SEM-OL and IBO data the overlay direction.
are an average of 10 and 4 points per die, respectively. Over To evaluate the repeatability, overlay was measured 3
a 10-nm overlay range, the two techniques are correlated times with the wafer loaded and unloaded. The repeatability
(R2 ¼ 0.9) and the offset is small (=0.1 nm). This validates is defined using deviations of variations among repeated
the good sensitivity and better representing OL in device measurements for each site. σ1, σ2, and σ3 are the deviations

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

#1 #2 #3

#1 Dc (dXc, dYc)

Dr(dXr, dYr)

OL (ex, ey)
Golden Image #2, 3
Dc (dXc, dYc)
ex = dXc - dXr
#1 ey = dYc - dYr
Overlay Calculation

Dr (dXr, dYr)
Test Image Layer #2, 3
Recognition Template matching
Fig. 11 Process flow diagram of overlay measurement using iPQ. Layers #1 and #2 correspond to the
reference layers and layer #3 corresponds to the current layer. A golden image is taken in advance,
which has an ideal overlay defined as zero overlay. Overlay of test image is measured using template
matching with golden image.

Conditions: Vacc = 5 kV, Current = 20 pA, 16 Frame, pix size = 0.66 nm 6 SEM-OL Metrology for Buried Patterns
Metal0
(current layer) 6.1 SEM-OL by HV-SEM Using Material Contrast
For a case where reference patterns for overlay measurement
Contact hole (filled) exist in the buried layer, SEM-OL metrology technique,
(reference layer)
which detects buried patterns using BSE or charging-up
phenomena as well as measure current patterns using SE,
(a) was evaluated. For example, when overlay at ADI is mea-
sured, the reference pattern is normally buried by interlayer
dielectric film and/or resist. OL measurement results at ADI
15 nm
can be feedback to lithography process immediately. It has
the potential to expand the range of application of SEM-OL
technique further. Imaging contrast of buried pattern using
high-voltage SEM depends on specimen structure and the
pattern size. We adopted simulation to evaluate the feasibility
and usefulness of an SEM condition.56 Characteristic con-
trasts in high-voltage SEM imaging were well-reproduced
in Monte Carlo simulation.
We used HV-SEM, CV5000, to observe the buried pattern
using BSE and evaluated the overlay at ADI. The current
pattern is resist, whereas the reference pattern is buried pat-
tern. Primary electrons with acceleration voltage of 5 to
0 nm 30 kV generate SE and BSE when they interact with the
10 nm
specimen. HV-SEM uses two detectors for OL measurement.
(b) BSE is captured by the lower detector at the bottom of the
object lens and SE is captured by the upper detector. SE gen-
Fig. 12 Application result with an advanced memory device: (a) exam- erated in the buried layer cannot escape to the surface, there-
ple of image for target layers and (b) wafer map of overlay directions
and magnitudes. fore, only the surface feature is efficiently observed as SE
image. High-energy electrons penetrate resist and capture the
difference in the material of the buried pattern. BSE and SE
of variations between first and second measurement, images of the same location can be observed simultaneously.
between second and third measurement, and between third BSE generated on the buried layer penetrates resist again
and first measurement, respectively. The repeatability is cal- and generates SE with the contrast dependent on the buried
culated using root mean squares value of σ1, σ2, and σ3. pattern. To improve TIS, calibration of the beam axis is
Repeatability (3σ) of overlays X and Y are 0.85 and 0.92 nm, performed and is discussed in Sec. 2.
respectively. A measurement repeatability of <1.0 nm was Figure 13 shows SE and BSE images at ADI using
achieved. Harada has shown the proposed method has HV-SEM. At each optimized condition, SE image shows the
linearity and sensitivity for the subpixel order overlay in resist pattern as the current pattern and BSE image shows the
the numerical experiments even if the patterns have size buried pattern as the reference pattern. The edge detection
variations.55 algorithm is the same as SEM-OL using CD-SEM explained

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Conditions: TV scan, 512pixel, 256Frame

Vacc
5kV 10kV 15kV 20kV 25kV 30kV
OPL Resist
SE M1B
Current
M1B 225nm
Resist M1A

BSE
Reference
M1A SiO/TiN
HM etch 0.9μ m =20/25nm
Best condition M1B at ADI
(a)

Conditions: TV scan, 512pixel, 256Frame

Vacc
5kV 10kV 15kV 20kV 25kV 30kV
V0B
SE
Current
225nm
V0B V0A
resist

BSE
Reference
V0A
HM etch 1.1μ m TiN =25nm OPL

Best condition V0B at ADI

(b)

Conditions: TV scan, 512pixel, 256Frame

Vacc
5kV 10kV 15kV 20kV 25kV 30kV

SE V0B
Current
V0B 370nm
resist
M1A

BSE
Reference
M1A
1.1μ m SiO/TiN
OPL
HM etch =20/25nm
Best condition
(c) V0B at ADI

Fig. 13 Images of SEM-OL using HV-SEM at ADI and the schematic cross section. (a) M1B to M1A
after M1B lithography, (b) V0B to V0A, and (c) V0B to M1A after V0B lithography.

in Sec. 2. The overlay value is calculated by the difference evaluation condition. The V0B at ADI needs two types of
of the respective points of two images. Figure 13(a) shows overlay measurement: overlay for V0B to V0A and for
acceleration voltage dependence of M1B at ADI. SE image V0B to M1A. Figure 13(b) shows images for overlay for
corresponds to M1B resist pattern, and BSE image corre- V0B to V0A at ADI. SE image corresponds to V0B resist
sponds to reference M1A pattern in the buried SiO2 ∕TiN pattern, and BSE image corresponds to reference V0A pat-
layer. The depth is 225 nm from resist surface to SiO2 ∕ tern in the buried TiN HM layer. The depth is 225 nm from
TiN layers whose thicknesses are 20/25 nm. The M1A pat- the resist surface to the TiN HM layer whose thickness is
tern is not visible at 5 kV but can be seen at 10 kV or higher 25 nm. When confirming the acceleration voltage depend-
acceleration voltage. The contrast ratio of line and space of ence, the reference layer pattern is confirmed at 10 kV or
15 to 20 kV was the best. When the acceleration voltage is more, and the contrast ratio is equivalent at 20 to 30 kV.
25 kV or higher, the contrast becomes lower since primary From this result, acceleration voltage of 25 kV was chosen
electrons transmit through the buried SiO2 ∕TiN layer. From for evaluation condition. Figure 13(c) shows images for
this result, acceleration voltage of 15 kV was chosen as overlay for V0B to M1A at ADI. SE image corresponds

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Table 4 SEM-OL performance in multiple patterning layers (M1B to Table 5 Correlation between SEM-OL and Optical DBO at ADI.
M1A and V0B to V0A) and in layer-to-layer (V0B to M1A) at ADI. Linearpregression
ffiffiffi (slope, offset, and R 2 ) and NRE which defined
as 3∕ 2 of difference between two techniques.

Repeat. TIS
Current to Current to Offset NRE
reference 3σ (nm) Ave. (nm) 3σ (nm) reference Slope (nm) R2 (nM)

M1B to M1A OL X 0.47 0.37 0.50 M1B to M1A X 0.92 −0.51 0.98 1.4

OL Y 0.45 0.67 0.48 Y 0.95 0.22 0.99 1.2

V0B to V0A OL X 0.25 0.23 0.33 V0B to V0A X 0.98 −0.79 0.99 1.6

OL Y 0.23 −1.60 0.74 Y 1.00 1.17 1.00 0.9

V0B to M1A OL X 0.21 −0.57 0.71 V0B to M1A X 1.02 1.14 0.97 2.0

OL Y 0.25 −0.06 0.92 Y 0.96 −0.32 1.00 3.1

to V0B resist pattern, and BSE image corresponds to refer- interfield. We checked the linearity with Optical DBO using
ence M1A pattern in the buried SiO2 ∕TiN layer. The depth a program-shifted wafer. In the correlation, both the slope
is 370 nm from resist surface to the SiO2 ∕TiN layers whose and R-square are close to 1, indicating good correlation
thicknesses are 20/25 nm. 25 kV or higher acceleration volt- shown in Table 5. On the other hand, some offsets of overlay
age is the optimized condition based on the contrast ratio. for V0B to V0A and for V0B to M1A are >1 nm. It may be
The acceleration voltage of 25 kV was chosen for evaluation caused by charge-up and damage of specimen. NREs of
condition. overlays X and Y for V0B to M1A are larger than 2 nm,
Repeatability average of TIS and TIS variation over the which include factors that are the same as evaluations at
wafer for the three evaluations is presented in Table 4. AEI in Sec. 4, measurement uncertainty and CD-SEM over-
Repeatability of M1B to M1A is >0.4 nm. Some TIS values lay, precision of Opt-OL, sample variations of both targets,
of overlay for V0B to V0A and M1A are >1.0 nm. This is and overlay variation due to distance of the Opt-OL and
not enough for overlay metrology for 3-nm node. These SEM-OL marks.
parameters are degraded from SEM-OL at AEI in Sec. 4.
Degradation of repeatability is mainly caused by charge-up
and damage of specimen by irradiation of EB during 10 time 6.2 SEM-OL by Low Voltage SEM Using Transit
measurements. Factors of TIS increasing involve asymmetry Charging State
of signal profile and difference of specimen damage be- HV-SEM using high-irradiation energy for buried pattern
tween 0-deg and 180-deg measurement during evaluation. detection has potential for a damage of device properties.
Reoptimization of SEM condition (acceleration voltage, Therefore, we are evaluating new scan (VT Scan) with low
magnification, scan mode, etc.) and dedicated target design irradiation energy.42,57,58 It detects transient voltage contrast
and evaluation method is needed to improve them to meet for subsurface imaging in Fig. 1. Modulated electron irradi-
logic overlay measurement specification. The results depend ation system enables to optimize condition for signal
on specimen condition. In these cases, buried patterns are detection. Figure 15(a) shows a schematic diagram of
trench or hole in 25- or 45-nm thickness layer. Material con- experimental set up for VT scan evaluation. The system is
trast is mainly between the pattern (SiO2 or TiN) and organic basically a low-voltage scanning electron microscope. Main
planarization layer. feature is pulsating electron irradiation system, which ena-
Results of the correlation of SEM-OL at ADI and Optical bles accurate control electron dose at pulse width T p .
DBO are shown in Fig. 14. DBO measurements are per- Pulsating electron beam is generated by a function generator
formed using Yield Star S-200 from ASML with standard installed with the flood–electron–gun. In addition, imaging
μDBO target. The sampling plan was two targets at each site system for pulse electron microscopy is developed and tran-
for both overlays X and Y, 8 sites in a chip, and 15 chips sient signals are detected at selected timing and time–width

30 30 30
SEM-OL (nm)

SEM-OL (nm)

SEM-OL (nm)

15 15 15

0 0 0
-30 -15 0 15 30 -30 -15 0 15 30 -30 -15 0 15 30
-15 Overlay X -15 Overlay X -15 Overlay X
Overlay Y Overlay Y Overlay Y
-30 -30 -30
(a) Optical DBO (nm) (b) Optical DBO (nm) (c) Optical DBO (nm)

Fig. 14 Correlation between SEM-OL and optical DBO at ADI: (a) M1B to M1A, (b) V0B to V0A, and
(c) V0B to M1A.

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Temporal gate of
Pulsed electron beam
signal-detection
(Irradiation)
Td B
Pulse A
width Tp 3
C D
Detector Image

Emitted SEs (a.u.)

Emitted contrast
SEs 2 P1 (Large
Capacitance)

Range few nm
1
Tp
P1 P2 P2(Small
1 μ m 500 nm SiO2 Capacitance)
0
100nm 0 1 2 3 4 5
100nm
poly-Si 0.1 0.3 0.7 3.0μ s
(a) (b) Irradiation-time (μ s)

Fig. 15 (a) Schematic diagram for VT scan set up, P1 with underlayer and P2 without underlayer and
(b) decay of emitted SE signal at P1 and P2 by continuous irradiation. Difference of decay rate creates
contrast between P1 and P2.

Conditions: Vacc=300V, Current=20pA

A B C D

Buried poly-Si

(a) Tp=0.1 μs (b) Tp=0.3 μs (c) Tp=0.7 μs (d) Tp=3.0 μs

Fig. 16 SEM imaging of VT scan whose contrast between with and without under layer is dependent
on pulse time T p . Each T p is (a) 0.1 s, (b) 0.4 s, (c) 0.7 s, and (d) 3.0 s.

T d . Structure of test specimen in Fig. 15(a) is the 1.2-μm- contrast with optimization of T p . Buried patterns and struc-
thick SiO2 layer, which contains 100-nm thick Poly-Si tures can be visualized using difference of dynamic electrical
pattern buried at 1.0-μm depth. Point 1 (P1) is with buried properties. The VT scan condition is calculated using RC
structure, which is Poly-Si pattern, and Point 2 (P2) is with- property of device circuit. While VT scan was developed for
out buried structure. Capacitance of structure under P1 is
larger than P2. Energy of primary beam is 300 eV and irra-
1 2
diation current is 20 pA. Under the condition, transit of
emitted SEs by continuous irradiation is shown in Fig. 15(b). Top view
320nm SiO / SiOC:160nm
The emitted Ses decrease with irradiation-time, because SiCN/SiOC/SiCN
part of generated Ses returns to specimen for an increase :30/100/30nm
in positive charge on the surface. The decay rate of emitted Cu : 160nm
Ses at P1 is slower than P2. The difference in the emitted Ses SiCN: 30nm
enhance at the transient state until T p is about 0.7 μs. This Cross section SiOC :160nm Oxide: 100nm
result indicates that the difference in decay rate depends on (a)
the difference in the capacitance caused by buried structure.
Figure 16 shows SEM imaging at each T p condition. At Conditions: Vacc=500V, Current=20pA
T p ¼ 0.7 μs, buried Poly-Si pattern contrast can be detected
1 2
most clearly. The most effective condition of T p for buried
pattern contrast depends on the specimen structure and the
pattern size.
In Fig. 17, see-through observation using buried Cu speci-
men is shown using VT scan. Cu, which is covered by SiO/
SiOC, was detected at several VT scan conditions. The depth Tp= 1.2 μs Tp= 0.7 μs Tp= 0.2 μs
from the surface to the buried Cu layer pattern is 320 nm.
Acceleration voltage is low under 500 V. This condition (b)
is the same or lower than the standard condition for CD Fig. 17 SEM imaging of device like structure using VT scan: (a) sche-
measurement. VT scan at middle T p in Fig. 17(b) detected matic cross section of specimen and (b) SEM imagings that are
buried Cu most effectively. The VT scan enhances the charge dependent on condition of T p .

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 Inoue and Hasumi: Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

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50. C. P. Ausschnitt et al., “Blossom overlay metrology implementation,” of Tokyo, Japan, in 1997. He joined Hitachi, Ltd. in 1997 and worked
Proc. SPIE 6518, 65180G (2007) on the development of ArF lithography process and phase shifting and
51. A. Charley et al., “Advanced CD-SEM solution for edge placement error OPC technique. From 2003 to 2009, he developed CVD process of
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52. J. Bekaert et al., “SAQP and EUV block patterning of BEOL metal Hitachi High-Technologies Corp. since 2009.
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53. Y. Boykov and V. Kolmogorov, “An experimental comparison of min-
cut/max-flow algorithms for energy minimization in vision,” IEEE Kazuhisa Hasumi joined the Device Development Center, Hitachi,
Trans. Pattern Anal. Mach. Intell. 26, 1124–1137 (2004). Ltd., Tokyo, Japan, in 1991. He has been engaged in work on improv-
54. Y. Boykov, O. Veksler, and R. Zabih, “Fast approximate energy min- ing semiconductor process yield. He worked on device development
imization via graph cuts,” IEEE Trans. Pattern Anal. Mach. Intell. 23, from 2000 to 2008. He has been engaged in developing SEM appli-
1222–1239 (2001). cations at Hitachi High-Technologies Corp. since 2009.

J. Micro/Nanolith. MEMS MOEMS 021206-15 Apr–Jun 2019 • Vol. 18(2)