DIGITAL COMPUTER CONTROL: IMPLEMENTATION CONSIDERATIONS By G. Perdikaris and S, Lesavich University of Wisconsin-Parkside P.O. Box 2000 Kenosha, Wisconsin 53141 ABSTRACT The software implementation of a control algorithm offers flexibility, reliability, and a high degree of accuracy. However, such an implementation offers limitations, too. For instance, the sampling frequency, the comput: tional delay, the finite vordlength of the digital computer, and the finite wordlength of the interface devices must be properly coordinated because they affect the performance :as:well as the-cost of the digital control systen. In addition, the quéntization errors that result in fixed-point Amplenentations must be properly handled by the system designer if the ap- plication is to be successful. 1. INTRODUCTION In the past, most of the signal transformations implied by filters and controllers have been accomplished by analog hardware. However, the in- creased speed and decreased size and cost of modern microprocessors and microcomputers have permitted the economical use of digital processing of signals to implement filtering and control algorithms in real time. ‘The software implementation offers several advantages. First, it offers flexibility, because the characteristics of the transformation algorithm can be easily changed by simply reading in a new set of parameters. Second, a software implementation results in a more reliable system, because there are no physical components to age or deteriorate with temperature variations. This in turn implies consistency in system performance and independence from bulky component problems, usually associated with low-frequency analog rea- lizations. Finally, a greater degree of accuracy can be attained with pro- gramming a digital controller algorithm, because the parameters are control- led by the designer who can set them to obtain an efficient and cost-effec— tive system that meets the problem specifications. However, the software implementation has also limitations. For in- stance, the finite wordlength and the computational delay of the computer used to program the control algorithm affect the performance of the digital control system and must be taken into consideration by the system designer. 2. SAMPLING FREQUENCY SELECTION Assume that a digital control system can be represented by the block 448 MOTOR-CON » OCTOBER 1985 PROCEEDINGSdiagram shovn in Fig. 1. In this figure, r represents the reference input, e the error, m the manipulation, and c the output. Also, Gq(z) denotes the transfer function of the discrete controller, and C,(e) the transfer function of the analog plant. WNotethat Analog-to-Digital (abc) and Digital-to-Analog (AC) converter interfaces have been assumed. CONTROLLER DAC (ZOH) PLANT m(k) m(t) r(k) + e(k) Fig. 1. Block diagram of digital control system. ‘The DAC can be represented mathematically by the transfer function of the Zero-Order-Hold (20H) element, given by oT go) - +=, @ where T represents the sampling time of the digital control system. The digital controller, Gq(z), is a discrete system which operates on the discrete signal (sequence of numbers) input, e(k), to produce a discrete signal output, m(k), according to some computational process or algorithm. The control algorithm, described by the transfer function M(z)/E(2), is d signed to meet the problem specifications. That is, the appropriate dif— ference equation (or discrete transfer function) is designed which satisfies the given specifications as closely as possible. The design of digital controllers is often carried out by first de- signing an analog prototype controller that meets the problem requirements for the analog control system. Once this is accomplished, the analog con- troller transfer function is converted to the corresponding digital control- jer transfer function by some approximation technique. The motivation for this approach is, of course, that successful designs of analog controllers are well established, which implies that the designer's main concern is to find the discrete equivalent of the analog controller so that the performance of the digital control system resenbles that of its analog counterpart. In general, the performance of a digital control system can be made to approach that of the corresponding analog control system if the sampling time (T) is omall, or the sampling rate (1/T) is large, relative to the dominant time constant of the controlled plant. If this ts not the case, however, the performance of the digital control system may deteriorate and become unsatisfactory. MOTOR-CON + OCTOBER 1985 PROCEEDINGS 449analog form by means of a DAC. The ADC quantizes the incoming signal and encodes it into a digital word. The digital wordlength of the ADC is usually expressed as n-bits-plus- sign, that is, n bits are allocated for the magnitude and one for the sign of the value being sampled. The DAC operation may be viewed as one of decoding, that is, as one of transforming a digital word into an equivalent analog signal level. The re- solution of the DAC can also be calculated from its number of bits and maxi- mum output range. The quantization error can be appreciable for short wordlength ADC and DAC devices. Its effect on the performance of the control system must be analyzed by the system designer. The voltage range and wordlength effects that the ADC and DAC components can have on the digital control system may be easily verified by simulation. Another factor that should be considered when selecting an ADC is the noise (error) level present in the signal we intend to sample. For instance, the wordlength of the ADC must be such that its quantization error does not exceed the error im the signal of a transducer. In addition, the DAC, being ess expensive than the ADC, should be coordinated with the ADC. 3.2 Parameter Quantization Effects If the encoding of the coefficients of the control algorithm is not ec curate enough, the resulting controller may exhibit characteristics which differ substantially from those of the original design. For instance, the poles and zeros of the implemented controller may end up in locations which are not close enough to the intended ones. This movement of the poles and zeros may in turn cause the Frequency: response characteristics (i.e., the magnitude, phase, and critical frequencies) to shift appreciably, so that the digital control system performance becomes unsatisfactory. It is, therefore, important that the frequency characteristics of the resultant digital control system be recalculated to see if they still meet the specifications. One way of determining the effects that finite wordlength has on the frequency characteristics of a digital control system is to obtain the trans- fer function of the approximating system and analyze it using conventional techniques. A less practical but more rigorous approach is to use sensitiv ity analysis. For instance, we can assess the effect of changing a control- ler coefficient on the frequency response of the control system by differen- tiating the closed-loop magnitude function with respect to that coefficient and use the value of the derivative as an indication of the sensitivity of the frequency characteristics to variations in the value of the particular coefficient. Another alternative is to simulate the digital control system on the digital computer. This approach is flexible because it allows one to verify the effect that ADC, DAC, and coefficient resolution have on the performance of the digital control system. In addition, the computer simulation can be used to investigate the effect of parameter quantization on the steady-state error and, thus, on the accuracy and stability of the control system. Some of the problems due to parameter quantization and how these pro- blems affect the performance of the digital control system for the various controller realization structures, are illustrated in the following example. 452, MOTOR-CON + OCTOBER 1985 PROCEEDINGS; EXAMPLE 1 ‘Assume that the transfer function of the plant in the digital control system of Fig. 1 is given by 10 Sp) = Ste By? and that the control loop sampling time is T= 0.1 sec. Assume, also, that 4t is required for the digital control system to track ramp inputs with zero steady state error and in deadbeat fashion, More specifically, it is re~ quired that the output match the reference ramp from the third sampling point on, and that there be little or no oscillation after that point. It can be shown that the desired digital controller is given by the dis~ crete transfer function = 34-245 (2-0.59332) (2-0.60651) (e-1) (2+0,66865) ‘The objective is to investigate the coefficient quantization effects on the different controller realization forms by analyzing the above controller assuming wordlengths of 10 bits, and 6 bits, respectively. Note that the digital controller has been expressed in both its unfac— tored form which corresponds to a direct form realization, and in factored form which is relevant for either cascade or parallel realizations. Consider the 10-bit wordlength coefficient representation case first. Assuming that truncation rather than rounding is used, this implies that the controller coefficients will be stored as integers, determined by miltiplying their decimal value by the scale factor 1024 (2 raised to the power of 10, the number of bits). For instance, the coefficient 11.2436 will be stored as TRUNC(11.2436*1024) = 11513, and so forth, Thus, the above digital control- ler transfer function forme are approximated by the transfer functions 3199427- 383882 + 11513 | 31.244142— 37, 488282 + 1.24316 10242” - 3392 ~ 684 2? — .331052 - .66797 for the direct form, Gq(z) = 21994 (0242-607) (10242~621) _ 31,22414(2-0,59277) (2-0, 60644) ie 10242-1024) (102424684) z - 1)@ + 0.66796) for the cascade/parallel form. Go) = The poles and zeros of the new direct form filter are determined to be zeros: 0,59209, and 0.60776 and poles: 0.99941, and -0.66836. Comparing the approximating controller transfer functions to the origi- nal ones, we observe that the poles and zeros of the cascade/parallel form controller have not shifted as much, from the original controller locations, MOTOR-CON + OCTOBER 1985 PROCEEDINGS 453as the poles and zeros of the direct form controller. In other words, the cascade/parallel realization is a more accurate representation of the origi- nal digital controller. Equivalently, the controller coefficients of the cascade/parallel form realization are less sensitive to wordlength con~ straints than the coefficients of the direct forn. Consider now the 6-bit wordlength case to see, first, if our conclusions about controller realization forms still hold and, second, how much worse the quantization error has become. For a 6-bit resolution, the scale factor is 64, that is, the coefficient values are obtained by multiplying by 64 and truncating the result, This leads to the direct form controller transfer function 199922 23992 + 719 | 31.234372"— 37.843752 + 11.23437 642" - 212 - 42 2? ~ 0.328122 - 0.65625 Gee) = which has poles and zeros given by zeros: 0.52026, and 0.69135, and poles: 0.9906, and -0.66248, ‘The cascade/parallel form controller is given by Gee) = 29996642237) Gie-38) 3123437 (9-0, 57812) (6-0,59575) eG. (Gh2~64) (642442) @ ~ DG + 0.65625) . As expected, the quantization error of the 6-bit resolution case is worse than that of the 10-bit resolution case. Of course, whether a 6-bit resolution is adequate or not depends on the problem specifications and eco- nomic considerations. It should be noted, though, that if the sampling fre~ quency used in the design is increased appreciably, the 6-bit resolution may not be acceptable. This example seems to reinforce the previous observation, namely, that the direct form is inferior to the cascade/parallel form. Next, 4n order to determine the coefficient quantization effect on the performance of the systen, the digital control system shown in Fig. 1 was simulated on a digital computer. The simulation results due to the original controller (exact case) as well as to the controllers obtained assuming 10- bit and 6-bit coefficient resolution, are shown in Table 1. As expected, there is deterioration in performance and it gets worse for the 6-bit reso— lution case. The effects of the ADC and DAC resolution on the performance of the previous digital control system can be easily analyzed by simulation as well. In summary, coefficient quantization errors depend on wordlength size as well as on controller realization forms. Specifically, if the wordlength is small and/or the controller is of relatively high order, the direct form rea- lization should be avoided. The reason for this is that a coefficient error in a direct form realization will affect all poles and zeros of ite transfer function, In 4 cascade/parallel form realization, on the other hand, the change of one coefficient affects only the poles and zeros of that section. 454 MOTOR-CON + OCTOBER 1985 PROCEEDINGSTable 1. Simulation R wits for Control System of EXAMPLE 1 Salis a WOsbit Case etbi cee Time r(t) (t) e(t) (t) c(t) a ° 0.0 0.0 0.0 0.0 0.0 or 4 1.0 0.0 1.0 0.0 1.0 0.0 0:21 ee 0.66865 1.33135 0.66869 1.33131 0.66910 1.33090 3 3 -0.00013 3.00013 0.00033 2.99967 0.02026 2.97974 04 4 9-00009 3.9999 0.00156 3.99844 0.05528 3.9447 0.5 5 9-00012 4.99988 0.00161 4.99839 0.05342 2.94657 06 6 0.0 6.0 0.00102 5.99898 0.03461 5.96539 0.7 7 0.0 7.0 0.001 6.99899 0.02907 6.97093 0.8 8 0.0 8.0 0.00099 7.999 0.02526 7.97474 0.9 9 0.0 9.0 0.00099 8.99901 0.02234 8.97766 1.0 10 9.0 = 10.0 0.00098 9.99902 0.02050 9.9795 4, COMPUTER WORDLENGTR sicrocomputers have limited wordlengths, usually 8 or 16 bits long. Therefore, the error input and the manipelation output of a digital control- der mist be quantized and the effects of the quancictioy on the performance of the system must be investigated. raetoct Suffictent accuracy for coefficient encoding and/or internal 8 referred to as limit cycle. The timit cycle phenomenon is characterized by a periodic output, even though there is no input causing it, For snaller wordlength computers, care must aleo be exercised so that Jeagrmettc overflow does not occur to avoid undesired ressite, at che very be monitored, and the calculation resuits should be gital controller in the laboratory, it 1s necessary microcomputer must be fast enough so that the implied by the difference equation form of the con within the sampling time interval. As an exazple, an order to implenent the control algorithm of EXAMPLE 1 in real time, we ett epcommuter that can perform the five multiplications ae well es che adds the time limit of 0.1 sec, MOTOR-CON + OCTOBER 1985 PROCEEDINGS 455Many practical applications require that the five multiplications of the algorithm in the above example must be done in 5 msec or less. Add to this the requirement that the multiplies, adds, and substracts must be done in double precision, and we see the reason that, in such cases, 16-bit proces- sors and fixed-point, rather than floating-point, arithmetic become attrac- tive. If the computational delay is too large relative to the sampling time, it can adversely affect the performance of the digital control system. It is useful, therefore, to have a good estimate of the computational delay for a control algorithm. The computational delay can be determined experimentally, for instance, by turning a signal on when entering the control algorithn evaluation and turning the signal off when done. Once the computational de- lay ie estimated, it can then be included as a time delay in the plant model and, thus, considered by the system designer when computing the control law. 6. CONCLUSIONS The sampling frequency, the wordlength of the computer system, and the wordlengths of the ADC and DAC interface devices must be sufficiently large and properly coordinated. Tf we sample fast, the speed and wordlength of the computer and the interfaces, and thus the cost of the overall system, will have to be high. If we sample relatively slow, in order to keep the system cost low, the system performance may become unsatisfactory. Thus, it is important that the system designer selects 2 sampling rate that properly balances the system cost and system performance characteristics for the application at hand. At the low end, the sampling frequency can not be smaller than twice the highest frequency of the reference input expected to be tracked by the digi- tal control system, Equivalently, the sampling frequency must be at least twice as large, and perhaps 10-20 times larger, than the system bandwidth. The proper sampling frequency must also be higher than the dominant pole(s) of the plant, and for proper disturbance-rejection characteristics for the control system, the sampling frequency should be relatively high when com pared to the highest frequency of the disturbance signal. To avoid excessive quantization errors, the computer wordlength, and the wordlengths of the ADC and DAC must be sufficiently large. Internal preci- sion should be adequate so that quantization effects, overflows, and limit cycles do not degrade the performance of the digital control system. REFERENCES: 1, BENNETT, S., and LINKENS, D.A., eds., Computer Control of Industrial Processes, Peter Peregrinus Ltd., 1982. 2. FRANKLIN, G.F., and POWELL, J.D., Digital Control of Dynamic Systems, ‘Addison-Wesley, 1980. 3, ISERMANN, R., Digital Control System, Springer-Verlag, 1981. 4. JACQUOT, R.G., Modern Digital Control Systems, Marcel Dekker, 1981. 5. KAISER, J.F., and KUO, P.P., Systems Analysis by Digital Computers, John Wiley & Sons, 1966. 6, KATZ, P., Digital Control Using Microprocessors, Prentice-Hall, 1981. 7. KNOWLES, J.B., and EDWARDS, R., "Effect of a Finite-Wordlength Computer in a Sampled-Data Feedback System", Proc. IEE, 112(6), 1197-1207, (1965). 458 MOTOR-CON + OCTOBER 1985 PROCEEDINGSOFFICIAL PROCEEDINGS OF THE SEVENTH INTERNATIONAL MOTOR-CON ’85 CONFERENCE OCTOBER 24-25, 4985 CHICAGO ILLINOIS MOTOR-CON + OCTOBER 1985 PROCEEDINGS |