PROJECT REPORT

Device Modeling and Simulation Practice (July - December 2024)

Course Code: EC5012

A Single MOSFET-Based Oscillator on a Bulk-Silicon Wafer

Hae-Yeon Kim, Seung-Il Kim, Joon-Kyu Han, Jin-Woo Jung, and Yang-Kyu Choi
IEEE Transactions on Electron Devices 45, no. 1 (2024): 1558-0563

Presented by

Subashini D, KV Manoj, JPR Prudvi, & E Ankitha

Roll No: EC24M2001, EC24M2002, EC24M2003 & EC24M2004

Course Instructor

Dr. Kumar Prasannajit Pradhan

Indian Institute of Information Technology

Design and Manufacturing (IIITDM) Kancheepuram,
Chennai-600127

December 12, 2024

1
1 Introduction
Oscillators are now applied in various fields, like communication, medical devices, and also in brain-like
hardware in the electronic system. Classic oscillators consist of several constituents, including resistors,
capacitors, and comparators; hence they are large as well as power-hungry. Researchers are therefore
now working on alternative possibilities, like single-transistor oscillators, small and energy-friendly. It
demonstrates this new technique via a fabricated oscillator with one MOSFET on a large silicon wafer [1].
The study begins by discussing the floating body (FB) effect. This is very common in silicon-on-insulator
(SOI) MOSFETs. In the effect of a physical FB, charge carriers build up to cause oscillations. This
approach has been widely utilized in SOI technology, but it would be interesting to see if the same
can happen in bulk-silicon MOSFETs [1]. The electrical floating body in a bulk MOSFET formed due
to the natural voltage between the moderately doped p-well and the lightly doped p-type wafer. This
will make it possible to generate oscillations even in large structures and fill the gap between the two
technologies [2].

Figure 1: Single MOSFET Based Relaxation oscillator

The manufactured oscillating bulk MOSFET operates on a unique principle. This is unlike conventional
MOSFETs, where inputted voltages at drain terminals are output as currents; the OB-MOSFET, unlike
these, takes current input at drain terminals and then delivers oscillating voltage output. It works with
an architectural mechanism called single transistor latch (STL) [2]. The STL causes the rapid switching
between high and low resistance states due to impact ionization. The output is in the form of a wedge-
shaped oscillating voltage waveform; thus, OB-MOSFET is like a replacement for relaxation oscillators.
One of the foremost merits enumerated is that it occupies much less space as compared to other devices.
The reason for this is that the circuit is not built from many circuit components and therefore takes a
smaller area and is very suitable for miniaturized systems [3]. This circuit also works beautifully on CMOS
technology. Therefore, it can be easily integrated into existing circuits with very little modifications. It
is also very versatile as it could adjust its oscillation frequency based on conditions such as input current
and capacitance [3].
Standard 180nm CMOS technology and provide interpretation in terms of energy band processes while
the oscillation phenomenon occurs. Input current and capacitance soar as oscillation frequency increases.
The two phenomena point to the direct relationship frequency-current [4]. These also coincide well with
those observed in SOI MOSFETs, thus validating e-FB as an alternative as applied to bulk devices. The
OB-MOSFET has great potential in biomedical and neuromorphic applications. It can generate low-
frequency sawtooth waveforms that are extremely suitable for future artificial neurons and other biology-
inspired hardware. In addition, in future low-power systems, energy savings and simple design make it
an important component. It has also been demonstrated here that one device-the MOSFET-can produce
oscillations on a bulk-silicon wafer, which seems to be the feature attributed to SOI technology [4] [5].
STL mechanism and e-FB effects to realize the manufacture of a new small-size device with adjustable
compatibility. As electronics takes another leap into facilitating the manufacture of minuscule and efficient
components, such innovations as the OB-MOSFET will find a role in technology development in the
future [5].

2
2 Literature Survey
2.1 Ferroelectric Relaxation Oscillators and Spiking Neurons
In their work, Wang and Khan introduced ferroelectric relaxation oscillators as a novel approach
to emulate biological spiking neurons. These devices leverage the non-linear polarization response of
ferroelectric materials to generate periodic waveforms that mimic the behavior of neurons [2]. Unlike
traditional oscillators that rely on resistors and capacitors, these ferroelectric devices utilize material
properties to improve energy efficiency and reduce power consumption.

Figure 2: The schematic of the ferroelectric relaxation oscillator

Their study highlights the potential of these oscillators in neuromorphic systems, where compact
and low-power solutions are critical. Additionally, the work explores how the ferroelectric relaxation
oscillators can be integrated into artificial neural networks, offering a pathway toward more efficient
hardware implementations for neural computations. This pioneering study provides a foundation for
exploring alternative oscillator designs for spiking neural systems [2].

2.2 Optimized Bio-Impedance Models Using Oscillators

Mohsen et al. explored the use of oscillators for optimizing bio-impedance model parameters, specif-
ically targeting biomedical applications. Their study demonstrated how relaxation oscillators can be
tailored to operate at low frequencies, ideal for biomedical sensing and monitoring. By employing dif-
ferent oscillator topologies, the researchers achieved significant improvements in measurement accuracy,
noise reduction, and stability [3].

Figure 3: Relaxation Oscillator circuits for optimizing bio-impedance model parameters

The paper emphasizes the importance of oscillators in creating robust biomedical devices that are both
energy-efficient and adaptable to a variety of medical conditions. This work underscores the versatility
of relaxation oscillators in addressing real-world challenges, such as wearable sensors and implantable
medical systems, where precision and reliability are paramount.

3
2.3 Floating Well Operation in CMOS Devices
Zappe et al. introduced the concept of floating wells in CMOS devices, which later became a cornerstone
for understanding oscillatory mechanisms in single-transistor designs [4]. Their study focused on the
dynamics of charge carriers within the floating body, explaining how these carriers accumulate and release
to facilitate oscillations. This foundational work illustrated the potential of CMOS devices to achieve
oscillatory behavior without requiring additional circuit elements. It also provided critical insights into
the role of floating wells in enhancing charge storage and dynamic response, which is crucial for modern
oscillators. Their research serves as a theoretical and experimental basis for advancements in bulk-
MOSFET oscillators, where similar charge dynamics are utilized.

2.4 Single-Transistor Latch (STL) in SOI MOSFETs

Chen et al. made significant contributions to the understanding of the Single-Transistor Latch (STL)
mechanism in SOI MOSFETs. The STL mechanism involves abrupt transitions between high and low
resistance states due to impact ionization, enabling oscillatory behavior. Their research demonstrated
how this latch mechanism could be effectively used in single-transistor oscillators, reducing the complexity
and size of oscillatory circuits. Furthermore, the study highlighted the advantages of SOI MOSFETs in
isolating the floating body, leading to enhanced stability and performance. This work laid the foundation
for adapting the STL mechanism in bulk-MOSFET oscillators, where similar principles are applied but
with electrical floating bodies instead of physical ones [5].

2.5 CMOS Voltage-Controlled Oscillators (VCOs) for High-Frequency Sys-

tems
Panigrahy et al. investigated strategies for improving the performance of CMOS voltage-controlled
oscillators (VCOs) in high-frequency communication systems [6]. Their work focused on reducing phase
noise and power consumption while maintaining high performance. The authors presented methods to
optimize VCO design for applications requiring stable oscillations, such as wireless communication and
signal processing. The study’s relevance extends to compact oscillator designs, where similar principles
can be applied to enhance stability and efficiency in single-transistor oscillators.

2.6 Tunable VO2 Relaxation Oscillators

Pattanayak et al. proposed a new class of relaxation oscillators based on VO2, a material known for its
phase-transition properties. Their study demonstrated how these oscillators could be tuned for specific
applications by adjusting external parameters. The compact design and high tunability of VO2-based
oscillators make them suitable for various analog applications, including neuromorphic hardware [7].

Figure 4: Tunable VO2 Relaxation Oscillator Circuit

This research highlighted the potential of material engineering to create innovative oscillatory devices,
paving the way for future advancements in compact oscillator technologies.

4
3 Methodology
3.1 Design
The design is a single n-channel MOSFET-based oscillator [1], which serves as the core element of
the proposed system. Unlike conventional oscillators that rely on external passive components such as
capacitors and inductors, this innovative approach capitalizes on the intrinsic properties of the MOSFET
to achieve oscillation. The design significantly simplifies the circuit by reducing component count, making
it compact and cost-effective while remaining compatible with standard CMOS fabrication processes.
The device is an n-channel MOSFET, fabricated on a bulk-silicon wafer. The gate length of the
MOSFET ranges between 180 nm and 300 nm, while the channel width varies from 220 nm to 500 nm.
For the experimental analysis in the study, a specific device with a gate length of 200 nm and a channel
width of 500 nm was utilized. The short gate length ensures operation in the deep submicron regime,
enhancing the device’s frequency response but also introducing challenges such as short-channel effects.
The wider channel width, on the other hand, improves current-handling capability and stability, which
are essential for sustaining oscillations [1].

(a) (b)

Figure 5: (a) Bulk n-MOSFET. (b) PDSOI MOSFET

The bulk-silicon wafer serves as the substrate for the MOSFET, providing both mechanical stability
and an electrically conductive base. Additionally, the bulk silicon plays a crucial role in the operation
of the oscillator by contributing to the parasitic capacitances and resistances intrinsic to the device.
These parasitic elements are central to the oscillatory mechanism, as they form the positive feedback
loop required for sustaining oscillations. By leveraging the physical characteristics of the MOSFET and
its layout, the design eliminates the need for external capacitive and inductive components.
The gate length and channel width significantly influence the performance of the MOSFET-based
oscillator. The short gate length of 200 nm enhances the carrier transit time, allowing the device to
operate at higher frequencies. However, it also introduces short-channel effects, such as increased leakage
currents and reduced threshold voltage. Meanwhile, the wide channel width of 500 nm increases the
current-driving capability of the device, ensuring better stability for oscillations. The reduced resistance
due to the wider channel balances the design, optimizing the device’s performance.
Another important aspect of the design is its compatibility with standard CMOS fabrication processes.
Since the oscillator relies solely on a single MOSFET without additional external components, it can be
easily integrated into existing CMOS-based systems. This compatibility makes the design particularly
attractive for applications requiring low-cost, compact solutions, such as IoT devices, RF communication
systems, and sensor nodes [1].

Key Design Features:

• Floating Body Effect (e-FB): Unlike SOI-MOSFETs, where a physical floating body exists, the
bulk-MOSFET creates an electrical floating body due to the built-in potential (qVbi) between the
moderately doped p-well and the underlying lightly doped p-type silicon wafer.

5
 • Single-Transistor Latch (STL): The device utilizes the STL mechanism, which results in abrupt
transitions between high resistance states (HRS) and low resistance states (LRS) when subjected
to an input current. The STL mechanism involves impact ionization, where high-energy carriers
generate electron-hole pairs, leading to the oscillatory behavior.

3.1.1 Device parameters

Device Parameters PDSOI MOSFET Bulk MOSFET

Channel/Gate Length 200nm 200nm
Width 500nm 500nm
Material SiO2 SiO2
Source/Drain Length/Width 50nm 50nm
Doping Concentration of Substrate 1e16cm−3 1e16cm−3
Doping Concentration of Source/Drain 1e18cm−3 1e18cm−3
Thickness Of Oxide Layer 10nm 10nm
Channel Thickness 50nm 150nm
BOX Thickness 100nm -
BOX Material SiO2 SiO2

Table 1: Device Parameters

3.2 Oscillation Mechanism

The oscillation mechanism involves how injected electrons and the resulting impact ionization influence
the current flow and potential distribution in a semiconductor device. Impact ionization occurs when high-
energy carriers (typically electrons) gain sufficient energy to knock additional charge carriers (electrons
and holes) out of the semiconductor lattice, creating an avalanche of carriers. This effect is significant
in many electronic devices, such as avalanche photodiodes, bipolar junc tion transistors, and devices
experiencing breakdown [1].

Figure 6: Oscillation mechanism of a single MOSFET Oscillator

1. Initial Condition: Vout < VLD

In this stage, the applied output voltage (Vout ) is less than a critical voltage (VLD ), which is the threshold
for significant carrier injection. Key characteristics include:

6
 • Voltage Profile: The potential barrier between the source (S) and drain (D) is high, defined by
the built-in potential qVbi,S at the source junction and qVbi,D at the drain junction.
• Current Flow: The current (Iin ) through the device is minimal because the potential barrier
limits the injection of electrons from the source into the drain region.
• Physical Effects: At this stage, there are no injected electrons with sufficient energy to cause
impact ionization, and the device operates in a stable low-current regime.

2. Intermediate Condition: VLD < Vout < VLU

As Vout increases beyond VLD , electrons begin to be injected from the source into the drain at higher
energy levels. This results in:
• Injected Electrons: A larger population of electrons crosses the potential barrier from the source
to the drain. These electrons are represented by the green arrows in the diagram.
• Impact Ionization Onset: Some of these high-energy electrons collide with atoms in the drain
region, causing impact ionization. This process generates additional electron-hole pairs, as shown
in the diagram by the red stars (ionization sites) and the newly created carriers.
• Current Flow: The injected electrons and the resulting carriers from ionization increase the total
current flow through the device.
• Voltage Profile: The potential difference across the device begins to decrease locally as the
ionization increases the number of charge carriers available to conduct current.

3. Critical Voltage Reached: Vout = VLU

When Vout reaches the critical voltage (VLU ), the device experiences a significant change in behavior:
• Maximal Impact Ionization: The rate of impact ionization peaks, as represented by more
pronounced red stars. The high-energy electrons injected from the source are efficiently creating
additional electron-hole pairs, which rapidly contribute to the current flow.
• Avalanche Effect: The multiplication of carriers due to impact ionization results in a near-
exponential increase in the current. This is sometimes referred to as avalanche breakdown if the
phenomenon continues unchecked.
• Voltage Profile Flattening: The increased carrier density reduces the local electric field and
flattens the voltage profile across the device.
• Current Dominance: The device transitions into a regime where the current is dominated by
impact ionization-generated carriers.

4. Post-Breakdown Behavior: Vout → VLD

In the final stage, the voltage across the device begins to drop as the avalanche of carriers leads to
additional effects:
• Out-Diffusion of Holes: The holes generated during impact ionization diffuse back toward the
source (represented by the blue arrows in the diagram). This contributes to charge redistribution
in the device.
• Maximal Electron Injection: Electrons continue to flow from the source to the drain, but the
dynamics are now influenced by the redistribution of holes and the reduction in the potential barrier.
• Stabilization: The system may stabilize or enter a regime of controlled operation if the device
design includes features to manage avalanche effects (e.g., resistive elements or other current-limiting
structures).
• Voltage Reduction: The output voltage (Vout ) decreases toward VLD as the current flow increases
and redistributes the potential.

7
4 Results
4.1 IdVg Curves for Bulk vs PDSOI n-type MOSFETs
4.1.1 IdVg Curve at Vd = 0.05 Volts

Figure 7: IdVg curve for Bulk vs PDSOI n-type MOSFET at Vd= 0.05 volts

The Id-Vg (Drain Current vs. Gate Voltage) curves compare the performance of Bulk and PDSOI
n-type MOSFETs at a constant drain voltage of 0.05 volts. The PDSOI MOSFET shows a significantly
higher drain current (Id) for the same gate voltage (Vg), indicating better conduction properties. Its
curve has a steeper slope in the subthreshold region, reflecting a lower subthreshold slope and improved
switching efficiency.The threshold voltage (Vth) of the PDSOI MOSFET is slightly lower, enabling it to
turn on at a lower gate voltage. Additionally, its rapid increase in current suggests reduced drain-induced
barrier lowering (DIBL) effects compared to the Bulk MOSFET.

Overall, the PDSOI MOSFET demonstrates better electrical performance, including higher current
drive, faster switching, and greater efficiency. These characteristics make it ideal for low-power, high-
performance applications, while the Bulk MOSFET remains a practical choice for cost-effective solutions.

4.1.2 IdVg Curve at Vd = 1 Volt

Figure 8: IdVg curve for Bulk vs PDSOI n-type MOSFET at Vd= 1 volts

8
 The Id-Vg curves for Bulk and PDSOI n-type MOSFETs at Vd = 1 V illustrate key differences in
their electrical performance. The PDSOI MOSFET demonstrates a significantly higher drain current
compared to the Bulk MOSFET for the same gate voltage, making it more efficient in conduction. Its
steep current rise indicates superior subthreshold characteristics and faster switching performance.

Additionally, the PDSOI MOSFET has a slightly lower threshold voltage, allowing it to operate at
reduced power levels. In contrast, the Bulk MOSFET exhibits a more gradual increase in current, sug-
gesting higher susceptibility to drain-induced barrier lowering (DIBL), which can degrade performance
at higher voltages. These attributes position the PDSOI MOSFET as ideal for high-performance and
energy-efficient applications, especially in modern low-power electronic systems. However, the Bulk MOS-
FET remains a practical option for cost-sensitive, large-scale applications where absolute performance is
not the primary requirement.

4.2 IdVd Curve for Bulk vs PDSOI n-type MOSFETs

4.2.1 IdVd Curve at Vg = 1 Volt

Figure 9: IdVd curve for Bulk vs PDSOI n-type MOSFET at Vg= 1 volts

The graph compares the Id-Vd characteristics of Bulk and PDSOI MOSFETs at a gate voltage (Vg)
of 1 volt. The Id-Vd curve shows the relationship between the drain current (Id) and the drain voltage
(Vd).The red curve represents the Bulk MOSFET, and the green curve represents the PDSOI MOSFET.
For the same Vd, the Bulk MOSFET demonstrates higher drain current (Id) compared to the PDSOI
MOSFET. This difference can be attributed to the structural variations between the two technologies.

Bulk MOSFETs, having a conductive body, allow higher current flow, but they suffer from higher
leakage and reduced performance in scaled nodes. On the other hand, PDSOI MOSFETs feature a
thin silicon layer and buried oxide, reducing leakage and parasitic effects, which results in lower current
levels. These characteristics highlight the trade-offs in choosing between the two technologies for different
applications based on power efficiency and performance.

9
4.3 CV Curve for Bulk vs PDSOI n-type MOSFETs
4.3.1 CV curve at Frequency = 1KHz

Figure 10: CV curve for Bulk vs PDSOI n-type MOSFET at F=1KHz

At 1 kHz, the CV curves for Bulk and PDSOI MOSFETs demonstrate noticeable differences in their
capacitance profiles. The Bulk MOSFET shows lower capacitance in the inversion region due to the
stronger influence of the body effect, which leads to a wider depletion region and higher parasitic capaci-
tance. On the other hand, the PDSOI MOSFET exhibits higher capacitance values across the operating
regions, benefiting from reduced junction capacitances and the absence of a substrate, which eliminates
the body effect. These characteristics make the PDSOI MOSFET more efficient at lower frequencies,
where capacitance control and stability are critical for proper device operation.

Additionally, the Bulk MOSFET curve shows a slower transition between regions, indicating less ef-
ficient charge control. The higher and more stable capacitance of the PDSOI MOSFET reinforces its
suitability for low-frequency applications, highlighting its advantages in minimizing parasitic effects and
improving overall device performance.

4.3.2 CV curve at Frequency = 1MHz

Figure 11: CV curve for Bulk vs PDSOI n-type MOSFET at F=1MHz

At 1 MHz, the CV curves for Bulk and PDSOI MOSFETs show consistent trends that align with
their structural differences. The Bulk MOSFET exhibits lower capacitance in the inversion region and

10
a wider depletion region due to the body effect and substrate-related parasitics. Conversely, the PDSOI
MOSFET maintains a higher and more stable capacitance profile, attributed to the reduced parasitic
junction capacitances enabled by the SOI structure. The sharper transition observed in the PDSOI
MOSFET curve reflects its superior charge control and reduced impact of parasitics at this frequency.

The Bulk MOSFET’s curve also indicates slightly more susceptibility to frequency-dependent varia-
tions, which can hinder its performance in medium-frequency applications. Overall, the PDSOI MOSFET
outperforms the Bulk MOSFET at 1 MHz by providing better capacitance control, reduced body effect,
and improved transition characteristics, making it a more efficient choice for applications requiring stable
operation at intermediate frequencies.

4.3.3 CV curve at Frequency = 1GHz

Figure 12: CV curve for Bulk vs PDSOI n-type MOSFET at F=1GHz

At 1 GHz, the CV curve comparison between Bulk and PDSOI MOSFETs highlights their performance
differences at high frequencies. The PDSOI MOSFET exhibits a slightly higher capacitance in the
inversion region due to its reduced parasitic capacitances and the elimination of the body effect, leading to
improved charge control. Bulk MOSFETs show a wider depletion region and lower capacitance because of
the presence of the body effect and the substrate junction. This indicates that Bulk MOSFETs experience
more significant parasitic capacitances, which degrade performance at higher frequencies.

The sharper transition in the PDSOI MOSFET curve demonstrates its superior frequency response,
making it more suitable for high-speed applications. Furthermore, the reduced parasitic effects in PDSOI
MOSFETs enable better control of the capacitance across the operating regions. Overall, the CV curve
at 1 GHz emphasizes the enhanced performance of PDSOI MOSFETs over Bulk MOSFETs in high-
frequency scenarios.

11
4.4 Comparison

Device Type Components Complexity Active Area (µm2 ) Power Consumption (µW)
Ferroelectric FET 1FeFET + 1T (+/C) Low 7853.98 3.6
CMOS Circuit > 12T + 2C High 15000 219.8
CMOS Circuit > 10T + 17R + 1C High - < 1050
SOI-MOSFET 1T (+/C) Low 0.25 < 0.024
VO2 Memristor 1T + 1R + 1C Low 3000 -
Bulk-MOSFET 1T (+/C) Low 0.1 < 35.5
* (+/C) is optional.

Table 2: Device Characteristics Comparison

This document presents a comparative analysis of various device types based on their components,
complexity, active area, and power consumption, highlighting the advancements made in the proposed
Bulk-MOSFET device. The device types include Ferroelectric FET, CMOS circuits, SOI-MOSFET, VO2
Memristor, and Bulk-MOSFET, with a focus on their architectural and operational efficiency.

Components
The components column outlines the structural complexity of each device. Ferroelectric FET consists of
1FeFET and 1T, with an optional capacitor (+1C). CMOS circuits have significantly higher component
counts, with configurations like >12 transistors (T) and 2 capacitors (C) or >10T, 17 resistors (R), and
1C. In contrast, SOI-MOSFET and Bulk-MOSFET feature much simpler architectures, each using 1T
and an optional capacitor (+1C). The VO2 Memristor includes a 1T, 1R, and 1C configuration, providing
moderate complexity.

Complexity
The complexity levels are categorized as either low or high. Devices with simpler components, such as
SOI-MOSFET and Bulk-MOSFET, are classified as having low complexity. On the other hand, CMOS
circuits are marked as high complexity due to their intricate architectures, involving numerous transistors,
resistors, and capacitors.

Active Area
The active area column compares the physical footprint of each device on a chip. Ferroelectric FET
and CMOS circuits have large active areas, measuring 7853.98 µm2 and up to 15,000 µm2 , respectively.
VO2 Memristor requires 3000 µm2 , while SOI-MOSFET is significantly smaller, at just 0.25 µm2 . The
Bulk-MOSFET demonstrates the most compact design, with an active area of only 0.1 µm2 , making it
ideal for applications requiring minimal chip space.

Power Consumption
In terms of power consumption, the devices vary widely. Ferroelectric FET consumes 3.6 µW, and CMOS
circuits require substantial power, with one consuming 219.8 µW and another consuming up to 1050 µW.
SOI-MOSFET stands out for its exceptional energy efficiency, consuming less than 0.024 µW. The Bulk-
MOSFET offers a favorable balance, consuming less than 35.5 µW, while VO2 Memristor lacks specific
data in this table.

12
5 Conclusion
This paper introduces a novel oscillator design that utilizes a single n channel MOSFET fabricated
on a bulk silicon wafer, showcasing an innovative approach to simplifying oscillator circuits. Traditional
oscillators often rely on external passive components such as capacitors, resistors, and inductors to achieve
oscillation. However, this study demonstrates that by carefully leveraging the intrinsic properties of the
MOSFET, such as parasitic capacitances, resistances, and feedback mechanisms, stable oscillations can
be generated without the need for additional components. This groundbreaking design not only reduces
the overall circuit complexity but also aligns with modern trends toward compact, low cost, and highly
integrated solutions.
The n channel MOSFET used in the experiments was fabricated with a gate length of 200 nm and a
channel width of 500 nm, parameters carefully selected to ensure optimal performance. The short gate
length allows the device to operate in the deep submicron regime, enabling high speed operation, while the
wider channel width enhances the current driving capability and stabilizes the oscillatory behavior. These
design choices highlight the intricate balance required to achieve both high frequency and operational
stability. Additionally, the bulk silicon wafer serves as an effective substrate that contributes to the
oscillatory mechanism by providing essential parasitic elements and ensuring robust performance under
standard fabrication conditions.
The study also emphasizes the scalability and compatibility of the proposed oscillator with standard
CMOS fabrication processes. By eliminating external components, the design reduces manufacturing
complexity and cost, making it a practical solution for integration into existing systems. This charac-
teristic makes the oscillator particularly appealing for applications in resource constrained environments
such as IoT devices, wireless sensor networks, and compact RF communication systems. Furthermore,
the innovative use of device physics, specifically the interplay of intrinsic capacitances and resistances
within the MOSFET, demonstrates the potential to rethink traditional circuit design paradigms.
This research marks a significant step forward in simplifying oscillator design without sacrificing
performance. The findings provide a solid foundation for future explorations into single device circuits and
their applications. While the current design achieves notable success, it also opens up new challenges and
opportunities for further improvement. Areas such as frequency optimization, noise minimization, and
integration into larger systems can be further explored to extend the utility of this innovative oscillator.

13
References
[1] S. Ramasubramanian, J. Gopalakrishnan, and S. Ramasubbu, “A single mosfet-based oscillator on a
bulk-silicon wafer,” IEEE Transactions on Electron Devices, vol. 69, no. 5, pp. 2484–2491, May 2022.
[2] Z. Wang and A. I. Khan, “Ferroelectric relaxation oscillators and spiking neurons,” IEEE J. Explor.
Solid-State Comput. Devices Circuits, vol. 5, pp. 151–157, 2019.
[3] H. P. Zappe, R. K. Gupta, I. Sakai, and C. Hu, “Operation of cmos devices with a floating well,”
IEEE Trans. Electron Devices, vol. ED-34, no. 2, pp. 335–343, Feb. 1987.
[4] M. Mohsen, L. A. Said, A. S. Elwakil, A. H. Madian, and A. G. Radwan, “Extracting optimized
bio-impedance model parameters using different topologies of oscillators,” IEEE Sensors J., vol. 20,
no. 17, pp. 9947–9954, Sep. 2020.
[5] C.-D. Chen, M. Matloubian, R. Sundaresan, B.-Y. Mao, C. C. Wei, and G. P. Pollack, “Single-
transistor latch in soi mosfets,” IEEE Electron Device Lett., vol. 9, no. 12, pp. 636–638, Dec. 1988.
[6] A. Panigrahy, A. Patnaik, and R. K. Patjoshi, “Performance evaluation of cmos voltage-controlled
oscillator for high-frequency communication system,” in Pattern Recognition and Data Analysis With
Applications. Springer, Singapore, 2022, pp. 729–742.

[7] M. Pattanayak, M. N. F. Hoque, Y. Zhao, Z. Fan, and A. A. Bernussi, “Tunable vo2 relaxation
oscillators for analog applications,” Semicond. Sci. Technol., vol. 34, no. 10, Sep. 2019.

14