Design of a Multicore Processor with RISC-Based ISA

Using Verilog HDL

N. JAGAN MOHAN REDDY Dr. A. VANI

Department of ECE Department of ECE
Chaitanya Bharathi Institute of, Chaitanya Bharathi Institute of
Technology, Hyderabad, India Technology, Hyderabad, India
Jaganmohanreddyece@cbit.ac.in avaniece@cbit.in

AASIM SHAIK NISHATH BEGUM

Department of ECE Chaitanya Department of ECE Chaitanya
Bharathi Institute of Technology, Bharathi Institute of Technology,
Hyderabad, India Hyderabad, India
nshthshaik@gmail.com

ABSTRACT— Development of a multicore processor with microarchitecture of MIPS ISA on FPGA, emphasizing its
a RISC-based Instruction Set Architecture in Verilog is a compliance with RISC principles, which make it easier to
multifaceted task that encompasses a number of phases. This implement and understand for students. Their research
project deals with the design and implementation of a included six basic MIPS instructions implemented with
multicore processor with a RISC based ISA. The processor is Verilog HDL. Likewise, [4] aimed at designing and
designed using Verilog Hardware Description Language simulating a high-performance 32-bit MIPS processor with
(HDL), and its architecture is tailored to support efficient a five-stage pipeline, implemented in Verilog with the
parallel processing, scalability, and high performance. The
ModelSim simulator and Xilinx RTL logic tools.
multicore processor design includes multiple RISC cores
interconnected through a shared bus or Network-on-Chip In [5], VHDL was used to design and implement a 16-
(NoC) architecture. Each core is a fully functional RISC bit RISC processor that can run 16 instructions of various
processor with a simplified instruction set that allows for instruction classes, such as arithmetic, logical, conditional
faster execution and reduced complexity in hardware design. and unconditional jumps, and memory interface
The primary objective of this paper is to achieve a four-core operations. The authors compared the power efficiency and
processor design. Each core is parallel and pipelined, programmability of 8-bit and 16-bit processors. Their work
following multicycle and stages also implementing 3-Levels
was based on Xilinx ISE 14.5 and targeted the Spartan 6
of cache, Level-1 per-core, Level-2 Shared memory for one
or more cores, Level 3-Shared among all cores (which avoids
FPGA, and the simulations were performed using the ISIM
Cache coherency problem). The performance of the simulator. Additional improvements were achieved in [6],
processor is measured using criteria like execution speed, where the dual-core and quad-core pipelined RISC
power dissipation, and area consumption. processor was designed with Verilog and targeted a Virtex-
6 FPGA. These multi-core systems provided less power
Keywords—Multicore, Risc-V, Pipeline, Cache Coherency. usage and more performance. The Harvard memory
architecture was adopted by the authors, providing
independent logical and physical access to the data and
I. INTRODUCTION instruction memories. The pipelined design enhanced
Parallel systems provide direct access to instant execution speed for the 23-instruction set the processor.
improvement in processing power and efficiency of energy
[1]. RISC microprocessor design employs a highly
optimized instruction set. RISC processors make use of
many registers and follow a load-store instruction set,
where instructions access memory only by explicit load
and store operations. Microprocessor without Interlocked
Pipeline Stage (MIPS) is a RISC instruction set
architecture (ISA) designed by MIPS Technologies. There
are different versions of the MIPS instruction set, such as
MIPS-32 and MIPS-64 [2]. The latest version of MIPS-32
is used for 32-bit machines.
The design of the MIPS processor has five major FIG 1
stages: Instruction Fetch (IF), Instruction Decode (ID), Moreover, [7] presented a soft-core five-stage pipeline
Execution (EXE), Memory (MEM), and Write Back (WB). processor with a programmable instruction set, enabling
It includes a 32-bit data bus, a 32-bit × 1024 memory dynamic adjustment according to FPGA capabilities. This
organization, and a 32-bit internal addressable register set. method improves efficiency via pipeline processing, which
The characteristics of data in applications like image, is becoming more important in processor and System-on-
audio, and video processing offer scopes for high Chip (SoC) design. The system was developed with Xilinx
parallelism in computation. Researchers in [3] analyzed the

XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE

ISE 14.1, Verilog HDL, and the Xilinx Spartan 6 C- Load Capacitance
XC6SLX9-3CSG324 FPGA. The paper in [8] suggested a
V- Supply Voltage
32-bit pipelined MIPS processor with a five-stage pipeline,
a 32-bit register file, and a 32-bit Arithmetic Logic Unit f- Clock Frequency
(ALU). The outcomes revealed that the pipelined MIPS
processor had three times less power consumption than its Thus, if we increase the clock frequency, the power
non-pipelined equivalent. The design was implemented by increases thereby leading to overheating. Thus, the concept
utilizing Xilinx ISE software, Verilog HDL, and a Spartan of multicore technology is to utilize multiple cores rather
3E XC3S500E FPGA. than a single (such as single processor) at a relatively
lower frequency, but a total enhancement in the
ISA is the common lexicon by which hardware and performance is provided through multiple cores
software can exchange information [9]. In the last two functioning simultaneously on multiple instructions.
decades, two powerful firms, ARM and Intel, have Multicore processors process multiple instructions and
controlled ISA, and consequentially,their microprocessors multiple data. Multiple cores process multiple threads
are now implemented in all devices of computing ranging (multiple processes/instructions) while utilizing various
from smallest to the speediest. However, following the aspects of memory (various data). This strengthens TLP.
recent emergence of the RISC-V ISA [10], everything is The primary memory is used by every core. Every core is
evolving, and the microprocessor business is flipping over linked with its own cache, and they all use the system bus.
[11]. RISC-V is an open and free instruction set with good [18] The efficiency of a multicore processor heavily relies
modularity design, offering an extremely high degree of on the algorithm or application design that is regulated by
flexibility for a very low expense and enabling users to Amdahl's Law. Geva Amdahl, a computer architect,
generate custom chips optimized for particular uses. While provided this law. This law is applied to calculate the
Linux became more popular and renowned in the operating theoretical maximum rate with multiple processors in
systems, RISC-V strives to become Linux in the parallel computing. According to this law, the rate of a
processors [12], and is now being employed in different process in parallel computing is bounded by the time
commercial products one by one. required for the sequential portion of the process. For
instance, if a process takes X hours to finish on one core,
and a fraction of the process that takes Y hours to run
II. LITERATURE REVIEW which cannot be parallelized, while the remaining (X-Y)
hours can be parallelized, then no matter how many
Research in multi-core RISC-V processor design is
processors, the shortest time taken for the execution cannot
directed towards effective use of resources and power
be less than (X-Y) hours.[19]
reduction [13], [14]. Work is done on cache coherence
protocols, interconnect structure, and task scheduling
algorithms, with others suggesting asymmetric multi-core
III. PIPELINE MIPS PROCESSOR DESIGN
processors with cores of different capabilities and power
usage. Scheduling Algorithms for Multi-Core RISC-V For the MIPS processor using a pipeline system of five
Processors: Optimal scheduling algorithms play a stages, instructions are processed through five steps with
significant role in performance and power optimization. each phase utilizing a uniform period of time. The outlined
Earlier research has proposed static, dynamic, and hybrid interval typically represents a clock cycle of the processor
scheduling strategies. The study has also investigated [20]. All the instructions follow one pipe stage after the
RISC-V microarchitecture, instruction set architecture, and other sequence, although instruction does nothing in
multi-core scheduling techniques [15]. The multicore certain stages. Stages of the developed MIPS processor are
processor consists of two or more cores or as follows: Instruction Fetch (IF), Instruction Decode (ID),
computational/processing units that run in parallel to read Instruction Execution (IE), Memory Stage, Write Back
and execute instructions. These several processing units or (WB) Stage [21]. Three components are there in MIPS
cores are built on a single die. So, it is also referred to as a pipeline processor: 32-bit data path on pipeline, control
Chip Multiprocessor (CMP). The most important aspect of unit, and hazard detection unit.
multicore processor is that it provides the same
performance of a single faster processor at lower power IV.DATA PATH 32-BIT MIPS PIPELINE
dissipation and at a lower clock speed by executing more
tasks or instructions simultaneously. [16] This improves
the ILP (Instructions Level Parallelism). The performance Data path refers to the integration of different
of a processor is a function of three key factors, which functional units like Arithmetic Logic Unit (ALU),
includes IPC (instructions per cycle), CPI (clock cycles per multiplier, registers, and buses, which execute processing
instruction) and clock cycle (or clock frequency). The IPC operations. These operations are managed by the control
can be improved by improving ILP and TLP (thread level unit. The data path of MIPS is separated into five stages to
parallelism). Pipelining techniques can be used to improve make development and implementation simpler [22].
the CPI. But there is a constraint to improving the clock Figure 1 shows the phases utilized in the proposed
frequency. [17] processor. Every stage in the proposed MIPS processor is
designed for a particular purpose, and all the purposes are
The dynamic power dissipation is represented by described in detail in the following subsections.
P = QCV2
Q- Number of Transistors
 computer architecture teaching and comprehension [24].
The design principles of the MIPS system have been
utilized in explaining the pipeline and avoiding
interlocking states. Typically, the pipeline segments the
work of executing instructions into various steps such that
the processor is able to initiate work on the "first step"
instructions even before others are finished.
The MIPS processor's architecture does not include a
series of advanced instructions in order to keep its
processes simple [25]. The fundamental MIPS pipeline is
depicted in Figure 1 [26]. The development of this
microprocessor was mostly motivated by greater demands.
A number of design approaches were utilized to cater to
different forms of parallel programs. Computer
engineering has experienced dramatic technological
developments in recent years, which have immensely
impacted the field, especially in the propagation of Single
The flow of a MIPS processor follows a structured Instruction Multi-Data (SIMD) architectures for
sequence of steps to execute instructions efficiently. It pedagogical reasons [27]. To enhance performance and
begins with Instruction Fetch (IF), where the processor lower power consumption, these architectures were
retrieves the next instruction from memory using the combined onto a single chip by replicating four pipelined
program counter (PC) and increments the PC to point to core processors, developing a SIMD configuration that
the next instruction. Next, during Instruction Decode (ID), doubles the overall processing speed by performing
the instruction is broken into its components (opcode, multiple data in parallel [28].
source registers, destination register, etc.), and the register A multicore processor is an Integrated Circuit (IC) that
file is accessed to read necessary data. The Execution (EX) has two or more separate processing units, or cores, on one
stage follows, where the Arithmetic Logic Unit (ALU) chip. Multicore chips have seen extensive use in consumer
performs operations such as addition, subtraction, and and industrial markets, starting with special-purpose, niche
logical comparisons, and computes effective addresses for uses like high-end graphics and network devices.
memory instructions. If the instruction involves memory, it Multicore processors have recently entered the general-
proceeds to Memory Access (MEM), where data is either purpose market as well [29]. A common block diagram of
read from or written to memory for load (LW) and store a multicore system for this project is provided in Figure 2.
(SW) instructions. Finally, in Write-Back (WB), the result
from the ALU or memory is written back to the destination Benefits of multi-core systems are minimizing the
register, completing the instruction cycle. execution time, scalability of the data size and processor
performance, cost saving, and concurrency. Nowadays,
To optimize performance, MIPS uses pipelining, most desktop and high-performance computer processors
allowing multiple instructions to be processed are adopting the multicore architecture in their designs.
simultaneously in different stages, improving throughput. Therefore,Multi-core processors are gaining more
However, this can lead to hazards—data hazards (when popularity in various applications [30].
one instruction depends on the result of another), control
hazards (caused by branch instructions), and structural
VI.RESEARCH OBJECTIVES AND SIGNIFICANCE
hazards (when hardware resources are insufficient). These
hazards are handled using techniques such as forwarding, OF THE STUDY
stalling, and branch prediction. Branch prediction attempts
to guess the outcome of a branch instruction (taken or not
The main objective of the paper entitled ” , is to develop a
taken) to minimize delays. If the prediction is incorrect, the
multi-core RISC-V processor usingHardware Description
processor flushes the pipeline and fetches the correct
instructions, ensuring smooth execution Language (HDL) programming and sequential circuitry.
The specific objectives of the study include the following:
Cache Coherency: Though less of a concern in single-
V .OVERVIEW OF PIPELINE AND MULTICORE core processors, ensure the cache is efficient and
MIPS PROCESSOR minimizes latency for faster data access.
Level 1-May be per-core or shared among a few core.
A Microprocessor without Interlocked Pipelined
Stages (MIPS) is an example of RISC architecture Level 2- Shared memory for one or more cores .
produced by computer systems. RISC is a core architecture
Level 3-Shared among all cores .
that became very popular over the last decade [23]. MIPS
has gained notable acclaim in computing history for Power/Area Trade-Offs: Balance the processor's power
various reasons. To begin with, it is an innovative consumption with its physical size to ensure energy
processor since it is one of the pioneers in its line. efficiency and optimal use of space.
Secondly, it was designed within an educational institution
as opposed to a giant industrial company like Intel or
Motorola. Finally, MIPS has left a lasting effect on
Basic Core Communication: Optimize inter-process
communication within the single core, ensuring smooth IX.ADVANTAGES OF MULTI-CORE
data flow and effective multitasking. PROCESSORS
Multi-core processors have several advantages over
single-core designs. One of the main advantages is
VII. OVERVIEW OF MULTI-CORE RISC-V increased performance since different cores are able to
PROCESSOR USING HDL AND SEQUENTIAL carry out tasks at the same time, resulting in higher
CIRCUITRY processing speeds. This multi-tasking capability is
The Introduction section presents the research goals, especially useful for multi-threaded programs, allowing for
purpose of the study, and the paper's organization. The better distribution of workload. Multi-core processors also
Background and Related Work section gives a concise increase energy efficiency since the workload is shared
description of RISC-V processors, HDL programming, among different cores, with the result being less power per
and sequential circuitry while discussing related work on core compared to high-frequency single-core processors.
They also improve system dependability since activities
multi-core RISC-V processor design and
can be allocated to separate cores, eliminating system
implementation[31].
bottlenecks and lessening the potential for failure.
The Processor Architecture Design discusses the Additionally, multi-core architectures provide improved
processor architecture design of the multi-core RISC-V multitasking capabilities, with users being able to execute
processor, including its parts, functions, and the numerous applications smoothly without appreciable
employment of HDL programming. The Sequential degradation in performance. All these benefits render
Circuitry Design addresses the sequential circuitry multi-core processors a crucial part of current computing,
development, which includes pipelining, data forwarding, ranging from common consumer equipment to high-
and cache memory. performance computing devices.

The Performance Evaluation section evaluates the

performance of the processor through benchmark tests and X.CHALLENGES OF MULTI-CORE PROCESSORS
compares it with current state-of-the-art multi-core
processors. The Conclusion section finally summarizes Though multi-core processors bring tremendous
the findings, conclusions, and future recommendations on performance and efficiency advantages, they do come with
several challenges. One such key problem is parallel
multi-core RISC-V processor development via HDL
programming complexity, whereby the software has to be
programming and sequential circuitry.
tuned in order to leverage multiple cores, necessitating
complex techniques like thread synchronization and
workload distribution. Furthermore, cache coherence
VIII. RISC-V PROCESSOR DESIGN becomes an issue in multi-core environments, whereby
multiple cores access and modify common data and
inconsistencies arise, necessitating sophisticated coherence
protocols like MESI. Another key challenge is power
Implementing a 64-bit RISC-V processor with Verilog consumption and heat dissipation, since adding more cores
requires a number of important elements, such as creates more heat, requiring effective cooling mechanisms.
pipelining and parallelmulti-core design. First, a RISC-V Inter-core communication latency also affects
processor is a processor architecture that follows the RISC performance, since data transfer between cores can cause
(Reduced Instruction SetComputing) philosophy. That is, delays if not handled effectively through high-speed
it employs a limited set ofsimple instructions to execute interconnects. In addition, scalability constraints occur
operations, instead of many complex instructions. This when increasing the number of cores, since decreasing
results in simpler, more efficient processors that are easier returns in performance may result from memory
to design and implement [32].RISC-V processor design bandwidth and interconnect architecture bottlenecks.
Solving these issues is essential for maximizing multi-core
emphasizes building an open-source, flexible, and scalable
processor performance in contemporary computing
design for a variety of applications, ranging from
systems.
embedded systems to high-performance computing. The
modular ISA enables performance- and power-related
customization. RISC-V processor design with multiple
cores encompasses central features such as cache XI.CACHE COHERENCE PROBLEM IN RISC-V
coherence protocol, interconnect architecture, and MULTI-CORE PROCESSORS
effective task scheduling to maximize performance and
resource efficiency. Researchers have also investigated
new architectures, such as asymmetric multi-core In multi-core RISC-V processors, every core usually
processors, in which different cores possess different has a private cache to enhance performance by minimizing
capabilities and power usage. Furthermore, the memory access latency. But when several cores read and
optimization of scheduling algorithms, e.g., static, write the same memory location, inconsistencies can
occur, resulting in a cache coherence issue. This happens
dynamic, and hybrid, is important to enhance efficiency
when one core writes to a memory location while other
and decrease power usage in multi-core RISC-V systems.
cores retain stale copies of that data in their caches, bus or Network-on-Chip (NoC), the processor ensures
resulting in erroneous computations and system crashes. high-performance execution with lower complexity. The
To mitigate this, RISC-V cores utilize cache coherence pipelined architecture, with fetch, decode, execute,
protocols like MESI (Modified, Exclusive, Shared, memory access, and write-back phases, increases
Invalid) or MOESI (Modified, Owner, Exclusive, Shared, instruction throughput, while the three-level cache
Invalid). These protocols maintain data consistency in all hierarchy improves memory access and avoids cache
the cores by synchronizing read and write operations, coherency problems. Performance analysis in terms of
invalidating outdated data, and propagating updates in an execution speed, power consumption, and area utilization
efficient manner. Directory-based coherence and snooping- confirms the merits of this design. This project brings the
based methods are also typically used to monitor shared importance of RISC architecture into focus for use in
memory states and provide synchronization among caches. multicore processor and introduces insightful knowledge
The software-based schemes are methods of caching and concerning design trade-offs, scalability, and optimization
ensuring data coherency in software through examination trends for processor design in the future.
of shared data [33]–[35]. These schemes primarily address
ACKNOWLEDGMENT
the cache coherence problem by enhancing the compiler,
and occasionally by demanding special hardware assist. The authors thank the management of CBIT for their
Regrettably, however, a compiler that fully addresses the invaluable financial support and resources at college
cache coherence problem has not yet been released on the throughout this research.
market [39].
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