UNIT-III

8086 Interfacing:

1. Semiconductor memories interfacing (RAM, ROM).

2. Intel 8255 programmable peripheral interface.
3. Interfacing switches and LED.
4. Interfacing seven segment displays.
5. Software and hardware interrupt applications.
6. Intel 8251 USART architecture and interfacing.
7. Intel 8237a DMA controller.
8. Stepper motor.
9. A/D and D/A converters.
10. Need for 8259 programmable interrupt controllers.
Semiconductor memories interfacing (RAM, ROM)

Definition:- Semiconductor memory is the main memory element of a microcomputer-based

system and is used to store program and data. The main memory elements are nothing but
semiconductor devices that stores code and information permanently. The semiconductor
memory is directly accessible by the microprocessor. And the access time of the data present
in the primary memory must be compatible with the operating time of the microprocessor.

Types of semiconductor memory

Electronic semiconductor memory technology can be split into two main types or categories,
according to the way in which the memory operates :

1. RAM - Random Access Memory

2. ROM - Read Only Memory

(i) Random Access Memory (RAM)

As the names suggest, the RAM or random access memory is a form of semiconductor
memory technology that is used for reading and writing data in any order - in other words as
it is required by the processor. It is used for such applications as the computer or processor
memory where variables and other storage are required on a random basis. Data is stored and
read many times to and from this type of memory.

Random access memory is used in huge quantities in computer applications as current day
computing and processing technology requires large amounts of memory to enable them to
handle the memory hungry applications used today. Many types of RAM including SDRAM
with its DDR3, DDR4, and soon DDR5 variants are used in huge quantities.
DRAM

Dynamic RAM is a form of random access memory. DRAM uses a capacitor to store each bit
of data, and the level of charge on each capacitor determines whether that bit is a logical 1 or
0. However these capacitors do not hold their charge indefinitely, and therefore the data
needs to be refreshed periodically. As a result of this dynamic refreshing it gains its name of
being a dynamic RAM.

DRAM is the form of semiconductor memory that is often used in equipment including
personal computers and workstations where it forms the main RAM for the computer. The
semiconductor devices are normally available as integrated circuits for use in PCB assembly
in the form of surface mount devices or less frequently now as leaded components.

Disadvantages of DRAM

1. Complex manufacturing process

2. Data requires refreshing
3. More complex external circuitry required (read and refresh periodically)
4. Volatile memory
5. Relatively slow operational speed
6. Need to refresh the capacitor charge every once in two milliseconds.

SRAM

SRAM is stands for Static Random Access Memory. This form of semiconductor memory
gains its name from the fact that, unlike DRAM, the data does not need to be refreshed
dynamically. These semiconductor devices are able to support faster read and write times
than DRAM (typically 10 ns against 60 ns for DRAM), and in addition its cycle time is much
shorter because it does not need to pause between accesses.

However they consume more power, they are less dense and more expensive than DRAM. As
a result of this SRAM is normally used for caches, while DRAM is used as the main
semiconductor memory technology.

SDRAM

Synchronous DRAM. This form of semiconductor memory can run at faster speeds than
conventional DRAM. It is synchronized to the clock of the processor and is capable of
keeping two sets of memory addresses open simultaneously. By transferring data alternately
from one set of addresses, and then the other, SDRAM cuts down on the delays associated
with non-synchronous RAM, which must close one address bank before opening the next.

Within the SDRAM family there are several types of memory technologies that are seen.
These are referred to by the letters DDR - Double Data Rate. DDR4 is currently the latest
technology, but this is soon to be followed by DDR5 which will offer some significant
improvements in performance.

MRAM

This is Magneto-resistive RAM, or Magnetic RAM. It is a non-volatile RAM memory

technology that uses magnetic charges to store data instead of electric charges. Unlike
technologies including DRAM, which require a constant flow of electricity to maintain the
integrity of the data, MRAM retains data even when the power is removed.

An additional advantage is that it only requires low power for active operation. As a result
this technology could become a major player in the electronics industry now that production
processes have been developed to enable it to be produced.

(ii) Read Only Memory (ROM)

A ROM is a form of semiconductor memory technology used where the data is written once
and then not changed. In view of this it is used where data needs to be stored permanently,
even when the power is removed - many memory technologies lose the data once the power
is removed. As a result, this type of semiconductor memory technology is widely used for
storing programs and data that must survive when a computer or processor is powered down.

For example, the BIOS of a computer will be stored in ROM. As the name implies, data
cannot be easily written to ROM. Depending on the technology used in the ROM, writing the
data into the ROM initially may require special hardware. Although it is often possible to
change the data, this gain requires special hardware to erase the data ready for new data to be
written in.

PROM

This stands for Programmable Read Only Memory. It is a semiconductor memory which can
only have data written to it once, the data written to it is permanent. These memories are
bought in a blank format and they are programmed using a special PROM programmer.
Typically a PROM will consist of an array of fuseable links some of which are "blown"
during the programming process to provide the required data pattern.

The PROM stores its data as a charge on a capacitor. There is a charge storage capacitor for
each cell and this can be read repeatedly as required. However it is found that after many
years the charge may leak away and the data may be lost. Nevertheless, this type of
semiconductor memory used to be widely used in applications where a form of ROM was
required, but where the data needed to be changed periodically, as in a development
environment, or where quantities were low.
EPROM

This is an Erasable Programmable Read Only Memory. This form of semiconductor

memory can be programmed and then erased at a later time. This is normally achieved by
exposing the silicon to ultraviolet light. To enable this to happen there is a circular window in
the package of the EPROM to enable the light to reach the silicon of the chip. When the
PROM is in use, this window is normally covered by a label, especially when the data may
need to be preserved for an extended period.

EEPROM

This is an Electrically Erasable Programmable Read Only Memory. Data can be written to
it and it can be erased using an electrical voltage. This is typically applied to an erase pin on
the chip. Like other types of PROM, EEPROM retains the contents of the memory even when
the power is turned off. Also like other types of ROM, EEPROM is not as fast as RAM.
EEPROM memory cells are made from floating-gate MOSFETS (known as FGMOS).

Flash memory

Flash memory may be considered as a development of EEPROM technology. Data can be

written to it and it can be erased, although only in blocks, but data can be read on an
individual cell basis. To erase and re-program areas of the chip, programming voltages at
levels that are available within electronic equipment are used. It is also non-volatile, and this
makes it particularly useful. As a result Flash memory is widely used in many applications
including memory cards for digital cameras, mobile phones, computer memory sticks and
many other applications.

Flash memory stores data in an array of memory cells. The memory cells are made from
floating-gate MOSFETS (known as FGMOS). These FG MOSFETs (or FGMOS in short)
have the ability to store an electrical charge for extended periods of time (2 to 10 years) even
without a connecting to a power supply.

Disadvantages of Flash Memory

1. Higher cost per bit than hard drives

2. Slower than other forms of memory
3. Limited number of write / erase cycles
4. Data must be erased before new data can be written
5. Data typically erased and written in blocks

PCM

This type of semiconductor memory is known as Phase change Random Access Memory, P-
RAM or just Phase Change memory, PCM. It is based around a phenomenon where a form of
chalcogenide glass changes is state or phase between an amorphous state (high resistance)
and a polycrystalline state (low resistance). It is possible to detect the state of an individual
cell and hence use this for data storage. Currently this type of memory has not been widely
commercialized, but it is expected to be a competitor for flash memory.

Programmable peripheral interface 8255

PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with
its outside world such as ADC, DAC, keyboard etc. We can program it according to the
given condition. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can
assign different ports as input or output functions.
Block diagram –

It consists of 40 pins and operates in +5V regulated power supply. Port C is further divided
into two 4-bit ports i.e. port C lower and port C upper and port C can work in either BSR
(bit set rest) mode or in mode 0 of input-output mode of 8255. Port B can work in either
mode 0 or in mode 1 of input-output mode. Port A can work either in mode 0, mode 1 or
mode 2 of input-output mode.
It has two control groups, control group A and control group B. Control group A consist of
port A and port C upper. Control group B consists of port C lower and port B.
 Depending upon the value if CS’, A1 and A0 we can select different ports in different
modes as input-output function or BSR. This is done by writing a suitable word in control
register (control word D0-D7).
CS’ A1 A0 Selection Address

0 0 0 PORT A 80 H

0 0 1 PORT B 81 H

0 1 0 PORT C 82 H

0 1 1 Control Register 83 H

1 X X No Seletion X
Pin diagram –

 PA0 – PA7 – Pins of port A

 PB0 – PB7 – Pins of port B
 PC0 – PC7 – Pins of port C
 D0 – D7 – Data pins for the transfer of data
 RESET – Reset input
 RD’ – Read input
 WR’ – Write input
 CS’ – Chip select
 A1 and A0 – Address pins
Operating modes –
1. Bit set reset (BSR) mode –
If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits
are used for set or reset.

2. Input-Output mode –
If MSB of control word (D7) is 1, PPI works in input-output mode. This is further
divided into three modes:

 Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input
function or simple output function. In this mode there is no interrupt handling capacity.
 Mode 1 – Handshake I/O mode or strobed I/O mode. In this mode either port A or port
B can work as simple input port or simple output port, and port C bits are used for
handshake signals before actual data transmission. It has interrupt handling capacity
and input and output are latched.
Example: A CPU wants to transfer data to a printer. In this case since speed of
processor is very fast as compared to relatively slow printer, so before actual data
transfer it will send handshake signals to the printer for synchronization of the speed of
the CPU and the peripherals.
  Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B
can work either in mode 0 or mode 1. 6 bits port C are used as handshake signals. It
also has interrupt handling capacity.

Interfacing switches and LED

LIGHT EMITTING DIODE (LED)

Led comes in various colour, its colour depends on its semiconductor material. Led have two
leads one is the cathode and another one is the anode.We can easily identify the cathode and
anode to see the length of leads, the length of cathode leads is lesser than the length of anode
but sometimes they come in equal size.

When the length of both leads cathode and anode are equal in the size that time we can
identify the anode and cathode to see their filament, the cathode has broader filament than the
anode.
Connection of Led

It is important to remember never connected the led directly with Vcc (output voltage which
comes from directly 7805 ). If you connected the Led directly with the Vcc then maybe your
led burnout.

So always connect the led using the resistance, if you need good brightness then you can
select the value of resistance between 100 to 150-ohm either for medium brightness, you can
select 300 ohms.

Electrical Switch

The switch is a basic input device, use to control the operation of any output device using the
microcontroller or control unit. It basically breaks the electrical circuit and interrupts the flow
of current.

Interfacing Seven Segment Display with 8051

A seven segment display module is an electronic device used to display digital numbers and
it is made up of seven LED segments. Because of the small size of the LEDs, it is really easy
for a number of them to be connected together to make a unit like seven segment display. In
the seven segment display module, seven LED s are arranged in a rectangle. Sometimes, an
additional LED is seen in a seven segment display unit which is meant for displaying a
decimal point.
Each LED segment has one of its pins brought out of the rectangular package. Other pins are
connected together to a common terminal. Seven segment displays can only display 0 to 9
numbers. These seven LEDs indicate seven segments of the numbers and a dot point.

Seven segment displays are seen associated with a great number of devices such as clocks,
digital home appliances, signal boards on roads etc.

Types of Seven segment displays

As mentioned in previous paragraphs, seven segment displays come up with two different
configurations. They are the common anode and a common cathode. One pin each from each
segment is connected to a common terminal. According to the pins which are connected to
the common terminal, the seven segment display is categorized as a common anode and
common cathode.

Common Cathode 7-segment display

As the name indicates, its cathode is connected to a common terminal. Below is the
schematic diagram to indicate its common cathode structure. It should be connected to the
ground while operating the display. If a high voltage is given to the anode, then it will turn on
the corresponding segment.
Common Anode 7-segment display

In this type, the anode is common. It should be connected to a high voltage (to the supply
through a resistor to limit current). In order to turn on a particular segment, a ground level
voltage is given to the corresponding pin. Since logic circuits can sink more current than they
can source, common anode connection is used most widely.

Display codes
Display codes are the voltages to be applied to the segments to display a number. It is in the
order of segments ABCDEFG(DP), total 8 bits. For example, below is the common cathode
display code of ‘0’ with decimal point OFF.
Below is a table with display codes of all the digits with decimal point OFF.

If number 0 has to be displayed, then the segments A through F are turned on. In order to turn
on the segments, in common cathode mode, the anode terminals are subjected to a high
voltage while in common anode mode, the cathode terminals are given a low voltage.

Interfacing with Microcontroller

In order to display 0, we first need send the display code for 0 in port 2. Here we use a
common cathode display.

P2 = 0X3F; // Display code for Zero with DP OFF

Advanced circuits
To avoid drawing high current from controller port, we can use a transistor driver in each of
the segment lines. We can use either PNP or NPN transistors. In the case of PNP, the display
codes should be inverted because PNP transistors turn ON by applying a LOW signal (i.e.,
for common cathode, use common anode’s display codes). The transistor acts as a high
current switch when voltage and current levels are in the correct range with the switch being
controlled by the lower current digital logic signal. In most cases, the transistor used is a BJT,
especially in the case of low voltage circuits.
Here we can turn on the segment by giving a high in transistor base. In the case of PNP
transistor, we need to give a low voltage for turning on.
Multiplexed 7 segment display
Consider the case when two or more seven segment displays have to be used and the
microcontroller unit does not have enough I/O ports to accommodate all the input pins of the
seven segment display units. The best method to be adopted in such cases would be to use a
multiplexer. By multiplexing, the number of seven segment units multiplexed would be using
only the seven output ports and enable pins equal to the number of display units to display the
output.
Now, how it is made possible to use only seven output ports to display output of the number
of seven segment display units at a single time? The principle behind this is the persistence of
vision. Only one unit is working at a single time and the switching between the seven
segment display units are made faster so that the onlooker is not able to recognize the
switching.

7 segment display driver IC

The driver circuit is included between the decoder circuit and the seven segment display
units. It is necessary when high current is required to drive the display. In normal cases,
decoder functions as a driver but when a number of seven segment units are multiplexed, then
there is a requirement of high current. In such cases, a driver circuit is introduced between the
decoder and seven segment display units. Besides, the driver circuit is helpful in simplifying
the entire circuit as it reduces the number of components such as transistors.
One example of this type of IC is MAX7219, a serial I/O common-cathode display driver. It
can interface up to eight 7-segment displays at a time. The communication with MAX7219 is
achieved through a 4-wire serial interface. External components can be minimized using this
type of drivers, in this case, we need only one external resistor.
Interrupt is the method of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor. The microprocessor responds to that
interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct the
microprocessor on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts

Hardware interrupt is caused by any peripheral device by sending a signal through a specified
pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable
interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin
associated is INTA called interrupt acknowledge.
NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable
interrupt request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of the return
address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear
interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is
disabled, then the microprocessor first completes the current execution and sends ‘0’ on
INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and
during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable
interrupt controller.
These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the return address
are pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0

Software Interrupts

Some instructions are inserted at the desired position into the program to create interrupts.
These interrupt instructions can be used to test the working of various interrupt handlers. It
includes −
INT- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the
stack.
 IP is loaded from the contents of the word location ‘type number’ × 4
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly
for type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers.
i.e. −
 TYPE 0 interrupt represents division by zero situation.
 TYPE 1 interrupt represents single-step execution during the debugging of a program.
 TYPE 2 interrupt represents non-maskable NMI interrupt.
 TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for hardware and software interrupts.
INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the
program so that when the processor reaches there, then it stops the normal execution of
program and follows the break-point procedure.
Its execution includes the following steps −
  Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the
stack.
 IP is loaded from the contents of the word location 3×4 = 0000CH
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH.
As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the
overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number is
4. If the overflow flag is reset then, the execution continues to the next instruction.
Its execution includes the following steps −
 Flag register values are pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed on to the
stack.
 IP is loaded from the contents of word location 4×4 = 00010H
 CS is loaded from the contents of the next word location.
 Interrupt flag and Trap flag are reset to 0

8251 universal synchronous asynchronous receiver transmitter (USART) acts as a

mediator between microprocessor and peripheral to transmit serial data into parallel form
and vice versa.

1. It takes data serially from peripheral (outside devices) and converts into parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into serial
form.
4. After converting data into serial form, it transmits it to outside device (peripheral).
Block Diagram of 8251 USART –
It contains the following blocks:

1. Data bus buffer –

This block helps in interfacing the internal data bus of 8251 to the system data bus.
The data transmission is possible between 8251 and CPU by the data bus buffer
block.
2. Read/Write control logic –
It is a control block for overall device. It controls the overall working by selecting the
operation to be done. The operation selection depends upon input signals as:
 In this way, this unit selects one of the three registers- data buffer register, control
register, status register.

3. Modem control (modulator/demodulator) –

A device converts analog signals to digital signals and vice-versa and helps the
computers to communicate over telephone lines or cable wires. The following are
active-low pins of Modem.
 DSR: Data Set Ready signal is an input signal.
 DTR: Data terminal Ready is an output signal.
 CTS: It is an input signal which controls the data transmit circuit.
RTS: It is an output signal which is used to set the status RTS.
4. Transmit buffer –
This block is used for parallel to serial converter that receives a parallel byte for
conversion into serial signal and further transmission onto the common channel.
 TXD: It is an output signal, if its value is one, means transmitter will transmit
the data.
5. Transmit control –
This block is used to control the data transmission with the help of following pins:
 TXRDY: It means transmitter is ready to transmit data character.
 TXEMPTY: An output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
 TXC: An active-low input pin which controls the data transmission rate of
transmitted data.
6. Receive buffer –
This block acts as a buffer for the received data.
 RXD: An input signal which receives the data.
7. Receive control –
This block controls the receiving data.
 RXRDY: An input signal indicates that it is ready to receive the data.
 RXC: An active-low input signal which controls the data transmission rate of
received data.
 SYNDET/BD: An input or output terminal. External synchronous mode-input
terminal and asynchronous mode-output terminal.

DMA

Suppose any device which is connected to input-output port wants to transfer data to
memory, first of all it will send input-output port address and control signal, input-output
read to input-output port, then it will send memory address and memory write signal to
memory where data has to be transferred. In normal input-output technique the processor
becomes busy in checking whether any input-output operation is completed or not for next
input-output operation, therefore this technique is slow.

This problem of slow data transfer between input-output port and memory or between two
memory is avoided by implementing Direct Memory Access (DMA) technique. This is
faster as the microprocessor/computer is bypassed and the control of address bus and data
bus is given to the DMA controller.
  HOLD – hold signal

 HLDA – hold acknowledgment

 DREQ – DMA request

 DACK – DMA acknowledgment

Suppose a floppy drive that is connected at input-output port wants to transfer data to
memory, the following steps are performed:

 Step-1: First of all the floppy drive will send a DMA request (DREQ) to the DMAC,
it means the floppy drive wants its DMA service.

 Step-2: Now the DMAC will send a HOLD signal to the CPU.

 Step-3: After accepting the DMA service request from the DMAC, the CPU will
send hold acknowledgment (HLDA) to the DMAC, it means the microprocessor has
released control of the address bus the data bus to DMAC and the
microprocessor/computer is bypassed during DMA service.

 Step-4: Now the DMAC will send one acknowledgement (DACL) to the floppy drive
which is connected at the input-output port. It means the DMAC tells the floppy drive
 be ready for its DMA service.

 Step-5: Now with the help of input-output read and memory write signal the data is
transferred from the floppy drive to the memory.

Modes of DMAC:
1. Single Mode – In this only one channel is used, means only a single DMAC is
connected to the bus system.

2. Cascade Mode – In this multiple channels are used, we can further cascade
more number of DMACs.

Stepper Motor

Stepper motors are used to translate electrical pulses into mechanical movements. In some
disk drives, dot matrix printers, and some other different places the stepper motors are used.
The main advantage of using the stepper motor is the position control. Stepper motors
generally have a permanent magnet shaft (rotor), and it is surrounded by a stator.
Normal motor shafts can move freely but the stepper motor shafts move in fixed repeatable
increments.

Some parameters of stepper motors −

 Step Angle − The step angle is the angle in which the rotor moves when one pulse is
applied as an input of the stator. This parameter is used to determine the positioning
of a stepper motor.
 Steps per Revolution − This is the number of step angles required for a complete
revolution. So the formula is 360° /Step Angle.
 Steps per Second − This parameter is used to measure a number of steps covered in
each second.
 RPM − The RPM is the Revolution Per Minute. It measures the frequency of
rotation. By this parameter, we can measure the number of rotations in one minute.
The relation between RPM, steps per revolution, and steps per second is like below:

Steps per Second = rpm x steps per revolution / 60

Interfacing Stepper Motor with 8051 Microcontroller

Weare using Port P0 of 8051 for connecting the stepper motor. HereULN2003 is used. This
is basically a high voltage, high current Darlington transistor array. Each ULN2003 has
seven NPN Darlington pairs. It can provide high voltage output with common cathode clamp
diodes for switching inductive loads.

The Unipolar stepper motor works in three modes.

 Wave Drive Mode − In this mode, one coil is energized at a time. So all four coils
are energized one after another. This mode produces less torque than full step drive
mode.
The following table is showing the sequence of input states in different windings.

Steps Winding A Winding B Winding C

1 1 0 0

2 0 1 0

3 0 0 1

4 0 0 0

 Full Drive Mode − In this mode, two coils are energized at the same time. This mode
produces more torque. Here the power consumption is also high
The following table is showing the sequence of input states in different windings.

Steps Winding A Winding B Winding C

1 1 1 0

2 0 1 1

3 0 0 1

4 1 0 0

 Half Drive Mode − In this mode, one and two coils are energized alternately. At first,
one coil is energized then two coils are energized. This is basically a combination
of wave and full drive mode. It increases the angular rotation of the motor
The following table is showing the sequence of input states in different windings.

Steps Winding A Winding B Winding C

1 1 0 0

2 1 1 0
 Steps Winding A Winding B Winding C

3 0 1 0

4 0 1 1

5 0 0 1

6 0 0 1

7 0 0 0

8 1 0 0

The circuit diagram is like below: We are using the full drive mode.

D/A Converters

D/A converters convert digital signals into analog format.

Digital Data:

Evenly spaced discontinuous values

Temporally discrete, quantitatively discrete

Analog Data (Natural Phenomena):

Continuous range of values

Temporally continuous, quantitatively continuous

A/D Converters

An A/D converter is a device that converts analog signals (usually voltage) obtained from
environmental (physical) phenomena into digital format
Conversion involves a series of steps, including sampling, quantization, and coding.

A/D and D/A Requirements

Electrically sophisticated and high-speed processing are performed digitally in CPUs and
DSPs.
Natural phenomena are converted to digital signals using an A/D converter for digital signal
processing, then converted back to analog signals via a D/A converter.
Advancements in Microfabrication Technology→Signal Processing Digitization
→A/D and D/A Converters Required

A/D Converter Applications

Digital Audio:

Digital audio workstations, sound recording, pulse-code modulation

Digital signal processing:

TV tuner cards, microcontrollers, digital storage oscilloscopes

Scientific instruments:

Digital imaging systems, radar systems, temperature sensors

D/A Converter Applications

Digital Audio：

CD, MD, 1-bit Audio

Digital Video：

DVD, Digital Still Camera

Communication Equipment：

Smartphones, FAX, ADSl equipment

PCs：

Audio, video cards

Measurement instruments：

Programmable power supplies, etc.

Basic Operation of a D/A Converter

A D/A converter takes a precise number (most commonly a fixed-point binary number) and
converts it into a physical quantity (example: voltage or pressure). D/A converters are often
used to convert finite-precision time series data to a continually varying physical signal.
An ideal D/A converter takes abstract numbers from a sequence of impulses that are then
processed by using a form of interpolation to fill in data between impulses. A conventional
D/A converter puts the numbers into a piecewise constant function made up of a sequence of
rectangular functions that is modeled with the zero-order hold.
A D/A converter reconstructs original signals so that its bandwidth meets certain
requirements. With digital sampling comes quantization errors that create low-level noise
which gets added to the reconstructed signal. The minimum analog signal amplitude that can
bring about a change in the digital signal is called the Least Significant Bit (LSB), while the
(rounding) error that occurs between the analog and digital signals is referred to as
quantization error.

Basic Operation of an A/D Converter

Now, let's take a look at the basic operation of an A/D converter.

The A/D converter breaks up (samples) the amplitude of the analog signal at discrete
intervals, which are then converted into digital values. The resolution of an analog to digital
converter (indicating the number of discrete values it can produce over a range of analog
values) is typically expressed by the number of bits. In the above case of a 3bit A/D
converter, the upper value (b2) is referred to as the Most Significant Bit (MSB) and the
lowest value (b0) the Least Significant Bit (LSB).
The graph below shows the relationship between the analog input and digital output.
In addition, the first digital change point (000→001) below 0.5LSB is the zero scale, while
the last digital change point (110→111) is termed full scale and the interval from zero to full
scale referred to as the full scale range.
Analog Signal to Digital Signal Conversion Methods
Sampling:

Sampling is the process of taking amplitude values of the continuous analog signal at
discrete time intervals (sampling period Ts).
[Sampling Period Ts = 1/Fs (Sampling Frequency)]
Sampling is performed using a Sample and Hold (S&H) circuit.

Quantization:

Quantization involves assigning a numerical value to each sampled amplitude value

from a range of possible values covering the entire amplitude range (based on the
number of bits).
[Quantization error: Sampled Value - Quantized Value]

Coding:

Once the amplitude values have been quantized they are encoded into binary using an
Encoder.
Intel 8259 is a Programmable Interrupt Controller (PIC)
Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5 hardware
interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086 microprocessors
respectively. But by connecting Intel 8259 with these microprocessors, we can increase
their interrupt handling capability. Intel 8259 combines the multi-interrupt input sources
into a single interrupt output. Interfacing of single PIC provides 8 interrupts inputs from
IR0-IR7. For example, Interfacing of 8085 and 8259 increases the interrupt handling
capability of 8085 microprocessor from 5 to 8 interrupt levels.
Features of Intel 8259 PIC are as follows:

1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading
further 8259 PICs.
5. Clock cycle is not required.
Pin Diagram of 8259 – We can see through above diagram that there are total 28 pins in
Intel 8259 PIC where Vcc : 5V Power supply and Gnd : ground. Other pins use are
explained below. Block Diagram of 8259 PIC microprocessor –
 The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic,
Cascade Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR,
IMR.
1. Data bus buffer – This Block is used as a mediator between 8259 and 8085/8086
microprocessor by acting as a buffer. It takes the control word from the 8085 (let say)
microprocessor and transfer it to the control logic of 8259 microprocessor. After
selection of Interrupt by 8259 microprocessor (based on priority of the interrupt), it
transfer the opcode of the selected Interrupt and address of the Interrupt service sub
routine to the other connected microprocessor. The data bus buffer consists of 8 bits
represented as D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits
data can be transferred at a time.
2. Read/Write logic – This block works only when the value of pin CS is low (as this
pin is active low). This block is responsible for the flow of data depending upo n the
inputs of RD and WR. These two pins are active low pins used for read and write
operations.
3. Control logic – It is the center of the PIC and controls the functioning of every
block. It has pin INTR which is connected with other microprocessor for taking
interrupt request and pin INT for giving the output. If 8259 is enabled, and the other
microprocessor Interrupt flag is high then this causes the value of the output INT pin
high and in this way 8259 responds to the request made by other microprocessor.
 4. Interrupt request register (IRR) – It stores all the interrupt level which are
requesting for Interrupt services.
5. Interrupt service register (ISR) – It stores the interrupt level which are currently
being executed.
6. Interrupt mask register (IMR) – It stores the interrupt level which have to be
masked by storing the masking bits of the interrupt level.
7. Priority resolver – It examines all the three registers and set the priority of interrupts
and according to the priority of the interrupts, interrupt with highest priority is set in
ISR register. Also, it reset the interrupt level which is already been serviced in IRR.
8. Cascade buffer – To increase the Interrupt handling capability, we can further
cascade more number of pins by using cascade buffer. So, during increment of
interrupt capability, CSA lines are used to control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else
in slave mode. In Non Buffered mode, SP/EN pin is used to specify whet her 8259 work as
master or slave and in Buffered mode, SP/EN pin is used as an output to enable data bus.