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The document outlines the course structure for Computer Architecture, focusing on key topics such as the processor, memory hierarchy, and various levels of parallelism. It includes details on implementing a subset of MIPS instructions and the design of a CPU datapath for different instruction types. Additionally, it discusses the control signals and ALU operations necessary for executing these instructions.

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Abdalrhman Mohamed
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3 views

lec1

The document outlines the course structure for Computer Architecture, focusing on key topics such as the processor, memory hierarchy, and various levels of parallelism. It includes details on implementing a subset of MIPS instructions and the design of a CPU datapath for different instruction types. Additionally, it discusses the control signals and ALU operations necessary for executing these instructions.

Uploaded by

Abdalrhman Mohamed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

Computer Architecture

Course breakdown
• The processor
• Memory Hierarchy
• Instruction-level parallelism
• Data-level parallelism
• Thread-level parallelism
References
• Computer Organization and design
The hardware/software interface
David A. Patterson and John L. Hennessy
5th edition
• Computer Architecture
A quantitative approach
John L. Hennessy and David A. Patterson
5th edition
Chapter 4

The Processor
Achnowledgement
Jeremy R. Johnson
Anatole D. Ruslanov
William M. Mongan
Implementation of a subset of MIPS
It includes
– memory-reference instructions: lw, sw
– arithmetic-logical instructions: add, sub, and, or, slt
set if less than
– control flow instructions: beq, j

lw $t0, 8($t3)
sw $t0, 12($s4)
add $t0, $t0, $t1
slt $t0,$t1,$t2 # $t0=1 if $t1<$t2, $t0=0 otherwise
beq $s3, $s4, loop
j Exit
CPU Overview (single-cycle)
• Datapath : Elements that process data and addresses
Instruction memory, PC, Adder, Register File, ALU, Data Memory
• Longest delay determines clock period

Chapter 4 — The Processor


—6
Multiplexers
◼ Can’t just join wires
together
◼ Use multiplexers

Chapter 4 — The Processor


—7
Control

Chapter 4 — The Processor


—8
Building a Datapath: Instruction
Fetch

Increment by
4 for next
32-bit instruction
register

Chapter 4 — The Processor


—9
Building a Datapath: R-Format
Instructions
• Read two register operands
• Perform arithmetic/logical operation
• Write register result write register--> destination Reg

Chapter 4 — The Processor


— 10
R-Type Datapath

Chapter 4 — The Processor


— 11 Chapter 4 — The Processor — 11
Building a Datapath: Load/Store
Instructions
• Read register operands
• Calculate address using 16-bit offset
– Use ALU, but sign-extend offset
• Load: Read memory and update register
• Store: Write register value to memory

Chapter 4 — The Processor


— 12
R-Type/Load/Store Datapath

Chapter 4 — The Processor


— 13 Chapter 4 — The Processor — 13
Branch Instructions
• Read register operands
• Compare operands
– Use ALU, subtract and check Zero output
• Calculate target address
– Sign-extend displacement
– Shift left 2 places (word displacement)
– Add to PC + 4
• Already calculated by instruction fetch

Chapter 4 — The Processor


— 14
Branch Instructions
Just
re-routes
wires

Sign-bit wire
replicated
Chapter 4 — The Processor
— 15
Composing the Elements
• First-cut data path does an instruction in one
clock cycle
– Each datapath element can only do one function
at a time
– Hence, we need separate instruction and data
memories
• Use multiplexers where alternate data sources
are used for different instructions

Chapter 4 — The Processor


— 16
Full Datapath

Chapter 4 — The Processor


— 17
§4.4 A Simple Implementation Scheme
ALU Control
• ALU used for
– Load/Store: F = add
– Branch: F = subtract
– R-type: F depends on funct field
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than
1100 NOR

Chapter 4 — The Processor


— 18
ALU Control

6 ALUOp 4
Main ALU To
ALU ALU
Control Control
Op-code control

Instruction
funct field

From Dr. Sumanta Guha


ALU Control
• Assume 2-bit ALUOp derived from opcode
– Combinational logic derives ALU control
opcode ALUOp Operation funct ALU function ALU control
lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111

Chapter 4 — The Processor


— 20
The Main Control Unit
• Control signals derived from instruction

R-type 0 rs rt rd shamt funct


31:26 25:21 20:16 15:11 10:6 5:0

Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for sign-extend


read except R-type and and add
for load load

Chapter 4 — The Processor


— 21

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