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Le code de ACC

The document contains VHDL code for various digital components including an Accumulator (ACC), Instruction Register (IR), Program Counter (PC), Arithmetic Logic Unit (UAL), multiplexers (MUX_16 and MUX_12), a Read-Only Memory (ROM), and a sequencer for controlling the operation of a processor. Each component is defined with its respective inputs and outputs, along with behavioral architectures that describe their functionality. The sequencer manages state transitions and control signals based on the current state and opcode, facilitating instruction execution in a simulated processor environment.

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itsmayssa41
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8 views13 pages

Le code de ACC

The document contains VHDL code for various digital components including an Accumulator (ACC), Instruction Register (IR), Program Counter (PC), Arithmetic Logic Unit (UAL), multiplexers (MUX_16 and MUX_12), a Read-Only Memory (ROM), and a sequencer for controlling the operation of a processor. Each component is defined with its respective inputs and outputs, along with behavioral architectures that describe their functionality. The sequencer manages state transitions and control signals based on the current state and opcode, facilitating instruction execution in a simulated processor environment.

Uploaded by

itsmayssa41
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Le code de ACC :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ACC is
Port (

accLD : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out: out std_logic_vector(15 downto 0);
accZ : out std_logic;
acc15 : out std_logic
);
end ACC;

architecture Behavioral of ACC is


signal acc_reg : std_logic_vector(15 downto 0);
begin
process(accLD, data_in)
if accLD = '1' then
acc_reg <= data_in;
end if;
end process
data_out <= acc_reg;
accZ <= '1' when acc_reg = "0000000000000000" else '0';
acc15 <= '1' when acc_reg >= "0000000000000000" else '0';

end Behavioral;

CODE de IR :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity IR is
Port (
data_in : in STD_LOGIC_VECTOR(15 downto 0);
ir_ld : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(11 downto 0);
opcode : out STD_LOGIC_VECTOR(3 downto 0)
);
end IR;
architecture Behavioral_IR of IR is
signal data : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
begin
process(ir_ld, data_in)
begin
if ir_ld = '1' then
data <= data_in;
end if;
end process;
opcode <= data(15 downto 12);
data_out <= data(11 downto 0);
end Behavioral_IR;
CODE de PC:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PC is
Port (
data_in : in STD_LOGIC_VECTOR(15 downto 0);
pc_ld : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(11 downto 0)
);
end PC;
architecture Behavioral_PC of PC is
signal data : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
begin
process(pc_ld, data_in)
begin
if pc_ld = '1' then
data <= data_in;
end if;
end process;
data_out <= data(11 downto 0);
end Behavioral_PC;
le code de L’UAL :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity UAL is
Port (
inA : in std_logic_vector(15 downto 0);
inB : in std_logic_vector(15 downto 0);
alufs : in std_logic_vector(3 downto 0);
aluOut : out std_logic_vector(15 downto 0);
);
end UAL;

architecture Behavioral of UAL is


signal res : std_logic_vector(15 downto 0);
begin

process(inA, inB, alufs)


begin
case alufs is
when "0000" =>
res <= inB;

when "0001" =>


res <= std_logic_vector(unsigned(inA) – unsigned(inB));

when "0010" =>


res <= std_logic_vector(unsigned(inA) + unsigned( inB));

when "0011" =>


res <= std_logic_vector(unsigned(inB) - 1);
when others =>
res <= (others => '0');
end case;
end process;
end Behavioral;

Code de la triangle :
entity triangle is
Port (
data_in : in STD_LOGIC_VECTOR(15 downto 0);
acc_oe : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(15 downto 0)

);
end triangle;
architecture Behavioral_ triangle of triangle is
begin
process(data_in, acc_oe)

begin
if acc_oe = '1' then
data_out <= data_in;
else
data_out <= (others => 'Z');
end if;
end process;
end Behavioral_ triangle;
Code de MUX_16 :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_16bit is
Port (
A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
selB : in STD_LOGIC;
S : out STD_LOGIC_VECTOR(15 downto 0)
);
end Mux_16bit;

architecture Behavioral_mux of Mux_16bit is


begin
process(A, B, selB)
begin
if selB = '0' then
S <= A;
else
S <= B;
end if;
end process;
end Behavioral_mux;
Code de MUX_12 :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_12 is
Port (
A : in STD_LOGIC_VECTOR(12 downto 0);
B : in STD_LOGIC_VECTOR(12 downto 0);
selA : in STD_LOGIC;
S : out STD_LOGIC_VECTOR(12 downto 0)
);
end Mux_12bit;

architecture Behavioral_mux12 of Mux_12 is


begin
process(A, B, selA)
begin
if selA = '0' then
S <= A;
else
S <= B;
end if;
end process;
end Behavioral_mux12;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ROM is
Port (
addr : in std_logic_vector(11 downto 0); -- 12 bits d’adresse
dataOut : out std_logic_vector(15 downto 0) -- 16 bits de données
);
end ROM;

architecture Behavioral of ROM is


type memory_array is array(0 to 4095) of std_logic_vector(15 downto 0);
signal memory : memory_array := (
0 => x"1100", -- LDA @100h
1 => x"2101", -- ADD @101h
2 => x"4005", -- JNE 005h
3 => x"3100", -- SUB @100h
4 => x"3100", -- SUB @100h
5 => x"2100", -- ADD @100h
6 => x"F000", -- STP
others => x"0000" -- le reste = 0
);
begin
dataOut <= memory(to_integer(unsigned(addr)));
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sequencer is
Port (
clk : in std_logic;
reset : in std_logic;
opcode : in std_logic_vector(2 downto 0);
acc_Z : in std_logic;
acc_15 : in std_logic;
selA : out std_logic;
selB : out std_logic;
RnW : out std_logic;
pc_ld : out std_logic;
ir_ld : out std_logic;
acc_ld : out std_logic;
acc_oe : out std_logic;
alufs : out std_logic_vector(1 downto 0)
);
end sequencer;

architecture behavioral of sequencer is

-- Define a proper state type (much more readable!)


type state_type is (IDLE, FETCH, DECODE, EXECUTE, WRITEBACK);
signal current_state, next_state : state_type;

begin
-- Synchronous process for state transitions
process(clk, reset)
begin
if reset = '1' then
current_state <= IDLE;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;

-- Combinational process for next-state logic


process(current_state, opcode, acc_Z, acc_15)
begin
case current_state is
when IDLE =>
next_state <= FETCH;

when FETCH =>


next_state <= DECODE;

when DECODE =>


-- Decide next based on opcode and flags
if opcode = "000" then
next_state <= EXECUTE; -- Example: ADD
elsif opcode = "001" then
next_state <= EXECUTE; -- Example: SUB
elsif opcode = "010" and acc_Z = '1' then
next_state <= EXECUTE; -- Example: conditional branch if zero
elsif opcode = "011" and acc_15 = '0' then
next_state <= EXECUTE; -- Example: conditional branch if acc_15 =
0
else
next_state <= WRITEBACK; -- By default go to WRITEBACK
end if;

when EXECUTE =>


next_state <= WRITEBACK;

when WRITEBACK =>


next_state <= FETCH;

when others =>


next_state <= IDLE;
end case;
end process;

-- Combinational process for outputs


process(current_state, opcode, acc_Z, acc_15)
begin
-- Default all outputs to '0'
selA <= '0';
selB <= '0';
RnW <= '1'; -- Default is READ
pc_ld <= '0';
ir_ld <= '0';
acc_ld <= '0';
acc_oe <= '0';
alufs <= "00";

case current_state is
when FETCH =>
ir_ld <= '1'; -- Load instruction register
RnW <= '1'; -- Read from memory
when DECODE =>
-- Could add additional decoding control signals if needed
null;

when EXECUTE =>


selA <= '1';
selB <= '1';
acc_ld <= '1';
alufs <= "10"; -- Example ALU function code

when WRITEBACK =>


acc_oe <= '1'; -- Output accumulator content
pc_ld <= '1'; -- Load PC for next instruction

when others =>


null;
end case;
end process;

end behavioral;

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