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The document discusses the challenges of verifying configurable IP, particularly with the addition of power gating in the USB OTG design. It outlines the verification process, including RTL functional testing and gate-level simulation to ensure proper power down functionality. Additionally, it highlights the transition to using UPF for packaging IP, which simplifies the inclusion of power strategies and configurations for users.

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Serajeldeen Ghalyoub 201-801-104
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5 views

paper 1 - Copy (3)

The document discusses the challenges of verifying configurable IP, particularly with the addition of power gating in the USB OTG design. It outlines the verification process, including RTL functional testing and gate-level simulation to ensure proper power down functionality. Additionally, it highlights the transition to using UPF for packaging IP, which simplifies the inclusion of power strategies and configurations for users.

Uploaded by

Serajeldeen Ghalyoub 201-801-104
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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8.5 Verification Verification for any configurable IP is a major challenge.

This
challenge is increased by adding power gating. In developing the power-
gated version of the USB OTG, we initially did full RTL functional testing
without the power gating circuitry in place. Once the USB OTG passed all
diagnostics, we added the power gating functionality and re-ran the diag
nostics. Once these all passed, we ran a set of diagnostics for testing the
power down feature itself. 110 Low Power Methodology Manual Since the
power gating function is completely independent of other USB functions, this
approach seemed the appropriate way to minimize the verification effort and
still provide strong verification. At the RTL level, we simulated the power
switching fabric by forcing register outputs to “X” during power down. This
approach allowed us to completely verify the core at the RTL level. But
because power gating is so closely tied to the physical implemen tation of a
switching fabric, we also did extensive gate-level simulation of the power
down function. This allowed us to use a detailed model for the switching
fabric, including the time it takes to power up or down completely. 8.6
Packaging IP for Reuse with Power Intent The SALT chip was developed
before UPF was available to provide a convenient way of specifying the
power strategy for an IP block. With the introduction of UPF, it becomes
much more straightforward to include power strategies in the final packag
ing of the IP. Any IP needs to be packaged in a way that enables users to
configure the IP to their application. Often this is done using a configuration
tool. For soft IP, the final packag ing includes: • Configuring the RTL (for the
USB, this includes selecting the number of end points and configuring each
endpoint) • Ability to generate a test bench for the verifying the configured
core, both pre and post-synthesis • Synthesis scripts for the configured core,
including support for clock gating and multi-VT For cores that support power
gating, we need to add: • The ability to configure the power controller • The
ability to generate a test bench for verifying pre and post-synthesis power
operation • The ability to configure the power intent, including the target
retention registers • Synthesis scripts that support the power intent •
Configurable UPF code to support the configurable power strategies IP
Design for Low Power 8.7 UPF for the USB OTG Core 111 Figure 8-3 on page
112 shows a more detailed block diagram of the USB OTG digital core. In the
original SALT chip, we had to add retention, isolation, and the power switch
directly in the RTL. With the introduction of UPF, we can describe this func
tionality using UPF tcl commands. Note that the Power Control block still has
to be designed in RTL and instantiated in the design. The UPF code for
adding power gating, retention, and isolation is shown below. The block
names otg (top level of the core), biu, mac, etc., are the names of the
instances of these modules in the RTL. To make the UPF code portable, we
use a variable ($otg) to indicate the actual path from the top of the design to
the top level of the core in the RTL. We also use vari ables for the origin of
the VDD and VSS power nets. Most likely these would be at the top level of
the chip

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