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MID-II CA Spring 2025 Solution

The document is an exam paper for the Computer Architecture course at the National University of Computer and Emerging Sciences, Karachi Campus, dated April 10th, 2025. It includes instructions for students, questions on logical reasoning, processor design, and code dependencies, with a total of 30 marks available. The exam covers topics such as load-store architecture, RISC-V ISA encoding formats, pipelining speedup, and hazard resolution in code sequences.

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k230517
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31 views6 pages

MID-II CA Spring 2025 Solution

The document is an exam paper for the Computer Architecture course at the National University of Computer and Emerging Sciences, Karachi Campus, dated April 10th, 2025. It includes instructions for students, questions on logical reasoning, processor design, and code dependencies, with a total of 30 marks available. The exam covers topics such as load-store architecture, RISC-V ISA encoding formats, pipelining speedup, and hazard resolution in code sequences.

Uploaded by

k230517
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

National University of Computer and Emerging Sciences

Karachi Campus
Computer Architecture (EE-3009) Sessional-II Exam
Date: April 10th 2025
Total Time (Hrs): 1
Course Instructor(s)
Total Marks: 30
Mr. Aashir Mahboob, Dr. Nausheen , Mr. Kashan ,
Total Questions: 3
Mr. Shoaib Rauf

___________ __________ _____________________


Roll No Section Student Signature
Do not write below this line

INSTRUCTION: Attempt all the questions in-order.


CLO # 2 Solution
Q1: Logical Reasoning [ 3x 2=6 Marks]

a. In load –store Architecture, what is the maximum number of operands allowed in an instruction?
Does it support memory addressing?
3 operands allowed in an instruction. No it does not support memory addressing.
b. In RISC-V ISA, which encoding format is used for ALU operations and for branches?
R – Type for ALU operations (R-R) , I- Type for ALU immediate.
S/B- Type for Branches.

c. Why memory alignment restrictions are significant in architecture design?


Misalignment causes hardware complications, because the memory is typically aligned on
a multiple of a word or double-word boundary. A misaligned memory access may,
therefore, take multiple aligned memory references. Thus, even in computers that allow
misaligned access, programs with aligned accesses run faster.

CLO # 3 Solution
Q2: You are given a non-pipelined processor design which has a 5 GHz clock and it uses 3 cycles for
ALU operations, 2 cycles for branch operations and 4 cycles for memory operations. Assume that the
relative frequencies of these operations are 40%, 20%, and 40%, respectively. [ 3x3=09 Marks]

a. What is the best speedup you can get by pipelining it into 5 stages?

Spring 2025 Department of Computer Science Page 1 of 6


National University of Computer and Emerging Sciences
Karachi Campus
b. If the 5 stages are 1ns, 1.5ns, 4ns, 3ns, and 0.5ns, what is the best speedup you can get compared
to the original processor?
c. If each pipeline stage added also adds 2ns due to register setup delay, what is the best speedup
you can get compared to the original processor?

Spring 2025 Department of Computer Science Page 2 of 6


National University of Computer and Emerging Sciences
Karachi Campus

CLO # 3 Solution
Q3: Consider the following code sequences,
 Identify the type of Dependencies (Hazards).
 Suggest a possible solution to resolve the hazard.
 Draw Pipeline diagram for each case to support your answer.

[3.5x4=15 Marks]
A) B)
ld x1,45(x2) ld x1,45(x2)
add x5,x1,x7 add x5,x6,x7
sub x8,x6,x7 sub x8,x1,x7
or x9,x6,x7 or x9,x6,x7
C) D)
ld x1,45(x2) Ld x1,0(x4)
add x5,x6,x7 Ld x2,4(x4)
sub x8,x6,x7 add x3,x2,x1
or x9,x1,x7 sd x3,8(x4)
addi x4,x4,4

Spring 2025 Department of Computer Science Page 3 of 6


National University of Computer and Emerging Sciences
Karachi Campus

Spring 2025 Department of Computer Science Page 4 of 6


National University of Computer and Emerging Sciences
Karachi Campus

=================== Good Luck ===================

Spring 2025 Department of Computer Science Page 5 of 6


National University of Computer and Emerging Sciences
Karachi Campus

Spring 2025 Department of Computer Science Page 6 of 6

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