ELEC 335

Digital Logic Design

Chapter 5:
Large Combinational systems

Instructor:
Dr. Abdul-Halim Jallad
 Outline
• Gate Delay
• Decoders
• Encoders
• Multiplexers
• Demultiplexers

5–2
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 CLOs Covered
1. Manipulate number system, binary codes, and computer
arithmetic. [PLO-1]
2. Apply Boolean algebra and Karnaugh map minimization
techniques to simplify Boolean expressions. [PLO-1]
3. Design binary adders, decoders, encoders, multiplexers, and de-
multiplexers to implement combinational logic circuits. [PLO-1, 2]
4. Design with flip-flops, synchronous and asynchronous sequential
circuits, state diagrams, and state tables. [PLO-1, 2]
5. Design registers (serial, parallel, and shift) ripple counters, and
synchronous counters. [PLO-1, 2]
6. Design digital circuits with memory devices of ROMs, PLAs, &
PALs. [PLO-2, 4]

5–3 ELEC 335, Digital Logic Design, UAE University

 Gate Delay

5–4 ELEC 335, Digital Logic Design, UAE University

 Gate Delay

5–5
ELEC 335, Digital Logic Design, UAE University
 Combinational Logic Building
Blocks
• Decoders:
– Binary n-to-2n decoders.
– Implementing functions using
decoders.
• Encoders:
– 2n -to-n binary decoders.
• Multiplexers.
• DeMultiplexers.
5–6
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Decoders
A decoder is a logic circuit that detects the presence of a specific
combination of bits at its input. Two simple decoders that detect the
presence of the binary code 0011 are shown. The first has an active
HIGH output; the second has an active LOW output.

A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011

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Decoders

Assume the output of the decoder shown is a

logic 1. What are the inputs to the decoder?

A0 = 0
A1 = 1
1
A2 = 0
A3 = 1

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 A 2 x 4 Binary Decoder
X Y F0 F1 F2 F3 F0 = X'Y'
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0 F1 = X'Y
1 1 0 0 0 1

F2 = XY'
• From truth table, circuit
for 2x4 decoder is: F3 = XY

• Note: Each output is a

2-variable minterm
X Y
(X'Y', X'Y, XY' or
XY)
F0
X 2-to-4 F1
Y Decoder F2
F3

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 Active HIGH Decoder with Enable
A
B

5–10 ELEC 335, Digital Logic Design, UAE University

 Active LOW Decoder

1
0A
0
0B
1
1

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 Active LOW Decoder with Enable

1 A
11
0 B 1
11

1 10
1

11
1 0 E

5–12 ELEC 335, Digital Logic Design, UAE University

 Active HIGH Decoder with LOW Enable

A
B

5–13 ELEC 335, Digital Logic Design, UAE University

 3 x 8 Binary Decoder
x y z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0 F0 = x'y'z'
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0 F1 = x'y'z
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0 F2 = x'yz'
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0 F3 = x'yz
1 1 1 0 0 0 0 0 0 0 1
F4 = xy'z'
F5 = xy'z

F6 = xyz'
F0
F1 F7 = xyz
X

Y
3-to-8 F2
F3
Z
Decoder F4
F5
F6
x y z
F7

5–14 ELEC 335, Digital Logic Design, UAE University

Decoders
IC decoders have multiple outputs to decode any
combination of inputs. For example the binary-to-decimal
decoder shown here has 16 outputs – one for each
combination of binary inputs.
Bin/Dec
0 1
For the input shown, 1 1
2 1
what is the output? 3 1
4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 0 A2 8 1 outputs
9 1
1 A3 10 1
11 0
12 1
13 1
14 1
15 1

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Decoders
X/Y
0
A specific integrated circuit 1
decoder is the 74HC154 (shown as 2
3
a 4-to-16 decoder). It includes two 4

active LOW chip select lines which A0 1

5
6
must be at the active level to enable A1 2 7
A2
the outputs. These lines can be used A3
4
8
8
9
to expand the decoder to larger 10

inputs. 11
12
13
14
CS1 & 15
CS2 EN
74HC154

ELEC 335, Digital Logic Design, UAE University

 Decoder Expansion
Two or more decoders can be used to create larger decoders

Output 0
A0 2x4 Output 1
A1 decoder Output 2
E Output 3
A2
Output 4
2x4 Output 5
decoder Output 6
E
Output 7

5–17 ELEC 335, Digital Logic Design, UAE University

5 to 32 line Decoder using 74HC154

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 BCD/DEC
Decoders 0
(1)
(2)
1
(3)
2
(15) (4)
BCD-to-decimal decoders accept a binary A0
(14)
1 3
(5)
coded decimal input and activate one of ten A1 2 4
(13) (6)
A2 4 5
possible decimal digit indications. (12)
8
(7)
A3 6
(9)
7
Assume the inputs to the 74HC42 (10)
8
(11)
decoder are the sequence 0101, 0110, 9
0011, and 0010. Describe the output.
74HC42

All lines are HIGH except for one active output, which is
LOW. The active outputs are 5, 6, 3, and 2 in that order.

ELEC 335, Digital Logic Design, UAE University

BCD Decoder/Driver
Another useful decoder is the 74LS47. This is a BCD-to-
seven segment display with active LOW outputs.
VCC

(16)
BCD/7-seg
The a-g outputs are BI/RBO
(4)
BI/RBO
designed for much (7)
1
a
(13)
(12)
higher current than most BCD
(1)
2
b
(11)
Outputs
(2) c
devices (hence the word inputs
(6)
4
d
(10) to seven
8 (9) segment
driver in the name). (3)
e
(15) device
LT LT f
(5) (14)
RBI RBI g

74LS47 (8)

GND

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BCD Decoder/Driver
Here the 7447A is an connected to an LED seven segment
display. Notice the current limiting resistors, required to
prevent overdriving the LED display.
+5.0 V
1.0 kΩ
+5.0 V
74LS47 16
R's = MAN72
BCD/7-seg
3 VCC 330 Ω 3, 9, 14
LT a 13 1 a
4
BI/RBO b 12 13 b
5
RBI c 11 10 c
6 A 10 8
d d
2 B e 9 7 e
BCD
input 1 C f 15 2 f
g 14 11 g
7
D
GND
8

ELEC 335, Digital Logic Design, UAE University

 Implementing Functions Using Decoders

• Any n-variable logic function, in sum-of-minterms

form can be implemented using a single n-to-2n
decoder to generate the minterms, and an OR gate to
form the sum.
– The output lines of the decoder corresponding to the minterms
of the function are used as inputs to the or gate.

• Any combinational circuit with n inputs and m

outputs can be implemented with an n-to-2n decoder
with m OR gates.
• Suitable when a circuit has many outputs, and each
output function is expressed with few minterms.
5–22
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 Implementing Functions Truth Table
Using Decoders A B X
Example 0 0 1 AB
0 1 0
1 0 0
1 1 1 AB

A A B
B
A B X
A B

A B
1
5–23E ELEC 335, Digital Logic Design, UAE University
 A complete design procedure
x y z C S

• Example: Full adder 0

0
0
0
0
1
0 0
0 1
0 1 0 0 1
S(x, y, z) = Σ (1,2,4,7) 0 1 1 1 0
1 0 0 0 1
C(x, y, z) = Σ (3,5,6,7) 1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
0
1
S
X 2
Y 3
Z 3-to-8
decoder 4
5
C
6
7
5–24 ELEC 335, Digital Logic Design, UAE University
 Encoders
• If a decoder's output code has fewer bits than the
input code, the device is usually called an encoder.
e.g. 2n-to-n, priority encoders.
• The simplest encoder is a 2n-to-n binary encoder,
where it has only one of 2n inputs = 1 and the output
is the n-bit binary number corresponding to the
active input.

• Encoders are opposite of decoders.

5–25 ELEC 335, Digital Logic Design, UAE University

 Encoders
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
A0 =D1 + D3 + D5+ D7
A1 =D2 + D3 + D6+ D7
5–26 A2 =D4 + D5 + D6+ D7
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Encoders
An encoder accepts an active logic level on one of its
inputs and converts it to a coded output, such as BCD or
binary.
1
The decimal to BCD is an encoder A0
with an input for each of the ten 2

decimal digits and four outputs that 3

A1
represent the BCD code for the active
4
digit. The basic logic diagram is 5 A2
6
shown. There is no zero input 7
because the outputs are all LOW 8
A3
when the input is zero. 9

ELEC 335, Digital Logic Design, UAE University

Encoders
Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.
The top two OR gates have ones as indicated with
the red lines. Thus the output is 0111.

1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
9

ELEC 335, Digital Logic Design, UAE University

Encoders
The 74HC147 is an example of an IC encoder. It is has ten
active-LOW inputs and converts the active input to an
active-LOW BCD output. V CC

(16)
This device is offers additional (11) 1
HPRI/BCD

flexibility in that it is a priority (12)

2
(13)
encoder. This means that if more (1)
3
1
(9)
4 (7)
than one input is active, the one Decimal (2) 5
2
(6)
BCD
4
with the highest order decimal input (3)
(4)
6
8
(14)
output

digit will be active. (5)

7
8
(10) 9
(8)
74HC147
The next slide shows an application … GND

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 VCC
Encoders R7 R8 R9

Keyboard
7 8 9
encoder HPRI/BCD
1
R4 R5 R6 2
3
1
4 2
5 4 BCD complement of
6
4 5 6 7
8 key press
8
9

R1 R2 R3 74HC147

1 2 3

R0
The zero line is not needed by the
0 encoder, but may be used by other
circuits to detect a key press.

ELEC 335, Digital Logic Design, UAE University

Multiplexers
A multiplexer (MUX) selects one data line from two or
more input lines and routes data from the selected line to
the output. The particular data line that is selected is
determined by the select inputs.
MUX
Two select lines are shown S0
0
0
Data
here to choose any of the select S1
1 1
four data inputs.
D0 0 Data
D1 1 output
Data
D 2
inputs D2
Which data line is selected if 3 3
S1S0 = 10? D2

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 Multiplexers
S0 . . . Sn-1 Control lines

… Inputs
I0
Input 0 I1
I2 mux Y
Input 1
. MUX Output I3

. S1 S0
Input 2n-1 select

I0 I1 I2 I3 S1 S0 Y S1 S0 Y
d0 d1 d2 d3 0 0 d0 0 0 I0
4-to-1 MUX d0 d1 d2 d3 0 1 d1 0 1 I1
Truth Table d0 d1 d2 d3 1 0 d2 1 0 I2
d0 d1 d2 d3 1 1 d3 1 1 I3

5–32 ELEC 335, Digital Logic Design, UAE University

Demultiplexers
A demultiplexer (DEMUX) performs the opposite function
from a MUX. It switches data from one input line to two or
more data lines depending on the select inputs.
The 74LS138 was introduced
DEMUX
previously as a decoder but can also A0
Y 0
Data
serve as a DEMUX. When select A1
Y 1

Y
connected as a DEMUX, data is lines A2 2

Data
Y
applied to one of the enable inputs, Y
3
outputs
and routed to the selected output Enable G1 4

Y
G2A
5

line depending on the select inputs

G2B
Y 6

variables. Note that the outputs are Y 7

active-LOW as illustrated in the 74LS138

following example…

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 A 4 x 1 Multiplexer

1 0
0 0

S1 S0

1101 0
1 4-x-1
10 00 2 Mux
3

5–34 ELEC 335, Digital Logic Design, UAE University

 Design of a multiplexer
S1
S0
D0

Y
D1

D2

S1 S0 Y
D3
0 0 D0
0 1 D1
1 0 D2
5–35 ELEC 335, Digital Logic Design, UAE University
1 1 D3
 Multiplexers
• Larger multiplexers can be constructed from smaller ones.
• An 8-to-1 multiplexer can be constructed from smaller
multiplexers as shown:

I0
S2 S1 S0 Y I1 4:1
0 0 0 I0 I2 MUX
0 0 1 I1 I3
0 1 0 I2 2:1
0 1 1 I3 S1 S0 MUX Y
1 0 0 I4 I4
1 0 1 I5 I5 4:1
1 1 0 I6 I6 MUX S2
1 1 1 I7 I7

S1 S0

5–36 ELEC 335, Digital Logic Design, UAE University

 Using a multiplexer to implement a function
• Ex: use a 4X1 multiplexer to implement the function
F(x,y,z) = Σm (0, 2, 4, 7)
X Y Z F
0 0 0 1
F=Z Y S0
0 0 1 0 X S1
0 1 0 1 Z
F=Z F
0 1 1 0 0 4X1 Mux
1 0 0 1 1
F=Z 2
1 0 1 0 3
1 1 0 0
F=Z
1 1 1 1
5–37 ELEC 335, Digital Logic Design, UAE University
 Another multiplexer example
• Implement using a 4 x 1 multiplexer the function
F(x,y,z) = Σm (3, 4, 6, 7)
X Y Z F
0 0 0 0 Y S0
F=0 X S1
0 0 1 0
Z F
0 1 0 0
F=Z 0 0 4X1 Mux
0 1 1 1 1
1 0 0 1 2
F=Z 1 3
1 0 1 0
1 1 0 1
F=1
1 1 1 1
5–38 ELEC 335, Digital Logic Design, UAE University
 Demultiplexer
• A digital switch to connect data from one input
source to one of n outputs.
• Usually implemented by using n-to-2n binary
decoders where the decoder’s enable line is
used for data input of the demultiplexer.

5–39 ELEC 335, Digital Logic Design, UAE University

 1-to-4 Demultiplexer
Y0 = D.S1'.S0' S1 So Y0 Y1 Y2 Y3
2x4
S1 Y1 = D.S1'.S0 0 0 D 0 0 0
Decoder
0 1 0 D 0 0
S0 Y2 = D.S1.S0'
1 0 0 0 D 0
E Y3 = D.S1.S0 1 1 0 0 0 D

D
Outputs

Y0 = D.S1'.S0'
Y1 = D.S1'.S0
Data D demux
Y2 = D.S1.S0'
Y3 = D.S1.S0

S1 S0
select

5–40 ELEC 335, Digital Logic Design, UAE University

 A0
A1
Demultiplexers
A2
Determine the outputs, given the
inputs shown. G1
G2A LOW
The output logic is opposite to the input G2B LOW
because of the active-LOW convention. (Red
shows the selected line). Y0
DEMUX Y1
Y
Data A0 0

Y2
Y
select A1 1

lines A2
Y
2

Data
Y3
Y
Y4
3

Y outputs
Enable G1 4

G2A
Y
5
Y5
inputs Y
G2B 6

Y6
Y
7

74LS138 Y7
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 Mux-Demux Application Example

This enables sharing a single communication

line among a number of devices.
At any time, only one source and one
destination can use the communication line.

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 Selected Key Terms

Full-adder A digital circuit that adds two bits and an input

carry bit to produce a sum and an output carry.
Cascading Connecting two or more similar devices in a
manner that expands the capability of one device.
Ripple carry A method of binary addition in which the output
carry from each adder becomes the input carry of
the next higher order adder.

ELEC 335, Digital Logic Design, UAE University

 Selected Key Terms

Decoder A digital circuit that converts coded information into

a familiar or noncoded form.
Encoder A digital circuit that converts information into a
coded form.
Priority An encoder in which only the highest value input
encoder digit is encoded and any other active input is ignored.
Multiplexer A circuit that switches digital data from several input
(MUX) lines onto a single output line in a specified time
sequence.
Demultiplexer A circuit that switches digital data from one input line
(DEMUX) onto a several output lines in a specified time
sequence. ELEC 335, Digital Logic Design, UAE University
4. Assume you want to decode the binary number 0011 with
an active-LOW decoder. The missing gate should be
a. an AND gate A0

?
A1 X
b. an OR gate
A2
c. a NAND gate
A3
d. a NOR gate

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7. The decimal-to-binary encoder shown does not have a
zero input. This is because
a. when zero is the input, 1
A0
all lines should be LOW 2
3
A1
b. zero is not important
4
5 A2
c. zero will produce 6
7
illegal logic levels 8
A3
9
d. another encoder is used
for zero

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5. Assume you want to decode the binary number 0011 with
an active-HIGH decoder. The missing gate should be
a. an AND gate A0

?
A1 X
b. an OR gate
A2
c. a NAND gate
A3
d. a NOR gate

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8. If the data select lines of the MUX are S1S0 = 11, the
output will be
a. LOW MUX
S0 0
b. HIGH Data
1
select S1
c. equal to D0 D0 0 Data
D1 1 output
Data
d. equal to D3 D
inputs D2 2
3 3

ELEC 335, Digital Logic Design, UAE University