MKV-TEMPLATE for IPCC (26.04.

2022) Annexure-III

Embedded System Design Semester 06

Course Code BEC601 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2:0 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours
Examination nature (SEE) Theory
Course objectives:
● Identify various components, their purpose, and their application to the embedded system's
applicability.
● Program various embedded components using the embedded C program.
● Understand the embedded system's real-time operating system and its application in IoT
● Understand the fundamentals of ARM-based systems, including architecture and its units like
registers , debug interface, stack, MPU, Interrupts etc
● Use the various instructions to program the ARM controller.

Teaching-Learning Process (General Instructions)

These are sample Strategies; that teachers can use to accelerate the attainment of the various course outcomes.
1. In addition to the traditional lecture method, different types of innovative teaching methods
may be adopted so that the delivered lessons shall develop students’ theoretical and applied
Mathematical skills.
2. Provide real-life examples.
3. Support and guide the students for self–study.
4. You will assign homework, grading assignments and quizzes, and documenting students'
progress.
5. Encourage the students to group learning to improve their creative and analytical skills.
6. Show short related video lectures in the following ways:
● As an introduction to new topics (pre-lecture activity).
● As a revision of topics (post-lecture activity).
● As additional examples (post-lecture activity).
● As an additional material of challenging topics (pre-and post-lecture activity).
● As a model solution of some exercises (post-lecture activity).
MODULE-1
Introduction to Embedded System: What is an Embedded Systems? Embedded systems Vs General
computing systems, History of Embedded Systems, Classification of Embedded systems, Major
Application Areas of Embedded Systems. Purpose of Embedded Systems, The Typical Embedded
System, Microprocessor Vs Microcontroller, Differences between RISC and CISC, Harvard V/s Von-
Neumann Processor/Controller Architecture, Big-endian V/s Little-endian processors, Memory (ROM
and RAM types), Sensors & Actuators, The I/O Subsystem – I/O Devices, Light Emitting Diode (LED), 7-
Segment LED Display, Optocoupler, Relay, Piezo buzzer, Push button switch, Communication Interfaces,
On-board Communication Interface, External Communication Interface, Embedded Firmware, Other
System Components
(Text 1: All the Topics from Ch-1 and Ch-2.)
MODULE-2
Embedded System Design Concepts: Characteristics and Quality Attributes of Embedded Systems,
Operational and non-operational quality attributes, Embedded Systems-Application and Domain
specific, Hardware Software Co-Design and Program Modeling (excluding UML), Embedded firmware
design and development (excluding C language).

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Text 1: Ch-3, Ch-4 (4.1, 4.2.1 and 4.2.2 only), Ch-7 (Sections 7.1, 7.2 only), Ch-9 (Sections 9.1, 9.2,
9.3.1, 9.3.2 only)
MODULE-3
RTOS and IDE for Embedded System Design: Operating System basics, Types of operating systems,
Task, process and threads (Only POSIX Threads with an example program), Thread preemption,
Preemptive Task scheduling techniques, Task Communication, Task synchronization issues – Racing and
Deadlock. How to choose an RTOS, Integration and testing of Embedded hardware and firmware,
Embedded system Development Environment – Block diagram (excluding Keil).
(Text 1: Ch-10 (Sections 10.1, 10.2, 10.3, 10.5.2 , 10.7, 10.8.1.1, 10.8.1.2 only), Ch-12, Ch-13 (a block
diagram before 13.1, only).
MODULE-4
ARM Embedded Systems:
Introduction, RISC design philosophy, ARM design philosophy, Embedded system hardware – AMBA bus
protocol, ARM bus technology, Memory, Peripherals, Embedded system software – Initialization (BOOT)
code, Operating System, Applications.
ARM Processor Fundamentals, ARM core dataflow model, registers, current program status register,
Pipeline, Exceptions, Interrupts and Vector Table, Core extensions.
Text 2: Chapter 1, 2
MODULE-5
Introduction to the ARM Instruction set: Introduction, Data processing instructions, Load – Store
instruction, Software interrupt instructions, Program status register instructions, Loading constants,
ARMv5E extensions, Conditional Execution.
Text 2: Chapter 3

PRACTICAL COMPONENT OF IPCC

Conduct the following experiments on an ARM CORTEX M3 evaluation board to learn Assembly
Language Program and using evaluation version of Embedded 'C' & Keil uVision-4 tool/compiler.

Sl.NO Experiments
1 Write a program to find the sum of the first 10 integer numbers.
2 Write an Assembly Language Program (ALP) to i) Multiply two 16-bit numbers. ii) Add two
32-bit numbers.
3 Write a program to find the factorial of a number.
4 Write a program to add an array of 16 bit numbers and store the 32 bit result in internal RAM.
5 Write a program to find the square of a number (1 to 10) using a look-up table.
6 Write a program to find the largest or smallest number in an array of 32 numbers.
7 Write a program to arrange a series of 32 bit numbers in ascending/descending order.
8 Write a program to count the number of ones and zeros in two consecutive memory locations.
9 Interface a Stepper motor and rotate it in clockwise and anti-clockwise direction.

10 Interface a DAC and generate Triangular and Square waveforms.

11 Display the Hex digits 0 to F on a 7-segment LED interface, with a suitable delay in between.

12 Interface a simple Switch and display its status through Relay, Buzzer and LED

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Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:
● Describe the architectural features and instructions of 32-bit microcontroller ARM Cortex M3.
● Apply the knowledge gained for Programming ARM Cortex M3 for different applications.
● Understand the basic hardware components and their selection method based on the
characteristics and attributes of an embedded system.
● Understand the hardware software co-design and firmware design approaches.
● Explain the need of real time operating system for embedded system applications.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the
SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be
deemed to have satisfied the academic requirements and earned the credits allotted to each subject/
course if the student secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

CIE for the theory component of the IPCC (maximum marks 50)
● IPCC means practical portion integrated with the theory of the course.
● CIE marks for the theory component are 25 marks and that for the practical component is 25
marks.
● 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests (Two
Tests, each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other
assessment methods mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the
syllabus and the second test after covering 85-90% of the syllabus.
● Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for the
theory component of IPCC (that is for 25 marks).
● The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of IPCC.
CIE for the practical component of the IPCC
● 15 marks for the conduction of the experiment and preparation of laboratory record, and 10 marks
for the test to be conducted after the completion of all the laboratory sessions.
● On completion of every experiment/program in the laboratory, the students shall be evaluated
including viva-voce and marks shall be awarded on the same day.
● The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of
all experiments’ write-ups are added and scaled down to 15 marks.
● The laboratory test (duration 02/03 hours) after completion of all the experiments shall be
conducted for 50 marks and scaled down to 10 marks.
● Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 25 marks.
● The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the IPCC.
SEE for IPCC
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.

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MKV-TEMPLATE for IPCC (26.04.2022) Annexure-III

4. Marks scored by the student shall be proportionally scaled down to 50 Marks

The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will
have a CIE component only. Questions mentioned in the SEE paper may include questions from the
practical component.
Suggested Learning Resources:
Text Books
1. Shibu K V, “Introduction to Embedded Systems”, Tata McGraw Hill Education
2. Andrew N Sloss, Dominic System and Chris Wright, “ARM System Developers Guide”, Elsevier,
Morgan Kaufman publisher, 1st Edition, 2008.
Reference Book
1. Raj Kamal, “Embedded Systems: Architecture and Programming”, Tata McGraw Hill, 2008.

Web links and Video Lectures (e-Resources):

1. https://archive.nptel.ac.in/courses/106/105/106105193/
2. https://developer.arm.com/documentation/dui0068/b/ARM-Instruction-Reference
3. https://www.udemy.com/course/introduction-to-arm-cortex-m3-and-m4-processors/
4. www.Nuvoton .com/websites on Advanced ARM Cortex Processors
5. https://alison.com/tag/embedded-systems
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
Programming Assignments / Mini Projects can be given to improve programming skills

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VLSI Design and Testing Semester 5

Course Code BEC602 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 4:0:0:0 SEE Marks 50
Total Hours of Pedagogy 50 Hours Total Marks 100
Credits 04 Exam Hours 3 Hours
Examination nature (SEE) Theory
Course objectives:
1.This course deals with analysis and design of digital CMOS integrated circuits.

2. The course emphasizes on basic theory of digital circuits, design principles and techniques for
digital design blocks implemented in CMOS technology.

3. This course will also cover switching characteristics of digital circuits along with delay and power
estimation.
4. Understanding the CMOS sequential circuits and memory design concepts.

5.Explore the knowledge of VLSI Design flow and Testing

Teaching-Learning Process (General Instructions)

These are sample Strategies; that teachers can use to accelerate the attainment of the various course outcomes.
1. Lecture method (L) does not mean only traditional lecture method, but different type of teaching methods may be adopted
to develop the outcomes.
2. Show Video/animation films to explain the different concepts of Digital Signal Processing
3. Encourage collaborative (Group) Learning in the class
4. Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes critical thinking
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking skills such as the
ability to evaluate, generalize, and analyse information rather than simply recall it.
6. Topics will be introduced in a multiple representation.
7. Show the different ways to solve the same problem and encourage the students to come up with their own creative ways
to solve them.
8. Discuss how every concept can be applied to the real world - and when that's possible, it helps improve the students'
understanding.
9. Adopt Flipped class technique by sharing the materials / Sample Videos prior to the class and have discussions on the
that topic in the succeeding classes.

MODULE-1
Introduction to CMOS Circuits: Introduction, MOS Transistors, MOS Transistor switches, CMOS
Logic, Alternate Circuit representation, CMOS-nMOS comparison.

[Text 1: 1.1,1.2,1.3,1.4,1.5.1.6.]

Teaching-Learning Process: Chalk and talk method, YouTube videos, Power point
presentation RBT Level: L1, L2

MODULE-2
MOS Transistor Theory: n-MOS enhancement transistor, p-MOS transistor, Threshold Voltage,
Threshold voltage adjustment, Body effect, MOS device design equations, V-I characteristics, CMOS
inverter DC characteristics, Influence of βn / βp ratio on transfer characteristics, Noise margin,
Alternate CMOS inverters. Transmission gate DC characteristics. Latch-up in CMOS.
[Text 1: 2.1,2.2,2.3,2.4,2.5.2.6.]

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Teaching-Learning Process:
Chalk and talk method/Power point presentation RBT Level: L1, L2, L3.

MODULE-3
CMOS Process Technology: Silicon Semiconductor Technology, CMOS Technologies, Layout
Design Rules. [Text 1: 3.1,3.2,3.3.]
Circuit Characterization and Performance Estimation: Introduction, Resistance Estimation,
Capacitance Estimation, Switching Characteristics, CMOS gate transistor sizing, Determination of
conductor size, Power consumption, Charge sharing, Scaling of MOS transistor sizing, Yield.
[Text 1: 4.1,4.2,4.3,4.4,4.5.4.6.4.7,4.8,4.9,4.10]

Teaching-Learning Process:
Chalk and talk method/Power point presentation, YouTube Videos RBT Level: L1, L2, L3.

MODULE-4
CMOS Circuit and Logic Design: Introduction, CMOS Logic structures, CMOS Complementary logic,
Pseudo n-MOS logic, Dynamic CMOS logic, Clocked CMOS Logic, Cascade Voltage Switch logic, Pass
transistor Logic, Electrical and Physical design of Logic gates, The inverter, NAND and NOR gates, Body
effect, Physical Layout of Logic gates, Input output Pads.

[Text 1: 5.1,5.2,5.2.1, , 5.2.2, 5.2.3, 5.2.4, 5.2.6, 5.2.8, 5.3,5.3.1,5.3.2, 5.3.4 ,5.3.8,5.5]

Teaching-Learning Process:
Chalk and talk method, YouTube videos, Power point presentation RBT Level: L1, L2, L3.
MODULE-5
Sequential MOS Logic Circuits: Introduction, Behaviour of Bistable Elements (Excluding
Mathematical analysis) SR Latch Circuit, Clocked Latch and Flip-Flop Circuits, Clocked SR Latch,
Clocked JK Latch.
[Text2: 8.1, 8.2, 8.3, 8.4]
Structured Design and Testing: Introduction, Design Styles, Testing
[Text1: 6.1, 6.2. 6.5]

Teaching-Learning Process:
Chalk and talk method/Power point presentation RBT Level: L1, L2, L3

Text Books:
1. Principals of CMOS VLSI Design A System approach Neil H E Weste and Kamran
Eshraghain . Addition Wisley Publishing company.
2. “CMOS Digital Integrated Circuits: Analysis and Design”, Sung Mo Kang & Yosuf
Leblebici, Third Edition, Tata McGraw-Hill.
Reference Books:
1. “CMOS VLSI Design- A Circuits and Systems Perspective”, Neil H E Weste, and David
Money Harris 4th Edition, Pearson Education.
2. “Basic VLSI Design”, Douglas A Pucknell, Kamran Eshraghian, 3rd Edition, Prentice Hall of
India publication, 2005.

Course Outcomes: After completing the course, the students will be able to

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CO1 Apply the fundamentals of semiconductor physics in MOS transistors and analyze the
geometrical effects of MOS transistors
CO2 Design and realize combinational, sequential digital circuits and memory cells in CMOS
logic.
CO3 Analyze the synchronous timing metrics for sequential designs and structured design basics.
CO4 Understand designing digital blocks with design constraints such as propagation delay
and dynamic power dissipation.
C05 Understand the concepts of Sequential circuits design and VLSI testing

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 Annexure-II 1

Multimedia Communication Semester 6

Course Code BCE613A CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours
Examination type (SEE) Theory
Course objectives:
● Gain fundamental knowledge in understanding the basics of different multimedia
Networks and applications.
● Understand digitization principle techniques required to analyze different media
Types.
● Analyze compression techniques required to compress text and image and gain
Knowledge of DMS.
● Analyze compression techniques required to compress audio and video.
● Gain fundamental knowledge about multimedia communication across different
Networks.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Lecture method (L) does not mean only the traditional lecture method, but a different type of
teaching method may be adopted to develop the outcomes.
2. Show Video/animation films to explain the functioning of various techniques.
3. Encourage collaborative (Group) Learning in the class.
4. Ask at least three HOTS(Higher-order Thinking)questions in the class, which promotes critical
thinking
5. Topics will be introduced in multiple representations.
6. Discuss how every concept can be applied to the real world-and when that's possible, it helps improve
the students' understanding.

Module-1
Multimedia Communications: Introduction, Multimedia information representation, Multimedia
networks, multimedia applications, Application and networking terminology.
(Chapter 1 of Text1)
Module-2
Information Representation: Introduction, Digitization principles, Text, Images, Audio and Video. (Chapter
2 of Text 1
Module-3
Text and Image Compression: Introduction, Compression principles, text compression, image Compression.
(Chapter 3 of Text 1 )

Module-4
Audio and video compression: Introduction, Audio compression, video compression, video compression
principles, video compression. (Chapter 4 of Text 1)
Module-5
Multimedia Information Networks: Introduction, LANs, Ethernet, Token ring, Bridges, FDDI (Chapter 8.1
to8.6of Text 1).

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 Annexure-II 2

Course outcome (Course Skill Set)

At the end of the course, the student will be able to :
1. Understand the basics of multimedia Communication and applications
2. Analyze media types to represent them in digital form.
3. Apply the compression techniques on text, images, audio and video.
4. Understand multimedia information networks.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50)
and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). A
student shall be deemed to have satisfied the academic requirements and earned the credits allotted
to each subject/ course if the student secures a minimum of 40% (40 marks out of 100) in the sum
total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken
together.

Continuous Internal Evaluation:

● For the Assignment component of the CIE, there are 25 marks and for the Internal Assessment
Test component, there are 25 marks.
● The first test will be administered after 40-50% of the syllabus has been covered, and the second
test will be administered after 85-90% of the syllabus has been covered
● Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based
then only one assignment for the course shall be planned. The teacher should not conduct two
assignments at the end of the semester if two assignments are planned.
● For the course, CIE marks will be based on a scaled-down sum of two tests and other methods
of assessment.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for
the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored shall be proportionally reduced to 50 marks.

Suggested Learning Resources:

Textbooks:
Multimedia Communications –Fred Halsall, Pearson Education,2001,ISBN-978813170994
ReferenceBooks:
1. Multimedia: Computing, Communications and Applications- Raif Steinmetz, Klara Nahrstedt, Pearson
Education, 2002, ISBN-978817758
2. FundamentalsofMultimedia–Ze-NianLi,MarkSDrew,andJiangchuanLiu.
Web links and Video Lectures (e-Resources):

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 Annexure-II 3

● Implementation of compression algorithms using MATLAB/any open source tools (Python, Scilab,
etc.)

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

● https://www.slideshare.net
NPTEL Video Lectures
● https://archive.nptel.ac.in/courses/117/105/117105083/
● Multimedia Computing lecture: Communications & Networking –You Tube

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 Annexure-II 3

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and
for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The student
is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100) in the
sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken
together.

Continuous Internal Evaluation:

• There are 25 marks for the CIE's Assignment component and 25 for the Internal Assessment Test
component.
• Each test shall be conducted for 25 marks. The first test will be administered after 40-50% of the
coverage of the syllabus, and the second test will be administered after 85-90% of the coverage
of the syllabus. The average of the two tests shall be scaled down to 25 marks
• Any two assignment methods mentioned in the 22OB2.4, if an assignment is project-based then
only one assignment for the course shall be planned. The schedule for assignments shall be
planned properly by the course teacher. The teacher should not conduct two assignments at the
end of the semester if two assignments are planned. Each assignment shall be conducted for 25
marks. (If two assignments are conducted then the sum of the two assignments shall be scaled
down to 25 marks)
• The final CIE marks of the course out of 50 will be the sum of the scale-down marks of tests and
assignment/s marks.
Internal Assessment Test question paper is designed to attain the different levels of Bloom’s taxonomy
as per the outcome defined for the course.

Semester-End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for
the course (duration 03 hours).
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
Suggested
4. MarksLearning Resources:
scored shall be proportionally reduced to 50 marks.

Text Book:
1 Digital Systems Design Using Verilog First Edition, Charles H. Roth, Jr. The University of
Texas at Austin, Lizy Kurian John The University of Texas at Austin, Byeong Kil Lee The
University of Texas at San Antonio

Reference Books:
1. Advanced FPGA Design Architecture, Implementation, and Optimization Steve Kilts
Spectrum
2. ASIC and FPGA Verification: A guide to component Modelling.
Richard Munden, Morgan Kaufmann Publishers is an imprint of Elsevier

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VLSI Design and Testing LAB

Course Code BECL606 CIE Marks 50
Teaching Hours/Week (L: T: P: S) 0:0:2:0 SEE Marks 50
Credits 1 Exam Hours 3
Course objectives:
This laboratory course enables students to
• Design, model, simulate and verify digital circuits.
• Perform ASIC design flow and understand the process of synthesis, synthesis constraints
and evaluating the synthesis reports to obtain optimum gate level netlist.
• Perform RTL-GDSII flow and understand the ASIC Design flow.

Sl.No Experiments
.
1 Design a 4-Bit Adder
• Write a Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and generate the gate level netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required
2 4-Bit Shift and add Multiplier
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the gate level netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells,
Power requirement and Total area required
3 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if statement for
ALU Behavioral Modeling
• Write Verilog description
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path
4 Flip-Flops ( D,SR and JK )
• Write the Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the gate level netlist.
From the report gate level netlist identify Critical path, Maximum delay, Total number of
cells, Power requirement and Total area required.
• Verify the functionality using Gate level netlist and compare the results at RTL and
gate level netlist.
5 Four bit Synchronous MOD-N counter with Asynchronous reset
• Write Verilog Code
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
Identify Critical path
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• Verify the functionality using Gate level netlist and compare the results at RTL and
gate level netlist.

6 a) Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set
the widths of inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected
technology. Carry out the following:

i. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns
and the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
ii. From the simulation result compute tpHL, tpLH and td for all three geometrical
settings of width?
iii. Tabulate the results of delay and find the best geometry for minimum delay for
CMOS inverter.

b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for
DRC and LVS, extract parasitic and perform post layout simulations, compare the results
with pre layout simulations and compare the results.

7 Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NOR gate and also find
out the delay td for all four possible combinations of input vectors. Table the results.
Increasethe drive strength to 2X and 4X and tabulate the results.

8
Construct the schematic of the Boolean Expression

Y= AB+CD+E using CMOS Logic. Verify the functionality of the expression find out the
delay td for some combination of input vectors. Tabulate the results.

9 a) Construct the schematic of Common Source Amplifier with PMOS Current Mirror Load
and find its transient response and AC response? Measure the Unit Gain Bandwidth (UGB),
amplification factor by varying transistor geometries, study the impact of variation in width
to UGB.

b) Draw Layout of common source amplifier, use optimum layout methods. Verify for DRC
& LVS, extract parasitic and perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.
10 a) Construct the schematic of two-stage operational amplifier and measure the following:
i. Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and phase margin with and
without coupling capacitance iv. Use the op-amp in the inverting and non-inverting
configuration and verify its functionality. v. Study the UGB, 3dB bandwidth, gain and power
requirement in op-amp by varying the stage wise transistor geometries and record the
observations.

b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in
180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained
in part a. Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform
post layout simulations, compare the results with pre-layout simulations and perform the
comparative analysis.
Demonstration Experiments ( For
CIE )

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11 UART
• Write Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist, Identify Critical path

12 Design and characterize 6T binary SRAM cell and measure the following:
• Read Time, Write Time, SNM, Power
• Draw Layout of 6T SRAM, use optimum layout methods. Verify for DRC & LVS, extract
parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.
Course outcomes (Course Skill Set):
On the completion of this laboratory course, the students will be able to:
1. Design and simulate combinational and sequential digital circuits using Verilog HDL.
2. Understand the synthesis process of digital circuits using EDA tool.
3. Perform ASIC design flow and understand the process of synthesis, synthesis constraints
and evaluating the synthesis reports to obtain optimum gate level netlist.
4. Design and simulate basic CMOS circuits like inverter, NOR gate and any Boolean
expression .
5. Perform RTL_GDSII flow and understand the stages in ASIC design.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE)
is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student
shall be deemed to have satisfied the academic requirements and earned the credits allotted to each
course. The student has to secure not less than 35% (18 Marks out of 50) in the semester-end
examination (SEE).
Continuous Internal Evaluation (CIE):
CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
• Each experiment to be evaluated for conduction with observation sheet and record write-up.
Rubrics for the evaluation of the journal/write-up for hardware/software experiments designed by
the faculty who is handling the laboratory session and is made known to students at the
beginning of the practical session.
• Record should contain all the specified experiments in the syllabus and each experiment write-up
will be evaluated for 10 marks.
• Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
• Weightage to be given for neatness and submission of record/write-up on time.
• Department shall conduct 02 tests for 100 marks, the first test shall be conducted after the 8th
week of the semester and the second test shall be conducted after the 14th week of the semester.
• In each test, test write-up, conduction of experiment, acceptable result, and procedural
knowledge will carry a weightage of 60% and the rest 40% for viva-voce.
• The suitable rubrics can be designed to evaluate each student’s performance and learning
ability. Rubrics suggested in Annexure-II of Regulation book
• The average of 02 tests is scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and average marks of two tests
is the total CIE marks scored by the student.

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Semester End Evaluation (SEE):
SEE marks for the practical course is 50 Marks.
SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed
by the University
All laboratory experiments are to be included for practical examination.
(Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be
strictly adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be

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decided jointly by examiners.

Students can pick one question (experiment) from the questions lot prepared by the internal /external
examiners jointly.
Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by
examiners.
General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and
result in -60%, Viva-voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks
and scored marks shall be scaled down to 50 marks (however, based on course type, rubrics shall be
decided by the examiners).
Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be
made zero.
The duration of SEE is 03 hours.
Rubrics suggested in Annexure-II of Regulation book

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 IoT (Internet of Things) Lab Semester 6
Course Code BEC657C CIE Marks 50
Teaching Hours/Week (L:T:P: S) 0:0:2:0 SEE Marks 50
Credits 01 Exam Hours 3
Examination type (SEE) Practical
Course Objectives:
This course will enable students to
 To impart necessary and practical knowledge of components of the Internet of Things
 To develop skills required to build real-life IoT-based projects.

Sl.No. Experiments
1(i) To interface LED/Buzzer with Arduino /Raspberry Pi and write a program to ‘turn ON’ LED
for 1 sec after every 2 seconds.
1(ii) To interface the Push button/Digital sensor (IR/LDR) with Arduino /Raspberry Pi and write
a program to ‘turn ON’ LED when a push button is pressed or at sensor detection.
2 (i) To interface the DHT11 sensor with Arduino /Raspberry Pi and write a program to print
temperature and humidity readings.
2(ii) To interface OLED with Arduino /Raspberry Pi and write a program to print its temperature
and humidity readings.
3 To interface the motor using a relay with Arduino /Raspberry Pi and write a program to ‘turn
ON’ the motor when a push button is pressed.
4(i) Write an Arduino/Raspberry Pi program to interface the Soil Moisture Sensor.
4(ii) Write an Arduino/Raspberry Pi program to interface the LDR/Photo Sensor.
5 Write a program to interface an Ultrasonic Sensor with Arduino /Raspberry Pi.
6 Write a program on Arduino/Raspberry Pi to upload temperature and humidity data
to thingspeak cloud.
7 Write a program on Arduino/Raspberry Pi to retrieve temperature and humidity data
from thingspeak cloud.
8 Write a program to interface LED using Telegram App.
9 Write a program on Arduino/Raspberry Pi to publish temperature data to the MQTT broker.
10 Write a program to create a UDP server on Arduino/Raspberry Pi and respond with humidity
data to the UDP client when requested.
11 Write a program to create a TCP server on Arduino /Raspberry Pi and respond with humidity
data to the TCP client when requested.
12 Write a program on Arduino / Raspberry Pi to subscribe to the MQTT broker for temperature
data and print it.
Course outcomes (Course Skill Set):
At the end of the course, the student will be able to:
 Explain the Internet of Things and its hardware and software components.
 Interface I/O devices, sensors & communication modules.
 Remotely monitor data and control devices.

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  Develop real-life IoT-based projects.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the SEE minimum
passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be deemed to have satisfied the
academic requirements and earned the credits allotted to each subject/ course if the student secures a minimum of
40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End
Examination) taken together.

Continuous Internal Evaluation (CIE):

CIE marks for the practical course are 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment will be evaluated for conduction with an observation sheet and record write-up. Rubrics for
the evaluation of the journal/write-up for hardware/software experiments are designed by the faculty who is
handling the laboratory session and are made known to students at the beginning of the practical session.
 The record should contain all the specified experiments in the syllabus and each experiment write-up will be
evaluated for 10 marks.
 The total marks scored by the students are scaled down to 30 marks (60% of maximum marks).
 Weightage is to be given for neatness and submission of record/write-up on time.
 The department shall conduct a test of 100 marks after the completion of all the experiments listed in the
syllabus.
 In a test, test write-up, conduction of experiment, acceptable result, and procedural knowledge will carry a
weightage of 60% and the rest 40% for viva-voce.
 The suitable rubrics can be designed to evaluate each student’s performance and learning ability.
 The marks scored shall be scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and marks of a test is the total CIE marks
scored by the student.
Semester End Evaluation (SEE):
 SEE marks for the practical course are 50 Marks.
 SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed
by the Head of the Institute.
 The examination schedule and names of examiners are informed to the university before the conduction of
the examination. These practical examinations are to be conducted within the schedule mentioned in the
university's academic calendar.
 All laboratory experiments are to be included for practical examination.
 (Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be
strictly adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be
decided jointly by examiners.
 Students can pick one question (experiment) from the questions lot prepared by the examiners jointly.
 Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by examiners.
 General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and result in -60%,
Viva-voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks and scored marks shall
be scaled down to 50 marks (however, based on course type, rubrics shall be decided by the examiners)
 Change of experiment is allowed only once and 15% of Marks allotted to the procedure part are to be made
zero.

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 The minimum duration of SEE is 02 hours

Suggested Learning Resources:

 Vijay Madisetti, Arshdeep Bahga, Internet of Things. "A Hands-on Approach", University Press
 Dr. SRN Reddy, Rachit Thukral, and Manasi Mishra, "Introduction to Internet of Things: A Practical
Approach", ETI Labs
 Pethuru Raj and Anupama C Raman, "The Internet of Things: Enabling Technologies, Platforms, and
Use Cases", CRC Press
 Jeeva Jose, "Internet of Things", Khanna Publishing House, Delhi
 Adrian McEwen, "Designing the Internet of Things", Wiley
 Raj Kamal, "Internet of Things: Architecture and Design", McGraw Hill

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