Switching Theory & Logic Design Chapter 4

1403271-4 Combinational Logic

Ch1: Digital Systems and Binary Numbers

Ch2: Boolean Algebra and Logic Gates
Ch3: Gate-Level Minimization
Ch4: Combinational Logic
Ch5: Synchronous Sequential Logic
Ch6: Registers and Counters

Chapter 4
Combinational Logic
Switching Theory & Logic Design
1403271-4

Prof. Adnan Gutub

Main Ref: M. Morris Mano and Michael D. Ciletti, Digital Design, Prentice Hall

Content
Combinational Logic
• 4.1 Introduction 125
• 4.2 Combinational Circuits 125
• 4.3 Analysis Procedure 126
• 4.4 Design Procedure 129
• 4.5 Binary Adder–Subtractor 133
• 4.6 Decimal Adder 144
• 4.7 Binary Multiplier 146
• 4.8 Magnitude Comparator 148
• 4.9 Decoders 150
• 4.10 Encoders 155
• 4.11 Multiplexers 158
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Switching Theory & Logic Design Chapter 4
1403271-4 Combinational Logic

4.1 Introduction
• Logic Circuits: Combinational or Sequential

• Combinational
– No Memory (No Storage)
– Outputs fully based on combination of inputs

• Sequential
– Memory (Storage) + Combinational Logic
3

4.2 Combinational Circuits

Analysis
Design

Sequential

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4.3 Analysis Procedure

1. Label all gate outputs as functions of input
variables.
– Use arbitrary symbols—with meaningful names.
2. Label gates as functions of input variables.
Find the Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the
outputs of the circuit are obtained.
4. Obtain output Boolean functions in terms of
input variables.
5

Analysis Example
Find F1 & F2 in terms of inputs?

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Truth Table

4.4 Design Procedure

• Determine required number of inputs and
outputs → assign a symbol to each.

• Derive truth table relating inputs and outputs.

• Simplify outputs Boolean function.

• Derive Logic Diagram

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Code Conversion Example

Code
Conversion
Example

•Utilize Don’t Care

•Simplify Functions

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Code Conversion Example Logic Diagram

11

4.5 Binary Adder–Subtractor

• simple addition consists of four possible
elementary operations:
• 0+0 = 0
• 0+1 = 1
• 1+0 = 1
• 1+1 = 10 ← Sum has Carry
– Half Adder (two ‘2’ input bits)
– Full Adder (three ‘3’ input bits)
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Half Adder (Top Overview)

• Binary addition used frequently
• Addition Development:
– Half-Adder (HA), a 2-input bit-wise addition
functional block,
– Full-Adder (FA), a 3-input bit-wise addition
functional block,
– Ripple Carry Adder, an iterative array to perform
binary addition, and
– Carry-Look-Ahead Adder (CLA), a hierarchical
structure to improve performance.
13

Functional Block: Half-Adder

A 2-input, 1-bit width binary adder that performs the

following computations:
X 0 0 1 1
+Y +0 +1 +0 +1
CS 00 01 01 10
A half adder adds two bits to produce a two-bit sum
The sum is expressed as a X Y C S
sum bit , S and a carry bit, C 0 0 0 0
The half adder can be specified 0 1 0 1
as a truth table for S and C ⇒
1 0 0 1
1 1 1 0

Chapter 4 14

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Logic Simplification: Half-Adder

The K-Map for S, C is: S Y C Y

This is a pretty trivial map!
By inspection: 0 11 0 1

X 12 3 X 2 13
S = X ⋅Y + X⋅Y = X ⊕ Y
S = (X + Y ) ⋅ (X + Y )
and
C = X ⋅Y
C = ( ( X⋅ Y ) )
These equations lead to several implementations.

Chapter 4 15

Half Adder Implementation

Chapter 4 16

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Functional Block: Full-Adder

A full adder is similar to a half adder, but includes a

carry-in bit from lower stages. Like the half-adder, it
computes a sum bit, S and a carry bit, C.
• For a carry-in (Z) of Z 0 0 0 0
0, it is the same as X 0 0 1 1
the half-adder: +Y +0 +1 +0 +1
CS 00 01 01 10
• For a carry- in
(Z) of 1: Z 1 1 1 1
X 0 0 1 1
+Y +0 +1 +0 +1
CS 01 10 10 11
Chapter 4 17

Logic Optimization: Full-Adder

Full-Adder Truth Table: X Y Z C S

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
Full-Adder K-Map: 1 1 0 1 0
1 1 1 1 1

S Y C Y

0
11 3
12 0 1
13 2

X 14 17 X 15 17 16
5 6 4

Z Z

Chapter 4 18

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Equations: Full-Adder

From the K-Map, we get:

S = XYZ+ XY Z+ XYZ+ XYZ
C = XY+X Z+YZ
The S function is the three-bit XOR function (Odd
Function):
S = X⊕ Y⊕ Z
The Carry bit C is 1 if both X and Y are 1 (the sum is
2), or if the sum is 1 and a carry-in (Z) occurs. Thus C
can be re-written as:
C = X Y + (X ⊕ Y ) Z
The term X·Y is carry generate.
The term X⊕Y is carry propagate.

Chapter 4 19

Full Adder Implementation

Chapter 4 20

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Full Adder as 2-Half Adders

21

Binary Adders

To add multiple operands, we “bundle” logical signals

together into vectors and use functional blocks that
operate on the vectors
Description Subscript Name
Example: 4-bit ripple carry 3210
adder: Adds input vectors Carry In 0110 Ci
A(3:0) and B(3:0) to get Augend 1011 Ai
a sum vector S(3:0) Addend 0011 Bi
Note: carry out of cell i Sum 1110 Si
becomes carry in of cell Carry out 0011 Ci+1
i+1

Chapter 4 22

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4-bit Ripple-Carry Binary Adder

A four-bit Ripple Carry Adder made from four

1-bit Full Adders:
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1
FA FA FA FA C0

C4 S3 S2 S1 S0

Chapter 4 23

Carry Propagation → Carry Lookahead Adder

Chapter 4 24

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Binary Subtraction: Signed Integers

Positive numbers and zero can be represented by
unsigned n-digit, radix r numbers. We need a
representation for negative numbers.
To represent a sign (+ or –) we need exactly one more
bit of information (1 binary digit gives 21 = 2 elements
which is exactly what is needed).
Since computers use binary numbers, by convention,
the most significant bit is interpreted as a sign bit:
s an–2 … a2a1a0
where:
s = 0 for Positive numbers
s = 1 for Negative numbers
and ai = 0 or 1 represent the magnitude in some form.
Chapter 4 25

Signed Integer Representations

Signed-Magnitude – here the n – 1 digits are

interpreted as a positive magnitude.
Signed-Complement – here the digits are
interpreted as the rest of the complement of the
number. There are two possibilities here:
• Signed 1's Complement
Uses 1's Complement Arithmetic
• Signed 2's Complement
Uses 2's Complement Arithmetic

Chapter 4 26

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Signed Integer Representation Example

r =2, n=3

Number Sign -Mag. 1's Comp. 2's Comp.

+3 011 011 011
+2 010 010 010
+1 001 001 001
+0 000 000 000
–0 100 111 —
–1 101 110 111
–2 110 101 110
–3 111 100 101
–4 — — 100

Chapter 4 27

Signed-Magnitude Arithmetic

If the parity of the three signs is 0:

1. Add the magnitudes.
2. Check for overflow (a carry out of the MSB)
3. The sign of the result is the same as the sign of the
first operand.
If the parity of the three signs is 1:
1. Subtract the second magnitude from the first.
2. If a borrow occurs:
• take the two’s complement of result
• and make the result sign the complement of the
sign of the first operand.
3. Overflow will never occur.

Chapter 4 28

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Sign-Magnitude Arithmetic Examples

Example 1: 0010
+0101

Example 2: 0010
+1101

Example 3: 1010
− 0101

Chapter 4 29

Signed-Complement Arithmetic
Addition:
1. Add the numbers including the sign bits,
discarding a carry out of the sign bits (2's
Complement), or using an end-around carry (1's
Complement).
2. If the sign bits were the same for both
numbers and the sign of the result is different, an
overflow has occurred.
3. The sign of the result is computed in step 1.
Subtraction:
Form the complement of the number you are
subtracting and follow the rules for addition.
Chapter 4 30

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Signed 2’s Complement Examples

Example 1: 1101
+0011

Example 2: 1101
−0011

Chapter 4 31

Binary Subtractor

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2’s Complement Adder/Subtractor

Subtraction can be done by addition of the 2's Complement.
1. Complement each bit (1's Complement.)
2. Add 1 to the result.
The circuit shown computes A + B and A – B:
For S = 1, subtract,
B A B A B A B A
the 2’s complement 3 3 2 2 1 1 0 0

of B is formed by using S

XORs to form the 1’s

comp and adding the 1
applied to C0.
C 3 C C 2 C 1 0
For S = 0, add, B is FA FA FA FA

passed through
unchanged C
4 S3 S S
2 S 1 0

Chapter 4 33

Overflow

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Overflow Detection

Overflow occurs if n + 1 bits are required to contain the

result from an n-bit addition or subtraction
Overflow can occur for:
• Addition of two operands with the same sign
• Subtraction of operands with different signs
Signed number overflow cases with correct result sign
0 0 1 1
+0 −1 − 0 +1
0 0 1 1
Detection can be performed by examining the result
signs which should match the signs of the top operand

Chapter 4 35

Overflow Detection
Signed number cases with carries Cn and Cn−1 shown for correct
result signs:
0 00 01 11 1
0 0 1 1
+ 0 −1 − 0 + 1
0 0 1 1
Signed number cases with carries shown for erroneous result signs
(indicating overflow):
0 10 11 01 0
0 0 1 1
+ 0 − 1 −0 + 1
1 1 0 0
Simplest way to implement overflow V = Cn + Cn − 1
This works correctly only if 1’s complement and the addition of the
carry in of 1 is used to implement the complementation! Otherwise
fails for − 10 ... 0
Chapter 4 36

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4.6 Decimal Adder: BCD Adder

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BCD Adder
C=K+Z8Z4+Z8Z2

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4.7 Binary Multiplication

The binary multiplication table is simple:

0∗0=0 | 1∗0=0 | 0∗1=0 | 1∗1=1
Extending multiplication to multiple digits:
Multiplicand 1011
Multiplier x 101
Partial Products 1011
0000 -
1011 - -
Product 110111

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4.7 Binary Multiplier

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4.8 Magnitude Comparator

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4.9 Decoders (3 x 8 Decoder)

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4.9 Decoders
3 x 8 Decoder

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Complemented Decoder
with Active Low Enable

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4 x 16 Decoder
made from two 3 x 8 decoders

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Implementation with Decoder

Ex: Full Adder Design
S(x,y,z) = ∑ (1,2,4,7) C(x,y,z) = ∑ (3,5,6,7)

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4.10 Encoders

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Priority Encoder

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Implementation of Priority Encoder

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4.11 Multiplexers
2 x 1 Mux

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4 x 1 Mux

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4-Bits 2x1 Mux

Quadruple 2x1
multiplexer

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Boolean Function Implementation

F(x,y,z) = ∑ (1,2,6,7)

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Example of Implementation with Mux

F(A,B,C,D)= ∑ (1,3,4,11,12,13,14,15)

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Three-State Gate (Tri-State Buffer)

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