Machine Structure II

ZAIRI HADJER

Chapter I: combinational circuits

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In this Chapter
I. Introduction
II. Definition.
III.Combinatorial circuits.
IV. Steps in designing a combinatorial circuit:
1. Establishing the truth table.
2. Simplifying logical functions.
3. Creating the logical diagram.

V. Study of some common combinatorial circuits:

1. Half-adder. 2. Full-adder.
3. Subtractor-adder (in two complement).
4. Decoders. 5. Multiplexers.
6. Priority encoders. 7. Demultiplexers.

- Other examples of combinatorial circuits.

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Chapter- 1 : introduction

Definition
• A logic circuit is defined as an electronic circuit
implementing one or more logical function(s). It is
defined by the interconnection of a set of logic gates
connecting outputs to inputs. Thus, overall, a logic circuit
can be schematized as a black box with inputs (binary)
and binary outputs (the logical functions). Of course, the
black box is composed of a set of interconnected logic
gates that can be schematized by a diagram called a logic
diagram.

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Chapter- 1 : introduction
Digital logic circuits
Digital circuits are classified as combinational or sequential.
• A combinational circuit’s outputs depend only on the current values of the inputs; in other
words, it combines the current input values to compute the output
• No Feedback between input and output.
• No memory
• A sequential circuit’s outputs depend on both current and previous values of the inputs; in
other words, it depends on the input sequence
• Feedback is present
• Memory is present
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Chapter- 1 : Combinational circuits
Example Which of the circuits in the following figure are combinational circuits
according to the rules of combinational composition?

Solution: Circuit (a) is combinational. (b) is not combinational, because there is a

cyclic path: the output of the XOR feeds back to one of its inputs. (c) is
combinational.
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Chapter- 1 : Combinational circuits
• Are specially designed using multiple interconnected logic gates such that the You should
output will be generated by computing the logical combinations of the
present input only. know
Basic gates
• Combinational circuit consist of :
Input variables
for ' n ' input variables, there will be 2N possible combinations..
Logic gates
Generate signals from the inputs to the output Universal gates
Output variables
For each combination of input, find the output values. there is one
possible output value.
Boolean laws

De-Morgans
Theorem

Kmaps
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Chapter- 1 : Combinational circuits
Classification of Combinational circuits

Are basically divided into 3 classes:

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Chapter- 1 : Combinational circuits
Applications of Combinational Circuit
Combinational circuits are fundamental building blocks in digital electronics and are widely used in various
applications. Here are some key applications of combinational circuits:

Arithmetic & Logic Operations (ALU)

Microprocessors (Intel, AMD, ARM) –Calculators (Casio, Texas Instruments)
Data Encoding & Decoding
Barcode & QR Code Scanners –Digital TV & Set-Top Boxes – Networking (Routers & Modems) –
Memory Addressing
RAM & Cache in Computers –SSD Controllers – Graphics Cards (NVIDIA, AMD)
Display Systems
Seven-Segment Displays in Digital Clocks & Elevators –LED Billboards & Scoreboards – Automobile Dashboards

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Chapter- 1 : Combinational circuits
Example Design a combinational logic circuit with three input Truth table of circuit
variables that will produce a logic 1 output when more than one
input variable are logic 1. Input 1 Input 2(B) Input 3 (C) Output (X)
𝐵ത 𝐶ҧ ത
𝐵𝐶 𝐵𝐶 𝐵 𝐶ҧ (A)
0 0 0 0
𝐴ҧ 0 0 1 0
𝐴 0 1 1 1 0 0 1 0

0 1 0 0
𝑿 = 𝑨𝑪 + 𝑨𝑩 + 𝑩𝑪
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

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Chapter- 1 : Design of arithmetic combination circuits
Integrated Logic Circuit 7483
Design of adder circuits
- Full Adder
❑ The most basic arithmetic operation is the addition.
❑ Simple addition of two bits consists of 4 possible elementary
operations:
0+0=0
0+1=1
1+0=1
1+1=0 with a carry of 1
❑ A combinational circuit that performs the addition is called adder.
❑ Adder circuits are divided in two types;
✓ half adder circuit
✓ full adder circuit

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Chapter- 1 : Design of arithmetic combination circuits
Designing of half adder
❑ Half adder is a combinational circuit that adds two single-bit binary numbers and
produces two outputs: the sum and the carry. Truth table of circuit
❑ A half adder does not take into account any carry input from previous A B S C
calculations
❑ We can draw Block diagram
0 0 0 0
0 1 1 0
A Sum (S)
B
HA
Carry(C) ≡ 1 0 1 0

Half adder 1 1 0 1

ഥ B + A𝑩
S= 𝑨 ഥ =A⨁B C = A.B
𝐵ത B 𝐵ത B
𝐴ҧ 0 1 𝐴ҧ 0 0
𝐴 1 0 𝐴 0 1
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Chapter- 1 : Design of arithmetic combination circuits
Designing of full adder
➢ A full adder is a combinational circuit that adds three single-bit binary numbers: two
input bits (A and B) and a carry input (𝑪𝒊𝒏 ). A S
➢ It produces two outputs sum (S), carry out 𝑪𝒐𝒖𝒕
➢ Takes into account a carry-in from the previous addition B FA
𝐶𝑖𝑛 𝐶𝑜𝑢𝑡
Truth table of circuit
A B 𝐶𝑖𝑛 S 𝐶𝑜𝑢𝑡 S ത 𝑖𝑛
𝐵𝐶 ത 𝑖𝑛
𝐵𝐶 𝐵𝐶𝑖𝑛 ҧ
𝐵 𝐶𝑖𝑛
𝐴ҧ 0 1 0 1
0 0 0 0 0 𝐴 1 0 1 0 ത 𝑖𝑛 𝐵𝐶
𝐶𝑜𝑢𝑡 𝐵𝐶 ത 𝑖𝑛 𝐵𝐶𝑖𝑛 ҧ
𝐵 𝐶𝑖𝑛
0 0 1 1 0
S=𝐴.ҧ 𝐵.
ത 𝐶𝑖𝑛 + 𝐴.ҧ 𝐵. 𝐶𝑖𝑛 + 𝐴. 𝐵.
ത 𝐶𝑖𝑛 + 𝐴. 𝐵. 𝐶𝑖𝑛 = 𝐴ҧ 0 0 1 0
0 1 0 1 0 (𝐴 ⨁ 𝐵)⨁𝐶𝑖𝑛 𝐴 0 1 1 1
0 1 1 0 1
1 0 0 1 0 𝐶𝑜𝑢𝑡 = ഥ𝐴. 𝐵. 𝐶𝑖𝑛 + 𝐴. 𝐵.
ത 𝐶𝑖𝑛 + 𝐴. 𝐵. 𝐶𝑖𝑛 +
1 0 1 0 1 𝐴. 𝐵. 𝐶𝑖𝑛 = (𝐴 ⨁ 𝐵). 𝐶𝑖𝑛 + 𝐴. 𝐵 = 𝐴. 𝐵 +
𝐴. 𝐶𝑖𝑛 + 𝐵. 𝐶𝑖𝑛
1 1 0 0 1
1 1 1 1 1
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 Chapter- 1 : Design of arithmetic combination circuits
Design of full adder by half adder To design a full adder using half adders, we
needs:
from half adder To full adder • Uses two half adders and an OR gate.
S= (𝐴 ⨁ 𝐵)⨁𝐶𝑖𝑛 • First half adder: Adds A and B to get an
S= 𝐴 ⨁ 𝐵 A intermediate sum and carry.
A • Second half adder: Adds intermediate
HA B FA sum with Cin.
B
• OR gate: Combines both carry outputs.
𝐶𝑖𝑛
C= 𝐴. 𝐵 𝐶𝑜𝑢𝑡 = (𝐴 ⨁ 𝐵). 𝐶𝑖𝑛 + 𝐴. 𝐵

1st half adder

S= (𝐴 ⨁ 𝐵)⨁𝐶𝑖𝑛
A S
HA1 HA2
B
Cout 2nd half adder
Cin
𝐶𝑜𝑢𝑡 = (𝐴 ⨁ 𝐵). 𝐶𝑖𝑛 + 𝐴. 𝐵

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Chapter- 1 : Design of arithmetic combination circuits
Design of 4 bits adder B4B3B2B1 A4A3A2A1
❑ A parallel adder (also called a cascading adder) is used to add multi-bit binary
numbers.
❑ It is constructed by connecting multiple full adders in series, where each full adder C 4-bit full Adder
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handles one bit of the input numbers.
❑ The carry output of one full adder is connected to the carry input of the next full
adder, allowing the addition of numbers with multiple bits. S3 S2 S1 S0
Carry bit from the
A= (A4, A3, A2, A1) B= (B4, B3, B2, B1) previous stage.
A4 A3 A2 A1
B4 B3 B2 B1

c 4 c3 c2 c1 .
+ A4 A3 A2 A1 C0 =0
+ B4 B3 B2 B1 C0 =0 FA FA FA FA
────────
C4 S3 S2 S1 S0
c3 c2 c1 C4 C3 C2 C1
S3 S2 S1 S0
 Chapter- 1 : Design of arithmetic combination circuits
Design of half subtractor Design of Full subtractor
➢ A half subtractor is a combinational circuit that ➢ The full subtractor performs subtraction of three
performs subtraction of two single-bit binary single-bit binary numbers: two input bits (A and B) and
numbers. a borrow input (Bin).
➢ It has two inputs (A and B) and two outputs: ➢ It produces two outputs: the difference (D) and
the difference (D) and the borrow (Bout). the borrow output (Bout).
Truth table of circuit A D
A B 𝐵𝑖𝑛 D 𝑩𝑜𝑢𝑡 B FS
A Diff (D)
HS 0 0 0 0 0 𝐵𝑜𝑢𝑡
B 𝐵𝑖𝑛
Borrow(Bout)
0 0 1 1 1
ҧ + A𝐵ത = A ⨁ B
D= 𝐴B ҧ
𝐵𝑜𝑢𝑡 = 𝐴𝐵 0 1 0 1 1
0 1 1 0 1
Truth table of circuit 1 0 0 1 0
A B D 𝐵𝑜𝑢𝑡 1 0 1 0 0
1 1 0 0 0
0 0 0 0
1 1 1 1 1
0 1 1 1
𝐵𝑜𝑢𝑡 = ഥ𝐴𝐵𝐵
ത 𝑖𝑛 + 𝐴𝐵𝐵ҧ 𝑖𝑛 + 𝐴𝐵𝐵ҧ 𝑖𝑛
1 0 1 0 D=𝐴.ҧ 𝐵.
ത 𝐵𝑖𝑛 + 𝐴.ҧ 𝐵. 𝐵𝑖𝑛 + 𝐴. 𝐵.
ത 𝐵𝑖𝑛 +
+ 𝐴𝐵𝐵𝑖𝑛 = (𝐴 ⨁ 𝐵). 𝐵𝑖𝑛 + 𝐴.ҧ 𝐵
1 1 0 0 𝐴. 𝐵. 𝐵𝑖𝑛 = (𝐴 ⨁ 𝐵)⨁𝐵𝑖𝑛 15
𝐵𝑜𝑢𝑡 = 𝐴.ҧ 𝐵 + ഥ𝐴. 𝐵𝑖𝑛 + 𝐵. 𝐵𝑖𝑛
Chapter- 1 : Design of arithmetic combination circuits
Design of 4 bits full subtractor with full adder
➢ To design a full subtractor using full adders, we can leverage the fact that subtraction can be achieved by
adding the minuend A with the two's complement of the subtrahend B.
➢ The two's complement of a binary number can be obtained by flipping all the bits and then adding 1 to
the result.
▪ A – B = A + (-B) = A +2’s complement of (B)= A +(1’s complement of (B) +1)
▪ 1’s complement of (B)= 𝑩 ഥ

A4 B4 A3 B3 A2 B2 A1 B1

C0=1

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0 16
 Chapter- 1 : Design of arithmetic combination circuits
Design of full adder /subtractor
➢ A full adder/subtractor is a versatile circuit that can perform both addition and subtraction. It uses the
same set of inputs for both operations
➢ By adding a control signal (C), we can configure the circuit to operate as either an adder or a subtractor
When C is 0, addition is performed; when C is 1, subtraction is performed.
➢ The XOR gate is used to toggle between the input A and its complement 𝑨 ഥ based on the Signal control
C (0/1)
C Operation A⨁C 𝑪𝒊𝒏 /𝑩𝒊𝒏
0 Addition 𝑨 0
1 Subtraction ഥ
𝑨 1
S= D = (𝐴 ⨁ 𝐵)⨁𝐶𝑖𝑛

ഥ. 𝐵
𝐵𝑜𝑢𝑡 = (𝑨 ⨁ 𝑩). 𝐵𝑖𝑛 + 𝑨

𝐶𝑜𝑢𝑡 = (𝑨 ⨁ 𝑩). 𝐶𝑖𝑛 + 𝑨. 𝐵 17

Chapter- 1 : Design of arithmetic combination circuits
Design of 4 bits full adder /subtractor
➢ Each bit of B is XORed with the control signal (C).
C Operation B⨁C 𝑪𝒊𝒏
• If C=0, B remains unchanged (for addition).
0 Addition 𝑩 0
• If C=1, B is complemented (for subtraction) ഥ
1 Subtraction 𝑩 1

B4 B3 B2 B1
C(0/1)

A4 A3 A2 A1

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0 18
Chapter- 1 : Design of arithmetic combination circuits
Magnitude Comparator
➢ A magnitude comparator is a combinational circuit used to compare the magnitudes of two binary numbers. It
determines whether one number is greater than, less than, or equal to the other.

The outcome of the comparison is specified by three binary variables that indicate whether A > B, A = B, or A < B.

A G (A > B) Greater
1-bit E (A = B) Equal
B comp
S (A < B) Smaller

A B E G S ≡
𝑬 = 𝐴.ҧ 𝐵ത + 𝐴. 𝐵 = (𝐴 ⨁ 𝐵)
0 0 1 0 0
G= 𝐴. 𝐵ത ;
0 1 0 0 1 𝑺 = 𝐴.ҧ 𝐵
1 0 0 1 0
1 1 1 0 0 ഥ +𝑨
𝑬 = 𝑨. 𝑩 ഥ . 𝑩 = ( 𝑮 + 𝑺)
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Chapter- 1 : Design of arithmetic combination circuits Truth table of circuit
A2 A1 B2 B1 A>B A=B A<B
2-bits Magnitude Comparator
0 0 0 0 0 1 0
➢ A 2-bit comparator compares the magnitudes of two 2-bit
0 0 0 1 0 0 1
binary numbers A=A2 A1, B= B1B2
0 0 1 0 0 0 1
A2 G (A > B) Greater 0 0 1 1 0 0 1
A
A1 2-bits E (A = B) Equal 0 1 0 0 1 0 0
B B2 comp
S (A < B) Smaller 0 1 0 1 0 1 0
B1
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
It can be said that :
1 0 0 1 1 0 0
𝐴 = 𝐵 𝑖𝑓 𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 = 𝐵1 ;
𝐴 > 𝐵 𝑖𝑓 𝐴2 > 𝐵2 𝒐𝒓 𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 > 𝐵1 ; 1 0 1 0 0 1 0
𝐴 < 𝐵 𝑖𝑓 𝐴2 < 𝐵2 𝒐𝒓𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 < 𝐵1 1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 20 0
Chapter- 1 : Design of arithmetic combination circuits
2-bits Magnitude Comparator
➢ A 2-bit comparator compares the magnitudes of two 2-bit binary numbers A=A2 A1, B= B2B1

A>B A<B
B2B1 00 01 11 10 B2B1 00 01 11 10
A2 A1 A2 A1

00 00 1 1 1
01 1 01 1 1
11 1 1 1 11
10 1 1 10 1

𝐵2 𝐴2 + 𝐵2 𝐵1 𝐴1 + 𝐵2 𝐴2 𝐴1 𝐴2 𝐵2 + 𝐴2 𝐴1 𝐵1 + 𝐴1 𝐵2 𝐵1

B2B1 00 01 11 10
A2 A1

00 1
01 1 𝐴1 ⨁ 𝐵1 (𝐴2 ⨁ 𝐵2 )
A=B
11 1
10 1 21
 Chapter- 1 : Design of arithmetic combination circuits
2-bit comparator using 1-bit comparators
G (A > B) E (A = B) S (A < B)
➢ It is possible to create a 2-bit comparator using 1-bit comparators
and logic gates.
➢ One comparator should be used to compare the least significant
bits, and another one to compare the most significant bits.
➢ The outputs of the two comparators used must be combined to
generate the outputs of the final comparator.

As a result:
𝐴 = 𝐵 𝑖𝑓 𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 = 𝐵1 ;
𝐹𝑒 = 𝐸1 𝐸2

𝐴 > 𝐵 𝑖𝑓 𝐴2 > 𝐵2 𝒐𝒓 𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 > 𝐵1 ;

𝐹𝑔 = 𝐺2 + 𝐸1𝐺1

𝐴 < 𝐵 𝑖𝑓 𝐴2 < 𝐵2 𝒐𝒓𝐴2 = 𝐵2 𝒂𝒏𝒅 𝐴1 < 𝐵1

𝐹𝑠 = 𝑆2 + 𝐸2𝑆1

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Chapter- 1 : Design of data transmission circuits
Multiplexers Block Diagram:
➢ A multiplexer , often abbreviated as "mux," is a multi-input and single- D0
output combinational circuit.
➢ The basic operation of a multiplexer involves selecting one information D1 Output
Mux

Input
from a set of 2n possible input and passing its data to the output line based Y

,
,,,,,,,,,,,,,,,,
2n:1
on a control signal. Dm
➢ Multiplexers come in different configurations, such as 2-to-1, 4-to-1, 8-to-1,
etc., depending on the number of input lines and the size of the control ,,,,,,,,,,,,,,,,
,

signal. S0 Sn-1
➢ Basic Multiplexing Switch: Select
.

1. Two-to-one-line multiplexer
E
D0 E S0 Y
Mux
Input

D1 Y 0 x 0 𝐹 = 𝐷0. 𝑆0 + 𝑆0 𝐷1
2:1 Output
1 0 D0
1 1 D1 23
S0
 Chapter- 1 : Design of data transmission circuits
Multiplexers Block Diagram:
2. Four -to-one-line multiplexer D0
➢ A 4-to-1 multiplexer (often denoted as 4:1 mux) is a type of multiplexer that D1 Output
Mux

Input
has four input lines and one output line. It selects one of the four input lines D2 4:1 Y
based on the combination of control signals D3
.
S1 S0 Y
0 0 D0 S0 S1
0 1 D1 𝑌 = 𝑆0 𝑆ഥ1 𝐷0 + 𝑆0 𝑆ഥ1 𝐷1+ 𝑆0 𝑆1 𝐷2 + 𝑆0 𝑆1 𝐷3
1 0 D2
1 1 D3

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 Chapter- 1 : Design of data transmission circuits
Multiplexers E
2. Four -to-one-line multiplexer D0
➢ In case we need to take into consideration the enable, the truth table is D1 Output
Mux

Input
modified as follows: D2 4:1 Y

E S1 S0 Y 𝑌 = 𝐸(𝑆0 𝑆ഥ1 𝐷0 + 𝑆0 𝑆ഥ1 𝐷1+ 𝑆0 𝑆1 𝐷2 + 𝑆0 𝑆1 𝐷3) D3

0 X X 0 Block Diagram
1 0 0 D0 S0 S1
1 0 1 D1
1 1 0 D2
1 1 1 D3
E S1 S0 Y
➢ This enable is used to activate the multiplexer, when it is high, the mux works, when it is 1 X X 0
low, the mux is disabled. The multiplexer can be either active high or active low.
0 0 0 D0
➢ In other hand, when it is active low, then the multiplexer works when the enable is set to 0 as 0 0 1 D1
in the following truth table: 𝑌 = 𝐸ത (𝑆 𝑆ഥ 𝐷0 + 𝑆 𝑆ഥ 𝐷1+ 𝑆 𝑆 𝐷2 + 𝑆 𝑆 𝐷3)
0 1 0 1 0 1 0 1 0 1 0 D2
➢ The logic expression for the following active low multiplexer is: 0 1 1 25 D3
 Chapter- 1 :Design of data transmission circuits
Multiplexers Block Diagram
3. Eight -to-one-line multiplexer D0
➢ A 8-to-1 multiplexer (often denoted as 8:1 mux) is another type of multiplexer that D1
has 8 input lines D0, D1, D2…………..D7 , single output line (Y) and three select D2

Input
(control) line (S0, S1,S2). D3 Output
D4 Mux Y
𝑌 = 𝐸(𝑆2 𝑆ഥ1 𝑆0 𝐷0 + 𝑆2 𝑆ഥ1 𝑆0 𝐷1+ 𝑆2 𝑆1 𝑆0 𝐷2 + 8:1
E S2 S1 S0 Y 𝑆2 𝑆1 𝑆0 𝐷3 + 𝑆2 𝑆ഥ1 𝑆0 𝐷4 + 𝑆2 𝑆ഥ1 𝑆0 𝐷5 + D5
0 X X X 0 𝑆2 𝑆1 𝑆0 𝐷6 + 𝑆2 𝑆1 𝑆0 𝐷7) D6
1 0 0 0 D0 D7
1 0 0 1 D1
1 0 1 0 D2
1 0 1 1 D3
S0 S1 S3
1 1 0 0 D4
1 1 0 1 D5
1 1 1 0 D6
1 1 1 1 D7

26
 Chapter- 1 : Design of data transmission circuits
Multiplexers
4. 8-to-1 Mux using 4-to-1 Mux and 2-to-1 Mux
➢ If you observe the Boolean Expression of 8-to-1 Multiplexer shown above, we consider the multiplexer is in active high, we
can re-write it as follows:
𝑌 = 𝑆2 𝑆ഥ1 𝑆0 𝐷0 + 𝑆2 𝑆ഥ1 𝑆0 𝐷1+ 𝑆2 𝑆1 𝑆0 𝐷2 + 𝑆2 𝑆1 𝑆0 𝐷3 + 𝑆2 𝑆ഥ1 𝑆0 𝐷4 + 𝑆2 𝑆ഥ1 𝑆0 𝐷5 + 𝑆2 𝑆1 𝑆0 𝐷6 + 𝑆2 𝑆1 𝑆0 𝐷7

𝑌 = 𝑆2 (𝑆ഥ1 𝑆0 𝐷0 + 𝑆ഥ1 𝑆0 𝐷1+ 𝑆1 𝑆0 𝐷2 + 𝑆1 𝑆0 𝐷3) + 𝑆2 (𝑆ഥ1 𝑆0 𝐷4 + 𝑆ഥ1 𝑆0 𝐷5 + 𝑆1 𝑆0 𝐷6 + 𝑆1 𝑆0 𝐷7)

The expression in the first red bracket is similar to the Boolean Expression of a 4-to-1 Multiplexer with D0, D1, D2 and D3
as inputs and S1 and S0 as Select Lines. Let this expression be P1. P1 = (𝑆ഥ1 𝑆0 𝐷0 + 𝑆ഥ1 𝑆0 𝐷1+ 𝑆1 𝑆0 𝐷2 + 𝑆1 𝑆0 𝐷3)

Similarly, the expression in the second blue bracket is similar to the Boolean Expression of another 4-to-1 Multiplexer with
D4, D5, D6 and D7 as inputs and S1 and S0 as Select Lines. Let this expression be P2. P2 = (𝑆ഥ1 𝑆0 𝐷4 + 𝑆ഥ1 𝑆0 𝐷5 +
𝑆1 𝑆0 𝐷6 + 𝑆1 𝑆0 𝐷7)
Now, replacing the above expressions with P1 and P2, we get : 𝑌 = 𝑆2 𝑃1 + 𝑆2 𝑃2

This expression is similar to a 2-to-1 Multiplexer with P1 and P2 (where, P1 and P2 are outputs of respective 4-to-1
Multiplexers) as Inputs and S2 as Select Signal. So, finally, we can deduce that an 8-to-1 Multiplexer can be implemented
using two 4-to-1 Multiplexers and one 2-to-1 Multiplexer. The block diagram of the same is shown below: 27
 Chapter- 1 : Design of data transmission circuits
Multiplexers
4. 8-to-1 Mux using 4-to-1 Mux and 2-to-1 Mux
So, finally, we can deduce that an 8-to-1 Multiplexer can be implemented using two 4-to-1 Multiplexers and one 2-to-1
Multiplexer. The block diagram of the same is shown below:

Block Diagram
D0
D1 Mux P1 Mux Output
Y
D2 4:1 2:1
D3

S0 D4
S1
D5 P2 S2
Mux
D6 4:1
D7
S0 S1
28