CONTENT BEYOND SYLLABUS

SystemVerilog

SystemVerilog is the industry's first unified hardware description and verification language
[HDVL] standard. SystemVerilog is a major extension of the established IEEE 1364 TM Verilog language.
It was developed originally by Accellera to dramatically improve productivity in the design of large gate-
count, IP-based, bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and
verification flow, with powerful links to the system-level design flow. SystemVerilog has been adopted
by 100's of semiconductor design companies and supported by more than 75 EDA, IP and training
solutions worldwide.

DESIGN FEATURES

Enhanced variable types add new capability to Verilog's "reg" type:

logic [31:0] my_var;

Verilog-1995 and verilog-2001 limit reg variables to behavioral statements such as RTL code.
SystemVerilog extends the reg type so it can be driven by a single driver such as gate or module.
SystemVerilog names this type "logic" to remind users that it has this extra capability and is not a
hardware register. The names "logic" and "reg" are interchangeable. A signal with more than one driver
needs to be declared a net type such as "wire" so System Verilog can resolve the final value.

Multidimensional packed arrays unify and extend Verilog's notion of "registers" and "memories":

logic [1:0][2:0] my_pack[32];

Classical Verilog permitted only one dimension to be declared to the left of the variable name.
System Verilog permits any number of such "packed" dimensions. A variable of packed array type maps
1:1 onto an integer arithmetic quantity. In the example above, each element of my_pack may be used in
expressions as a six-bit integer. The dimensions to the right of the name (32 in this case) are referred to as
"unpacked" dimensions. As in Verilog-2001, any number of unpacked dimensions is permitted.

Enumerated data types allow numeric quantities to be assigned meaningful names. Variables
declared to be of enumerated type cannot be assigned to variables of a different enumerated type without
casting. This is not true of parameters, which were the preferred implementation technique for
enumerated quantities in Verilog-2005:

typedef enum logic [2:0] {

RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW

} color_t;

color_t my_color = GREEN;

initial $display("The color is %s", my_color.name());

As shown above, the designer can specify an underlying arithmetic type ( logic [2:0] in this case) which
is used to represent the enumeration value. The meta-values X and Z can be used here, possibly to
represent illegal states. The built-in function name() returns an ASCII string for the current enumerated
value.

New integer types: SystemVerilog defines byte, shortint, int and longint as two-state signed integral
types having 8, 16, 32, and 64 bits respectively. A bit type is a variable-width two-state type that works
much like logic. Two-state types lack the X and Z metavalues of classical Verilog; working with these
types may result in faster simulation.

Structures and unions work much like they do in the C programming language. SystemVerilog
enhancements include the packed attribute and the tagged attribute. The tagged attribute allows runtime
tracking of which member(s) of a union are currently in use. The packed attribute causes the structure or
union to be mapped 1:1 onto a packed array of bits. The contents of it occupy a continuous block of
memory (with no gaps):
Types of ASICs
Full-Custom ASICs
In a full-custom ASIC an engineer designs some or all of the logic cells, circuits, or
layout specifically for one ASIC. This means the designer abandons the approach of using
pretested and precharacterized cells for all or part of that design. It makes sense to take this
approach only if there are no suitable existing cell libraries available that can be used for the
entire design. This might be because existing cell libraries are not fast enough, or the logic cells
are not small enough or consume too much power. You may need to use full-custom design if the
ASIC technology is new or so specialized that there are no existing cell libraries or because the
ASIC is so specialized that some circuits must be custom designed. Fewer and fewer full-custom
ICs are being designed because of the problems with these special parts of the ASIC. There is
one growing member of this family, though, the mixed analog/digital ASIC, which we shall
discuss next.

Standard-Cell–Based ASICs
A cell-based ASIC (cell-based IC, or CBIC —a common term in Japan, pronounced “sea-
bick”) uses predesigned logic cells (AND gates, OR gates, multiplexers, and flip-flops, for
example) known as standard cells . We could apply the term CBIC to any IC that uses cells, but
it is generally accepted that a cell-based ASIC or CBIC means a standard-cell–based ASIC.
The standard-cell areas (also called flexible blocks) in a CBIC are built of rows of standard cells
—like a wall built of bricks. The standard-cell areas may be used in combination with larger
predesigned cells, perhaps microcontrollers or even microprocessors, known as megacells .
Megacells are also called megafunctions, full-custom blocks, system-level macros (SLMs), fixed
blocks, cores, or Functional Standard Blocks (FSBs).

Gate-Array–Based ASICs
In a gate array (sometimes abbreviated to GA) or gate-array–based ASIC the transistors
are predefined on the silicon wafer. The predefined pattern of transistors on a gate array is the
base array , and the smallest element that is replicated to make the base array (like an
M. C. Escher drawing, or tiles on a floor) is the base cell (sometimes called a primitive cell ).
Only the top few layers of metal, which define the interconnect between transistors, are defined
by the designer using custom masks. To distinguish this type of gate array from other types of
gate array, it is often called a masked gate array ( MGA ). The designer chooses from a gate-
array library of predesigned and precharacterized logic cells. The logic cells in a gate-array
library are often called macros . The reason for this is that the base-cell layout is the same for
each logic cell, and only the interconnect (inside cells and between cells) is customized, so that
there is a similarity between gate-array macros and a software macro.

Channeled Gate Array

The important features of this type of MGA are:
o Only the interconnect is customized.
o The interconnect uses predefined spaces between rows of base cells.
o Manufacturing lead time is between two days and two weeks.
Channelless Gate Array
The important features of this type of MGA are as follows:
o Only some (the top few) mask layers are customized—the interconnect.
o Manufacturing lead time is between two days and two weeks.

Structured Gate Array

An embedded gate array or structured gate array (also known as masterslice or
masterimage ) combines some of the features of CBICs and MGAs.
o Custom blocks (the same for each design) can be embedded.
o Manufacturing lead time is between two days and two weeks.

Programmable Logic Devices

PLDs may be configured or programmed to create a part customized to a specific
application, and so they also belong to the family of ASICs. PLDs use different technologies to
allow programming of the device. Figure 1.8 shows a PLD and the following important features
that all PLDs have in common:
 No customized mask layers or logic cells
 Fast design turnaround
 A single large block of programmable interconnect
 A matrix of logic macrocells that usually consist of programmable array logic followed
by a flip-flop or latch

Field-Programmable Gate Arrays

A step above the PLD in complexity is the field-programmable gate array ( FPGA ). There is
very little difference between an FPGA and a PLD—an FPGA is usually just larger and more
complex than a PLD.
 None of the mask layers are customized.
 A method for programming the basic logic cells and the interconnect.
 The core is a regular array of programmable basic logic cells that can implement
combinational as well as sequential logic (flip-flops).
 A matrix of programmable interconnect surrounds the basic logic cells.
 Programmable I/O cells surround the core.
 Design turnaround is a few hours.
ASIC DESIGN FLOW