AMBA protocol questionaries

1. What AMBA stand for and what are different AMBA protocol? What
are important differences between these protocols.

AMBA : Advanced Microcontroller Bus Architecture

AMBA Protocols : APB,AHB,AXI

APB for low speed and single master – mulitiple slaves

AHB for high speed and arbitration multiple masters – multiple slaves (only
alignes address)
AXI for high speed and high performance multiple masters – multiple
slaves ( both aligned and non aligned address)

2. Draw a timing diagram of basic write transaction in APB, address

is 0x2000?

3. Draw the timing diagram basic read transaction of AHB at slave

interface?

4. What are channels of AXI protocol? Specify the signals of AW

channel and R channel along with their widths.
5. What is the handshake in the case of AXI protocol?
a. What are the rules pertaining the valid signal and ready
signal.
b. Explain using timing diagram when the transaction is
initiated and when it is accepted (@ Master interface). //
hint handshaking mechanism
6. Timing diagrams for following scenarios and indicate when a
transfer is accepted by receiving agent.
a. Ready signal is asserted by default.
b. Ready signal is asserted after valid signal assertion.
c. Ready signal is asserted along with valid signal.
7. Timing diagram for simple write transaction with AWADRR = 0x42,
AWBURST =INCR, AWSIZE = 4Bytes and AWLEN = 4 beat carried
on 64bit bus.
Each write transfer is accepted one cycle after assertion of
WVALID signal.
8. Timing diagram for simple read transaction with ARADDR = 0x4,
ARBURST = WRAP, ARSIZE = 4Bytes and ARLEN = 8 beats carried
on 32bit bus
a. List transfer addresses for each transfer for above burst .
b. What is wrap starting address and wrap ending address
for above burst.
9. What is early bust termination?
a. Does AHB protocol permits early burst termination?
b. Dose AXI protocol permits early burst termination? if not
how can the same be achieved in the case of write burst?
10. What is the mechanism by which protection is enabled in
the AXI protocol?
a. What signal is used for protection?
b. What is the significance of the each bit in this signal?
11. What is significance of AxCACHE signal?
a. What hint bufferable bit provide ?
b. What hint cacheable /Modifiable bit provide?
c. What hint Read Allocate(RA) and Write Allocate(WA) bits?
12. What is different response values (RRESP (AXI) and HRESP
(AHB)) and what does each value signify?
13. What is locked transaction?
14. How do we start a we start the locked transaction? How do
we complete locked transaction?
15. What are advantages and dis-advantage of locked
transaction?
16. What is an exclusive transaction:
How do we start exclusive transaction and how do we complete an
exclusive transaction?
What is advantage and disadvantage of exclusive transaction?
17. Expected responses (with reason) for below exclusive
transactions reaching a single slave
Exclusive Read with ID = 0x0, Address = 0x40
Exclusive Read with ID = 0x1, Address = 0x80
Exclusive write with ID = 0x0, Address = 0x40
Exclusive write with ID = 0x1, Address = 0x80
18. Expected responses (with reason) for below exclusive
transactions reaching a single slave
Exclusive Read with ID = 0x0, Address = 0x40
Exclusive Read with ID = 0x0, Address = 0x80
Exclusive Write with ID = 0x0, Address = 0x40
Exclusive Write with ID = 0x0, Address = 0x80.
19. What are ordering rules in the AXI protocol? Explain using
arrow diagrams
20. What are the dependencies between different channels in
AXI protocol?
(Expectation from this question: E.g. rvalid should not wait for
assertion of rready signal, similarly explain for other signals).
21. Timing diagram for following non-outstanding transactions
 a. Write transaction of length 3 beats starting at T2
followed by write transaction of length 2 beats starting
at T8.
b. Read transaction of address of length 2 beats starting at
T2 followed by read transaction of length 3 beats staring
at T5.
22. Timing diagram for following outstanding transactions
a. Write address of length 3 beats starting T2 followed by
write address of length 2 beats starting at T3
b. Read address of length 2 beats starting at T2 followed by
read address of length 3 beats staring at T3
23. Write ID rules:
a. How can two write transactions with same ID can be
completed ?
Show timing diagram of in order execution of two write
transactions with same ID.
b. How can two write transactions with different ID can be
completed?
Show a timing diagram of execution of two read
transactions with different ID.
c. What is the impact of re-ordering on write data bus.
d. Explain the concept of write interleaving for the system
that has three outstanding transactions
24 Read ID rules:
How can two read transactions with same ID can be
completed ?
How can two read transactions with different ID can be
completed?
Show timing diagram of in order execution of two read
transactions with different ID.
Show a timing diagram of out of execution of two read
transactions with different ID.
Explain the concept of read interleaving for the system that
has three outstanding transactions
25 What is the use of strobe signal and how is the strobe signal
used? Why we don’t have similar signal in the read path?
26 Timing diagram of AWADDR = 0x53, AWSIZE = 4bytes and AWLEN
= 4 beats on 16byte width data bus. specify next subsequent
address and strobe value for each transfer.
27 What are different AXI interface attributes, what is your
understanding on?
a. write interleaving depth
b. Write issuing capability.