Module-1

1. Introduction to ASICs:
An Application Specific Integrated Circuit or simply an ASIC can be defined as an
integrated circuit customized for a particular application or end-use rather than using it for
general purpose. Some basic examples of ASICs are the IC in a DVD Player to decode the
information on an optical disc or an IC designed as a Charge Controller for Lithium Ion
batteries. In contrast, an ASIC can only be used in the application it was specifically designed
to run.
Due to the application specific custom nature of the ASICs, they often pack more
functionality at the same time being small in size, consuming less power and dissipating less
heat when compared to a standard IC solution. The other main difference between standard
ICs like Memories, for example and ASICs is that the designer of the ASIC can directly be
the customer, who might have a clearer idea of the application.

2.What are the Different Types of ASIC?

Basically, all ASICs can be categorized into three types. They are:
 Full – Custom ASICs
 Semi – Custom ASICs
 Programmable ICs
The semi-custom ASICs are again divided into Gate Array based designs and Cell based
designs. Gate Arrays are further divided into Channelled and Channel-less Arrays while Cell
based designs are further divided into Standard Cell and Macrocell.
Coming to Programmable ICs, all the Programmable Logic Devices like PAL, PLA, EPROM
based PLD (EPLD), EEPROM based PLD (EEPLD), and field programmable devices like
FPGA come under this category.
The following image shows the different types of ASIC and also the sub-categories in each
type.
Let us now briefly see some of the important types of ASICs.

2.1 Full-Custom ASIC:

In Full-Custom ASIC, all the logic cells, circuits and layouts are designed specifically for that
particular ASIC from the ground up. The designer may choose a full-custom ASIC design
only if he thinks that either the existing libraries are not fast enough or the logic cells are not
small or the power consumption is high.
The main advantages of full-custom ASICs over other IC designs are it delivers the highest
possible performance at the smallest possible die size. But this high performance and small
size comes at a price of increased design time, complex design and overall cost of the IC
itself.
Some of most common full-custom ASISs are Microprocessors, Memories, Analog
Processors, Analog / Digital Communication devices, Sensors, Transducers, high-voltage ICs
for Automobiles, etc.

2.2Semi-Custom ASIC:

To shorten the design time and cut down the cost of full-custom ASICs, numerous other
design approaches have been developed and these are called as Semi-Custom ASIC Designs.
Usually, the lowest level of hierarchy involved in semi-custom design is the logic level or
gate level. This is in contrast to full-custom job, where the design and layout individual
transistor might be involved.
As mentioned earlier, the semi-custom ASIS design can be further divided into Gate Arrays
and Standard Cells. Let us see a little bit about these types.

2.2.1Gate Array ASIC

In Gate Array based ASICs, p and n types transistors are predefined on a silicon wafer as
arrays. Based on the design from the customer and the interconnections obtained from the
design, the silicon vendor provides these base wafers. Therefore, the base wafer is specific to
the customer as it is designed based on the customer provided connections between the
transistors of the gate array.
The gate arrays are again divided into two types called the Channelled Gate Array and the
Channel-less Gate Array. In channelled gate arrays, the interconnections between the logic
cells are performed within the predefined channels between the rows of the logic cells. In
case of channel-less gate arrays, the connections are made on an upper metal layer on top of
the logic cells.
2.2.2 Standard Cell based ASIC:

A Standard Cell based ASIC uses predesigned logic cells like Gates, Multiplexers, Flip-flops,
Adders etc. These logic cells are known as Standard Cells that are already designed and
stored in a library. This library is imported into the CAD tool and the design can performed
using the components of the library as inputs.
Typically, Standard Cell based designs are organized as rows of constant height cells on the
chip, just like a row of bricks. When combined with logic-level components, standard cell-
based designs can be used to implement complex functions like Multipliers and Memory
Arrays.
The standard cell design may also contain a larger and more complex predesigned cells like
Microcontrollers or Microprocessors. These larger cells are called as Megacells.

3.Design Flow

Until now, you have seen a brief introduction to ASIC and also few important types of
ASICs. In this section let us try to briefly understand the specific process flow and procedures
involved in designing and developing an ASIC.
The following image shows a typical design flow involved in designing a semicustom ASIC.
It can be basically divided into 10 steps.
  Design Entry: In the step, the logic design is created using a Hardware Description
Language (HDL) like VHDL or Verilog or with the help of Schematic entry.
 Logic Synthesis: Once the logic is designed using HDL or Schematic entry, the next
step is to extract the description of the logic cells and their interconnections. This
information is also called as Netlist.
 System Partitioning: The next step is to logically divide the entire system into small
ASIC sized blocks.
 Pre-layout Simulation: Before going into the actual physical layout of the design, a
simulation tool checks the circuit for proper working. In fact, this process is
performed at every step so that if any errors are found, then it would be easy to correct
them at this stage itself. The process until this step is usually regarded as Logical
Design. The steps after this are related to the actual physical layout of the design.
 Floor planning: The first step in the physical design is arrange all the blocks of the
circuit on the chip.
 Placement: In this step, the location of the logic cells in a block are set.
 Routing: Once the placement of the blocks and cells is completed, then it is time to
create the connections between the cells and the blocks.
 Extraction: The next step is to determine the resistance and capacitance of the
interconnections previously made, since they decide the delay of the signal. Also, the
delays are calculated at this stage.
 Post-layout Simulation: Once the physical design is complete, the circuit is again
tested for working. The delays previously calculated are also taken into consideration
for the simulation process.
 Design Rule Check (DRC): Final step is to verify the layout of the entire circuit and
check whether it complies with the design rule specifications.

Conclusion
 The ASIC design flow is a comprehensive process that requires collaboration between
various teams, including design, verification, and physical design engineers.
Following a structured approach ensures that the final product meets the desired
specifications and performance criteria, ultimately leading to successful ASIC
development. By adhering to best practices and utilizing appropriate Electronic
Design Automation (EDA) tools, engineers can efficiently navigate the complexities
of ASIC design.

4.ASIC cell libraries.

Standard cell library is an integral part of ASIC design flow and it helps to reduce the design
time drastically. Standard cells used in the ASIC design is a part of a standard cell library
along with some other file sets. In this article, we will discuss the important content inside the
standard cell library and its uses.
You can:
(1) use a design kit from the ASIC vendor
(2) buy an ASIC-vendor library from a library vendor
(3) you can build your own cell library (1) is usually a phantom library—the cells are empty
boxes, or phantoms, you hand off your design to the ASIC vendor and they perform phantom
instantiation (Synopsys CBA)
(2) involves a buy-or-build decision. You need a qualified cell library (qualified by the ASIC
foundry) If you own the masks (the tooling) you have a customer-owned tooling (COT, pro
nounced “see-oh-tee”) solution (which is becoming very popular)

(3)involvesacomplexlibrary developmentprocess:cell layout•behavioralmodel•Ver

ilog/VHDLmodel•timing model •teststrategy•characterization •circuit extraction • pro cess
control monitors(PCMs)ordrop-ins•cell schematic•cell icon• layout versus
schematic(LVS)check•cell icon•logic synthesis •retargeting•wire-load model•rout ing
model•phanto

Standard Cell Library:

Standard cell library is a collection of well defined and pre-characterized logic cells with
multi-drive strength and multi-threshold voltage cells in the form of a predefined
standard cell layout. It also contains a number of physical only cells and a set of library
files required by Place and Route (PnR) tool for automatic placement and routing
(APR).

Pre-characterization:

Before including a standard cell into standard cell library, the cells are gone through
schematic design, simulations followed by Symbol creation, layout design (as per standard
cells layout rules), physical verifications, abstraction, extraction and characterization. So the
cells available in standard cell library are free from any DRC violations, well-characterized
and suitable for PnR tool for automatic placement and routing.

Multi-drive strength cells:

A low drive strength cell will require less power and area but having more delay and more
transition time whereas a high drive strength cell can drive a larger number of cells and
having a fast transition. So as per the requirement, a PnR design engineer chooses the drive
strength of cells to optimize the area, power and performance.

Multi-Vt cells:

A low threshold voltage (LVT) cell will have a lesser delay but higher leakage power as
compared to a high threshold voltage (HVT) cell. So as per the requirement of timing and
power a PnR engineer uses HVT and LVT cell to balance the power and timing of the design.
There is no difference in the area on multi-Vt cells. A modern standard cell library contains
generally ULVT, LVT, SVT, HVT types of cells in which Vt is in increasing order.
Physical only cells:

In physical design, We need to add a variety to standard cells to mitigate various effects and
manufacturing issues. These cells do not have any logical functions. For example to
overcome the latch-up issue we need to add well tap cells. Decap cells, endcap cells, antenna
cells and filler cells are the example of such cells.

In the next section, we will discuss various cells collection and standard cells library and the
set of important files.

Cell Collections:

In general, a standard cell library contains the following types of cell:

 All basic and universal gates (like AND, OR, NOT, NAND, NOR, XOR etc)
 Complex gates (like MUX, HA, FA, Comparators, AOI, OAI etc)
 Clock tree cells (like Clock buffers, clock inverters, ICG cells etc)
 Flip flops and latches
 Delay cells
 Physical only cells
 Scannable Flip flops
File Collections:

Apart from the standard cells, Standard cell library is delivered with a collection of files
which contains all the information required to auto place and route. These files are mainly:

 LIB files (.lib)

 LEF files (.lef)
 Netlist file (.v )
 GDS file (.gds)
 SPICE Netlist (.sp)
 Model file (.m)
All the format of files mentioned here with the reference of the Cadence tool. Some files
format is different in the Synopsys tool but the information inside the file is the same. Brief
information of these files is given below. Detailed information of all these files can be found
in the “File in VLSI” section of this blog.

Timing library (LIB or DB) files are generated during the characterization of cells. Library
files contain cell delay, power and area information. Physical library (LEF) file is an abstract
view of the layout of the cells. LEF file contains the information of cell boundary, Pins inside
the cell, location, direction, and metal layer of each pin. Netlist file is a Verilog file of the
standard cell which defines the functionality of a cell. GDS file is the layout of the standard
cell. SPICE netlist is the netlist of cell in SPICE format is used for simulation. Model file
contains the various design parameters of the cell required for SPICE simulation.

5. CMOS Logic: Data path Logic Cells: Data Path Elements:

Adders: Carry skip, carry bypass, Carry save, Carry select, Conditional sum, Multiplier
(Booth encoding), Data path Operators, I/O cells, Cell Compilers.

Module-2
ASIC Library Design: Logical effort: Predicting Delay, Logical area and logical efficiency,
Logical paths, Multi stage cells, Optimum delay and number of stages, library cell design.
Programmable ASIC Logic Cells:
MUX as Boolean function generators, Acted ACT: ACT 1, ACT 2 and ACT 3 Logic
Modules, Xilinx LCA:
XC3000 CLB, Altera FLEX and MAX, Programmable ASIC I/O Cells: Xilinx and Altera
I/O Block.