----

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Hardware Reference
Library

Technical
Reference
Options and Adapters
Volume 2
Revised Edition (April 1984)
The following paragraph does not apply to the United Kingdom or any country where such
provisions are inconsistent with local law: International Business Machines Corporation
provides this manual "as is," without warranty of any kind, either expressed or implied,
including, but not limited to the particular purpose. IBM may make improvements and/or
changes in the product(s) and/or the program(s) described in this manual at any time.

This product could include technical inaccuracies or typographical errors. Changes are
made periodically to the information herein; these changes will be incorporated in new
editions of the publication.

It is possible that this material may contain reference to, or information about, IBM
products (machines or programs), programming, or services that are not announced in
your country. Such references or information must not be construed to mean that IBM
intends to announce such IBM products, programming, or services in your country.

Products are not stocked at the address below. Requests for copies of this product and for
technical information about the system should be made to your authorized IBM Personal
Computer dealer.

The following paragraph applies only to the United States and Puerto Rico: A Reader's
Comment Form is provided at the back of this publication. If the form has been removed,
address comments to: IBM Corp., Personal Computer, P.O. Box 1328-C, Boca Raton,
Florida 33432. IBM may use or distribute any of the information you supply in any way it
believes appropriate without incurring any obligations whatever.

© Copyright International Business Machines Corporation 1981, 1982, 1983, 1984

ii
Federal Communications Commission
Radio Frequency Interference Statement

Warning: The equipment described herein has been certified

to comply with the limits for a Class B computing device,
pursuant to Subpart J of Part 15 of the FCC rules. Only
peripherals (computer input/ output devices, terminals,
printers, etc.) certified to comply with the Class B limits may
be attached to the computer. Operation with non-certified
peripherals is likely to result in interference to radio and TV
reception. If peripherals not offered by IBM are used with the
equipment, it is suggested to use shielded grounded cables
with in-line filters if necessary.

CAUTION
The product described herein is equipped with a grounded
plug for the user's safety. It is to be used in conjunction with
a properly grounded receptacle to avoid electrical shock.

iii
iv
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Personal Computer
--_.- -- Hardware Reference
Library

mM Monochrome
Display and Printer
Adapter

6361511
ii
Contents

Introduction ................................... 1
Monochrome Display Adapter Function .............. 1
Description ................................ 1
Programming Considerations .................. 5
Specifications .............................. 9
Printer Adapter Function ........................ 11
Description ............................... 11
Programming Considerations ................. 13
Specifications ............................. 17
Logic Diagrams ................................ 19

ill
iv
Introduction

The IBM Monochrome Display and Printer Adapter has two

functions. The first is to provide an interface to the IBM
Monochrome Display. The second is to provide a parallel
interface for the IBM Printers. We will discuss this adapter by
function.

Monochrome Display Adapter Function

Description
The IBM Monochrome Display and Printer Adapter is designed
around the Motorola 6845 CRT Controller module. There are
4K bytes of RAM on the adapter that are used for the display
buffer. This buffer has two ports to which the system unit's
microprocessor has direct access. No parity is provided on the
display buffer.

Two bytes are fetched from the display buffer in 553 ns,
providing a data rate of 1.8M bytes/second.

The adapter supports 256 different character codes. An 8K-byte

character generator contains the fonts for the character codes.
The characters, values, and screen characteristics are given in "Of
Characters, Keystrokes, and Colors" in your Technical Reference
system manual.

This adapter, when used with a display containing P39 phosphor,

does not support a light pen.

Where possible, only one low-power Schottky (LS) load is

present on any I/O slot. Some of the address bus lines have two
LS loads. No signal has more than two LS loads.

Monochrome Adapter 1
Characteristics of the adapter are:

• Supports 80-character by 25-line screen

• Has direct-drive output

• Supports 9-PEL by 14-PEL character box

• Supports 7-PEL by 9-PEL character

• Has 18-kHz monitor

• Has character attributes

2 Monochrome Adapter
The following is a block diagram of the monochrome display
adapter portion of the IBM Monochrome Display and Printer
Adapter.

Processor (12)
Address Memory
Address
(1~ Multiplexer (10) (10)

2K Memory
2K Memory
Character
Attribute
Code

(8)
Processor Data
Bus (8)
Data I~
Gating I"""
Character
Clock ,Ir
BDO-7 I (8)

Octal 1 Octal
MA ~

Latch Latch

f--
RA ~ Character Attribute
AO
~ -.. Generator Decode
(4)

Chip MC6845

Select
-.
~

CRTC
DOTCLK

Timing
Shift
Register
L...
...
Signals Video
Process
Serial Dots Logic

r
HSYNC, VSYNC, CURSOR, DISPEN

Character
I
Clock

*
Monitor
Direct Drive
Outputs

IBM Monochrome Display Adapter Block Diagram

Monochrome Adapter 3
4 Monochrome Adapter
Programming Considerations
The following table summarizes the 6845 controller module's
internal data registers, their functions, and their parameters. For
the IBM Monochrome Display, the values must be programmed
into the 6845 to ensure proper initialization of the display.

IBM Monochrome
Register Register Program Display
Number File Unit (Address in hex)

RO Horizontal Total Characters 61

R1 Horizontal Displayed Characters 50
R2 Horizontal Sync Position Characters 52
R3 Horizontal Sync Width Characters F
R4 Vertical Total Character Rows 19
R5 Vertical Total Adjust Scan Line 6
R6 Vertical Displayed Character Row 19
R7 Vertical Sync Position Character Row 19
R8 Interlace Mode --------- 02
R9 Maximum Scan Line Scan Line D
Address
R10 Cursor Start Scan Line B
R11 Cursor End Scan Line C
R12 Start Address (H) --------- 00
R13 Start Address (Ll --------- 00
R14 Cursor (H) --------- 00
R15 Cursor (L) --------- 00
R16 Reserved --------- --
R17 Reserved --------- --

To ensure proper initialization, the first command issued to the

IBM Monochrome Display and Printer Adapter must be sent to
the CRT control port 1 (hex 3B8), and must be a hex 01, to set
the high-resolution mode. If this bit is not set, the system unit's
microprocessor's access to the adapter must never occur. If the
high-resolution bit is not set, the system unit's microprocessor will
stop running.

System configurations that have both an IBM Monochrome

Display and Printer Adapter, and an IBM Color/Graphics
Monitor Adapter, must ensure that both adapters are properly
initialized after a power-on reset. Damage to either display may
occur if not properly initialized.

Monochrome Adapter 5
The IBM Monochrome Display and Printer Adapter supports 256
different character codes. In the character set are alphanumerics
and block graphics. Each character in the display buffer has a
corresponding character attribute. The character code must be an
even address, and the attribute code must be an odd address in
the display buffer.

7 6 5 4 3 2 0
Character Code
Even Address (M)

7 6 5 4 3 2 0

FI R G
I B
I I
I R G
B I Attribute Code
Odd Address (M + 1)

Foreground

~
Intensity
I I I Background
I Blink

The adapter decodes the character attribute byte as defined

above. The blink and intensity bits may be combined with the
foreground and background bits to further enhance the character
attribute functions listed below:

Background Foreground
R G B R G B Function

0 0 0 0 0 0 Non-Display
0 0 0 0 0 1 Underline
0 0 0 1 1 1 White Character/Black Background
1 1 1 0 0 0 Reverse Video

The 4K display buffer supports one screen of the 25 rows of 80

characters, plus a character attribute for each display character.
The starting address of the buffer is hex BOOOO. The display
buffer can be read using direct memory access (DMA); however,
at least one wait state will be inserted by the system unit's
microprocessor. The duration of the wait state will vary, because
the microprocessor/monitor access is synchronized with the
character clock on this adapter.

6 Monochrome Adapter
Interrupt level 7 is used on the parallel interface. Interrupts can
be enabled or disabled through the printer control port. The
interrupt is a high-level active signal.

The following table breaks down the functions of the I/O address
decode for the adapter. The i/O address decode is from hex 3BO
through hex 3BF. The bit assignment for each I/O address
follows:

1/0 Register
Address Function
3BO Not Used
3B1 Not Used
3B2 Not Used
3B3 Not Used
3B4 6845 Index Register
3B5 6845 Data Register
3B6 Not Used
3B7 Not Used
3B8 CRT Control Port 1
3B9 Reserved
3BA CRT Status Port
3BB Reserved
3BC Parallel Data Port
3BD Printer Status Port
3BE Printer Control Port
3BF Not Used

1/0 Address and Bit Map

Monochrome Adapter 7
 Bit
Number Function
0 + High Resolution Mode
1 Not Used
2 Not Used
3 + Video Enable
4 Not Used
5 + Enable Blink
6,7 Not Used

6845 CRT Control Port 1 (Hex 388)

Bit
Number Function
0 + Horizontal Drive
1 Reserved
2 Reserved
3 + Black/White Video

6845 CRT Status Port (Hex 38A)

8 Monochrome Adapter
Specifications

9-Pin
Monochrome
Display
connector
o
1~6
5U
o
9

At Standard TTL Levels

Ground 1
Ground 2
Not Used 3
Not Used 4 IBM
IBM
Monochrome
Monochrome Not Used 5 Display and
Display
+ Intensity 6 Printer Adapter
+ Video 7
+ Horizontal 8
- Vertical 9

Note: Signal voltages are 0.0 to 0.6 Vdc at down level and + 2.4 to 3.5
Vdc at high level.

Connector Specifications

Monochrome Adapter 9
10 Monochrome Adapter
Printer Adapter Function

Description
The printer adapter portion of the IBM Monochrome Display and
Printer Adapter is specifically designed to attach printers with a
parallel-port interface, but it can be used as a general
input/ output port for any device or application that matches its
input/output capabilities. It has 12 TTL-buffer output points,
which are latched and can be written and read under program
control using the microprocessor In or Out instruction. The
adapter also has five steady-state input points that may be read
using the microprocessor's In instructions.

In addition, one input can also be used to create a microprocessor

interrupt. This interrupt can be enabled and disabled under
program control. A reset from the power-on circuit is also ORed
with a program output point, allowing a device to receive a
'power-on reset' when the system unit's microprocessor is reset.

The input/output signals are made available at the back of the

adapter through a right-angle, printed-circuit-board-mounted,
25-pin, D-shell connector. This connector protrudes through the
rear panel of the system unit or expansion unit, where a cable may
be attached.

When this adapter is used to attach a printer, data or printer

commands are loaded into an 8-bit, latched, output port, and the
strobe line is activated, writing data to the printer. The program
then may read the input ports for printer status indicating when
the next character can be written, or it may use the interrupt line
to indicate "not busy" to the software.

The output ports may also be read at the card's interface for
diagnostic loop functions. This allows faults to be isolated to the
adapter or the attaching device.

Monochrome Adapter 11
The following is a block diagram of the printer adapter portion of
the Monochrome Display and Printer Adapter.

L 8 25-Pin D-Shell
Connector

BUffe~r8:::....>-l~Data h_.....,8"--~
Bus
-..
Latc...
.
~ Enable ~ Clock

Trans- 14C8~___+-____~

r ceiver
DIR
L...---..J

,DIR O.C.
SLCTIN
Read Drivers
A~ Data
STROBE
Write Data I----r~
Command ~::..:..:..:~:....:.-:_ _ _ _+---.J AUTO
Decoder Write Control
FDXT
Read Status

Read INIT
I Control

Bus Control
Buffers Latch

~ Enable
~ 4 Clock f-
. 5

Y Enable
SLCT
r.
Reset
r rl Clear
PE

ACK

BUSY

Printer Adapter Block Diagram

12 Monochrome Adapter
Programming Considerations
The printer adapter portion of the IBM Monochrome Display and
Printer Adapter responds to five I/O instructions: two output
and three input. The output instructions transfer data into 2
latches whose outputs are presented on pins of a 25-pin D-shell
connector.

Two of the three input instructions allow the system unit's

microprocessor to read back the contents of the two latches. The
third allows the system unit's microprocessor to read the real-time
status from a group of pins on the connector.

A description of each instruction follows.

IBM Monochrome Display &

Printer Adapter
Output to address hex 3BC
Bit 7 Bit 6 Bit 5 Bit4
Pin 9 Pin 8 Pin 7 Pin 6

The instruction captures data from the data bus and is present on
the respective pins. Each of these pins is capable of sourcing 2.6
rnA and sinking 24 rnA.

It is essential that the external device does not try to pull these
lines to ground.

IBM Monochrome Display &

Printer Adpater

Output to address hex 3BE

Bit4

IRQ
Enable

This instruction causes the latch to capture the five least

significant bits of the data bus. The four least significant bits
present their outputs, or inverted versions of their outputs, to the

Monochrome Adapter 13
respective pins as shown in the previous figure. If bit 4 is written
as aI, the card will interrupt the system unit's microprocessor on
the condition that pin 10 changes from high to low.

These pins are driven by open-collector drivers pulled to +5 Vdc

through 4.7 kQ resistors. They can each sink approximately 7 mA
and maintain 0.8 volts down-level.

IBM Monochrome Display &

Printer Adapter
Input from address hex 3BC

This instruction presents the system unit's microprocessor with

data present on the pins associated with the output to hex 3BC.
This should normally reflect the exact value that was last written
to hex 3BC. If an external device should be driving data on these
pins at the time of an input (in violation of usage ground rules),
this data will be ORed with the latch contents.

IBM Monochrome Display &

Printer Adapter
Input from address hex 3BD

This instruction presents the real-time status to the system unit's

microprocessor from the pins as follows.

Bit 7 Bit 6 Bit 5 I Bit4 Bit 3 I Bit 2 I Bit 1 I Bit 0 I

Pin 11 Pin 10 Pin 12 I Pin 13 Pin 15 I- I -
r -
1

IBM Monochrome Display &

Printer Adapter
Input from address hex 3BE

14 Monochrome Adapter
This instruction causes the data present on pins 1, 14, 16, 17, and
the IRQ bit to be read by the system unit's microprocessor. In
the absence of external drive applied to these pins, data read by
the system unit's microprocessor will match data last written to
hex 3BE in the same bit positions. Notice that data bits 0-2 are
not included. If external drivers are dotted to these pins, that
data will be ORed with data applied to the pins by the hex 3BE
latch.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-
IRQ Pin 17 Pin 16 Pin 14 Pin 1
Enable
Por= 0 Por = 1 Por=O Por= 1 Por= 1

These pins assume the states shown after a reset from the system
unit's microprocessor.

Monochrome Adapter 15
16 Monochrome Adapter
Specifications

• • 14
• •
• •
• •
• •
• •
• •
•
• ••
• •
• ••
13 • 25
0

At Standard TTL Levels

Signal Adapter
Name Pin Number

- Strobe 1
+ D.ata Bit 0 2
+ Data Bit 1 3
+ Data Bit 2 4
+ Data Bit 3 5
+ Data Bit 4 6
+ Data Bit 5 7 IBM
+ Data Bit 6 8 Monochr orne
Printer + Data Bit 7 9 Display and
- Acknowledge 10 Printer
+ Busy 11 Adapter
+ P. End (out of paper) 12
+ Select 13
-Auto Feed 14
- Error 15
- Initialize Printer 16
- Select Input 17
Ground 18-25

Connector Specifications

Monochrome Adapter 17
18 Monochrome Adapter
 110 SLOT

~
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f 820

Monochrome Display Adapter (Sheet 1 of 10)

1/0 CLOCK [8H14)
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Monochrome Display Adapter (Sheet 2 of 10)

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Monochrome Display Adapter (Sheet 3 of 10)

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1 • 5~
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Monochrome Display Adapter (Sheet 4 of 10)

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2 12 ClR OA 11 "BLINK
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---
----
---
- - --- - Personal Computer
------
-
--_.-- ---
--- Hardware Reference
Library

mM Color/Graphics
Monitor Adapter

6361509
ii
Contents

Description .................................... 1
Controller ................................. 5
Mode Set Register . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
Character Generator ......................... 5
Timing Generator ........................... 6
Composite Color Generator ................... 6
Alphanumeric Mode ......................... 6
Graphics Modes ............................ 9
Basic Operations ........................... 12
Programming Considerations ..................... 15
Programming the Mode Control and Status Register 15
Programming the 6845 CRT Controller ......... 15
Color-Select Register ....................... 18
Mode-Control Register ...................... 19
Mode-Control Register Summary .............. 20
Status Register ............................ 20
Sequence of Events for Changing Modes ........ 21
Memory Requirements ...................... 22
Specifications ................................. 23
Logic Diagrams ................................ 27

Index ........................................ Index-l

iii
iv
Description

The IBM Color/Graphics Monitor Adapter is designed to attach

to the IBM Color Display, to a variety of television-frequency
monitors, or to home television sets (user-supplied RF modulator
is required for home television sets). The adapter is capable of
operating in black-and-white or color. It provides three video
interfaces: a composite-video port, a direct-drive port, and a
connection interface for driving a user-supplied RF modulator. A
light pen interface is also provided.

The adapter has two basic modes of operation: alphanumeric

(A/N) and all-points-addressable (APA) graphics. Additional
modes are available within the A/N or APA graphics modes. In
the A/N mode, the display can be operated in either a 40-column
by 25-row mode for a low-resolution monitor or home television,
or in an 80-column by 25-row mode for high-resolution monitors.
In both modes, characters are defined in an 8-wide by 8-high
character box and are 7-wide by 7-high, double dotted characters
with one descender. Both uppercase and lowercase characters are
supported in all modes.

The character attributes of reverse video, blinking, and

highlighting are available in the black-and-white mode. In the
color mode, 16 foreground and 8 background colors are available
for each character. In addition, blinking on a per-character basis
is available.

The monitor adapter contains 16K bytes of storage. As an

example, a 40-column by 25-row display screen uses 1000 bytes
to store character information and 1000 bytes to store
attribute/ color information. This means that up to eight screens
can be stored in the adapter memory. Similarly, in an 80-wide by
25-row mode, four display screens can be stored in the adapter
memory. The entire 16K bytes of storage in the display adapter
are directly accessible by the processor, which allows maximum
program flexibility in managing the screen.

In A/N color modes, it is also possible to select the color of the

screen's border. One of 16 colors can be selected.

Color/Graphics Monitor Adapter 1

In the AP A graphics mode, there are two resolutions available: a
medium-resolution color graphics mode (320 PELs by 200 rows)
and a high-resolution black-and-white graphics mode (640 PELs
by 200 rows). In the medium-resolution mode, each picture
element (PEL) may have one of four colors. The background
color (Color 0) may be any of the 16 possible colors. The
remaining three colors come from one of the two
program-selectable palettes. One palette contains
green/red/brown; the other contains cyan/magenta/white.

The high-resolution mode is available only in black-and-white

because the entire 16K bytes of storage in the adapter is used to
define the on or off state of the PELs.

The adapter operates in noninterlace mode at either 7 or 14 MHz,

depending on the mode of the operation selected.

In the A/N mode, characters are formed from a ROS character

generator. The character generator contains dot patterns for 256
different characters. The character set contains the following
major groupings of characters.

• 16 special characters for game support

• 15 characters for word-processing editing support

• 96 characters for the standard ASCII graphics set

• 48 characters for foreign-language support

• 48 characters for business block-graphics support (for the

drawing of charts, boxes, and tables using single and double
lines)

• 16 selected Greek characters

• 15 selected scientific-notation characters

The color/graphics monitor function is on a single adapter. The

direct-drive and composite-video ports are right-angle mounted
connectors on the adapter, and extend through the rear panel of

2 Color/Graphics Monitor Adapter

the system unit. The direct-drive video port is a 9-pin, D-shell,
female connector. The composite-video port is a standard female
phonojack.

The display adapter uses a Motorola 6845 CRT Controller device.

This adapter is highly programmable with respect to raster and
character parameters. Therefore, many additional modes are
possible with programming of the adapter.

On the following page is a block diagram of the Color/Graphics

Monitor Adapter.

Color/Graphics Monitor Adapter 3

Processor
A ddress o.
.. Address
Latch ~~ .
,o.
Display
Buffer
(16K Bytes)
r--
Input
Buffer
....
..... n
Processo
Data

~~ ~,

Processor
Data . 6845
CRT
~
Address
Latch r-
,Ir
Data
Latch
•
Data
Latch
~
Output
Latch
I--

Controller
f- .... Graphics
Serializer
I--

Character
~R
..
rL:..
Alpha
~
o.
Generator
~G
Serializer
ROM Color

I~
Palette/
Encoder
r-. B

~
Overscan

o.
..
I

Composite
. Horizontal
Vertical

4 Model
Control
.... Timing
Generator
o.
Color
Generator
r-.
& Control

Color/Graphics Monitor Adapter Block Diagram

Controller
The controller is a Motorola 6845 Cathode Ray Tube (CRT)
Controller. It provides the necessary interface to drive the
raster-scan CRT.

Mode Set Register

The mode set register is a general-purpose, programmable, I/O
register. It has I/O ports that may be individually programmed.
Its function in this adapter is to provide mode selection and color
selection in the medium-resolution color-graphics mode.

Display Buffer
The display buffer resides in the processor-address space, starting
at address hex B8000. It provides 16 bytes of dynamic
read/write memory. A dual-ported implementation allows the
processor and the graphics control unit access to this buffer. The
processor and the control unit have equal access to this buffer
during all modes of operation, except in the high-resolution
alphanumeric mode. In this mode, only the processor should have
access to this buffer during the horizontal-retrace intervals.
While the processor may write to the required buffer at any time,
a small amount of display interference will result if this does not
occur during the horizontal-retrace intervals.

Character Generator
A ROS character generator is used with 8K bytes of storage that
cannot be read from or written to under program control. This is
a general-purpose ROS character generator with three character
fonts. Two character fonts are used on the Color/Graphics
Monitor Adapter: a 7-high by 7-wide double-dot font and a
7 -high by 5-wide single-dot font. The font is selected by a
jumper (P3). The single-dot font is selected by inserting the
jumper; the double-dot font is selected by removing the jumper.

Color/Graphics Monitor Adapter 5

Timing Generator
This generator produces the timing signals used by the 6845 CRT
Controller and by the dynamic memory. It also solves the
processor/ graphic controller contentions for access to the display
buffer.

Composite Color Generator

This generator produces base-band-video color information.

Alphanumeric Mode
Every display character position in the alphanumeric mode is
defined by two bytes in the regen buffer (a part of the monitor
adapter), not the system memory. Both the Color/Graphics
Monitor Adapter and the Monochrome Display and Printer
Adapter use the following 2-byte character-attribute format.

Display-Character Code Byte Attribute Byte

7 6 543 2 o 7 6 543 2 o

The following table shows the functions of the attribute byte.

Attribute Function Attribute Byte

7 6 5 4 3 2 1 0
B R G B I R G B
FG Background Foreground
Normal B 0 0 0 I 1 1 1
Reverse Video B 1 1 1 I 0 0 0
Nondisplay (Black) B 0 0 0 I 0 0 0
Nondisplay (White) B 1 1 1 I 1 1 1

I = Highlighted Foreground (Character)

B = Blinking Foreground (Character)

6 Color/Graphics Monitor Adapter

The definitions of the attribute byte are in the following table.

7 654 3 2 1 0
IBIR G BII IR G BI

I L - - - _~: ~n~~e::i:~nd
I Color
I - : Background Color
Blinking

In the alphanumeric mode, the display can be operated in either a

low-resolution mode or a high-resolution mode.

The low-resolution alphanumeric mode has the following features:

• Supports home color televisions or low-resolution monitors.

• Displays up to 25 rows of 40 characters each.

• Has a ROS character generator that contains dot patterns for

a maximum of 256 different characters.

• Requires 2,000 bytes of read/write memory (on the adapter).

• Has an 8-high by 8-wide character box.

• Has two jumper-controlled character fonts available: a 7-high

by 5-wide single-dot character font with one descender, and a
7-high by 7-wide double-dotted character font with one
descender.

• Has one character attribute for each character.

The high-resolution alphanumeric mode has the following

features:

• Supports the IBM Color Display or other color monitor with

direct-drive capability.

• Supports a black-and-white composite-video monitor.

• Displays up to 25 rows of 80 characters each.

Color/Graphics Monitor Adapter 7

• Has a ROS display generator that contains dot patterns for a
maximum of 256 characters.

• Requires 4,000 bytes of read/write memory (on the adapter).

• Has an 8-high by 8-wide character box.

• Has two jumper-controlled character fonts available: a 7-high

by 5-wide single-dot character font with one descender, and a
7-high by 7-wide double-dot character font with one
descender.

• Has one character attribute for each character.

The Color/Graphics Monitor Adapter will change foreground and

background colors according to the color value selected in the
attribute byte. The following figure shows the color values for
the various red, green, blue, and intensity bit settings.

R G B I Color
0 0 0 0 Black
0 0 1 0 Blue
0 1 0 0 Green
0 1 1 0 Cyan
1 0 0 0 Red
1 0 1 0 Magenta
1 1 0 0 Brown
1 1 1 0 White
0 0 0 1 Gray
0 0 1 1 Light Blue
0 1 0 1 Light Green
0 1 1 1 Light Cyan
1 0 0 1 Light Red
1 0 1 1 Light Magenta
1 1 0 1 Yellow
1 1 1 1 White (High Intensity)

Note: Not all Monitors recognize the intensity (I) bit.

8 Color/Graphics Monitor Adapter

Graphics Modes
The Color/Graphics Monitor Adapter has three graphics modes:
low-resolution, medium-resolution, and high-resolution color
graphics. However, only medium- and high-resolution graphics
are supported in ROM. The following figure shows these modes.

Mode Horizontal Vertical Number of Colors Available

(PELs) (Rows) (Includes Background Color)
Low Resolution 160 100 16 (Includes black-and-white)
Medium 320 200 4 Colors Total
Resolution 1 of 1 6 for Background and
1 of Green, Red, or Brown or
1 of Cyan, Magenta, or White
High Resolution 640 200 Black-and-white only

Low-Resolution Color/Graphics Mode

The low-resolution mode supports home televisions or color
monitors. This mode, not supported in ROM, has the following
features:

• Contains a maxImum of 160 PELs by 100 rows, with each

PEL being 2-high by 2-wide.

• Specifies 1 of 16 colors for each PEL by the I, R, G, and B

bits.

• Requires 16,000 bytes of read/write memory on the adapter.

• Uses memory-mapped graphics.

Medium-Resolution Color/Graphics Mode

The medium-resolution mode supports home televisions or color
monitors. It has the following features:

• Contains a maximum of 320 PELs by 200 rows, with each

PEL being I-high by I-wide.

Color/Graphics Monitor Adapter 9

• Preselects 1 of 4 colors for each PEL.

• Requires 16,000 bytes of read/write memory on the adapter.

• Uses memory-mapped graphics.

• Formats 4 PELs per byte in the following manner:

7 6 5 4 3 2 o
C1 CO C1 CO C1 CO C1 CO
First Second Third Fourth
Display Display Display Display
PEL PEL PEL PEL

• Organizes graphics storage into two banks of 8,000 bytes,

using the following format:

Memory
Address
(in hex) Function
B8000
Even Scans
(0,2,4, ... 198)
8,000 bytes
B9F3F
Not Used
BAOOO
Odd Scans
(1,3,5 ... 199)
8,000 Bytes
BBF3F
Not Used
BBFFF

Address hex B8000 contains the PEL instruction for the

upper-left corner of the display area.

10 Color/Graphics Monitor Adapter

• Color selection is determined by the following logic:

C1 co Function
0 0 Dot takes on the color of 1 of 16 preselected background colors
0 1 Selects first color of preselected Color Set 1 or Color Set 2
1 0 Selects second color of preselected Color Set 1 or Color Set 2
1 1 Selects third color of preselected Color Set 1 or Color Set 2

C 1 and CO select 4 of 16 preselected colors. This color

selection (palette) is preloaded in an II a port.

The two color sets are:

Color Set 1 Color Set 2

Color 1 is Green Color 1 is Cyan
Color 2 is Red Color 2 is Magenta
Color 3 is Brown Color 3 is White

The background colors are the same basic 8 colors defined for
low-resolution graphics, plus 8 alternate intensities defined by
the intensity bit, for a total of 16 colors, including black and
white.

High-Resolution Black-and-White Graphics Mode

The high-resolution mode supports color monitors. This mode
has the following features:

• Contains a maximum of 640 PELs by 200 rows, with each

PEL being I-high by I-wide.

• Supports black-and-white only.

• Requires 16,000 bytes of read/write memory on the adapter.

• Addressing and mapping procedures are the same as

medium-resolution color/graphics, but the data format is
different. In this mode, each bit in memory is mapped to a
PEL on the screen.

Color/Graphics Monitor Adapter 11

• Formats 8 PELs per byte in the following manner:

First Display PEL I

~ I II
Second Display PEL
Third Display PEL
Fourth Display PEL
Fifth Display PEL
Sixth Display PEL
Seventh Display PEL
Eighth Display PEL

Basic Operations
In the alphanumeric mode, the adapter fetches character and
attribute information from its display buffer. The starting address
of the display buffer is programmable through the CRT
controller, but it must be an even address. The character codes
and attributes are then displayed according to their relative
positions in the buffer. The following addresses will produce an
"AB" in the upper-left corner of a 40 by 25 screen and an "X" in
the lower-right corner.

Memory
Address
(in hex) Display Buffer
B8000
(Even) Character Code A
Starting B8001
Address Attribute A
B8002 (Example of a 40 by 25 Screen)
Character Code B
B8003 AB
Attribute B

X
B87CE
Character Code X Video Screen
Last B87CF
Address Attribute X

12 Color/Graphics Monitor Adapter

The processor and the display control unit have equal access to
the display buffer during all of the operating modes, except the
high-resolution alphanumeric mode. During this mode, the
processor gains access to the display buffer during the vertical
retrace time. If it does not, the display will be affected with
random patterns as the microprocessor is using the display buffer.
In the alphanumeric mode, the characters are displayed from a
pre-stored ROM character generator that contains the dot
patterns for all of the displayable characters.

In the graphics mode, the displayed dots and colors, up to 16K

bytes, are fetched from the display buffer.

Color/Graphics Monitor Adapter 13

14 Color/Graphics Monitor Adapter
Programming Considerations

Programming the Mode Control and Status

Register
The following I/O devices are defined on the Color/Graphics
Monitor Adapter.

Hex
Address A9 AS A7 A6 A5 A4 A3 A2 A1 AD Function of Register

308 1 1 1 1 0 1 1 0 0 0 Mode Control Register (001

309 1 1 1 1 0 1 1 0 0 1 Color Select Register (001
30A 1 1 1 1 0 1 1 0 1 0 Status Register (011
30B 1 1 1 1 0 1 1 0 1 1 Clear Light Pen Latch
30C 1 1 1 1 0 1 1 1 0 0 Preset Light Pen Latch
304 1 1 1 1 0 1 0 Z Z 0 6845 Index Register
305 1 1 1 1 0 1 0 Z Z 1 6845 Oata Register

Z = don't care condition

Programming the 6845 CRT Controller

The controller has 19 internal accessible registers, which are used
to define and control a raster-scan CRT display. One of these
registers, the index register, is used as a pointer to the the other
18 registers. It is a write-only register, which is loaded from the
processor by executing an 'out' instruction to I/O address hex
3D4. The five least-significant bits of the I/O bus are loaded into
the index register.

In order to load any of the other 18 registers, the index register is

first loaded with the necessary pointer, then the data register is

Color / Graphics Monitor Adapter 15

loaded with the information to be placed in the selected register.
The data register is loaded from the processor by executing an
'out' instruction to I/O address hex 3D5.

The table on the next page defines the values that must be loaded
into the 6845 CRT Controller registers to control the different
modes of operation supported by the attachment.

16 Color/Graphics Monitor Adapter

 40 by 25 80 by 25
Address Register Register Alpha- Alpha- Graphic
Register Number Type Units I/O numeric numeric Modes
0 RO Horizontal Character Write 38 71 38
Total Only
1 R1 Horizontal Character Write 28 50 28
Displayed Only
2 R2 Horizontal Character Write 20 5A 20
Sync Position Only
3 R3 Horizontal Character Write OA OA OA
Sync Width Only
4 R4 Vertical Total Character Write 1F 1F 7F
Row Only
5 R5 Vertical Total Scan Write 06 06 06
Adjust Line Only
6 R6 Vertical Character Write 19 19 64
Displayed Row Only
7 R7 Vertical Character Write 1C 1C 70
Sync Position Row Only
8 R8 Interlace Write 02 02 02
Mode Only
9 R9 Maximum Scan Write 07 07 01
Scan Line Line Only
Address
A R10 Cursor Start Scan Write 06 06 06
Line Only
B R11 Cursor End Scan Write 07 07 07
Line Only
C R12 Start - Write 00 00 00
Address (H) Only
0 R13 Start Write 00 00 00
Address (L) Only
E R14 Cursor Read/ XX XX XX
Address (H) Write
F R15 Cursor Read/ XX XX XX
Address (L) Write
10 R16 Light Pen (H) - Read XX XX XX
Only
11 R17 Light Pen (L) - Read XX XX XX
Only

Note: All register values are given in hexadecimal

6845 Register Description

Color / Graphics Monitor Adapter 17

Color-Select Register
The color-select register is a 6-bit output-only register. Its I/O
address is hex 3D9, and it can be written to using a processor
'out' command. The following are the bit definitions for this
register.

Bit 0 Selects blue border color in 40 by 25 alphanumeric

mode.
Selects blue background color (CO-Cl) in 320 by 200
graphics mode.
Selects blue foreground color in 640 by 200 graphics
mode.

Bit 1 Selects green border color in 40 by 25 alphanumeric

mode.
Selects green background color (CO-Cl) in 320 by 200
graphics mode.
Selects green foreground color in 640 by 200 graphics
mode.

Bit 2 Selects red border color in 40 by 25 alphanumeric mode.

Selects red background color (CO-Cl) in 320 by 200
graphics mode.
Selects red foreground color in 640 by 200 graphics
mode.

Bit 3 Selects intensified border color in 40 by 25

alphanumeric mode.
Selects intensified background color (CO-Cl) in 320 by
200 graphics mode.
Selects intensified foreground color in 640 by 200
graphics mode.

Bit 4 Selects alternate, intensified set of colors in the graphics

mode.
Selects background colors in the alphanumeric mode.

Bit 5 Selects active color set in 320 by 200 graphics mode.

18 Color/Graphics Monitor Adapter

 When bit 5 is set to 1, colors are determined as follows:

C1 co Set Selected
0 0 Background (Defined by bits 0-3 of port hex 3D9)
0 1 Cyan
1 0 Magenta
1 1 White

When bit 5 is set to 0, colors are determined as follows:

C1 co Set Selected
0 0 Background (Defined by bits 0-3 of port hex 3D9)
0 1 Green
1 0 Red
1 1 Brown

Bit 6 Not used

Bit 7 Not used

Mode-Control Register
The mode-control register is a 6-bit output-only register. Its I/O
address is hex 3D8, and it can be written to using a processor
'out' command. The following are bit definitions for this register.

Bit 0 A 1 selects 80 by 25 alphanumeric mode.

A 0 selects 40 by 25 alphanumeric mode.

Bit 1 A 1 selects 320 by 200 graphics mode.

A 0 selects alphanumeric mode.

Bit 2 A 1 selects black-and-white mode.

A 0 selects color mode.

Bit 3 A 1 enables the video signal. The video signal is

disabled when changing modes.

Color/Graphics Monitor Adapter 19

Bit 4 A 1 selects the high-resolution (640 by 200)
black-and-white graphics mode. One of eight colors can
be selected on direct-drive monitors in this mode by
using register hex 3D9.

Bit 5 A 1 will change the character background intensity to

the blinking attribute function for alphanumeric modes.
When the high-order attribute is not selected, 16
background colors or intensified colors are available.
This bit is set to 1 to allow the blinking function.

Mode-Control Register Summary

Bits
0 1 2 3 4 5 40 x 25 Alphanumeric Black-and-White
0 0 1 1 0 1 40 x 25 Alphanumeric Color
0 0 0 1 0 1 80 x 25 Alphanumeric Black-and-White
1 0 1 1 0 1 80 x 25 Alphanumeric Color
1 0 0 1 0 1 320 x 200 Black-and-White Graphics
0 1 1 1 0 z 320 x 200 Color Graphics
0 1 0 1 0 z 640 x 200 Black-and-White Graphics
0 1 1 1 1 z

Enable Blink Attribute

640 x 200 Black-and-White
Enable Video Signal
Select Black-and-White Mode
Select 320 x 200 Graphics
80 x 25 Alphanumeric Select

z = don't care condition

Note: The low-resolution (160 by 100) mode requires special programming and is
set up as the 40 by 25 alphanumeric mode.

20 Color/Graphics Monitor Adapter

Status Register
The status register is a 4-bit read-only register. Its I/O address is
hex 3DA, and it can be read using the processor 'in' instruction.
The following are bit definitions for this register.

Bit 0 A 1 indicates that a regen-buffer memory access can be

made without interfering with the display.

Bit 1 A 1 indicates that a positive-going edge from the light

pen has set the light pen's trigger. This trigger is reset
when power is turned on and may also be cleared by a
processor 'out' command to hex address 3DB. No
specific data setting is required; the action is
address-activated.

Bit 2 The light pen switch is reflected in this bit. The switch
is not latched or debounced. A 0 indicates that the
switch is on.

Bit 3 A 1 indicates that the raster is in a vertical retrace mode.

Screen-buffer updating can be performed at this time.

Sequence of Events for Changing Modes

1 Determine the mode of operation.

2 Reset the video-enable bit in the mode-control register.

3 Program the 6845 CRT Controller to select the mode.

4 Program the mode-control and color-select registers

including re-enabling the video.

Color/Graphics Monitor Adapter 21

Memory Requirements
The memory used by this adapter is self-contained. It consists of
16K bytes of memory without parity. This memory is used as
both a display buffer for alphanumeric data and as a bit map for
graphics data. The regen buffer's address starts at hex B8000.

Read/Write Memory
Address Space (in hex)
01000
System
Read/Write
Memory
AOOOO

B8000
128K Reserved
Display Buffer Regen Area
(16K Bytes)
BCOOO

COOOO

22 Color/Graphics Monitor Adapter

Specifications

The following pages contain card and connector specifications for

the IBM Color/Graphics Monitor Adapter.

Color/Graphics Monitor Adapter 23

 0

· ·· 6
·
·
5 ··
·· 9
0

Color Direct
Drive 9-Pin
D-Shell Connector

At Standard TTL Levels

Ground 1
Ground 2
Red 3
IBM Color Display Green 4 Color/Graphics
or other Direct-Drive Blue 5 Direct-Drive
Monitor Adapter
Intensity 6
Reserved 7
Horizontal Drive 8
Vertical Drive 9

Composite Phono Jack

Hookup to Monitor

Composite Video Signal of

Approximately 1.5 Volts
V ideo Peak to Peak Amplitude Color/Graphics
1
M onitor Composi teJack
Chassis Ground 2

Connector Specifications (Part 1 of 21

24 Color/Graphics Monitor Adapter

 P1 (4- Pin Berg Strip) P2 (6-Pin Berg Strip)
for RF Modulator for Light-Pen
Connector

Color/Graphics
Monitor Adapter

+ 12 Volts 1
RF (key) Not Used 2 Color/Gr aphics
Mo dulator Monitor
Composite Video Output 3
Adapter
Logic Ground 4

RF Modulator Interface

- Light Pen Input 1

(key) Not Used 2
Lig ht Color/Gr aphics
Pe n - Light Pen Switch 3 Monitor
Chassis Ground 4 Adapter
+ 5 Volts 5
+ 12 Volts 6

Light Pen Interface

Connector Specifications (Part 2 of 2)

Color / Graphics Monitor Adapter 25

26 C910r/ Graphics Monitor Adapter
Logic Diagrams

The following pages contain the logic diagrams for the IBM
Color/Graphics Monitor Adapter.

Color/Graphics Monitor Adapter 27

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Color/Graphics Monitor Adapter (Sheet 1 of 6)

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Color/Graphics Monitor Adapter (Sheet 2 of 6)

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Color/Graphics Monitor Adapter (Sheet 6 of 6)

34 Color/Graphics Monitor Adapter
Index

alphanumeric mode 6

B
basic operations 12

c
change modes 21
character generator 5
color-select register 18
composite color generator 6
controller 5

description 1
display buffer 5

Index-l
G

graphics modes 9
high-resolution black-and-white 11
low-resolution color 9
medium-resolution color 9

H
high-resolution black-and-white graphics mode 11

logic diagrams 27
low-resolution color/graphics mode 9

medium-resolution color/graphics mode 9

memory requirements 22
mode set register 5
mode types
alphanumeric 6
graphics 9
mode-control register 19
mode-control register summary 20
modes of operation 1

Index-2
p

programming considerations 15
programming the mode control and status register 15
programming the 6845 crt controller 15

registers
color-select 18
mode control and status 15
mode set 5
mode-control 19
status 21

s
sequence of events for changing modes 21
specifications 23
status register 21

timing generator 6

Index-3
Index-4
---
----
- ----
---- -
------
- - --- Personal Computer

IBM Enhanced Graphics

Adapter
Contents

Description .................................... 1
Major Components .......................... 3
Modes of Operation ......................... 5
Basic Operations ............................ 8
Registers ................................. 12
Programming Considerations ..................... 62
Programming the Registers ................... 62
RAM Loadable Character Generator ........... 69
Creating a 512 Character Set ................. 70
Creating an 80 by 43 Alphanumeric Mode ....... 71
Vertical Interrupt Feature .................... 72
Creating a Split Screen ...................... 73
Compatibility Issues ........................ 74
Interface ..................................... 76
Feature Connector ......................... 76
Specifications ................................. 79
System Board Switches ...................... 79
Configuration Switches ...................... 80
Direct Drive Connector ...................... 83
Light Pen Interface ......................... 84
Jumper Descriptions ........................ 85
Logic Diagrams ................................ 87
BIOS Listing ................................. 103
Vectors with Special Meanings ............... 103

Index ........................................ Index-1

v
vi
Description

The IBM Enhanced Graphics Adapter (EGA) is a graphics

controller that supports both color and monochrome direct drive
displays in a variety of modes. In addition to the direct drive port,
a light pen interface is provided. Advanced features on the
adapter include bit-mapped graphics in four planes and a RAM
(Random Access Memory) loadable character generator. Design
features in the hardware substantially reduce the software
overhead for many graphics functions.

The Enhanced Graphics Adapter provides Basic Input Output

System (BIOS) support for both alphanumeric (A/N) modes and
all-points-addressable (AP A) graphics modes, including all modes
supported by the Monochrome Display Adapter and the
Color/Graphics Monitor Adapter. Other modes provide APA
640x350 pel graphics support for the IBM Monochrome Display,
full 16 color support in both 320x200 pel and 640x200 pel
resolutions for the IBM Color Display, and both A/N and APA
support with resolution of 640x350 for the IBM Enhanced Color
Display. In alphanumeric modes, characters are formed from one
of two ROM (Read Only Memory) character generators on the
adapter. One character generator defines 7x9 characters in a
9x14 character box. For Enhanced Color Display support, the
9x14 character set is modified to provide an 8x14 character set.
The second character generator defines 7x7 characters in an 8x8
character box. These generators contain dot patterns for 256
different characters. The character sets are identical to those
provided by the IBM Monochrome Display Adapter and the IBM
Color/Graphics Monitor Adapter.

The adapter contains 64K bytes of storage configured as four

16K byte bit planes. Memory expansion options are available to
expand the adapter memory to 128K bytes or 256K bytes.

The adapter is packaged on a single 13-1/8 inch (333.50 mm)

card. The direct drive port is a right-angle mounted connector at
the rear of the adapter and extends through the rear panel of the
system unit. Also on the card are five large scale integration
(LSI) modules custom designed for this controller.

August 2, 1984 IBM Enhanced Graphics Adapter 1

Located on the adapter is a feature connector that provides access
to internal functions through a 32-pin berg connector. A separate
64-pin connector provides an interface for graphics memory
expansion.

The following is a block diagram of the Enhanced Graphics

Adapter:

CPU
Addr.
.
..J... MUX L
CPU ... ... CRTC ~
Data LSI
• H 1~
:1 GRAPH L
~ LSI ....
~ BIT 0 -
MAP ~~

..- -j GRAPH ...'" ..

.:J 3 ~~
... LSI 2
4 I-- '\ f- ~ BIT r-
SEQ
MAP ~~
lSI
I--
..
r
~
...
.. ATTRIB ... DIRECT
LSI .. DRIVE
-""
i OUTPUT

Enhanced Graphics Adapter Block Diagram

2 IBM Enhanced Graphics Adapter August 2, 1984

Major Components
CRT Controller
The CRT (Cathode Ray Tube) Controller (CRTC) generates
horizontal and vertical synchronous timings, addressing for the
regenerative buffer, cursor and underline timings, and refresh
addressing for the dynamic RAMs.

Sequencer
The Sequencer generates basic memory timings for the dynamic
RAMs and the character clock for controlling regenerative
memory fetches. It allows the processor to access memory during
active display intervals by inserting dedicated processor memory
cycles periodically between the display memory cycles. Map
mask registers are available to protect entire memory maps from
being changed.

Graphics Controller
The Graphics Controller directs the data from the memory to the
attribute controller and the processor. In graphics modes,
memory data is sent in serialized form to the attribute chip. In
alpha modes the memory data is sent in parallel form, bypassing
the graphics controller. The graphics controller formats the data
for compatible modes and provides color comparators for use in
color painting modes. Other hardware facilities allow the
processor to write 32 bits in a single memory cycle, (8 bits per
plane) for quick color presetting of the display areas, and
additional logic allows the processor to write data to the display
on non-byte boundaries.

Attribute Controller
The Attribute Controller provides a color palette of 16 colors,
each of which may be specified separately. Six color outputs are

August 2, 1984 IBM Enhanced Graphics Adapter 3

available for driving a display. Blinking and underlining are
controlled by this chip. This chip takes data from the display
memory and formats it for display on the CRT screen.

Display Buffer
The display buffer on the adapter consists of 64K bytes of
dynamic read/write memory configured as four 16K byte video
bit planes. Two options are available for expanding the graphics
memory. The Graphics Memory Expansion Card plugs into the
memory expansion connector on the adapter, and adds one bank
of 16K to each of the four bit planes, increasing the graphics
memory to 128K bytes. The expansion card also provides DIP
sockets for further memory expansion. Populating the DIP
sockets with the Graphics Memory Module Kit adds two
additional 16K banks to each bit plane, bringing the graphics
memory to its maximum of 256K bytes.

The address of the display buffer can be changed to remain

compatible with other video cards and application software. Four
locations are provided. The buffer can be configured at segment
address hex AOOOO for a length of 128K bytes, at hex AOOOO for
a length of 64K bytes, at hex BOOOO for a length of 32K bytes, or
at hex B8000 for a length of 32K bytes.

BIOS
A read-only memory (ROM) Basic Input Output System (BIOS)
module on the adapter is linked to the system BIOS. This ROM
BIOS contains character generators and control code and is
mapped into the processor address at hex COOOO for a length of
16K bytes.

Support Logic
The logic on the card surrounding the LSI modules supports the
modules and creates latch buses for the CRT controller, the

4 IBM Enhanced Graphics Adapter August 2, 1984

processor, and character generator. Two clock sources (14 MHz
and 16 MHz) provide the dot rate. The clock is multiplexed
under processor I/O control. The four I/O registers on the card
are not part of the LSI devices.

Modes of Operation
IBM Color Display
The following table describes the modes supported by BIOS on
the IBM Color Display:

Alpha Buffer Box Max.

Mode # Type Colors Format Start Size Pages Resolution
0 A/N 16 40x25 B8000 8x8 8 320x200
1 A/N 16 40x25 B8000 8x8 8 320x200
2 A/N 16 80x25 B8000 8x8 4/8/8 640x200
3 A/N 16 80x25 B8000 8x8 4/8/8 640x200
4 APA 4 40x25 B8000 8x8 1 320x200
5 APA 4 40x25 B8000 8x8 1 320x200
6 APA 2 80x25 B8000 8x8 1 640x200
D APA 16 40x25 AOOOO 8x8 2/4/8 320x200
E APA 16 80x25 AOOOO 8x8 1/2/4 640x200

°
Modes through 6 emulate the support provided by the IBM
Color/Graphics monitor Adapter.

Modes 0, 2, and 5 are identical to modes 1, 3, and 4, respectively,

at the adapter's direct drive interface.

The "MAX. PAGES" fields for modes 2,3, D, and E indicate the
number of pages supported when 64K, 128K, or 256K bytes of
graphics memory is installed, respectively.

January 20, 1986 IBM Enhanced Graphics Adapter 5

IBM Monochrome Display
The following table describes the modes supported by BIOS on
the IBM Monochrome Display.

Alpha Buffer Box Max.

Mode # Type Colors Format Start Size Pages Resolution
7 A/N 4 80x25 BOOOO 9x14 4/8 720x350
F APA 4 80x25 AOOOO 8x14 1/2 640x350

The "MAX. PAGES" fields for modes 7 and F indicate the

number of pages supported when either 64K or greater than 64K
of graphics memory is installed, respectively.

Mode 7 emulates the support provided by the IBM Monochrome

Display Adapter.

IBM Enhanced Color Display

The Enhanced Graphics Adapter supports attachment of the IBM
Enhanced Color Display. The IBM Enhanced Color Display is
capable of running at the standard television frequency of 15.75
KHz as well as running21.85 KHz. The tabl~ below summarizes
the characteristics of the IBM Enhanced Color Display:

Parameter TV Frequency High Resolution

Horiz Scan Rate 15.75 KHz. 21.85 KHz.
Vertical Scan Rate 60 Hz. 60 Hz.
Video Bandwidth 14.318 MHz. 16.257 MHz.
Displayable Colors 16 Maximum 16 or 64
Character Size 7 by 7 Pels 7 by 9 Pels
Character Box Size 8 by8 Pels 8 by 14 Pels
Maximum Resolution 640x200 Pels 640 by 350 Pels
Alphanumeric Modes 0,1,2,3 0,1,2,3
Graphics Modes 4,5,6,D,E 10

In the television frequency mode, the IBM Enhanced Color

Display displays information identical in color and resolution to
the IBM Color Display.

6 IBM Enhanced Graphics Adapter January 20, 1986

In the high resolution mode, the adapter provides enhanced
alphanumeric character support. This enhanced alphanumeric
support consists of transforming the 8 by 8 character box into an
8 by 14 character box, and providing 16 colors out of a palette of
64 possible display colors. Display colors are changed by altering
the programming of the color palette registers in the Attribute
Controller. In alphanumeric modes, any 16 of 64 colors are
displayable. The screen resolution is 320x350 for modes 0 and 1,
and 640x350 for modes 2 and 3.

The resolution displayed on the IBM Enhanced Color Display is

selected by the switch settings on the Enhanced Graphics
Adapter.

The Enhanced Color Display is compatible with all modes listed

for the IBM Color Display. The following table describes
additional modes supported by BIOS for the IBM Enhanced
Color Display:

Alpha Buffer Box Max.

Mode # Type Colors Format Start Size Pages Resolution
0* A/N 16/64 40x25 88000 8x14 8 320x350
1* A/N 16/64 40x25 88000 8x14 8 320x350
2* A/N 16/64 80x25 88000 8x14 4/8 640x350
3* A/N 16/64 80x25 88000 8x14 4/8 640x350
10 APA 4/16 80x25 AOOOO 8x14 1/2 640x350
16/64

* Note that modes 0, 1,2, and 3 are also listed for IBM Color
Display support. BIOS provides enhanced support for these
modes when an Enhanced Color Display is attached.

The values in the "COLORS" field indicate 16 colors of a 64

color palette or 4 colors of a sixteen color palette.

In modes 2, 3, and 10, the dual values for the "COLORS" field
and the "MAX. PAGES" field indicate the support provided
when eit4er 64K or greater than 64K of graphics memory is
installed, respectively.

January 20, 1986 IBM Enhanced Graphics Adapter 7

Basic Operations
Alphanumeric Modes
The data format for alphanumeric modes on the Enhanced
Graphics Adapter is the same as the data format on the IBM
Color / Graphics Monitor Adapter and the IBM Monochrome
Display Adapter. As an added function, bit three of the attribute
byte may be redefined by the Character Map Select register to act
as a switch between character sets. This gives the programmer
access to 512 characters at one time. This function is valid only
when memory has been expanded to 128K bytes or more.

When an alphanumeric mode is selected, the BIOS transfers

character patterns from the ROM to bit plane 2. The processor
stores the character data in bit plane 0, and the attribute data in
bit plane 1. The programmer can view bit planes 0 and 1 as a
single buffer in alphanumeric modes. The CRTC generates
sequential addresses, and fetches one character code byte and one
attribute byte at a time. The character code and row scan count
address bit plane 2, which contains the character generators. The
appropriate dot patterns are then sent to the palette in the
attribute chip, where color is assigned according to the attribute
data.

Graphics Modes

320x200 Two and Four Color Graphics (Modes 4 and 5)

Addressing, mapping and data format are the same as the

320x200 pel mode of the Color/Graphics Monitor Adapter. The
display buffer is configured at hex B8000. Bit image data is
stored in bit planes 0 and 1.

640x200 Two Color Graphics (Mode 6)

Addressing, mapping and data format are the same as the

640x200 pel black and white mode of the Color/Graphics

8 IBM Enhanced Graphics Adapter January 20, 1986

Monitor Adapter. The display buffer is configured at hex B8000.
Bit image data is stored in bit plane O.

640x350 Monochrome Graphics (Mode F )

This mode supports graphics on the IBM Monochrome Display

with the following attributes: black, video, blinking video, and
intensified video. Resolution of 640x350 requires 56K bytes to
support four attributes. By chaining maps 0 and 1, then maps 2
and 3 together, two 32K bit planes can be formed. This chaining
is done only when necessary (less than 128K of graphics
memory). The first map is the video bit plane, and the second
map is the intensity bit plane. Both planes reside at hex address
AOOOO.

Two bits, one from each bit plane, define one picture element
(pel) on the screen. The bit definitions for the pels are given in
the following table. The video bit plane is denoted by CO and the
Intensity Bit Plane is denoted by C2.

C2 co Pixel Color Valid Attributes

0 0 Black 0
0 1 Video 3
1 0 Blinking Video C
1 1 Intensified Video F

The byte organization in memory is sequential. The first eight

pels on the screen are defined by the contents of memory in
location AOOO:OH, the second eight pels by location AOOO:1H,
and so on. The first pel within anyone byte is defined by bit 7 in
the byte. The last pel within the byte is defined by bit 0 in the
byte.

Monochrome graphics works in odd/even mode, which means

that even CPU addresses go into even bit planes and odd CPU
addresses go into odd bit planes. Since both bit planes reside at
address AOOOO, the user must select which plane or planes he
desires to update. This is accomplished by the map mask register
of the sequencer. (See the table above for valid attributes).

August 2, 1984 IBM Enhanced Graphics Adapter 9

16/64 Color Graphics Modes (Mode 10)

These modes support graphics in 16 colors on either a medium or

high resolution monitor. The memory in these modes consists of
using all four bit planes. Each bit plane represents a color as
shown below. The bit planes are denoted as CO,Cl,C2 and C3
respectively.

co = Blue Pels
C 1 = Green Pels
C2 = Red Pels
C3 = Intensified Pels

Four bits (one from each plane) define one pelon the screen.
The color combinations are illustrated in the following table:

I R G B Color
0 0 0 0 Black
0 0 0 1 Blue
0 0 1 0 Green
0 0 1 1 Cyan
0 1 0 0 Red
0 .1 0 1 Magenta
0 1 1 0 Brown
0 1 1 1 White
1 0 0 0 Dark Gray
1 0 0 1 Light Blue
1 0 1 0 Light Green
1 0 1 1 Light Cyan
1 1 0 0 Light Red
1 1 0 1 Light Magenta
1 1 1 0 Yellow
1 1 1 1 Intensified White

The display buffer resides at address AOOOO. The map mask

register of the sequencer is used to select any or all of the bit
planes to be updated when a memory write to the display buffer is
executed by the CPU.

Color Mapping

The Enhanced Graphics Adapter supports 640x350 Graphics for

both the IBM Monochrome and the mM Enhanced Color

10 mM Enhanced Graphics Adapter August 2, 1984

Displays. Four color capability is supported on the EGA without
the Graphics Memory Expansion Card (base 64 KB), and sixteen
colors are supported when the Graphics Memory Expansion Card
is installed on the adapter (128 KB or above). This section
describes the differences in the colors displayed depending upon
the graphics memory available. Note that colors OH, 1H, 4H, and
7H map directly regardless of the graphics memory available.

Character Mode 10H Mode 10H

Attribute Monochrome 64KB >64KB
OOH* Black Black Black
01H* Video Blue Blue
02H Black Black Green
03H Video Blue Cyan
04H* Blinking Red Red
05H Intensified White Magenta
06H Blinking Red Brown
07H* Intensified White White
08H Black Black Dark Gray
09H Video Blue Light Blue
OAH Black Black Light Green
OBH Video Blue Light Cyan
OCH Blinking Red Light Red
ODH Intensified White Light Magenta
OEH Blinking Red Yellow
OFH Intensified White Intensified White

* Graphics character attributes which map directly regardless of

the graphics memory available.

August 2, 1984 IBM Enhanced Graphics Adapter 11

Registers
External Registers
This section contains descriptions of the registers of the Enhanced
Graphics Adapter that are not contained in an LSI device.

Name Port Index

Miscellaneous Output Register 3C2 -
Feature Control Register 3?A -
Input Status Register 0 3C2 -
Input Status Register 1 3?2 -
? = B in Monochrome Modes ? = D in Color Modes

Miscellaneous Output Register

This is a write-only register. The processor output port address is

hex 3C2. A hardware reset causes all bits to reset to zero.

Miscellaneous Output Register Format

Bit 7 6 5 4 3 2 1 0

I/O Address Select

Enable Ram
Clock Select 0
Clock Select 1
L--_ _ _ _ _~ Disable Internal Video Drivers
Page Bit For Odd/Even
Horizontal Retrace Polarity
L..-----------l~ Vertical Retrace Polarity

Bit 0 3BX/3DX CRTC I/O Address-This bit maps

the CRTC I/O addresses for IBM Monochrome
or Color/Graphics Monitor Adapter emulation.
A logical 0 sets CRTC addresses to 3BX and
Input Status Register 1 's address to 3BA for
Monochrome emulation. A logical 1 sets CRTC

12 IBM Enhanced Graphics Adapter August 2, 1984

 addresses to 3DX and Input Status Register l's
address to 3DA for Color/Graphics Monitor
Adapter emulation.

Bit 1 Enable RAM-A logical 0 disables RAM from

the processor; a logical 1 enables RAM to
respond at addresses designated by the Control
Data Select value programmed into the Graphics
Controllers.

Bit 2-Bit 3 Clock Select-These two bits select the clock

source according to the following table:

Bits
3 2

o 0- Selects 14 MHz clock from the processor

I/O channel
o 1- Selects 16 MHz clock on-board oscillator
1 0- Selects external clock source from the
feature connector.
1 1- Not used

Bit 4 Disable Internal Video Drivers-A logical 0

activates internal video drivers; a logical 1
disables internal video drivers. When the internal
video drivers are disabled, the source of the direct
drive color output becomes the feature connector
direct drive outputs.

Bit 5 Page Bit For Odd/Even-Selects between two

64K pages of memory when in the Odd/Even
modes (0,1,2,3,7). A logical 0 selects the low
page of memory; a logical 1 selects the high page
of memory.

Bit 6 Horizontal Retrace Polarity-A logical 0 selects

positive horizontal retrace; a logical 1 selects
negative horizontal retrace.

Bit 7 Vertical Retrace Polarity-A logical 0 selects

positive vertical retrace; a logical 1 selects

August 2, 1984 IBM Enhanced Graphics Adapter 13

 negative vertical retrace. The IBM Monochrome
display requires a negative vertical retrace
polarity.

Feature Control Register

This is a write-only register. The processor output register is hex

3BA or 3DA.

Feature Control Register Format

Bit 7 6 5 4 3 2 1 0

Feature Control Bit 0

Feature Control Bit 1
Reserved
Not Used

Bits 0 and 1 Feature Control Bits-These bits are used to

convey information to the feature connector.
The output of these bits goes to the FEAT 0 (pin
19) and FEAT 1 (pin 17) of the feature
connector.

Input Status Register Zero

This is a read-only register. The processor input port address is

hex 3C2.

14 mM Enhanced Graphics Adapter August 2, 1984

 Input Status Register Zero Format

Bit 7 6 5 4 3 2 1 0

IIII
I
I
: Not Used
Switch Sense
Reserved
Reserved
CRT Interrupt

Bit 4 Switch Sense-When set to 1, this bit allows the

processor to read the four configuration switches
on the board. The setting of the CLKSEL field
determines which switch is being read. The
switch configuration can be determined by
reading byte 40:88H in RAM.

Bit 3: Switch 4 ; Logical 0 = switch closed

Bit 2: Switch 3 ; Logical 0 = switch closed
Bit 1: Switch 2 ; Logical 0 = switch closed
Bit 0: Switch 1 ; Logical 0 = switch closed

Bits 5 and 6 Feature Code-These bits are input from the

Feat (0) and Feat (1) pins on the feature
connector.

Bit 7 CRT Interrupt-A logical 1 indicates video is

being displayed on the CRT screen; a logical 0
indicates that vertical retrace is occurring.

Input Status Register One

This is a read-only register. The processor port address is hex

3BA or hex 3DA.

August 2, 1984 IBM Enhanced Graphics Adapter 15

 Input Status Register One Format

Bit 7 6 5 4 3 2 1 0

Display Enable
Light Pen Strobe
Light Pen Switch
Vertical Retrace
Diagnostic 1
Diagnostic 0
Not Used

Bit 0 Display Enable-Logical 0 indicates the CRT

raster is in a horizontal or vertical retrace
interval. This bit is the real time status of the
display enable signal. Some programs use this
status bit to restrict screen updates to inactive
display intervals. The Enhanced Graphics
Adapter does not require the CPU to update the
screen buffer during inactive display intervals to
avoid glitches in the display image.

Bit 1 Light Pen Strobe-A logical 0 indicates that the

light pen trigger has not been set; a logical 1
indicates that the light pen trigger has been set.

Bit 2 Light Pen Switch-A logical 0 indicates that the

light pen switch is closed; a logical 1 indicates
that the light pen switch is open.

Bit 3 Vertical Retrace-A logical 0 indicates that video

information is being displayed on the CRT
screen; a logical 1 indicates the CRT is in a
vertical retrace interval. This bit can be
programmed to interrupt the processor on
interrupt level 2 at the start of the vertical
retrace. This is done through bits 4 and 5 of the
Vertical Retrace End Register of the CRTC.

Bits 4 and S Diagnostic Usage-These bits are selectively

connected to two of the six color outputs of the

16 IBM Enhanced Graphics Adapter August 2, 1984

 Attribute Controller. The Color Plane Enable
register controls the multiplexer for the video
wiring. The following table illustrates the
combinations available and the color output
wiring.

Color Plane Input Status

Register Register One
Bit S Bit4 BitS Bit4
0 0 Red Blue
0 1 Secondary Blue Green
1 0 Secondary Red Secondary Green
1 1 Not Used Not Used

August 2, 1984 IBM Enhanced Graphics Adapter 17

Sequencer Registers

Name Port Index

Address 3C4 -
Reset 3C5 00
Clocking Mode 3C5 01
Map Mask 3C5 02
Character Map Select 3C5 03
Memory Mode 3C5 04

Sequencer Address Register

The Address Register is a pointer register located at address hex

3C4. This register is loaded with a binary value that points to the
sequencer data register where data is to be written. This value is
referred to as "Index" in the table above.

Sequencer Address Register Format

Bit 7 6 5 4 3 2 1 0

IIII II I I
L...----L.---'.--------I_~
:: Sequencer Address
Not Used

Bit O-Bit 3 Sequencer Address Bits-A binary value pointing

to the register where data is to be written.

Reset Register

This is a write-only register pointed to when the value in the

address register is hex 00. The output port address for this
register is hex 3C5.

18 IBM Enhanced Graphics Adapter August 2, 1984

 Reset Register Format

Bit 7 6 5 4 3 2 1 0

IIIIIII~
Asynchronous Reset
Synchronous Reset
Not Used

Bit 0 Asynchronous Reset-A logical 0 commands the

sequencer to asynchronous clear and halt. All
outputs are placed in the high impedance state
when this bit is a O. A logical 1 commands the
sequencer to run unless bit 1 is set to zero.
Resetting the sequencer with this bit can cause
data loss in the dynamic RAMs.

Bit 1 Synchronous Reset-A logical 0 commands the

sequencer to synchronous clear and halt. Bits 1
and 0 must both be ones to allow the sequencer
to operate. Reset the sequencer with this bit
before changing the Clocking Mode Register, if
memory contents are to be preserved.

Clocking Mode Register

This is a write-only register pointed to when the value in the

address register is hex 01. The output port address for this
register is hex 3C5.

Clocking Mode Register Format

Bit 7 6 5 4 3 2 1 0

8/9 Dot Clocks

Bandwidth
Shift Load
Dot Clock
Not Used

August 2, 1984 IBM Enhanced Graphics Adapter 19

Bit 0 8/9 Dot Clocks-A logical 0 directs the
sequencer to generate character clocks 9 dots
wide; a logical 1 directs the sequencer to generate
character clocks 8 dots wide. Monochrome
alphanumeric mode (07H) is the only mode that
uses character clocks 9 dots wide. All other
modes must use 8 dots per character clock.

Bit 1 Bandwidth-A logical 0 makes CRT memory

cycles occur on 4 out of 5 available memory
cycles; a logical 1 makes CRT memory cycles
occur on 2 out of 5 available memory cycles.
Medium resolution modes require less data to be
fetched from the display buffer during the
horizontal scan time. This allows the CPU
greater access time to the display buffer. All high
resolution modes must provide the CRTC with 4
out of 5 memory cycles in order to refresh the
display image.

Bit 2 Shift Load-When set to 0, the video serializers

are reloaded every character clock; when set to 1,
the video serializers are loaded every other
character clock. This mode is useful when 16 bits
are fetched per cycle and chained together in the
shift registers.

Bit 3 Dot Clock-A logical 0 selects normal dot clocks

derived from the sequencer master clock input.
When this bit is set to 1, the master clock will be
divided by 2 to generate the dot clock. All the
other timings will be stretched since they are
derived from the dot clock. Dot clock divided by
two is used for 320x200 modes (0, 1,4,5) to
provide a pixel rate of 7 MHz, (9 MHz for mode
D).

Map Mask Register

This is a write-only register pointed to when the value in the

address register is hex 02. The output port address for this
register is hex 3C5.

20 IBM Enhanced Graphics Adapter August 2, 1984

 Map Mask Register Format

Bit 7 6 5 4 3 2 1 0

1 Enables Map 0
1 Enables Map 1
1 Enables Map 2
1 Enables Map 3
Not Used

Bit O-Bit 3 Map Mask-A logical 1 in bits 3 through 0

enables the processor to write to the
corresponding maps 3 through O. If this register
is programmed with a value of OFH, the CPU can
perform a 32-bit write operation with only one
memory cycle. This substantially reduces the
overhead on the CPU during display update
cycles in graphics modes. Data scrolling
operations are also enhanced by setting this
register to a value of OFH and writing the display
buffer address with the data stored in the CPU
data latches. This is a read-modify-write
operation. When odd! even modes are selected,
maps 0 and 1 and maps 2 and 3 should have the
same map mask value.

Character Map Select Register

This is a write-only register pointed to when the value in the

address register is hex 03. The output port address for this
register is 3C5.

August 2, 1984 IBM Enhanced Graphics Adapter 21

 Character Map Select Register Format

Bit 7 6 5 4 3 2 1 0

I I ~I::
IIII ~I - -
Character Map Select 8
Character Map Select A
'--""---'----'-------~ Not Used

Bit O-Bit 1 Character Map Select B-Selects the map used

to generate alpha characters when attribute bit 3
is a 0, according to the following table:

Bits Map
1 0 Selected Table Location

Value
0 0 0 1st 8K of Plane 2 Bank 0
0 1 1 2nd 8K of Plane 2 Bank 1
1 0 2 3rd 8K of Plane 2 Bank 2
1 1 3 4th 8K of Plane 2 Bank 3

Bit 2-Bit 3 Character Map Select A-Selects the map used

to generate alpha characters when attribute bit 3
is aI, according to the following table:

Bits Map
3 2 Selected Table Location

Value
0 0 0 1st 8K of Plane 2 Bank 0
0 1 1 2nd 8K of Plane 2 Bank 1
1 0 2 3rd 8K of Plane 2 Bank 2
1 1 3 4th 8K of Plane 2 Bank 3

In alphanumeric modes, bit 3 of the attribute byte normally has

the function of turning the foreground intensity on or off. This
bit however may be redefined as a switch between character sets.
This function is enabled when there is a difference between the
value in Character Map Select A and the value in Character Map
Select B. Whenever these two values are the same, the character
select function is disabled. The memory mode register bit 1 must
be a 1 (indicates the memory extension card is installed in the
unit) to enable this function; otherwise, bank 0 is always selected.

22 IBM Enhanced Graphics Adapter August 2, 1984

128K of graphics memory is required to support two character
sets. 256K supports four character sets. Asynchronous reset
clears this register to O. This should be done only when the
sequencer is reset.

Memory Mode Register

This is a write-only register pointed to when the value in the

address register is hex 04. The processor output port address for
this register is 3C5.

Memory Mode Register Format

Bit 7 6 5 4 3 2 1 0

E Alpha
Extended Memory
Odd/Even
Not Used

Bit 0 Alpha-A logical 0 indicates that a non-alpha

mode is active. A logical 1 indicates that alpha
mode is active and enables the character
generator map select function.

Bit 1 Extended Memory-A logical 0 indicates that the

memory expansion card is not installed. A logical
1 indicates that the memory expansion card is
installed and enables access to the extended
memory through address bits 14 and 15.

Bit 2 Odd/Even-A logical 0 directs even processor

addresses to access maps 0 and 2, while odd
processor addresses access maps 1 and 3. A
logical 1 causes processor addresses to
sequentially access data within a bit map. The
maps are accessed according to the value in the
map mask register.

August 2, 1984 IBM Enhanced Graphics Adapter 23

CRT Controller Registers

Name Port Index

Address Register 3?4 -
Horizontal Total 3?5 00
Horizontal Display End 3?5 01
Start Horizontal Blank 3?5 02
End Horizontal Blank 3?5 03
Start Horizontal Retrace 3?5 04
End Horizontal Retrace 3?5 05
Vertical Total 3?5 06
Overflow 3?5 07
Preset Row Scan 3?5 08
Max Scan Line 3?5 09
Cursor Start 3?5 OA
Cursor End 3?5 OB
Start Address High 3?5 OC
Start Address Low 3?5 00
Cursor Location High 3?5 OE
Cursor Location Low 3?5 OF
Vertical Retrace Start 3?5 10
Light Pen High 3?5 10
Vertical Retrace End 3?5 11
Light Pen Low 3?5 11
Vertical Display End 3?5 12
Offset 3?5 13
Underline Location 3?5 14
Start Vertical Blank 3?5 15
End Vertical Blank 3?5 16
Mode Control 3?5 17
Line Compare 3?5 18
? = B in Monochrome Modes and 0 in Color Modes

CRT Controller Address Register

The Address register is a pointer register located at hex 3B4 or

hex 3D4. If an IBM Monochrome Display is attached to the
adapter, address 3B4 is used. If a color display is attached to the
adapter, address 3D4 is used. This register is loaded with a binary
value that points to the CRT Controller data register where data
is to be written. This value is referred to as "Index" in the table
above.

24 IBM Enhanced Graphics Adapter August 2, 1984

 CRT Controller Address Register Format

Bit 7 6 5 4 3 2 1 0

Bit O-Bit 4 CRT Controller Address Bits-A binary value

pointing to the CRT Controller register where
data is to be written.

Horizontal Total Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 00. The processor output port
address for this register is hex 3B5 or hex 3D5.

Horizontal Total Register Format

Bit 7 6 5 4 3 2 1 0

&-.1-,-I---II-..L-I-L.I---II--L-I-,-I~.. Horizontal Total

This register defines the total number of characters in the

horizontal scan interval including the retrace time. The value
directly controls the period of the horizontal retrace output signal.
An internal horizontal character counter counts character clock
inputs to the CRT Controller, and all horizontal and vertical
timings are based upon the horizontal register. Comparators are
used to compare register values with horizontal character values
to provide horizontal timings.

Bit O-Bit 7 Horizontal Total-The total number of

characters less 2.

August 2, 1984 IBM Enhanced Graphics Adapter 25

Horizontal Display Enable End Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 01. The processor output port
address for this register is hex 3B5 or hex 3D5.

Horizontal Display Enable End Register Format

BH 7 6 5 4 3 2 1 0

L-I---LI--LI---II_.L..I--,-I---LI---LI_-t.~ Horizontal Display Enable End

This register defines the length of the horizontal display enable

signal. It determines the number of displayed character positions
per horizontal line.

Bit O-Bit 7 Horizontal display enable end -A value one less

than the total number of displayed characters.

Start Horizontal Blanking Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 02. The processor output port
address for this register is hex 3B5 or hex 3D5.

Start Horizontal Blanking Register Format

Bit 7 6 5 4 3 2 1 0

I I I I I I I I ~ Start Vertical Blanking

This register determines when the horizontal blanking output

signal becomes active. The row scan address and underline scan
line decode outputs are multiplexed on the memory address
outputs and cursor outputs respectively during the blanking
interval. These outputs are latched external to the CRT
Controller with the falling edge of the BLANK output signal.
The row scan address and underline signals remain on the output
signals for one character count beyond the end of the blanking
signal.

26 IBM Enhanced Graphics Adapter August 2, 1984

Bit O-Bit 7 Start Horizontal Blanking-The horizontal
blanking signal becomes active when the
horizontal character counter reaches this value.

End Horizontal Blanking Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 03. The processor output port
address for this register is hex 3B5 or hex 3D5.

End Horizontal Blanking Register Format

Bit 7 6 5 4 3 2 1 0

I I I
II I
End Blanking
Display Enable Skew Control
Not Used

This register determines when the horizontal blanking output

signal becomes inactive. The row scan address and underline scan
line decode outputs are multiplexed on the memory address
outputs and the cursor outputs respectively during the blanking
interval. These outputs are latched external to the CRT
Controller with the falling edge of the BLANK output signal.
The row scan address and underline signals remain on the output
signals for one character count beyond the end of the blanking
signal.

Bit O-Bit 4 End Horizontal Blanking-A value equal to the

five least significant bits of the horizontal
character counter value at which time the
horizontal blanking signal becomes inactive
(logical 0). To obtain a blanking signal of width
W, the following algorithm is used: Value of
Start Blanking Register + Width of Blanking
signal in character clock units = 5-bit result to be
programmed into the End Horizontal Blanking
Register.

August 2,1984 mM Enhanced Graphics Adapter 27

Bit 5-Bit 6 Display Enable Skew Control-These two bits
determine the amount of display enable skew.
Display enable skew control is required to
provide sufficient time for the CRT Controller to
access the display buffer to obtain a character
and attribute code, access the character generator
font, and then go through the Horizontal Pel
Panning Register in the Attribute Controller.
Each access requires the display enable signal to
be skewed one character clock unit so that the
video output is in synchronization with the
horizontal and vertical retrace signals. The bit
values and amount of skew are shown in the
following table:

Bits
6 5

o 0 Zero character clock skew

o lOne character clock skew
1 0 Two character clock skew
1 1 Three character clock skew

Start Horizontal Retrace Pulse Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 04. The processor output port
address for this register is hex 3B5 or hex 3D5.

Start Horizontal Retrace Pulse Register Format

Bit 7 6 5 4 3 2 1 0

IL.._.J..I........LI----'I~IL.._.L.I---LI___l~..~ Start Horizontal Retrace Pulse

This register is used to center the screen horizontally, and to

specify the character position at which the Horizontal Retrace
Pulse becomes active.

28 IBM Enhanced Graphics Adapter August 2, 1984

Bit O-Bit 7 Start Horizontal Retrace Pulse-The value
programmed is a binary count of the character
position number at which the signal becomes
active.

End Horizontal Retrace Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 05. The processor output port
address for this register is hex 3B5 or hex 3D5.

End Horizontal Retrace Register Format

Bit 7 6 5 4 3 2 1 0

III
II I
End Horizontal Retrace
Horizontal Retrace Delay
Start Odd Memory Address

This register specifies the character position at which the

Horizontal Retrace Pulse becomes inactive (logical 0).

Bit O-Bit 4 End Horizontal Retrace-A value equal to the

five least significant bits of the horizontal
character counter value at which time the
horizontal retrace signal becomes inactive (logical
0). To obtain a retrace signal of width W, the
following algorithm is used: Value of Start
Retrace Register + width of horizontal retrace
signal in character clock units = 5-bit result to be
programmed into the End Horizontal Retrace
Register.

Bit S-Bit 6 Horizontal Retrace Delay-These bits control

the skew of the horizontal retrace signal. Binary
00 equals no Horizontal Retrace Delay. For
some modes, it is necessary to provide a
horizontal retrace signal that takes up the entire
blanking interval. Some internal timings are
generated by the falling edge of the horizontal
retrace signal. To guarantee the signals are

August 2,1984 mM Enhanced Graphics Adapter 29

 latched properly, the retrace signal is started
before the end of the display enable signal, and
then skewed several character clock times to
provide the proper screen centering.

Bit 7 Start Odd/Even Memory Address-This bit

controls whether the first CRT memory address
output after a horizontal retrace begins with an
even or an odd address. A logical 0 selects even
addresses; a logical 1 selects odd addresses. This
bit is used for horizontal pel panning applications.
Generally, this bit should be set to a logical O.

Vertical Total Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 06. The processor output port
address for this register is hex 3B5 or 3D5.

Vertical Total Register Format

Bit 7 6 5 4 3 2 1 0

I I I I II I I• Vertical Total

Bit O-Bit 7 Vertical Total-This is the low-order eight bits of

a nine-bit register. The binary value represents
the number of horizontal raster scans on the CRT
screen, including vertical retrace. The value in
this register determines the period of the vertical
retrace signal. Bit 8 of this register is contained
in the CRT Controller Overflow Register hex 07
bit O.

CRT Controller Overflow Register

This is a write-only register pointed to when the value in the CRT

Controller Address Register is hex 07. The processor output port
address for this register is hex 3B5 or hex 3D5.

30 IBM Enhanced Graphics Adapter August 2, 1984

 CRTC Overflow Register Format

Bit 7 6 5 4 3 2 1 0

Vertical Total Bit 8

Vertical Display Enable End Bit 8
Vertical Retrace Start Bit 8
Start Vertical Blank Bit 8
Line Compare Bit 8
Cursor Location Bit 8
Not Used

Bit 0 Vertical Total-Bit 8 of the Vertical Total

register (index hex 06).

Bit 1 Vertical Display Enable End-Bit 8 of the

Vertical Display Enable End register (index hex
12).

Bit 2 Vertical Retrace Start-Bit 8 of the Vertical

Retrace Start register (index hex 10).

Bit 3 Start Vertical Blank-Bit 8 of the Start Vertical

Blank register (index hex 15).

Bit 4 Line Compare-Bit 8 of the Line Compare

register (index hex 18).

Bit 5 Cursor Location-Bit 8 of the Cursor Location

register (index hex OA).

Preset Row Scan Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 08. The processor output port
address for this register is hex 3B5 or hex 305.

August 2, 1984 mM Enhanced Graphics Adapter 31

 Preset Row Scan Register Format

Bit 7 6 5 4 3 2 1 0

Starting Row Scan Count after

a Vertical Retrace
Not Used

This register is used for pel scrolling.

Bit O-Bit 4 Preset Row Scan (Pel Scrolling)-This register

specifies the starting row scan count after a
vertical retrace. The row scan counter
increments each horizontal retrace time until a
maximum row scan occurs. At maximum row
scan compare time the row scan is cleared (not
preset).

Maximum Scan Line Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 09. The processor output port
address for this register is hex 3B5 or hex 3D5.

Maximum Scan Line Register Format

Bit 7 6 5 4 3 2 1 0

I I I I:
III Maximum Scan Line
Not Used

Bit O-Bit 4 Maximum Scan Line-This register specifies the

number of scan lines per character row. The
number to be programmed is the maximum row
scan number minus one.

Cursor Start Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex OA. The processor output port

32 mM Enhanced Graphics Adapter August 2, 1984

address for this register is hex 3B5 or hex 3D5.

Cursor Start Register Format

Bit 7 6 5 4 3 2 1 0

Row Scan Cursor Begins

Not Used

Bit O-Bit 4 Cursor Start-This register specifies the row scan

of a character line where the cursor is to begin.
The number programmed should be one less than
the starting cursor row scan.

Cursor End Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex OB. The processor output port
address for this register is hex 3B5 or hex 3D5.

Cursor End Register Format

Bit 7 6 5 4 3 2 1 0

I' ,
Row Scan Cursor Ends
Cursor Skew Control
Not Used

Bit O-Bit 4 Cursor End-These bits specify the row scan

where the cursor is to end.

Bit 5-Bit 6 Cursor Skew-These bits control the skew of the

cursor signal.

August 2, 1984 mM Enhanced Graphics Adapter 33

 Bits
6 5

o 0 Zero character clock skew

o lOne character clock skew
1 0 Two character clock skew
1 1 Three character clock skew

Start Address High Register

This is a read/write register pointed to when the value in the CRT

Controller address register is hex OC. The processor
input/output port address for this register is hex 3B5 or hex 305.

Start Address High Register Format

Bit 7 6 5 4 3 2 1 0

I I I I I I I ~ High Order Start Address

Bit O-Bit 7 Start. Address High-These are the high-order

eight bits of the start address. The 16-bit value,
from the high-order and low-order start address
registers, is the first address after the vertical
retrace on each screen refresh.

Start Address Low Register

This is a read/write register pointed to when the value in the CRT

Controller address register is hex 00. The processor
input/output port address for this register is hex 3B5 or hex 305.

Start Address Low Register Format

Bit 7 6 5 4 3 2 1 0

I I I I I I ~ Low Order Start Address

34 mM Enhanced Graphics Adapter August 2, 1984

Bit O-Bit 7 Start Address Low-These are the low-order 8
bits of the start address.

Cursor Location High Register

This is a read/write register pointed to when the value in the CRT

Controller address register is hex OE. The processor input/output
port address for this register is hex 3B5 or hex 3D5.

Cursor Location High Register Format

B~ 7 6 5 4 3 2 1 0

I I I I I I• High Order Cursor Location

Bit O-Bit 7 Cursor Location High-These are the high-order

8 bits of the cursor location.

Cursor Location Low Register

This is a read/write register pointed to when the value in the CRT

Controller address register is hex OF. The processor input/output
port address for this register is hex 3B5 or Hex 3D5.

Cursor Location Low Register Format

B~ 7 6 5 4 3 2 1 0

I I I I I I I• Low Order Cursor Location

Bit O-Bit 7 Cursor Location Low- These are the low-order

8 bits of the cursor location.

August 2, 1984 IBM Enhanced Graphics Adapter 35

Vertical Retrace Start Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 10. The processor output port
address for this register is hex 3B5 or hex 3D5.

Vertical Retrace Start Register Format

Bit 7 6 5 4 3 2 1 0

I I I I I I Low Order Vertical Retrace Pulse

Bit O-Bit 7 Vertical Retrace Start-This is the low-order 8

bits of the vertical retrace pulse start position
programmed in horizontal scan lines. Bit 8 is in
the overflow register location hex 07.

Light Pen High Register

This is a read-only register pointed to when the value in the CRT

Controller address register is hex 10. The processor input port
address for this register is hex 3B5 or hex 3D5.

Light Pen High Register Format

Bit 7 6 5 4 3 2 1 0

I I I I III I• High Order Memory Address

Counter

Bit O-Bit 7 Light Pen High-This is the high order 8 bits of

the memory address counter at the time the light
pen was triggered.

Vertical Retrace End Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 11. The processor output port

36 IBM Enhanced Graphics Adapter August 2, 1984

address for this register is hex 3B5 or hex 3D5.

Vertical Retrace End Register Format

Bit 7 6 5 432 1 0

I I I I Vertical Retrace End

I
~
O=Clear Vertical Interrupt
I
II O=Enable Vertical Interrupt
Not Used

Bit O-Bit 3 Vertical Retrace End-These bits determine the

horizontal scan count value when the vertical
retrace output signal becomes inactive. The
register is programmed in units of horizontal scan
lines. To obtain a vertical retrace signal of width
W, the following algorithm is used: Value of Start
Vertical Retrace Register + width of vertical
retrace signal in horizontal scan units = 4-bit
result to be programmed into the End Horizontal
Retrace Register.

Bit 4 Clear Vertical Interrupt-A logical 0 will clear a

vertical interrupt.

Bit 5 Enable Vertical Interrupt-A logical 0 will

enable vertical interrupt.

Light Pen Low Register

This is a read-only register pointed to when the value in the CRT

Controller address register is hex 11. The processor input port
address for this register is hex 3B5 or 3D5.

August 2, 1984 IBM Enhanced Graphics Adapter 37

 Light Pen Low Register Format

Bit 7 6 5 4 3 2 1 0

I I I I I I I I .. Low Order Memory Address

Counter

Bit O-Bit 7 Light Pen Low-This is is the low-order 8 bits of

the memory address counter at the time the light
pen was triggered.

Vertical Display Enable End Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 12. The processor output port
address for this register is hex 3B5 or hex 3D5.

Vertical Display Enable End Register Format

Bit 7 6 5 4 3 2 1 0

I I I I I I I I . Low Order Vertical Display

Enable End

Bit O-Bit 7 Vertical Display Enable End-These are the

low-order 8 bits of the vertical display enable end
position. This address specifies which scan line
ends the active video area of the screen. Bit 8 is
in the overflow register location hex 07.

Offset Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 13. The processor output port
address for this register is hex 3B5 or hex 3D5.

38 mM Enhanced Graphics Adapter August 2,1984

 Offset Register Format

Bit 7 6 5 4 3 2 1 a
I I I I I • Logical line width of the screen

Bit O-Bit 7 Offset-This register specifies the logical line

width of the screen. The starting memory
address for the next character row is larger than
the current character row by this amount. The
Offset Register is programmed with a word
address. Depending upon the method of clocking
the CRT Controller, this word address is either a
word or double word address.

Underline Location Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 14. The processor output port
address for this register is hex 3B5 or hex 3D5.

Underline Location Register Format

Bit 7 6 5 4 3 2 1 a
I I I
III : Horizontal row scan where
underline will occur
Not Used

Bit O-Bit 4 Underline Location-This register specifies the

horizontal row scan on which underline will
occur. The value programmed is one less than
the scan line number desired.

Start Vertical Blanking Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 15. The processor output port

August 2, 1984 IBM Enhanced Graphics Adapter 39

address for this register is hex 3BS or hex 3DS.

Start Vertical Blanking Register Format

Bit 7 6 5 4 3 2 1 0

I I I I I I I• Start Vertical Blanking

Bit O-Bit 7 Start Vertical Blank-These are the low 8 bits of

the horizontal scan line count, at which the
vertical blanking signal becomes active. Bit 8 bit
is in the overflow register hex 07.

End Vertical Blanking Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 16. The processor output port
address for this register is hex 3BS or hex 3DS.

End Vertical Blanking Register Format

BH 7 6 5 4 3 2 1 0

I I I I
III : End Vertical Blanking
Not Used

Bit O-Bit 4 End Vertical Blank-This register specifies the

horizontal scan count value when the vertical
blank output signal becomes inactive. The
register is programmed in units of horizontal scan
lines. To obtain a vertical blank signal of width
W, the following algorithm is used: Value of Start
Vertical Blank Register + width of vertical blank
signal in horizontal scan units = S-bit result to be
programmed into the End Vertical Blank
Register.

40 mM Enhanced Graphics Adapter August 2, 1984

Mode Control Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 17. The processor output port
address for this register is hex 3B5 or hex 3D5.

Mode Control Register Format

Bit 7 6 5 4 3 2 1 0

II I : ~::c~ Row Sea" Co",le,

Horizontal Retrace Select
'-------I~ Count by Two
L.--------i~ Output Control
L--_ _ _ _ _--I~ Address Wrap
L.----------i~ Word/Byte Mode

' - - - - - - - - - -.... Hardware Reset

Bit 0 Compatibility Mode Support- When this bit is

a logical 0, the row scan address bit 0 is
substituted for memory address bit 13 during
active display time. A logical 1 enables memory
address bit 13 to appear on the memory address
output bit 13 signal of the CRT Controller. The
CRT Controller used on the IBM
Color/Graphics Monitor Adapter is the 6845.
The 6845 has 128 horizontal scan line address
capability. To obtain 640 by 200 graphics
resolution, the CRTC was programmed for 100
horizontal scan lines with 2 row scan addresses
per character row. Row scan address bit 0
became the most significant address bit to the
display buffer. Successive scan lines of the
display image were displaced in memory by 8K
bytes. This bit allows compatibility with the
6845 and Color Graphics APA modes of
operation.

August 2, 1984 IBM Enhanced Graphics Adapter 41

Bit 1 Select Row Scan Counter-A logical 0 selects
row scan counter bit 1 on MA 14 output pin. A
logical 1 selects MA 14 counter bit on MA 14
output pin.

Bit 2 Horizontal Retrace Select-This bit selects

Horizontal Retrace or Horizontal Retrace divided
by 2 as the clock that controls the vertical timing
counter. This bit can be used to effectively
double the vertical resolution capability of the
CRT Controller. The vertical counter has a
maximum resolution of 512 scan lines due to the
9-bit wide Vertical Total Register. If the vertical
counter is clocked with the horizontal retrace
divided by 2 clock, then the vertical resolution is
doubled to 1024 horizontal scan lines. A logical
o selects HRTC and a logical 1 selects HRTC
divided by 2.

Bit 3 Count By Two- When this bit is set to 0, the

memory address counter is clocked with the
character clock input. A logical 1 clocks the
memory address counter with the character clock
input divided by 2. This bit is used to create
either a byte or word refresh address for the
display buffer.

Bit 4 Output Control-A logical 0 enables the module

output drivers. A logical 1 forces all outputs into
high impedance state.

Bit 5 Address Wrap-This bit selects Memory Address

counter bit MA 13 or bit MA 15, and it appears
on the MA 0 output pin in the word address
mode. If you are not in the word address mode,
MA 0 counter output appears on the MA 0
output pin. A logical 1 selects MA 15. In
odd/ even mode, bit MA 13 should be selected
when the 64K memory is installed on the board.
Bit MA 15 should be selected when greater then
64K memory is installed. This function is used to
implement Color Graphics Monitor Adapter
compatibility.

42 IBM Enhanced Graphics Adapter August 2, 1984

Bit 6 Word Mode or Byte Mode-When this bit is a
logical 0, the Word Mode shifts all memory
address counter bits down one bit, and the most
significant bit of the counter appears on the least
significant bit of the memory address outputs.
See table below for address output details. A
logical 1 selects the Byte Address mode.

Internal Memory Address Counter

Wiring to the Output Multiplexer
Byte Address Word Address
CRTC Out Pin Mode Mode
MA O/RFA 0 MAO MA 15 or MA 13
MA 1/RFA 1 MA1 MAO
MA 2/RFA 2 MA2 MA1
MA3/RFA 3 MA3 MA2
* * *
* * *
* * *
MA 14/RS 3 MA14 MA13
MA 15/RS 4 MA15 MA14

Bit 7 Hardware Reset-A logical 0 forces horizontal

and vertical retrace to clear. A logical 1 forces
horizontal and vertical retrace to be enabled.

Line Compare Register

This is a write-only register pointed to when the value in the CRT

Controller address register is hex 18. The processor output port
address for this register is hex 3B5 or hex 3D5.

Line Compare Register Format

Bit 7 6 5 4 3 2 1 0

I I I I I I I I Line Compare Target

Bit O-Bit 7 Line Compare-This register is the low-order 8

bits of the compare target. When the vertical

August 2, 1984 IBM Enhanced Graphics Adapter 43

 counter reaches this value, the internal start of
the line counter is cleared. This allows an area of
the screen to be immune to scrolling. Bit 8 of
this register is in the overflow register hex 07.

44 mM Enhanced Graphics Adapter August 2, 1984

Graphics Controller Registers

Name Port Index

Graphics 1 Position 3CC -
Graphics 2 Position 3CA -
Graphics 1 & 2 Address 3CE -
Set/Reset 3CF 00
Enable Set/Reset 3CF 01
Color Compare 3CF 02
Data Rotate 3CF 03
Read Map Select 3CF 04
Mode Register 3CF 05
Miscellaneous 3CF 06
Color Don't Care 3CF 07
Bit Mask 3CF 08

Graphics 1 Position Register

This is a write-only register. The processor output port address

for this register is hex 3CC.

Graphics I Position Register Format

Bit 7 6 5 4 3 2 1 0

IIIIIII~
Position 0
Position 1
Not Used

Bit O-Bit 1 Position-These 2 bits are binary encoded

hierarchy bits for the graphics chips. The
position register controls which 2 bits of the
processor data bus each chip responds to.
Graphics 1 must be programmed with a position
register value of 0 for this card.

August 2, 1984 mM Enhanced Graphics Adapter 45

Graphics 2 Position Register

This is a write-only register. The processor output port address

for this register is hex 3CA.

Graphics II Position Register Format

B~ 7 6 5 4 3 2 1 0

Position 0
Position 1
Not Used

Bit O-Bit 1 Position-These 2 bits are binary encoded

hierarchy bits for the graphics chips. The
position register controls which 2 bits of the
processor data bus to which each chip responds.
Graphics 2 must be programmed with a position
register value of 1 for this card.

Graphics 1 and 2 Address Register

This is a write-only register and the processor output port address

for this register is hex 3CE.

Graphics 1 and 2 Address Register Formats

Bit 7 6 5 4 3 2 1 0

IIII : Graphics Address

Not Used

Bit 0-B1t 3 Graphics 1 and 2 Address Bits-This output loads

the address register in both graphics chips
simultaneously. This register points to the data
register of the graphics chips.

46 IBM Enhanced Graphics Adapter August 2, 1984

Set/Reset Register

This is a write-only register pointed to by the value in the

Graphics 1 and 2 address register. This value must be hex 00
before writing can take place. The processor output port address
for this register is hex 3CF.

Set/Reset Register Format

E
Bit 7 6 5 4 3 2 1 0

I ~set/Reset Bit 0
~set/Reset Bit 1
Set/Reset Bit 2
Set/Reset Bit 3
L-~~--L-----------~NotUsed

Bit O-Bit 3 Set/Reset--These bits represent the value

written to the respective memory planes when the
processor does a memory write with write mode 0
selected and set! reset mode is enabled.
Set/Reset can be enabled on a plane by plane
basis with separate OUT commands to the
Set/Reset register.

Enable Set/Reset Register

This is a write-only register and is pointed to by the value in the

Graphics 1 and 2 address register. This value must be hex 01
before writing can take place. The processor output port for this
register is hex 3CF.

January 20, 1986 IBM Enhanced Graphics Adapter 47

 Enable Set/Reset Register Format

Bit 7 6 5 4 3 2 1 0

III~L~ "oabl. Sot,R"., BII a

Enable Set/Reset Bit 1
Enable Set/Reset Bit 2
Enable Set/Reset Bit 3
~~~--~----------~NotUsed

Bit O-Bit 3 Enable Set/Reset--These bits enable the

set/ reset function. The respective memory plane
is written with the value of the Set/Reset register
provided the write mode is o. When write mode is
o and Set/Reset is not enabled on a plane, that
plane is written with the value of the processor
data.

Color Compare Register

This is a write-only register pointed to by the value in the

Graphics 1 and 2 address register. This value must be hex 02
before writing can take place. The processor output port address
for this register is hex 3CF.

Color Compare Register Format

Bit 7 6 5 4 3 2 1 0

I I L: Colo' Comp'" a
Color Compare 1
Color Compare 2
L...-_ _ _~ Color Compare 3
~~~--~----------~NotUsed

Bit O-Bit 3 Color Compare--These bits represent a 4 bit

color value to be compared. If the processor sets

48 IBM Enhanced Graphics Adapter January 20, 1986

 read mode 1 on the graphics chips, and does a
memory read, the data returned from the memory
cycle will be a 1 in each bit position where the 4
bit planes equal the color compare register.

Data Rotate Register

This is a write-only register pointed to by the value in the

Graphics 1 and 2 address register. This value must be hex 03
before writing can take place. The processor output port address
for this register is hex 3CF.

Data Rotate Register Format

Bit 7 6 5 4 3 2 1 0

Rotate Count
Rotate Count 1
Rotate Count 2
Function Select
Not Used

Bit O-Bit 2 Rotate Count-These bits represent a binary

encoded value of the number of positions to
rotate the processor data bus during processor
memory writes. This operation is done when the
write mode is O. To write unrotated data the
processor must select a count of O.

Bit 3-Bit 4 Function Select-Data written to memory can

operate logically with data already in the
processor latches. The bit functions are defined
in the following table.

August 2, 1984 IBM Enhanced Graphics Adapter 49

 Bits
4 3

o0 Data unmodified.
o1 Data AND'ed with latched data.
1 0 Data OR'ed with latched data.
1 1 Data XOR'ed with latched data.

Data may be any of the choices selected by the Write Mode

Register except processor latches. If rotated data is selected, the
rotate applies before the logical function.

Read Map Select Register

This is a write-only register pointed to by the value in the

Graphics 1 and 2 address register. This value must be hex 04
before writing can take place. The processor output port address
for this register is hex 3CF.

Read Map Select Register Format

Bit 7 6 5 4 3 2 1 0

Map Select 0
Map Select 1
Map Select 2
Not Used

Bit O-Bit 2 Map Select-These bits represent a binary

encoded value of the memory plane number from
which the processor reads data. This register has
no effect on the color compare read mode
described elsewhere in this section.

Mode Register

This is a write-only register pointed to by the value in the

Graphics 1 and 2 address register. This value must be hex 05

50 IBM Enhanced Graphics Adapter August 2, 1984

before writing can take place. The processor output port address
for this register is 3CF.

Mode Register Format

Bit 7 6 5 4 3 2 1 0

II : : : Wdt, Mod,
Test Condition
Read Mode
'-------~ Odd/Even
'--------~ Shift Register Mode
'--..L-_ _ _ _ _ _ _ ~ Not Used

Bit O-Bit 1 Write Mode

Bits
1 0

o0 Each memory plane is written with the

processor data rotated by the number of
counts in the rotate register, unless
Set/Reset is enabled for the plane. Planes
for which Set/Reset is enabled are written
with 8 bits of the value contained in the
Set/Reset register for that plane.
o1 Each memory plane is written with the
contents of the processor latches. These
latches are loaded by a processor read
operation.
1 0 Memory plane n (0 through 3) is filled
with 8 bits of the value of data bit n.
1 1 Not Valid

The logic function specified by the function select

register also applies.

Bit 2 Test Condition-A logical 1 directs graphics

controller outputs to be placed in high impedance
state for testing.

August 2, 1984 IBM Enhanced Graphics Adapter 51

Bit 3 Read Mode-When this bit is a logical 0, the
processor reads data from the memory plane
selected by the read map select register. When
this bit is a logical 1, the processor reads the
results of the comparison of the 4 memory planes
and the color compare register.

Bit 4 Odd/Even-A logical 1 selects the odd/even

addressing mode, which is useful for emulation of
the Color Graphics Monitor Adapter compatible
modes. Normally the value here follows the value
of the Memory Mode Register bit 3 of the
Sequencer.

Bit S Shift Register-A logical 1 directs the shift

registers on each graphics chip to format the
serial data stream with even numbered bits on the
even numbered maps and odd numbered bits on
the odd maps.

Miscellaneous Register

This is a write-only register pointed to by the value in the

Graphics 1 and 2 address register. This value must be hex 06
before writing can take place. The processor output port for this
register is hex 3CF.

Miscellaneous Register Format

Bit 7 6 5 4 3 2 1 0

Graphics Mode
Chain Odd Maps to Even
Memory MapO
Memory Map 1
Not Used

S2 IBM Enhanced Graphics Adapter August 2, 1984

Bit 0 Graphics Mode-This bit controls alpha-mode
addressing. A logical 1 selects graphics mode.
When set to graphics mode, the character
generator address latches are disabled.

Bit 1 Chain Odd Maps To Even Maps-When set to 1,

this bit directs the processor address bit 0 to be
replaced by a higher order bit and odd/even
maps to be selected with odd/even values of the
processor AO bit, respectively.

Bit 2-Bit 3 Memory Map-These bits control the mapping of

the regenerative buffer into the processor address
space.

Bits
3 2

o0 Hex AOOO for 128K bytes.

o1 Hex AOOO for 64K bytes.
1 0 Hex BOOO for 32K bytes
1 1 Hex B800 for 32K bytes.

If the display adapter is mapped at address hex AOOO for 128K

bytes, no other adapter can be installed in the system.

Color Don't Care Register

This is a write-only register and is pointed to by the value in the

Graphics 1 and 2 address register. This value must be hex 07
before writing can take place. The processor output port for this
register is hex 3 CF.

August 2, 1984 mM Enhanced Graphics Adapter 53

 Color Don't Care Register Format

Bit 7 6 5 4 3 2 1 a

Color Plane a=Oon't Care

Color Plane 1=Oon't Care
Color Plane 2=Oon't Care
Color Plane 3=Oon't Care
Not Used

Bit 0 Color Don't Care-Color plane O=don't care

when reading color compare when this bit is set to
1.

Bit 1 Color Don't Care-Color plane 1 =don't care

when reading color compare when this bit is set to
1.

Bit 2 Color Don't Care-Color plane 2=don't care

when reading color compare when this bit is set to
1.

Bit 3 Color Don't Care-Color plane 3=don't care

when reading color compare when this bit is set to
1.

Bit Mask Register

This is a write-only register and is pointed to by the value in the

Graphics 1 and 2 address register. This value must be hex 08
before writing can take place. The processor output port for this
register is hex 3 CF.

Bit Mask Register Format

Bit 7 6 5 4 3 2 1 a

II I I II II• a-Immune to change

1-Unimpeded Writes

54 IBM Enhanced Graphics Adapter August 2, 1984

Bit O-Bit 7 Bit Mask-Any bit programmed to n causes the
corresponding bit n in each bit plane to be
immune to change provided that the location
being written was the last location read by the
processor. Bits programmed to a 1 allow
unimpeded writes to the corresponding bits in the
pit planes.

The bit mask applies to any data written by the processor (rotate,
AND'ed, OR'ed, XOR'ed, DX and SIR). To preserve bits using
the bit mask, data must be latched internally by reading the
location. When data is written to preserve the bits, the most
current data in latches is written in those positions. The bit mask
applies to all bit planes simultaneously.

January 20, 1986 IBM Enhanced Graphics Adapter 55

Attribute Controller Registers

Name Port Index

Address Register 3CO -
Palette Registers 3CO OO-OF
Mode Control Register 3CO 10
Overscan Color Register 3CO 11
Color Plane Enable Register 3CO 12
Horizontal Pel Panning Register 3CO 13

Attribute Address Register

This is a write-only register. The processor output port is hex

3CO.

Attribute Address Register Format

Bit

71 6
1
, i I I 1: Attribute Address
L-.-------i~Palette Address Source

~~--------~- Not Used

Bit O-Bit 4 Attribute Address Bits-The Address Register is

a pointer register located at hex 3CO. This
register is loaded with a binary value that points
to the attribute data register where data is to be
written. The Attribute Controller does not have
an address bit input to control selection of the
address and data registers. An internal address
flip-flop controls selection of either the address
or data registers. To initialize the flip-flop, an
lOR instruction is issued to the Attribute
Controller at address 3BA or 3DA. This clears
the flip-flop, and selects the Address Register.
After the Address Register has been loaded, the
next OUT instruction loads the data register.

56 IBM Enhanced Graphics Adapter January 20, 1986

 The flip-flop toggles each time an OUT is issued
to the Attribute Controller.

Bit 5 Palette Address Source-When loading the color

palette registers, bit 5 must be cleared to O. To
enable the memory data to access the color
palette, bit 5 must be set to 1.

Palette Register Hex 00 through Hex OF

This is a write-only register. The processor output port is hex

3CO.

'
Palette Registers Hex 00 through Hex OF Format

llli
Bit 7 6 5 4 3 2 1 0

~ Blue Video
~ Green Video
Red Video
Secondary Blue/Mono Video
1..-_ _ _ _ _ _ Secondary Green/Intensity
L-_ _ _ _ _ _~ Secondary Red Video
L-....L_ _ _ _ _ _ _ _ _ Not Used

Sit O-Bit 5 Palette-These 6-bit registers allow a dynamic

mapping between the text attribute or graphic
color input value and the display color in the
CRT screen. A logical 1 selects the appropriate
color. A logical 0 de-selects. The color palette
register should be modified only during the
vertical retrace interval to avoid glitches in the
displayed image. Note that some color monitors
do not have an intensity input and only a
maximum of eight colors are available. Monitors
with four color inputs display sixteen colors, and
monitors with six color inputs display 64 colors.

January 20, 1986 IBM Enhanced Graphics Adapter 57

Mode Control Register

This is a write-only register pointed to by the value in the

Attribute address register. This value must be hex 10 before
writing can take place. The processor output port address for this
register is hex 3CO.

Mode Control Register Format

Bit 7 6 5 4 3 2

II
1

I:
0

Grnph'"IAlphaoome", Mode
Display Type
Enable Line Graphics Character
Codes
L....-_ _ _~ Select Background Intensity Or
Enable Blink
I--....L...........I._.L.-_ _ _ _ _~ Not Used

Bit 0 Graphics/ Alphanumeric Mode-A logical 0

selects alphanumeric mode. A logical 1 selects
graphics mode.

Bit 1 Monochrome Display/Color Display-A logical

o selects IBM monochrome display attributes.A
logical 1 selects color Display attributes.

Bit 2 Enable Line Graphics Character Codes-When

this bit is set to 0, the ninth dot will be the same
as the background. A logical 1 enables the
special line graphics character codes for the IBM
Monochrome Display adapter. When enabled,
this bit forces the ninth dot of a line graphic
character to be identical to the eighth dot of the
character. The line graphics character codes for
the Monochrome Display Adapter are Hex CO
through Hex DF.

For character fonts that do not utilize the line

graphics character codes in the range of Hex CO

58 IBM Enhanced Graphics Adapter January 20, 1986

 through Hex DF, bit 2 of this register should be a
logical O. Otherwise unwanted video information
will be displayed on the CRT screen.

Bit 3 Enable Blink/Select Background Intensity-A

logical 0 selects the background intensity of the
attribute input. This mode was available on the
Monochrome and Color Graphics adapters. A
logical 1 enables the blink attribute in
alphanumeric modes. This bit must also be set to
1 for blinking graphics modes.

Overscan Color Register

This is a write-only register pointed to by the value in the

Attribute address register. This value must be hex 11 before
writing can take place. The processor output port address for this
register is hex 3CO.

Overscan Color Register Format

Bit 7 6 5 4 3 2 1 0

I' I : s.,.o" B',. Bom.ceo'",

Selects Green Border Color
Selects Red Border Color
Selects Secondary Blue
Border Color
Selects Intensified or
Secondary Green
Selects Secondary Red
Border Color
Not Used

Bit O-Bit S Overscan Color-This 6-bit register determines

the overscan (border) color displayed on the
CRT screen. For monochrome display this
register should be set to a value of O. A logical 1
selects the appropriate color.

August 2, 1984 IBM Enhanced Graphics Adapter S9

Color Plane Enable Register

This is a write-only register pointed to by the value in the

Attribute address register. This value must be hex 12 before
writing can take place. The processor output port address for this
register is 3CO.

Color Plane Enable Register Format

Bit 7 6 5 4 3 2 1 0

Enable Color Plane

Video Status MUX
Not Used

Bit O-Bit 3 Enable Color Plane-Writing a logical 1 in any

of bits 0 through 3 enables the respective display
memory color plane.

Bit 4-Bit 5 Video Status MUX-Selects two of the six color

outputs to be available on the status port. The
following table illustrates the combinations
available and the color output wiring.

COLOR PLANE INPUT STATUS

ENABLE REGISTER REGISTER ONE
BitS Bit4 BitS Bit4
0 0 Red Blue
0 1 Secondary Blue Green
1 0 Secondary Red Secondary Green
1 1 Not Used Not Used

Horizontal Pel Panning Register

This is a write-only register pointed to by the value in the

Attribute address register. This value must be hex 12 before
writing can take place. The processor output port address for this
register is hex 3CO.

60 IBM Enhanced Graphics Adapter August 2, 1984

 Horizontal Pel Panning Register Format

Bit 7 6 5 4 3 2 1 0

Bit O-Bit 3 Horizontal Pel Panning-This 4 bit register

selects the number of picture elements (pels) to
shift the video data horizontally to the left. Pel
panning is available in both A/N and AP A
modes. In Monochrome A/N mode, the image
can be shifted a maximum of 9 pels. In all other
A/N and AP A modes, the image can be shifted a
maximum of 8 pels. The sequence for shifting
the image is given below:

9 pels/character: 8,0, 1,2,3,4,5,6, 7

(Monochrome A/N mode only)

8 pels/character: 0, 1,2,3,4,5,6, 7 (All other

Modes)

August 2, 1984 IBM Enhanced Graphics Adapter 61

Programming Considerations

Programming the Registers

Each of the LSI devices has an address register and a number of
data registers. The address register serves as a pointer to the
other registers on the LSI device. It is a write-only register that is
loaded by the processor by executing an 'OUT' instruction to its
I/O address with the index of the selected data register.

The data registers on each LSI device are accessed through a

common I/O address. They are distinguished by the pointer
(index) in the address register. To write to a data register, the
address register is loaded with the index of the appropriate data
register, then the selected data register is loaded by executing an
'OUT' instruction to the common I/O address.

The external registers that are not part of an LSI device and the
Graphics I and II registers are not accessed through an address
register; they are written to directly.

The following tables define the values that are loaded into the
registers by BIOS to support the different modes of operation
supported by this adapter.

62 IBM Enhanced Graphics Adapter August 2, 1984

 Register Made of Operation

Hlme Part Index 0 1 2 3 4 5 6 7 0 E F 10 F: 10: 0- I- 2- 3-

Miscellaneous 3C2 - 23 23 23 23 23 23 23 A6 23 23 A2 A7 A2 A7 A7 A7 A7 A7
Feature Cntrl 3?A - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Input Stat 0 3C2 - - - - - - - - - - - - - - - - - - -

Input Stat 1 3?2 - - - - - - - - - - - - - - - - - - -

? = B in monochrome modes ? = D in color modes
'Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64 K Graphics Memory is installed

External Registers

Register Made of Operation

Nlme Port Index 0 I 2 3 4 5 6 7 0 E F 10 F: 10: 0- I- 2- 3-
Seq Address 3C4 - - - - - - - - - - - - - - - - - - -

Reset 3C5 00 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03
Clock Mode 3C5 01 DB DB 01 01 DB DB 01 00 DB 01 05 05 01 01 DB DB 01 01
Map Mask 3C5 02 03 03 03 03 03 03 01 03 OF OF OF OF OF OF 03 03 03 03
Char Gen Sel 3C5 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Memory Mode 3C5 04 03 03 03 03 02 02 06 03 06 06 00 00 06 06 03 03 03 03
'Values for these modes when the IBM Enhanced Color Display is attached

:Values for these modes when greater than 64K Graphics Memory is installed

Sequencer Registers

August 2, 1984 IBM Enhanced Graphics Adapter 63

 HI,lltlr Midi I' O,ll1llon
NIIII Ptrt lodn 0 I 2 3 4 5 6 7 0 E F 10 Ft 10: 0' I' 2' 3'
Address Reg 3?4 - - - - - - - - - - - - - - - - - - -
Horiz Total 3?5 00 37 37 70 70 37 37 70 60 37 70 60 5B 60 5B 20 20 5B 5B
Hrz Oisp End 3?5 01 27 27 4F 4F 27 27 4F 4F 27 4F 4F 4F 4F 4F 27 27 4F 4F
Strt Hrz Blk 3?5 02 20 20 5C 5C 20 20 59 56 20 56 56 53 56 53 2B 2B 53 53
End Hrz Blk 3?5 03 37 37 2F 2F 37 37 20 3A 37 20 1A 17 3A 37 20 20 37 37
Strt Hrz Retr 3?5 04 31 31 5F 5F 30 30 5E 51 30 5E 50 50 50 52 28 28 51 51
End Hrz Relr 3?5 05 15 15 07 07 14 14 06 60 14 06 EO BA 60 00 60 60 58 5B
Vert Total 3?5 06 04 04 04 04 04 04 04 70 04 04 70 6C 70 6C 6C 6C 6e 6C
Overflow 3?5 07 11 11 11 11 11 11 11 1F 11 11 1F 1F 1F 1F 1F 1F 1F 1F
Preset Row SC 3?5 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Max Scan line 3?5 09 07 07 07 07 01 01 01 00 00 00 00 00 00 00 00 00 00 00
Cursor Start 3?5 OA 06 06 06 06 00 00 00 DB 00 00 00 00 00 00 DB DB DB DB
Cursor End 3?5 DB 07 07 07 07 00 00 00 DC 00 00 00 00 00 00 DC DC DC DC
Strt Addr Hi 3?5 DC - - - - - - - - - - - - - - - - - -
Strt Addr Lo 3?5 00 - - - - - - - - - - - - - - - - - -
? = B in monochrome modes ? = 0 in color modes
'Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64 K Graphics Memory is installed

CRT Controller Registers (1 of 2)

64 IBM Enhanced Graphics Adapter August 2, 1984

 RIglsllr Mode of Oplration
Nlml Port fndex 0 1 2 3 4 5 6 7 0 E F 10 F: 10: 0' I' 2' 3'
Cursor LC Hi 3?5 OE - - - - - - - - - - - - - - - - - -
Cursor LC Low 3?5 OF - - - - - - - - - - - - - - - - - -
Vrt Retr Strt 3?5 10 EI EI EI EI EI EI EO 5E EI EO 5E 5E 5E 5E 5E 5E 5E 5E
Light Pen Hi 3?5 10 - - - - - - - - - - - - - - - - - -
Vert Retr End 3?5 II 24 24 24 24 24 24 23 2E 24 23 2E 2B 2E 2B 2B 2B 2B 2B
Lig ht Pen Low 3?5 11 - - - - - - - - - - - - - - - - - -

Vrt Oisp End 3?5 12 C7 C7 C7 C7 C7 C7 C7 50 C7 C7 50 50 50 50 50 50 50 50

Offsel 3?5 13 14 14 28 28 14 14 28 28 14 28 14 14 28 28 14 14 28 28
Underline Loc 3?5 14 08 08 08 08 00 00 00 00 00 00 00 OF 00 OF OF OF OF OF
Strt Vert Blk 3?5 15 EO EO EO EO EO EO OF 5E EO OF 5E 5F 5E 5F 5E 5E 5E 5E
End Vert Blk 3?5 16 FO FO FO FO FO FO EF 6E FO EF 6E OA 6E OA OA OA OA OA
Mode Control 3?5 17 A3 A3 A3 A3 A2 A2 C2 A3 E3 E3 8B 8B E3 E3 A3 A3 A3 A3
Line Compare 3?5 18 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
? = B in monochrome modes ? = 0 in color modes
'Values for these modes when the IBM Enhanced Color Display is attached
;Values for these modes when greater than 64K Graphics Memory is installed

CRT Controller Registers (2 of 2)

August 2, 1984 IBM Enhanced Graphics Adapter 65

 Register Mode of Operation
Name Port Index 0 1 2 3 4 5 6 7 0 E F 10 Ft 10i 0- 1- 2- 3-
Grphx I Pas 3CC - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Grphx II Pas 3CA - 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
Grphx III AD 3CE - - - - - - - - - - - - - - - - - - -
Set Reset 3CF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Enable SIR 3CF 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Color Compare 3CF 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Data Rotate 3CF 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Read Map Sel 3CF 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Mode Register 3CF 05 10 10 10 10 30 30 00 10 00 00 10 10 00 00 10 10 10 10
Miscellaneous 3CF 06 OE DE OE DE OF OF 00 OA 05 05 07 07 05 05 DE DE DE DE
Color No Care 3CF 07 00 00 00 00 00 00 00 00 OF OF OF OF OF OF 00 00 00 00
Bit Mask 3CF 08 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
'Values for these modes when the IBM Enhanced Color Display is attached
:values for these modes when greater than 64 K Graphics Memory is installed

Graphics 51 Registers

66 IBM Enhanced Graphics Adapter August 2, 1984

 Rlglsllr Modi 01 Oplrilian
MIIII Part Indl. 0 1 2 3 4 5 6 7 0 E F 10 Ft 10: 0* 1* 2* 3*
Address 3?A - - - - - - - - - - - - - - - - - - -
Palette 3CO Q() 00 Q() 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Palette 3CO 01 01 01 01 01 13 13 17 08 01 01 08 01 08 01 01 01 01 01
Palette 3CO 02 02 02 02 02 15 15 17 08 02 02 00 00 00 02 02 02 02 02
Palette 3CO 03 03 03 03 03 17 17 17 08 03 03 00 00 00 03 03 03 03 03
Palette 3CO 04 04 04 04 04 02 02 17 08 04 04 18 04 18 04 04 04 04 04
Palette 3CO 05 05 05 05 05 04 04 17 08 05 05 18 07 18 05 05 05 05 05
Palette 3CO 06 06 06 06 06 06 06 17 08 06 06 00 00 00 06 14 14 14 14
Palette 3CO 07 07 07 07 07 07 07 17 08 07 07 00 00 00 07 07 07 07 07
Palette 3CO 08 10 10 10 10 10 10 17 10 10 10 00 00 00 38 38 38 38 38
Palette 3CO 09 11 11 11 11 11 11 i7 18 11 11 08 01 08 39 39 39 39 39
Palette 3CO OA 12 12 12 12 12 12 17 18 12 12 00 00 00 3A 3A 3A 3A 3A
Palette 3CO OB 13 13 13 13 13 13 17 18 13 13 00 00 00 3B 3B 3B 3B 3B
? = B in monochrome modes ? = D in color modes
'Values for these modes when the IBM Enhanced Color Display is attached
!Values for these modes when greater than 64 K Graphics Memory is installed

Attribute Registers (1 of 2)

August 2, 1984 IBM Enhanced Graphics Adapter 67

 Reglsler Modi of Opll1llon
Nlme Pori Index 0 1 2 3 4 5 6 7 0 E F 10 F! 10l 0" I" 2" 3"
Palette 3CO OC 14 14 14 14 14 14 17 18 14 14 00 04 00 3C 3C 3C 3C 3C
Palette 3CO OD 15 15 15 15 15 15 17 18 15 15 18 07 18 3D 3D 3D 3D 3D
Palette 3CO OE 16 16 16 16 16 16 17 18 16 16 00 00 00 3E 3E 3E 3E 3E
Palette 3CO OF 17 17 17 17 17 17 18 17 17 00 00 00 3F 3F 3F 3F 3F 3F
Mode Conlrol 3CO 10 08 08 08 08 01 01 01 OE 01 01 DB DB OB 01 08 08 08 08
Overscan 3CO 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Color Plane 3CO 12 OF OF OF OF 03 03 01 OF OF OF 05 05 05 OF OF OF OF OF
Hrz Panning 3CO 13 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
'Values for these modes when Ihe IBM Enhanced Color Display is attached
:Values for these modes when greater than 64 K Graphics Memory is installed

Attribute Registers (2 of 2)

68 IBM Enhanced Graphics Adapter August 2, 1984

RAM Loadable Character Generator
The character generator on the adapter is RAM loadable and can
support characters up to 32 scan lines high. Two character
generators are stored within the BIOS and one is automatically
loaded into the RAM by the BIOS when an alphanumeric mode is
selected. The Character Map Select Register can be programmed
to define the function of bit 3 of the attribute byte to be a
character generator switch. This allows the user to select between
any two character sets residing in bit plane 2. This effectively
gives the user access to 512 characters instead of 256. character
tables may be loaded off line. The adapter must have 128K bytes
of storage to support this function. Up to four tables can be
loaded can be loaded with 256K of graphics memory installed.

The structure of the character tables is described in the following

figure. The character generator is in bit plane 2 and must be
protected using the map mask function.

Bit Plane 2
+OK
Character
Generator 0
+8K

Character
Generator 1

Character
I-++-+-++-+-+-HI-++-I-++-I-++-i-++-i-i Generator 2

Character
t-+-+-t-+-+-t-+-+-t-++-IH-+-IH-+-I-++-t-l Generator 3

+64K ~--------------------------~

The following figure illustrates the structure of each character

pattern. If the CRT controller is programmed to generate n row

August 2, 1984 IBM Enhanced Graphics Adapter 69

scans, then n bytes must be filled in for each character in the
character generator. The example assumes eight row scans per
character.

Address Byte Image Data

CC * 32 +0 18H

3EH

2 66H

3 66H

4 7EH

5 66H

6 66H

7 66H

CC = Value of the character code. For example, 41H in the case

of an ASCII "A".

Creating a 512 Character Set

This section describes how to create a 512 character set on the
IBM Color Display. Note that only 256 characters can be printed
on the printer. This is a special application which the Enhanced
Graphics Adapter will support. The 9 by 14 characters will be
displayed when attribute bit 3 is a logical 0, and the IBM
Color/Graphics Monitor Adapter 8 by 8 characters will be
displayed when the attribute bit 3 is a logical 1. This example is
for demonstrative purposes only. The assembly language routine
for creating 512 characters is given below. Debug 2.0 was used
for this example. The starting assembly address is 100 and the
character string is stored in location 200. This function requires
128K or more of graphics memory.

70 IBM Enhanced Graphics Adapter August 2, 1984

alOO
movax,1102 ;load 8x8 character font in character
mov bl,02 ;generator number 2
intlO

movax,1103 ;select 512 character operation

mov bl,08 ;if attribute bit 3 = 1 use 8x8 font
intlO ;if attribute bit 3=0 use 9x14 font

movax,lOOO ;set color plane enable to 7H to disable

mov bx,07l2 ;attribute bit 3 in the color palette
intlO ;lookup table

movax,130l
mov bx,OOOF ;write char. string with attribute bit 3 = 1
mov cx,003A ;cx = character string length
mov dx,1600 ;write character on line 22 of display
mov bp,0200 ;pointer to character string location
push cs
popes
intlO

mov ax ,1301
mov bx,0007 ;write char. string with attribute bit 3 =0
mov cx,003A ;cx = character string length
mov dx,1700 ;write character on line 23 of display
mov bp,0200 ;pointer to character string location
push cs
popes
intlO
int 3

a200 db "This character string is used to show 512

characters"

Creating an 80 by 43 Alphanumeric Mode

The following examples show how to create 80 column by 43
row, both alphanumeric and graphics, images on the IBM
Monochrome Display. The BIOS Interface supports an 80
column by n row display by using the character generator load
routine call. The print screen routine must be revectored to

August 2, 1984 IBM Enhanced Graphics Adapter 71

handle the additional character rows on the screen. The assembly
language required for both an alphanumeric and a graphics screen
is shown below.

moval,7 ;Monochrome alphanumeric mode

int10 ;video interrupt call
movax,1112 ;character generator BIOS routine
mov bI,O ;load 8 by 8 double dot character font
int10 ;video interrupt call
movax,1200 ;alternate screen routine
move bI,20 ;select alternate print screen routine
int10 ;video interrupt call
int3

movax,f ;Monochrome graphic mode

int10 ;video interrupt call
movax,1123 ;character generator BIOS routine
mov bl,O ;load 8 by 8 double dot character font
mov di,28 ;43 character rows
int10 ;video interrupt call
movax,1200 ;alternate screen routine
mov bl,20 ;alternate print screen routine
int10 ;video interrupt call
int3

Vertical Interrupt Feature

The Enhanced Graphics Adapter can be programmed to create an
interrupt each time the vertical display refresh time has ended.
An interrupt handler routine must be written by the application to
take advantage of this feature. The CRT Vertical interrupt is on
IRQ2. The CPU can poll the Enhanced Graphics Adapter Input
Status Register 0 (bit 7) to determine whether the CRTC caused
the interrupt to occur.

The Vertical Retrace End Register (11H) in the CRT controller

contains two bits which are used to control the interrupt circuitry.
The remaining bits must be output as per the value in the mode
table.

72 IBM Enhanced Graphics Adapter August 2, 1984

Bit 5 Enable Vertical Interrupt-A logical 0 will
enable vertical interrupt.

Bit 4 Clear Vertical Interrupt-A logical 0 will clear a

vertical interrupt.

The sequence of events which occur in an interrupt handler are

outlined below.

1. Clear IRQ latch and enable driver

2. Enable IRQ latch
3. Wait for vertical interrupt
4. Poll Interrupt Status Register 0 to determine if CRTC has
caused the interrupt
5. If CRTC interrupt, then clear IRQ latch; if not, then branch
to next interrupt handler.
6. Enable IRQ latch
7. Update Enhanced Graphics Adapter during vertical blanking
interval
8. Wait for next vertical interrupt

Creating a Split Screen

The Enhanced Graphics Adapter hardware supports an
alphanumeric mode dual screen display. The top portion of the
screen is designated as screen A, and the bottom portion of the
screen is designated as screen B as per the following figure.

Screen A

Screen 8

Dual Screen Definition

The following figure shows the screen mapping for a system

containing a 32K byte alphanumeric storage buffer. Note that the
Enhanced Graphics Adapter has a 32K byte storage buffer in
alphanumeric mode. Information displayed on screen A is

August 2,1984 IBM Enhanced Graphics Adapter 73

defined by the start address high and low registers (OCH and
ODH) of the CRTC. Information displayed on screen B always
begins at address OOOOH.

OOOOH . - - - - - - - - ,
Screen B
Buffer Storage Area
OFFFH 1 - - - - - - - - ;
1000H
Screen A
Buffer Storage Area
7FFFH '--_ _ _ _ _--'
Screen Mapping Within the Display Buffer Address Space

The Line Compare Register (18H) of the CRT Controller is

utilized to perform the split screen function. The CRTC has an
internal horizontal scan counter, and logic which compares the
horizontal scan counter value to the Line Compare Register value
and clears the memory address generator when a compare occurs.
The linear address generator then sequentially addresses the
display buffer starting at location zero, and each subsequent row
address is is determined by the 16 bit addition of the start of line
latch and the offset register.

Screen B can be smoothly scrolled onto the CRT screen by

updating the Line compare in synchronization with the vertical
retrace signal. The information on screen B is immune from
scrolling operations which utilize the Start Address High and Low
registers to scroll through the Screen A address map.

Compatibility Issues
The CRT Controller on the IBM Enhanced Graphics Adapter is a
custom design, and is different than the 6845 controller used on
the IBM Monochrome Monitor Adapter and the IBM
Color/Graphics Monitor Adapter. It should be noted that several
CRTC register addresses differ between the adapters. The
following figure illustrates the registers which do not map directly
across the two controllers.

74 IBM Enhanced Graphics Adapter August 2, 1984

 Register 6485 Function EGA CRTC Function
02H Start Horiz. Retrace Start Horiz. Blanking
03H End Horiz. Retrace End Horiz. Blanking
04H Vertical Total Start Horiz. Retrace
05H Vertical Total Adjust End Horiz. Retrace
06H Vertical Displayed Vertical Total
07H Vertical Sync Position Overflow
08H Interlace Mode and Skew Preset Row Scan

Existing applications which utilize the BIOS interface will

generally be compatible with the Enhanced Graphics Adapter.

Horizontal screen centering was required on the IBM

Color/Graphics Monitor Adapter in order to center the screen
when generating composite video. This was done through the
Horizontal Sync Position Register. Since the Enhanced Graphics
Adapter does not support a composite video monitor, programs
which do screen centering may cause loss of the screen image if
centering is attempted.

The Enhanced Graphics Adapter offers a wider variety of

displayable monochrome character attributes than the IBM
Monochrome Display Adapter. Some attribute values may
display differently between the two Adapters. The values listed in
the table below, in any combinations with the blink and intensity
attributes, will display identically.

Background Foreground
R G B R G B Function
0 0 0 0 0 0 Non-Display
0 0 0 0 0 1 Underline
0 0 0 1 1 1 White Character/Black Background
1 1 1 0 0 0 Reverse Video

Software which explicitly addresses 3D8 (Mode Select Register)

or 3D9 (Color Select Register) on the Color Graphics Monitor
Adapter may produce different results on the Enhanced Graphics
Adapter. For example, blinking which is disabled by writing to
3D8 on the Color Graphics Adapter will not be disabled on the
Enhanced Graphics Adapter.

August 2, 1984 IBM Enhanced Graphics Adapter 7S

Interface

Feature Connector
The following is a description of the Enhanced Graphics Adapter
feature connector. Note that signals coming from the Enhanced
Graphics Adapter are labeled "inputs" and the signals coming to
the Enhanced Graphics Adapter through the feature connector
are labeled "outputs".

Signal Description

J2 This pin is connected to auxiliary jack 2 on the rear

panel of the adapter.

R'OUT Secondary red output

ATRS/L Attribute shift load. This signal controls the

serialization of the video information. The shift
register parallel loads at the dot clock leading edge
when this signal is low.

G OUT Primary green output

R' Secondary red input

R Primary red input

FC1 This signal is input from bit 1 (Feature Control Bit

1) of the Feature Control Register.

FCO This signal is input from bit 0 (Feature Control Bit

0) of the Feature control Register.

FEAT 0 This signal is output to bit 5 (Feature Code 0) of

Input Status Register O.

B'/V Secondary blue input/Monochrome video

YIN Vertical retrace input

76 IBM Enhanced Graphics Adapter August 2, 1984

Internal This signal is output to bit 4 (Disable Internal Video
Drivers) of the Miscellaneous Output Register.

V OUT Vertical retrace output

J1 This pin is connected to auxiliary jack 1 on the rear

panel of the adapter.

G'OUT Secondary green output

B'OUT Secondary blue output

BOUT Blue output

G Green input

B Blue input

ROUT Red output

BLANK This is a composite horizontal and vertical blanking

signal from the CRTC.

FEAT 1 This signal is output to bit 6 (Feature Code 1) of

Input Status Register O.

G'/I Secondary green/Intensity input

HIN Horizontal retrace input from the CRTC

14MHZ 14 MHz signal from the system board

EXT OSC External dot clock output

HOUT Horizontal retrace output

August 2, 1984 IBM Enhanced Graphics Adapter 77

The following figure shows the layout and pin numbering of the
feature connector.

Signal Name Signal Name

Gnd 1 2 ...........
, -12V

+12V J1

J2 G'OUT

R'OUT B'OUT

ATRS/L BOUT

GOUT G

R' B

R ROUT

FEAT 1 BLANK

FEAT 0 FC1

FCO G'/I

B'!V HIN

VIN 14MHz

Internal EXTOSC

VOUT HOUT

GND 31 32 +SV

~
'"
Feature Connector Diagram

78 IBM Enhanced Graphics Adapter August 2, 1984

Specifications

System Board Switches

The following figure shows the proper system board DIP switch
settings for the IBM Enhanced Graphics Adapter when used with
the Personal Computer and the Personal Computer XT. The
switch block locations are illustrated in the Technical Reference
Manual "System Board Component Diagram". The Personal
Computer has two DIP switch blocks; the switch settings shown
pertain to DIP Switch Block 1. The Personal Computer XT has
one DIP switch block.

1 234 5 6 7 8

~DDDD~~DD
Switch Block (1)

Note: The DIP switches must be set as shown whenever the

IBM Enhanced Graphics Adapter is installed, regardless of
display type. This is true even when a second display adapter
is installed in the system.

August 2, 1984 IBM Enhanced Graphics Adapter 79

Configuration Switches
The following diagram shows the location and orientation of the
configuration switches on the Enhanced Graphics Adapter.

Optional
Graphics Memory
Expansion Card

Off On

80 IBM Enhanced Graphics Adapter August 2, 1984

Configuration Switch Settings
The configuration switches on the Enhanced Graphics Adapter
determine the type of display support the adapter provides, as
follows:

Switch Sellings lor Enhanced Graphics Adapter

as Primary Display Adapter
Configuration
Enhanced Monochrome Color/Graphics
SWI SW2 SW3 SW4 Adapter Adapter Adapter
On Off Off On Color Display Secondary -
40x25
Off Off Off On Color Display Secondary -
BOx25
On On On Off Enhanced Display Secondary -
Emulation Mode
Off On On Off Enhanced Display Secondary -
Hi Res Mode
On Off On Off Monochrome - Secondary
40x25
Off Off On Off Monochrome - Secondary
BOx25

August 2, 1984 IBM Enhanced Graphics Adapter 81

 Switch Settings lor Enhanced Graphics Adapter
as Secondary Display Adapter
Conllguratlon
Enhanced Monochrome Color/Graphics
SWI SW2 SW3 SW4 Adapter Adapter Adapter
On On On On Color Display Primary -
40x25
Off On On On Color Display Primary -
BOx25
On Off On On Enhanced Display Primary -
Emulation Mode
Off Off On On Enhanced Display Primary -
Hi Res Mode
On On Off On Monochrome - Primary
40x25
Off On Off On Monochrome - Primary
BOx25

82 IBM Enhanced Graphics Adapter August 2, 1984

Direct Drive Connector

9-Pin Direct
Drive Signal

Signal Name - Description Pin

Ground 1
Secondary Red 2
Direct
Drive Primary Red 3 Enhanced
Display Graphics Adapter
Primary Green 4
Primary Blue 5
Secondary Green/Intensity 6
Secondary Blue/Mono Video 7
Horizontal Retrace 8
Vertical Retrace 9

August 2, 1984 IBM Enhanced Graphics Adapter 83

Light Pen Interface

P-2 Connector

P-2 Connector Pin

+Light Pen Input 1
Light Pen Not used 2 Enhanced
Attachment Graphics Adapter
+Light Pen Switch 3
Ground 4
+5 Volts 5
12 Volts 6

84 IBM Enhanced Graphics Adapter August 2, 1984

Jumper Descriptions
Located on the adapter are two jumpers designated PI and P3.
Jumper PI changes the function of pin 2 on the direct drive
interface. When placed on pins 2 and 3, jumper PI selects ground
as the function of direct drive interface, pin 2. This selection is
for displays that support five color outputs, such as the mM
Color Display. When PI is placed on pins I and 2, red prime
output is placed on pin 2 of the direct drive interface connector.
This supports the mM Enhanced Color Display, which utilizes six
color outputs on the direct drive interface.

Jumper P3 changes the I/O address port of the Enhanced

Graphics Adapter within the system. In its normal position, (pins
I and 2), all Enhanced Graphics Adapter addresses are in the
range 3XX. Moving jumper P3 to pins 2 and 3 changes the
addresses to 2XX. Operation of the adapter in the 2XX mode is
not supported in BIOS.

The following figure shows the location of the jumpers and

numbering of the connectors.

August 2, 1984 mM Enhanced Graphics Adapter 85

86 IBM Enhanced Graphics Adapter August 2, 1984
 .. '"'' m ~
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- "
-
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SHT1Sl1~~"::=======:'::
27'28
CI
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:z:I
l>
"'a
...~
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en
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BIOS Listing

Vectors with Special Meanings

Interrupt Hex 42 - Reserved
When an IBM Enhanced Graphics Adapter is installed, the BIOS
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Interrupt Hex 43 - IBM Enhanced Graphics Video

Parameters
When an IBM Enhanced Graphics Adapter is installed, the BIOS
routines use this vector to point to a data region containing the
parameters required for the initializing of the IBM Enhanced
Graphics Adapter. Note that the format of the table must adhere
to the BIOS conventions established in the listing. The power-on
routines initialize this vector to point to the parameters contained
in the IBM Enhanced Graphics Adapter ROM.

Interrupt Hex 44 - Graphics Character Table

When an IBM Enhanced Graphics Adapter is installed the BIOS
routines use this vector to point to a table of dot patterns that will
be used when graphics characters are to be displayed. This table
will be used for the first 128 code points in video modes 4,5, and
6. This table will be used for 256 characters in all additional
graphics modes. See the appropriate BIOS interface for
additional information on setting and using the graphics character
table pointer.

August 2, 1984 IBM Enhanced Graphics Adapter 103

 1 PAGE, 120
2 TITLE ENHANCED GRAPHICS ADAPTER BIOS
3 EXTRN CGMN:NEAR, CGDDOT:NEAR. INT_1F_':NEAR, CGMN_FOG:NEAR
4 EXTRN END_ADDRESS: NEAR
5
6
7 THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH
6 SOFTWARE INTERRUPTS ONLY, ANY ADDRESSES PRESENT IN
9 THE LISTINGS ARE INCLUDED ONLY FOR COMPLETENESS,
10 NOT FOR REFERENCE. APPLICATIONS WHICH REFERENCE
11 ABSOLUTE ADDRESSES WITH I N THE CODE SEGMENT
12 VIOLATE THE STRUCTURE AND DESIGN OF BIOS.
13
14
15 • LIST
16 INCLUDE VFRONT. I Ne
17 SUBTTL VfRONT. I Ne
16 PAGE
19
20 I NT 10 - --------- ------ ----------- - - -- -- --------------------- ------.
21 VIDEO 10
22 -THESE ROUTINES PROVIDE THE CRT INTERFACE
23 THE FOLLOW I NG FUNCT IONS ARE PROV IDEO:
24 (AH)"'O SET MODE (All CONTAINS MODE VALUE
25
26 AL AD TYPE RES NOTES OF-DIM DISPLAY MAX PGS
27
26 * 0 B8 ALPHA 64DX200 40X25 COLOR - BW
29 1 S. ALPHA 640X200 40X25 COLOR
30 * 2 B8 ALPHA 640X200 80X25 COLOR - BW
31 3 S6 ALPHA 640X200 80X25 COLOR
32 4 S6 GRPHX 320X200 40X25 COLOR
33 5 S6 GRPHX 320X200 40X25 COLOR - BW
34 6 SS GRPHX 640X200 80X25 COLOR - BW
35 * 7 BO ALPHA 720X350 80X25 MONOCHROME
36
37 RESERVED
36 RESERVED
39 RESERVED
40 RESERVED - I NTERNAL USE
41 RESERVED - I NTERNAL USE
42
D AO GRPHX 320X200 40X25 COLOR
'"44
45
E AO
FAD
GRPHX
GRPHX
640X200
640X350
80X25
80X25
COLOR
MONOCHROME
46 10 AO GRPHX 640X350 80X25 HI RES
47
46
49 NOTE: HIGH BIT AL SET PREVENTS REGEN BUFFER CLEAR ON
50 MODES RUNNING ON THE COMBO VIDEO ADAPTER
51
52 *** NOTE BW MODES OPERATE SAME AS COLOR MODES, BUT
53 COLOR BURST I S NOT ENABLED
54 (AH):l SET CURSOR TYPE
55 (CH) '= BITS 4-0 = START LINE FOR CURSOR
56 ** HARDWARE WILL ALWAYS CAUSE BLI NK
57 ** SETTING BIT 5 OR 6 WILL CAUSE ERRATIC
56 BUNKING OR NO CURSOR AT All
59 (Cl) = BITS 4-0 = END LINE FOR CURSOR
60 (AH)=2 SET CURSOR POSITION
61 (DH,Dl) = ROW,COlUMN (0,0) IS UPPER lEFT
62 (BH) = PAGE NUMBER
63 (AH)=3 READ CURSOR POSITION
64 (BH) = PAGE NUMBER
65 ON EXIT (DH,Dl) = ROW,COLUMN OF CURRENT CURSOR
66 (CH,CL) = CURSOR MODE CURRENTLY SET
67 (AH)=4 READ LIGHT PEN POSITION
66 ON EXIT:
69 (AH) = 0 ~- LIGHT PEN SWITCH NOT DOWN/NOT TRIGGERED
70 (AH) '" 1 -- VALID liGHT PEN VALUE IN REGISTERS
71 (DH,DL) = ROW,COlUMN OF CHARACTER LP POSN
72 (CH) == RASTER LINE (0~199)
73 (CX) == RASTER LINE (O-NNN) NEW GRAPHICS MODES
74 (BX) = PIXEL COLUMN (0-319,639)
75 {AH)=5 SELECT ACTIVE DISPLAY PAGE
76 (AL) = NEW PAGE VALUE, SEE AH==O FOR PAGE INFO
77 (AH)=6 SCROLL ACTIVE PAGE UP
76 (Al) = NUMBER OF LINES, INPUT LINES BLANKED AT BOTTOM
79 OF WINDOW
60 AL '" 0 MEANS BLANK ENT I RE WI NDOW
61 (CH,Cl) = ROW,COLUMN OF UPPER LEFT CORNER OF SCROLL
62 (DH,Dl) = ROW,COLUMN OF lOWER RIGHT CORNER OF SCROLL
63 (BH) = ATTR IBUTE TO BE USED ON BLANK LINE
64 (AH)=7 SCROLL ACTIVE PAGE DOWN
65 (Al) = NUMBER OF LINES, INPUT LINES BLANKED AT TOP
66 OF WINDOW
67 AL = 0 MEANS BLANK ENTIRE WINDOW
66 (CH,Cl) = ROW,COlUMN OF UPPER LEFT CORNER OF SCROLL
69 (DH,Dl) = ROW,COLUMN OF LOWER RIGHT CORNER OF SCROLL
90 (BH) = ATTR I BUTE TO BE USED ON BLANK LINE
91
92 CHARACTER HANDL I NG ROUT I NES
93
94 (AH) '" 8 READ ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION
95 (BH) = DISPLAY PAGE
96 ON EXIT:
97 (ALI = CHAR READ
96 (AH) = ATTRIBUTE OF CHARACTER READ (ALPHA MODES ONLY)
99 (AH) = 9 WRITE ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION
100 (BH) = DISPLAY PAGE
101 (CX) = COUNT OF CHARACTERS TO WRITE
102 (AL) = CHAR TO WRITE
103 (BL) == ATTRIBUTE OF CHARACTER (ALPHA)/COLOR Of CHAR
104 (GRAPHICS)
105 SEE NOTE ON WRITE DOT FOR BIT 7 Of 8l == 1.
106 (AH) '" A WRITE CHARACTER ONLY AT CURRENT CURSOR POSITION
107 (BH) = DISPLAY PAGE
10. (CX) = COUNT OF CHARACTERS TO WRITE
109 (Al) == CHAR TO WRITE
110 FOR READ/WRITE CHARACTER INTERFACE WHILE IN GRAPHICS MODE, THE
111 CHARACTERS ARE fORMED FROM A CHARACTER GENERATOR IMAGE
112 MAINTAINED IN THE SYSTEM ROM. ONLY THE 1ST 128 CHARS
113 ARE CONTAINED THERE. TO READ/WRITE THE SECOND 128
114 CHARS, THE USER MUST INITIALIZE THE POINTER AT :
115 INTERRUPT lFH (lOCATION 0007CH) TO POINT TO THE 1K BYTE:
116 TABLE CONTAINING THE CODE POINTS fOR THE SECOND :
117 128 CHARS (128~255).
11.
119 FOR THE NEW GRAPH I CS MODES 256 GRAPH I CS CHARS ARE
120 SUPPL I ED I N THE SYSTEM ROM.
121
122 FOR WRITE CHARACTER INTERFACE IN GRAPHICS MODE, THE REPLICATION;
123 fACTOR CONTAINED IN (CX) ON ENTRY WILL PRODUCE VALID :
124 RESULTS ONLY FOR CHARACTERS CONTAINED ON THE SAME ROW. :
125 CONTINUATION TO SUCCEEDING LINES WILL NOT PRODUCE :
126 CORRECTLY. :

104 IBM Enhanced Graphics Adapter August 2, 1984

 127 C
126 C GRAPHICS INTERFACE
129 C (AH) = B SET COLOR PALETTE
130 C FOR USE IN COMPATIBILITY MODES
131 C (8H) = PALETTE COLOR ID BEING SET (0-127)
132 C (Bll = COLOR VALUE TO BE USED WITH THAT COLOR 10
133 C NOTE: FOR THE CURRENT COLOR CARD, THIS ENTRY POINT
134 C HAS MEANING ONLY FOR 320X2DO GRAPHICS.
135 C COLOR ID = 0 SELECTS THE BACKGROUND COLOR (0-15)
136 C COLOR 10 = 1 SELECTS THE PALETTE TO BE USED:
137 C O=GREEN(lj/RED(2)/BROWN(3)
138 C 1 = CYAN(1)/MAGENTA(2)/WHITE(3)
139 C IN 40><25 OR 60X25 ALPHA MODES, THE VALUE SET
140 C FOR PALETTE COLOR 0 INDICATES THE
141 C BORDER COLOR TO BE USED (VALUES 0-31,
142 C WHERE 16-31 SELECT THE HIGH INTENSITY
143 C BACKGROUND SET).
144 C (AH) = C WRITE DOT
145 C (SH) = PAGE
146 C (OX) '" ROW NUMBER
147 C (ex) = COLUMN NUMBER
148 C (AL) '" COLOR VALUE
149 C If BIT 7 Of AL '" 1, THEN THE COLOR VALUE IS
150 C EXCLUSIVE aR'D WITH THE CURRENT CONTENTS OF
151 C THE DOT
152 C (AH) '" 0 READ DOT
153 C (BH) '" PAGE
154 C (OX) = ROW NUMBER
155 C ICX} = COLUMN NUMBER
156 C (AL) RETURNS THE DOT READ
157 C
158 C ASC I I TELETYPE ROUT I HE FOR OUTPUT
159 C
160 C (AHI '" E WRITE TELETYPE TO ACTIVE PAGE
161 C (AL) = CHAR TO WRITE
162 C (BL) '" FOREGROUND COLOR IN GRAPHICS MODE
163 C NOTE -- SCREEN WIDTH IS CONTROLLED BY PREVIOUS MODE SET
164 C
165 C (AHl '" F CURRENT VIDEO STATE
166 C RETURNS THE CURRENT VIDEO STATE
167 C (ALI = MODE CURRENTLY SET (SEE AH=O FOR EXPLANATION)
168 C (AH) = NUMBER OF CHARACTER COLUMNS ON SCREEN
169 C (BH) = CURRENT ACTIVE DISPLAY PAGE
170 C
171 C (AH) '" 10 SET PALETTE REGISTERS
172 C
173 C (ALl = 0 SET INDIVIDUAL PALETTE REGISTER
174 C BL = PALETTE REG I STER TO BE SET
175 C BH = VALUE TO SET
176 C
, 77 C AL = 1 SET OVERSCAN REG I STER
178 C BH = VALUE TO SET
179 C
180 C AL = 2 SET ALL PALETTE REGISTERS AND OVERSCAN
181 C ES:DX POINTS TO A 17 BYTE TABLE
182 C BYTES 0 ~ 15 ARE THE PALETTE VALUES, RESPECTIVELY
183 C BYTE 16 L 5 THE OVERSCAN VALUE
184 C
185 C AL = 3 TOGGLE INTENSIFY/BLINKING BIT
186 C BL ~ 0 ENABLE INTENSI FY
187 C BL - 1 ENABLE BLINKING
188 C
189 C (AHl = 11 CHARACTER GENERATOR ROUTINE
190 C NOTE: THIS CALL WILL INITIATE A MODE SET, COMPLETELY
191 C RESETTING THE VIDEO ENVIRONMENT BUT MAINTAINING:
192 C THE REGEN BUffER,
193 C
194 C AL '" 00 USER ALPHA LOAD
195 C ES:BP - POINTER TO USER TABLE
196 C CX - COUNT TO STORE
197 C OX - CHARACTER OFFSET INTO TABLE
198 C BL - BLOCK TO LOAD
199 C BH - NUMBER OF BYTES PER CHARACTER
200 C AL = 01 ROM MONOCHROME SET
201 C BL - BLOCK TO LOAD
202 C AL = 02 ROM 8X8 DOUBLE DOT
203 C BL - BLOCK TO LOAD
204 C AL = 03 SET BLOCK SPEC I F I ER
205 C BL - CHAR GEN BLOCK SPECIFIER
206 C 03-02 ATTR BIT" 3 ONE, CHAR GEN 0-3
207 C 01-00 ATTR BIT 3 ZERO, CHAR GEN 0-3
208 C NOTE : WHEN US I NG AL = 03 A FUNCT I ON CALL
209 C AX = 1000H
210 C BX = 0712H
211 C I S RECOMMENDED TO SET THE COLOR PLANES
212 C RESULTING IN 512 CHARACTERS AND EIGHT
213 C CONS I STENT COLORS.
214 C
215 C NOTE: THE FOLLOWING INTERFACE (AL=lXl IS SIMILAR IN FUNCTION
216 C TO (AL=OX) EXCEPT THAT:
217 C - PAGE ZERO MUST BE ACT I VE
218 C - POINTS (BYTES/CHAR) WILL BE RECALCULATED
219 C • ROWS WILL BE CALCULATED FROM THE FOLLOWING:
220 C INT((200 OR 350) / POINTS] M 1
221 C - CRT_LEN WILL BE CALCULATED FROM:
222 C (ROWS + 1) * CRT COLS * 2
223 C - THE CRTC WI LL BE REPROGRAMMED AS fOLLOWS:
224 C R09H '" PO I NTS - 1 MAX SCAN LI NI::
225 C R09H DONE ONLY IN MODE 7
226 C ROAH '" POINTS - 2 CURSOR START
227 C ROBH = 0 CURSOR END
228 C R12H = VERT DISP END
229 C (ROWS + 1) *
POINTS] - 1
230 C R14H = POINTS UNDERLINE LOC
231 C
232 C THE ABOVE REGISTER CALCULATIONS MUST BE CLOSE TO THE
233 C ORIGINAL TABLE VALUES OR UNDETERMINED RESULTS WILL
234 C OCCUR.
235 C
236 C NOTE: THE fOLLOWING INTERfACE IS DESIGNED TO BE
237 C CALLED ONLY IMMEDIATELY AFTER A MODE SET HAS :
238 C BEEN ISSUED. FAILURE TO ADHERE TO THIS PRACTICE:
239 C MAY CAUSE UNDETERMINED RESULTS,
240 C
241 C AL = 10 USER ALPHA LOAD
242 C ES: BP - PO I NTER TO USER TABLE
243 C CX - COUNT TO STORE
244 C OX - CHARACTER OffSET INTO TABLE
245 C BL - BLOCK TO LOAD
246 C BH - NUMBER OF BYTES PER CHARACTER
247 C AL = 11 ROM MONOCHROME SET
248 C BL • BLOCK TO LOAD
249 C AL = 12 ROM 8xe DOUBLE DOT
250 C BL - BLOCK TO LOAD
251 C
252 C

August 2, 1984 IBM Enhanced Graphics Adapter 105

 253 e NOTE: THE FOLLOWING INTERfACE IS DESIGNED TO BE
254 e CALLED ONLY IMMEDIATELY AfTER A MODE SET HAS •
255 e BEEN ISSUED. FAILURE TO ADHERE TO THIS PRACTICE:
256 e MAY CAUSE UNDETERMI NED RESULTS. :
251 e
256 e AL = 20 USER GRAPHICS CHARS INT OlfH (8Xa)
259 e E5:BP ~ POINTER TO USER TABLE
260 e AL = 21 USER GRAPHICS CHARS
261 e ES:BP - POINTER TO USER TABLE
262 e ex - PO I NTS (BYTES PER CHARACTER)
263 e BL - ROW SPECIFIER
264 e
265 e BL '" 0 USER
266 e DL - ROWS
261 e Bl = 1 14 (OEH)
266 e Bl = 2 25 (19H)
269 e BL = 3 43 (28H)
210 e
211 e AL=22 ROM8X14SET
212 e BL - ROW SPECI FI ER
213 e AL = 23 ROM 8 X 8 DOUBLE DOT
214 e BL -ROWSPECIFIER
215 e
216 e
211 e AL = 30 INFORMATION
216 e ex - POINTS
219 e OL - ROWS
260 e BH - 0 RETURN CURRENT I NT 1 FH PTR
261 e ES: BP - PTR TO TABLE
262 e BH - 1 RETURN CURRENT I NT 44H PTR
283 e ES: BP - 'PTR TO TABLE
264 e BH - 2 RETURN ROM B X 14 PTR
265 e ES: BP - PTR TO TABLE
266 e BH - 3 RETURN ROM DOUBLE DOT PTR
261 e ES:BP - PTR TO TABLE
266 e BH - 4 RETURN ROM DOUBLE DOT PTR (TOP)
269 e ES:BP - PTR TO TABLE
290 e BH - 5 RETURN ROM ALPHA ALTERNATE 9X14
291 e ES:BP - PTR TO TABLE
292 e
293 e (AH) '" 12 ALTERNATE SELECT
294 e
295 e BL == 10 RETURN EGA INFORMATION
296 e BH == 0 - COLOR MODE IN EffECT <3><D><X>
291 e 1 - MONDC MODE I N EffECT <3><B><X>
296 e BL = MEMORY VALUE
299 e o
0 - 064K 0 1 - 128K
300 e 10-192K 11-256K
301 e CH = FEATURE BITS
302 e CL == SWI TCH SETT I NG
303 e
304 e BL = 20 SELECT ALTERNATE PRINT SCREEN ROUTINE
305 e
306 e (AH) == 13 WRITE STRING
301 e ES;BP - POINTER TO STRING TO BE WRITTEN
306 e CX - CHARACTER ONLY COUNT
309 e OX - POSITION TO BEGIN STRING, IN CURSOR
310 e TERMS
311 e BH - PAGE NUMBER
312 e
313 e AL == 0
314 e BL - ATTRIBUTE
315 e STRING - (CHAR, CHAR, CHAR, .. )
316 e CURSOR NOT MOVED
311 e AL == 1
316 e BL - ATTRIBUTE
319
320
e
e
STRING - (CHAR, CHAR,
CURSOR I S MOVED
CHAR, ... )
321 e AL = 2
322 e STRING - (CHAR, ATTR, CHAR, ATTR, .. )
323 e CURSOR NOT MOVED
324 e AL == 3
325 e STRING - (CHAR, ATTR, CHAR, ATTR, .. )
326 C CURSOR I S MOVED
321 e
326 e NOTE: CHAR RET, LI NE FEED, BACKSPACE, AND BELL ARE
329 e TREATED AS COMMANDS RATHER THAN PRINTABLE
330 e CHARACTERS.
331 e
332 e
333 e
334 e SRLOAD MACRO SEGREG, VALUE
335 e I FNB <VALUE>
336 e I fI ON <VALUE>, <0>
331 e SUB OX,OX
336 e ELSE
339 e MOV OX, VALUE
340 e ENOl F
341 e ENOl F
342 e MOV SEGREG,OX
343 e ENOM
344 e
345 e
346 e ; ----- LOW MEMORY SEGMENT
341 e
0000 346 e ABSO SEGMENT AT
0014 349 e ORe 005H*4 ; PR I NT SCREEN VECTOR
0014 350 e I NTS_PTR LABEL OWORD
0040 351 e ORe D1DH*4 ; VIDEO I/O VECTOR
0040 352 e VIDEO LABEL OWORD
007C 353 e ORe 01FH*4 ; GRAPHIC CHARS 128-255
007C 354 e EXT_PTR LABEL DWORD
355 e
0108 356 e ORe 042H*4 REVECTORED 10H*4
0108 351 e PLANAR_VIDEO LABEL aWaRD
356 e
Oloe 359 e ORG 043H*4 GRAPHIC CHARS 0-255
Oloe 360 e GRX_SET LABEL aWaRD
361 e
0410 362 e ORG 0410H
0410
0410
363
364
e
e
EQU I P_LOW
EQUI P_FLAG
LABEL
OW ,
BYTE

365 e
366 e ;----- REUSE RAM FROM PLANAR BIOS
361 e
0449 366 e ORG 449H
0449 ?1 369 e CRT MODE DB
044A 1711 310 e CRT-COLS OW
044C ???? 311 e CRT:::\EN OW '7
044E 11?7 312 e CRT START OW '7
0450 08 I 313 e CURSOR_POSN aw 8 OUP( 1)
7117 374 e
315 e
316 e
0460 ???? 311 e
0462 ?? 316 e

106 IBM Enhanced Graphics Adapter August 2, 1984

0463
0465
7117
77
37,
380
C
C
AoDR_6845
CRT_MODE_SET
OW
OB
0466 71 381 C CRTJALETTE OB
382 C
0472 383 C ORG 0472H
0472 1717 384 C RESET FLAG OW
0484 385 C - ORG 0484H
0484 71 386 C ROWS DB 1 ROWS ON THE SCREEN
0485 1117 387 C POI NTS OW ? BYTES PER CHARACTER
388 C
0487 11 38. C INFO 08
390 C
3"392 C
C
INFO
07 - HIGH BIT OF MODE SET, CLEAR/NOT CLEAR REGEN
393 C 06 - MEMORY 06 05 == 0 0 - 064K 0 1 1281<
394 C 05·- MEMORY 1 0 - '92K 1 1 - 256K
395 C 04 - RESERVED
396 C 03 - EGA ACTIVE MONITOR (0), EGA NOT ACTIVE (1)
397 C 02 - WAIT FOR DISPLAY ENABLE (1)
398 C 01 EGA HAS A MONOCHROME ATTACHED (1)
399 C 00 - SET C_TYPE EMULATE ACTIVE (O)
400 C
0488 11 401 C
402 C
403 C INFO_3
404 C 07-04 FEATURE BITS
405 C 03-00 SWITCHES
406 C
04A8 407 C 04A8H
04A8 408 C LABEL DWORD
409 C
410 C
4" C
412 C SAVE_PTR IS A PO I NTER TO A TABLE AS DESCR I BED AS FOLLOWS :
413 C
414 C DWORD 1 V IDEO PARAMETER TABLE PO INTER
4"
416
C
C
OWORD-2
OWORO-3
OYNAM I C SAVE AREA PO INTER
ALPHA MODE AUXILIARY CHAR GEN POINTER
417 C OWORD-4 GRAPHICS MODE AUXILIARY CHAR GEN POINTER
418 C OWORD-5 RESERVED
419 C OWORO-6 RESERVED
420 C DWORO=7 RESERVED
421 C
422 C DWORD_' PARAMETER TABLE PO INTER
423 C INITIALIZED TO BIOS EGA PARAMETER TABLE.
424 C TH I S VALUE MUST EX I ST.
4"
426
C
C PARAMETER SAVE AREA PO INTER
427 C INITIALIZED TO 0000:0000, THIS VALUE IS OPTIONAL.
428 C WHEN NON-ZERO, THIS POINTER WILL BE USED AS POINTER
429 C TO A RAM AREA WHERE CERTAIN DYNAMIC VALUES ARE TO
430 C BE SAVED. WHEN IN EGA OPERATION THIS RAM AREA WILL
431 C HOLD THE 16 EGA PALETTE REGISTER VALUES PLUS
432 C THE OVERSCAN VALUE IN BYTES 0-160 RESPECTIVELY.
4"
434
C
C
AT LEAST 256 BYTES MUST BE ALLOCATED FOR THIS AREA.

4"
436
C
C
ALPHA MODE AUXILIARY POINTeR
INITIALIZED TO 0000:0000, THIS VALUE IS OPTIONAL.
437 C WHEN NON-ZERO, THIS POINTER IS USED AS A POINTER
438 C TO A TABLES DESCRIBED AS FOLLOWS:
439 C
440 C BYTE BYTES/CHARACTER
441 C BYTE BLOCK TO LOAD, SHOULD BE ZERO FOR NORMAL
442 C OPERATION
443 C WORD COUNT TO STORE, SHOULD BE 2560 FOR NORMAL
444 C OPERATION
445 C WORD CHARACTER OFFSET, SHOULD BE ZERO FOR NORMAL
446 C OPERATION
447 C DWORD PO I NTER TO A FONT TABLE
448 C BYTE DISPLAYABLE ROWS
449 C IF 'FF' THE MAXIMUM CALCULATED VALUE WILL BE
450 C USED, ELSE TH I S VALUE WILL BE USED
4"
452
C
C
BYTE CONSECUTIVE BYTES OF MODE VALUES FOR WHICH
THIS FONT DESCRIPTION IS TO BE USED.
4"
.,4 C
C
THE END OF THIS STREAM IS INDICATED BY A
BYTE CODE OF 'Ff'
455 C
456 C NOTE: USE OF THIS POINTER MAY CAUSE UNEXPECTED
457 C CURSOR TYPE OPERATION. FOR AN EXPLANATION
458 C OF CURSOR TYPE SEE AH '" 01 I N THE INTERFACE
459 C SECT I ON.
460 C
461 C GRAPHICS MODE AUXILIARY POINTER
462 C INITIALIZED TO 0000:0000, THIS VALUE IS OPTIONAL.
463 C WHEN NON-ZERO, THIS POINTER IS USED AS A POINTER
464 C TO A TABLES DESCRIBED AS FOLLOWS:
465 C
466 C BYTE DISPLAYABLE ROWS
467 C WORO BYTES PER CHARACTER
468 C DWORD PO I NTER TO A FONT TABLE
469 C BYTE CONSECUT I VE BYTES OF MODE VALUES FOR WH I CH
470 C THIS FONT DESCRIPTION IS TO BE USED.
471 C THE END OF THIS STREAM IS INDICATED BY A
472 C BYTE CODE OF 'FF'
473 C
474 C DWORD_5 THRU DWORD_7
475 C RESERVED AND SET TO 0000:0000.
47. C
477 C
0500 478 C ORG 0500H
0500 17 479 C STATUS BYTE OB
0501 480 C ABSO - ENDS
481 C
== 0061 482 C PORT B EQU 61" 8255 PORT B ADDR
== 0040 483 C TIMER EQU 40"
484 C
485 C ; ----- EQUATES FOR CARD PORT ADDRESSES
486 C
'" 00C4 487 C SEQ ADDR EQU OC4H
'" 00C5 488 C SEcLDATA EQU OCSH
== 0004 489 C CRTC ADDR EQU OD4H
'" 00B4 490 C CRTC::::ADDR_B [QU OB4H
== 0005 491 C CRTC_DATA EQU OD5H OR OB5H
:= OOCC 492 C GRAPH_'_POS EQU OCCH
'" OOCA 493 C GRAPH_2_POS EQU OCAH
= OOCE 494 C GRAPH_ADDR EQU OCEH
= OOCF 495 C GRAPH DATA EQU OCFH
= OOC2 496 C MI SC OUT PUT EQU OC2H
'" 00C2 497 C I N_STAT_O EQU OC2H
'" OOBA 498 C I NPUT STATUS B EQU OBAH
'" OODA 499 C I NPU(=STATUS- EQU ODAH
= OODA 500 C ATTR READ EQU ODAH
= OOCO 501 C ATTR=WRITE EQU OCOH
502 C
503 C ;----- EQUATES FOR ADDRESS REGISTER VALUES
504 C

August 2, 1984 IBM Enhanced Graphics Adapter 107

 0000 505 S_RESET EQU 00"
0001 506 S_CLOCK EQU 01"
0002 507 S_MAP EQU 02"
0003 508 S_CGEN EQU 03"
0004 509 S_MEM EQO 04"
510
'" 0000 511 C_HRZ_TOT EQU 00"
'" 0001 512 C_HRZ_DSP EQU 01"
'" 0002 513 C_STRT_HRZ_BLK EQU 02"
=: 0003 514 C_END_HRZ_BLK EQU 03"
=: 0004 515 C_STRT_HRZ_SYN EQU 04"
= 0005 516 C_END_HRZ_SYN EQU 05"
= 0006 517 C_VRT_TOT EQU 06"
= 0007 518 C_OVERFLOW EQU 07"
'" 0008 519 C_PRE_ROW EQO 08"
=: 0009 520 C_MAX_SCAN_lN EQU 09"
= OOOA 521 C_CRSR_START EQU OA"
= 0008 522 C_CRSR_END EQU 08"
=: OOOC 523 C_STRT_HGH EQU OC"
= 0000 524 C_STRT_LOW EQU 00"
::: OOOE 525 C_CRSR_LOC_HGH EOU OE"
= OOOF 526 C_CRSR_LOC_LOW EOU OF"
'" 0010 527 C_VRT_SYN_STRT EOU 10" ; WRITE ONLY
::: 0010 528 C_LGHT_PEN_HGH EQU 10" ; READ ONLY
= 0011 529 C_YRT_SYN_END EQU ; WRITE ONLY
= 0011
= 0012
530
531
C_lGHT_PEN_LOW
C_VRT_DSP_END
EOU
EOU
""
""
12"
; READ ONLY

= 0013 532 C_OffSET EOU 13"

=: 0014 533 C_UNDERUCLOC EOU 14H
=: 0015 534 C_STRT_VRT_BLK EQU 15"
=: 0016 535 C_END_VRT_BLK EOU 16"
= 0017 536 C_MODE_CNTL EOU 17"
= 0018 537 C_LN_COMP EOU 18"
538
= 0000 539 G_SET_RESET EOU 00"
= 0001 540 G_ENBL_SET EOU 01"
= 0002 541 G_CLR_COMP EOU 02"
=: 0003 542 G DATA ROT EOU 03"
=: 0004 543 G-REAO-MAP EOU 04"
=: 0005 544 G=MOOC EOU 05"
'" 0006 545 G_MI SC EOU 06"
= 0007 546 G_COLOR EOU 07"
= 0008 547 G_BIT_MASK EOU 06H
548
= 0010 549 P_MODE EOU 10H
0011 550 P_OVERSC EOU
""
=:
= 0012 551 P CPLANE EOU 12"
=:0013 552 P=HPEL EOU 13H
553
554 SUBTTL
555
556 ; ----- CODE SEGMENT
557
0000 558 CODE SEGMENT PUBL! C
559
560 c INCLUDE VPOST. INC
561 c SUBTTL VPOST. INC
562 c PAGE
563 c
564
565
c
c
; ----- POST

566 c ASSUME CS: CODE, DS;ABSO

0000 567 c ORC OH
0000 55 568 c 08 055H ; SIGNATURE
0001 AA 569 c 08 OAAH ; BYTES
0002 20 570 c 06 020H ; LENGTH INDICATOR
571 c
572 c ;----- NOTE; 00 NOT USE THE SIGNATURE BYTES AS A PRESENCE TEST
573 c
574 c PLANAR VIDEO SWITCH SETTINGS
575 c
576 c o 0 - UNUSED
577 c 01-4QX25COlOR
578 c 10-8QX25COLOR
579 c 1 1 - 80 X 25 MONOCHROME
580 c NOTE : 0 0 MUST BE SET WHEN TH I S ADAPTER I S INSTALLED.
581 c
582 c V IDEO ADAPTER SW ITCH SETT I NGS
583 c
584 c o 0 0 0 - MONOC PRIMARY, EGA COLOR, 40X25
585 c a Q 0 1 - MONOC PRIMARY, EGA COLOR, 80X25
586 c 0010 - MONOC PRIMARY, EGA HI RES EMULATE (SAME AS 0001)
587 c o 0 1 1 - MONOC PR I MARY, EGA H I RES ENHANCED
588 c o 1 0 0 - COLOR 40 PRIMARY, EGA MONOCHROME
589 c o 1 0 1 - COLOR 80 PRIMARY, EGA MONOCHROME
590 c
591 c o 1 1 0 - MONOC SECONDARY, EGA COLOR, 40X25
592 c o 1 1 1 - MONOC SECONDARY, EGA COLOR, 80X25
593 c 1 0 a
0 - MoNOC SECONDARY, EGA HI RES EMULATE (SAME AS 0111)
594 c 1 0 a
1 - MONOC SECONDARY, EGA H I RES ENHANCED
595 c 1 0 1 0 - COLOR 40 SECONDARY, EGA MONOCHROME
596 c 1 0 1 1 - COLOR 80 SECONDARY, EGA MONOCHROME
597 c
598 c 1 1 0 0 - RESERVED
599 c 1 1 0 1 - RESERVED
600 c 1 1 1 0 - RESERVED
601 c , 1 1 1 - RESERVED
602 c
603 c ; ----- SETUP ROUT I NE fOR TH I S MODULE
604 c
0003 605 c VIDEO SETUP PROC FAR
0003 E8 28 606 c - JMP SHORT Ll
0005 32 34 30 30 607 c 08 '2400'
0009 36 32 37 37 33 35 608 c OB '6277356 (C)COPYRtGHT IBM 1984'
36 20 28 43 29 43 609 c
4F 50 59 52 49 47 610 c
48 54 20 49 42 40 611 c
20 31 39 38 34 612 c
0026 39 2F 31 33 2F 38 613 c 08 '9/13/84'
34 614 c
615 c
616 c ;----- SET UP VIDEO VECTORS
617 c
0020 618 C L1:
0020 86 03 619 C MOV DH,3
002F 82 OA 620 C MOV DL, INPUT_STATUS
0031 EC 621 C IN AL,DX
0032 B2 SA 622 C MOV OL, I NPUT_STATUS_B
0034 EC 623 C IN AL,DX
0035 82 CO 624 C MOV DL,ATTR_WRITE
0037 80 00 625 C MOV AL,O
0039 EE 626 C OUT DX,AL
627 C
628 C SRLOAO DS,O
003A 28 02 629 c+ SUB OX, OX
003C 8E OA 630 c+ MOV OS, OX

108 IBM Enhanced Graphics Adapter August 2, 1984

003E FA 631 e eLI
003f C7 06 0040 R OC07 R 6'2 e MOV WORD PTR VIDEO, OffSET COMBO_VIDEO
0045 8C DE 0042 R 633 e MOV WORD PTR VIDEO+2, CS
0049 C7 06 0108 R f065 6'4 C MOV WORD PTR PLANAR_V IDEO, Of065H
004f C7 06 OlOA R fOOD 635 C MOV WORD PTR PLANAR_V I DEO+2, OfOOOH
0055 C7 06 04A8 R 010C R 6'6 e MOV WORD PTR SAVE_PTR,OffSET SAVE_TBl
005B 8C DE 04AA R 6'7 e MOV WORD PTR SAVE_PTR+2, CS
005f C7 06 007C R 0000 E 6'. e MOV WORD PTR EXT_PTR, OFfSET INT_1F_l
0065 8C DE 007E R 6'9 e MOV WORD PTR EXT_PTR+2, CS
0069 C7 06 010C R 0000 E 640 e MOV WORD PTR GRX_SET, OFFSET CGODOT
006F 8C OE 010E R 641 C MOV WORD PTR GRX_SET+2, CS
0073 F. 642 C STI
64, C
644 C ;----- POST FOR COMBO VIDEO CARD
645 C
0074 C6 06 0487 R 04 646 c MOV INFO, 000001 OOB
0079 E8 009B R 647 C CAll RD_SWS
007C 88 lE 0488 R 646 C MOV INFO_3,Bl
0080 E8 OOCE R 649 C CAll F_BTS
0083 08 06 0488 R 650 e OR I NfO_3,Al
0087 8A lE 0488 R 651 e MOV Bl,INfO_3
008B E8 00F3 R 652 e CAll MK_ENV
008E E9 0244 R 653 e JMP POST
0091 654 e SKI P:
0091 e6 655 e RET
0092 656 C VIDEO_SETUP ENDP
657 e
656 e
0092 659 c POR_l PROC NEAR
0092 EE 660 e OUT DX,Al
0093 50 661 e PUSH AX
0094 56 662 e POP AX
0095 EC 66' e IN Al,DX
0096 24 10 664 C AND Al, 01 OH
0098 DO E8 665 C SHR Al,l
009A C' 666 C RET
009B 667 C POR_l ENDP
666 C
669 C ; ----- READ THE SW ITCH SETT I NGS ON THE CARD
670 e
009B 671 C RO_SWS PROC NEAR
672 C ASSUME DS:ABSO
009B B6 03 673 C MDV OH,3
0090 B2 C2 674 C MOV Dl,MISC_OUTPUT
009F BO 01 675 C MOV Al,'
OOAl EE 676 e OUT DX,Al
677 C
676 e ;----- COULD BE O,4,8,C
679 c
00A2 BO 00 660 e MDV Al,ODH
00A4 E8 0092 R 661 e CAll POR_l
00A7 00 E8 662 e SHR Al,l
DOA9 DO E8 66' e SHR Al,'
OOAB DO E8 664 C SHR Al,'
DOAD 8A 06 665 e MDV Bl,Al
666 e
OOAF BO 09 667 e MDV Al,9
OOBl E8 0092 R 666 e CAll POR_l
00B4 DO E6 669 e SHR Al,l
00B6 DO E8 690 e SHR Al,l
00B8 OA 06 691 e DR Bl,Al
692 e
OOBA BO 05 693 e MOV Al,5
OOBC E6 0092 R 694 e CAll POR_'
OOBf 00 E8 695 e SHR Al,l
OOCl OA 08 696 C OR 6l,Al
697 C
00C3 BO 01 696 C MOV Al,l
00C5 E8 0092 R 699 C CAll POR_l
00C8 OA 08 700 C OR Bl,AL
701 e
DOCA 80 E3 OF 702 C AND Bl,OFH
OOCO C' 70, e RET
OOCE 704 e RD_SWS ENOP
705 e
706 e ;----- OBTAIN THE FEATURE BITS FROM DAUGHTER CARD
707 C
OOCE 706 C F_BTS PROC NEAR
OOCE B6 03 709 C MOV DH,3
0000 B2 SA 710 e MOV Dl,DBAH
0002 60 01 711 C MOV Al,l
0004 EE 712 C OUT DX,Al
0005 B2 OA 713 C MOV Dl,OoAH
0007 EE 714 C OUT DX,AL
0008 62 C2 715 e MOV Dl, I N_STAT_O
DaDA EC 716 e IN Al,DX READ FEATURE BITS
00 DB 24 60 717 e AND Al,060H
0000 DO E8 716 e SHR Al,l
OOoF 8A 08 719 C MOV Bl,Al
OOEl B2 BA 720 C MOV Ol,OBAH
00E3 BO 02 721 C MOV Al,2
00E5 EE 722 C OUT OX,Al
OOE6 82 DA 72' C MOV Dl,ODAH
00E8 EE 724 C OUT OX,Al
00E9 B2 C2 725 C MOV Dl, IN_STAT_a
OOEB EC 726 C IN Al,DX ; READ FEATURE BITS
OOEC 24 60 727 C AND Al,060H
OOEE DO EO 726 C SHL Al,l
OOFO OA C3 729 c OR Al,8l
00f2 C' 7'0 C RET
OOf3 731 C F_BTS ENDP
732 C
733 C ;----- ESTABLISH THE VIDEO ENVIRONMENT, KEYED OFF Of THE SWITCHES
734 C
00F3 735 C MK_ENV PROC NEAR
7'6 C ASSUME DS:A8S0
OOFS 2A ff 737 C SU6 BH,BH
OOF5 80 E3 Of 7'8 C AND Bl,OFH
00F8 D1 E3 739 C SAL BX,l
Oaf A 52 740 C PUSH OX
OOfB B6 03 741 C MOV OH,3
OOFD 8A E6 742 C MOV AH,DH
DOFF 5A 743 C POP OX
0100 BO E4 01 744 C AND AH,l
0103 FE c4 745 C INC AH
0105 F6 04 746 C NOT AH
0107 2E: FF A7 0128 R 747 C JMP WORD PTR CS: I 8X + OffSET T5]
746 C
010C 749 C SAVE_TBl lABEL DWORD
010C 0717 R 750 C ow OffSET VIDEO_PARMS PARMS
alOE COOO 751 C OW OCOOOH PARMS
0110 0000 752 C OW 0 PAL SAVE AREA
0112 0000 753 C ow 0 PAL SAVE AREA
0114 0000 754 C ow 0 , ALPHA TABLES
0116 0000 755 C ow 0 ; ALPHA TABLES
0118 0000 756 C ow 0 ; GRAPH I CS TABLES

August 2, 1984 IBM Enhanced Graphics Adapter 109

OllA 0000 151 C DW GRAPH I CS TABLES
158 C
011C 0000 159 C DW
011E 0000 160 C DW
0120 0000 161 C DW
0122 0000 162 C DW
0124 0000 163 C DW
0126 0000 164 C DW
165 C
0128 166 C T5 LABEL WORD
0128 0171 R 161 C DW OffSET PST_O
012A 017E R 168 C DW OFFSET PST_l
012C 017E R 169 C DW OFfSET PST_2
012E 0189 R 110 C DW OFFSET PSC1

gn~H ~~i=~
0130 0194 R 111 C DW
0132 01A8 R 112 C DW
0134 OlBC R 113 C OW OfFSET PST_6
0136 01C7 R 114 C OW OfFSET PST_7
115 C
0138 01C7 R 116 C OW OFfSET PST 8
013A 0102 R 111 C DW OffSET PST-9
013C 0100 R 118 C DW OffSET PST-A
013E 01 f1 R 119 C DW OffSET PST-B
0140 0204 R 180 C DW OfFSET PST=OUT
0142 0204 R 181 C DW OfFSET PST OUT
0144 0204 R 162 C DW OFFSET PST-OUT
0146 0204 R 183 C DW OffSET PST=OUT
184 C
0148 185 C ENV_X PROC NEAR ; SET 40X25 COLOR ALPHA
0148 80 26 0410 R CF 166 C AND EQU I P_LOW, OCfH
0140 80 OE 0410 R 10 161 C OR EQUIP_LOW,010H
0152 B8 0001 188 C MOV AX,lH
0155 CD 10 169 C INT 10M
0157 C3 190 C RET
0158 191 C ENV_X ENOP
192 C
0158 193 C ENV_O PROC NEAR SET 80X25 COLOR ALPHA
0158 80 26 0410 R cr 194 C AND EQUIP_LOW,OCfH
0150 80 DE 0410 R 20 195 C OR EQU I P_LOW,020H
0162 B8 0003 196 C MOV AX,OlH
0165 CD 10 191 C INT 10M
0167 C3 196 C RET
0168 799 C [NV_O ENDP
600 C
0168 601 C ENV_1 PROC NEAR SET MONOCHROME ALPHA
0168 80 DE 0410 R 30 802 C OR EQUIP_LOW,030H
0160 B8 0007 603 C MOV AX,07H
0170 CO 10 604 C INT 10M
0172 C3 605 C RET
0173 606 C ENV_3 ENOP
601 C
606 C
0173 609 C PST_O:
0173 20 26 0487 R 610 C AND INFO,AH
0177 E8 0148 R 611 C CALL ENV X
017A E8 0168 R 612 C CALL ENV=l
0170 C3 613 C RET
017E 614 C PST_1:
017E 615 C PST_2:
017E 20 26 0487 R 616 C AND INFO,AH
0182 E8 0158 R 617 C CALL ENV_O
0185 E8 0168 R 616 C CALL ENV_1
0188 C3 619 C RET
0189 620 C PST_3:
0189 20 26 0487 R 621 C AND INFO,AH
0180 f8 0158 R 622 C CALL ENV_O
0190 E8 0168 R 823 C CALL fNV_1
0193 C3 824 C RET
0194 825 C PST_4:
0194 86 03 826 C MOV OH,3
0196 B2 C2 627 C MOV oL,M1SC_OUTPUT
0198 SO 00 628 C MOV AL,O
019A EE 629 C OUT DX,AL
019B f6 04 830 C NOT AM
0190 08 26 0487 R 831 C OR I NFO,AH
01Al E8 0168 R 632 C CALL ENV_3
01A4 E8 0148 R 833 C CALL ENV_X
01A7 C3 834 C RET
01A8 835 C PST_5:
01A8 86 01 836 C MOV OH,3
01AA 82 C2 837 C MOV Ol,MISC_OUTPUT
01AC BO 00 838 c MOV AL,O
01AE EE 839 C OUT OX,Al
OlAF F6 04 840 C NOT AM
OlBl 08 26 0487 R 641 C OR I NFO,AH
0185 £8 0168 R 842 C CALL ENV_3
01B8 £8 0158 R 843 C CALL ENV_O
0188 C3 644 C RET
01BC 645 C PST_6:
01SC 20 26 0487 R 846 C AND INFO,AH
OlCO £8 0168 R 847 C CALL ENV 3
01C1 £8 0148 R 848 C CAll ENV=X
01C6 C3 849 C RET
01C7 850 C PST_7:
01C7 851 C PST_8:
01C7 20 26 0487 R 852 C AND INFO,AH
01CB f8 0168 R 853 C CALL ENV_3
01CE £8 0158 R 854 C CALL ENV_O
0101 C3 855 C RET
0102 856 C PST_9:
0102 20 26 0487 R 851 C AND INFO,AH
0106 £8 0168 R 858 C CALL ENV_3
0109 E8 0158 R 859 C CALL ENV_O
010C c3 860 C RET
0100 661 C PST_A:
0100 B6 01 862 C MOV OH,3
010F B2 C2 863 C MOV OL, M I SC_OUTPUT
01E1 BO 00 864 C MOV AL,O
01E3 EE 665 C OUT OX,AL
01E4 F6 04 866 C NOT AM
01 E6 08 26 0487 R 867 C OR I NFO,AH
OlEA E8 0148 R 666 C CALL ENV_X
OlEO £8 0168 R 869 C CALL ENV_1
OHO C3 870 C RET
01 f1 871 C PST_B:
OlFl B6 03 872 C MOV OH,3
OlF3 B2 C2 873 C MOV OL, MI SC_OUTPUT
OH5 80 00 814 C MOV AL,O
01f7 EE 815 C OUT OX,AL
OH8 F6 04 876 C NOT AM
OHA 08 26 0487 R 811 C OR INfO,AH
OlFE E8 0158 R 878 C CALL ENV_O
0201 £8 0168 R 819 C CALL ENV_1
0204 880 C PST_OUT:
0204 C3 881 C RET
0205 882 c MK_ENV ENoP

110 IBM Enhanced Graphics Adapter August 2, 1984

 88' C
8.,
885
C
C ; ~T~is-ROUT i NE-jESTS -T~E-cRT-cARD-iNTERNAL-DATA -suS-AND -iN -A-LiMiTED ----
88. C ; WAY TESTS THE eRTC VIDEO CHIP BY WRITiNG/READING FROM CURSOR REGISTER
887 C ; CARRY I S SET I F AN ERROR I S FOUND
888 C
889 C ; REGISTERS BX,SI,ES,OS ARE PRESERVED,
890 C ; REG I STERS AX, CX, OX ARE MODI FYED,

0205
891
892
C
C
bD:pRESENcE:'fs'f-pRoc----NEAR--------------------------------------------
0205 53 89' C PUSH BX SAVE BX
0206 B8 007F 89' C MOV BX,07FH INITIAL WORD PATTERN BYTE
0209 88 FB 895 C MOV DI,BX
020B 50 89. C PUSH AX SAVE PORT ADDRESS
020C £8 022C R 897 C CALL RO_CURSOR
020F 88 FO 898 C MOV 51 ,AX SAVE OR I G I NAL VALUE
0211 58 899 C POP AX RECOVER PORT ADDRESS
0212 50 900 C PUSH AX SAVE PORT ADDRESS
0213 £8 0236 R 901 C CALL WR_CURSOR WR I TE CURSOR
0216 58 902 C POP AX RECOVER PORT ADDRESS
0217 50 90' C PUSH AX SAVE PORT ADDRESS
0218 £8 022C R 90, C
g~~L ~~;gyRSOR READ IT BACK
021B 38 C7 905 C SAME?
0210 58 90. C POP AX
021 E 75 03 907 C JNZ NOT_PRESENT EXIT IF NOT EQUAL
0220 EB 05 90 908 C JMP TST_EX
0223 909 C NOT_PRESENT:
0223 33 CO 910 C XOR AX,AX SET NOT PRESENT
0225 56 911 C POP BX
0226 C3 912 C RET
0227 913 C
0227 B8 0001 914 C MOV AX,l SET PRESENT ON EXIT
022A 56 915 C POP 8X RESTORE BX
0228 C3 91. C RET
022C 917 C CD_PRESENCE_ TST ENOP
918 C
919
920
G
G
; -MODULE- NAME--RO:CURSOR------ --------- -------- ------- -- --- ------ --------
921 G READ CURSOR POSITION [ADDRESS] (FROM CRTC) TO AX
922 C
923 G : REGISTER AX IS MODIFIED.

022C
924
925
G
C
~O-CURSOR--- ----;ROC-NEAR -- ---------- -------- ---- ------------------ ------
022C 52 92. G - PUSH OX ; SAVE REGS USED
0220 88 00 927 G MOV DX,AX
022F 80 DE 928 G MOV AL, C_CRSR_LOC_HGH
0231 H 929 G OUT DX,AL
0232 42 930 C ING OX
0233 EC 931 G IN AL,OX
932 G RETURN WITH CURSOR POS I N AX
933 G RESTORE REGS USED
0234 5A 934 G POP
0235 C3 9'5 C RET
0236 93. C RO_CURSOR ENDP
937 C
938
939
G
C
; -MODULE-N~M~--~~=~U~SO~ ------ -- ------- ------- ----- -------- --------------
940 C WR I TE CURSOR pas I T I ON [ADDRESS] (TO CRTC) 101 I TH CONTENTS OF AX
941 C
942 C ; ALL REGISTERS PRESERVED
94' C ~R=~U~S~R-------PR~C-NEAR-----------------------------------------------
0236 944 C
945 C SAVE REGS USED
0236 50 94. C PUSH AX
0237 52 947 C PUSH OX
0238 86 DO 948 C MOV DX,AX
023A B4 OE 949 G MOV AH, C CRSR LaC HGH CURSOR LOCATION HIGH INDEX
023C BO 7F 950 C MOV AL,07FH - - TEST VALUE
023E E8 0015 R 951 C CALL OUT_OX
952 C RETURN WITH CURSOR pas I N AX
953 G RESTORE REGS USED
0241 5A 954 C POP OX
0242 5B 955 C POP AX
0243 C3 95. C RET
0244 957 C WR_CURSOR ENOP
958 C
0244 959 G POST:
9.0
9.'
C
C
; --------------------------------------------------------
INITIALIZE AND START CRT CONTROLLER (6845)
9.2 G ON COLOR GRAPH I CS AND MONOCHROME CARDS
963 C TEST V IDEO READ/WR I TE STORAGE.
9.4 C OEseR I PT I ON
9.5 C RESET THE V IDEO ENABLE SI GNAl.
9 •• C SELECT ALPHANUMERIC MODE, 40 *
25, 8 & W.
9.7 C READ/WRITE DATA PATTERNS TO STG. GHECK STG
9.8 C ADDRESSABILJTY.
9.9 C . --------------------- - ----------------------------------
970 C ASSUME OS: ABSO, ES: ABSO
0244 [8 DC FE R 971 C CALL DOS
0247 F6 06 0487 R 02 972 C TEST INFO,2
024C 75 12 973 C JNZ COLOR_PRESENCE_ TST
024E B8 03B4 974 C MOV AX,03B4H
0251 E8 0205 R 975 C CALL CO PRESENCE TST
0254 30 0001 97. C CMP AX;1 -
0257 74 03 977 C JE CONT1
0259 E9 0317 R 978 C JMP P0014
025C 979 C CONTt:
02SC B4 30 980 C MOV AH,30H ; MONOCHROME CARD INSTALLED
025E EB 10 981 C JMP SHORT OVER
0260 982 C COLOR_PRESENCE_TST:
0260 88 0304 98' C MOV AX,03D4H
0263 E8 0205 R 984 C CALL CD_PRESENCE_ TST
0266 3D 0001 985 C CMP AX, 1
0269 74 03 98. C JE CONT2
026B E9 0317 R 987 C JMP POD14
026E 988 C CONT2 :
026E 84 20 989 C MOV AH,20H COLOR GRAPH I CS CARD INSTALLED
0270 990 C OVER:
0270 50 991 C PUSH AX RESAVE VALUE
0271 8S BODO 992 C MOV BX, OBOOOH BEG V I OEO RAM ADDR B/W CO
0274 8A 0368 99' C MOV OX,3B8H MODE CONTROL B/W
0277 89 1000 994 G MOV CX,4096 RAM BYTE CNT FOR B/W CO
027A BO 01 995 C MOV AL,l SET MODE FOR Bioi CARD
027C 60 FC 30 99. C CMP AH,30H B/W VIDEO CARD ATTACHED?
027F 74 08 997 C JE E9 YES - GO TEST V I DEO STG
0281 87 B8 99. C MOV BH,OB8H BEG VIDEO RAM AODR COLOR CD
0283 82 08 999 C MOV DL,OD8H MODE CONTROL COLOR
0285 85 40 1000 C MOV CH,40H RAM BYTE CNT FOR COLOR CO
0287 FE C8 1001 C DEC AL SET MODE TO 0 FOR COLOR CO
0289 1002 C E9: TEST_V I DEO_STG:
0289 EE 1003 C OUT DX,AL o I SABLE V IDEO FOR COLOR CD
1004 C
028A 8B 2E 0472 R 1005 C MOV BP, OS: RESET_FLAG POD INITIALIZED BY KBD RESET
1006 C
028E 81 FD 1234 1007 C CMP BP,1234H POD INITIATED BY KBD RESET?
0292 BE C3 1008 G MOV ES,BX POINT ES TO VIDEO RAM STC

August 2, 1984 IBM Enhanced Graphics Adapter 111

0294 74 07 1009 C JE El0 ; YES - SKIP VIDEO RAM TEST
0296 BE DB 1010 C MOV OS, BX ; POINT OS TO VIDEO RAM STG
lOll C ASSUME OS: NOTH lNG, ES: NOTH I NG
029B E8 020f R 1012 C CALL STGTST_CNT • GO TEST V IDEO R/W STG
029B 75 2E 1013 C JNE E17 ; R/W STG FA I LURE - BEEP SPK
1014 C
1015 C ~-------SETU;-;7~EO-OATA-ON-SCREEN-FOR-;7~EO-L7NE-TEST~----------
1016 C ; DESCRIPTION
1017 C ; ENABLE VIDEO SIGNAL AND SET MODE.
1018 C DISPLAY A HORIZONTAL BAR ON SCREEN.
1019 C ~~O~-------------------------------------------------------------
0290 1020 C
0290 58 1021 C POP AX GET VIDEO SENSE SWS (AH)
029E 50 1022 C PUSH AX SAVE IT
029f B8 7020 1023 C MOV AX,7020H WRT BLANKS IN REVERSE VIDEO
02A2 2B FF 1024 C SUB 01,01 SETUP STARTING LOC
02A4 B9 0028 1025 C MOV CX.40 NO. OF BLANKS TO DISPLAY
02A7 f3/ AB 1026 C REP STOSW WR I TE V IDEO STORAGE
1027
1028
C
C
; -------CRT-~NTERFACE-LiNES -TEST-------------------- -----
1029 C ; OESCRI PTION
1030 C ; SENSE ON/OFF TRANSITION OF THE VIDEO ENABLE

02A9 58
1031
1032
1033
C
C
C
;
;
AND HORIZONTAL SYNC LINES.
----------------------------------------------
POP AX
----------
GET VIDEO SENSE SW INFO
02AA 50 1034 C PUSH AX SAVE IT
02A8 80 FC 30 1035 C CMP AH,30H B/W CARD ATTACHED?
02AE BA 03BA 1036 C MOV OX,03BAH SETUP ADOR OF BW STATUS PORT
0281 74 02 1037 C JE E11 YES - GO TEST LJ /liES
02B3 B2 DA 1038 C MOV DL,ODAH COLOR CARD I S ATTACHED
0285 1039 C Ell: LlNE~TST:
0285 B4 08 1040 C MOV AH,8
0287 1041 C E12: ; OFLOOP~CNT:
02B7 2B C9 1042 C SUB CX,CX
02B9 1043 C £13:
02B9 EC 1044 C IN AL,OX READ CRT STATUS PORT
02BA 22 C4 1045 C ANO AL,AH CHECK V I OEO/HORZ LI NE
02BC 75 04 1046 C JNZ Et. ITS ON - CHECK I F IT GOES OFF
02BE E2 F9 1047 C LOOP E13 LOOP TILL ON OR TIMEOUT
02CO EB 09 1048 C JMP SHORT E17 GO PR I NT ERROR MSG
02C2 1049 C E14:
02C2 2B C9 1050 C SUB CX,CX
02Cl, 1051 C £15:
02C4 EC 1052 C IN AL,DX READ CRT STATUS PORT
02C5 22 C4 1053 C ANO AL,AH CHECK VIDEO/HORZ LI NE
02C7 74 OA 1054 C JZ E1. I TS ON - CHECK NEXT LI NE
02C9 E2 F9 1055 C LOOP Et5 LOOP If OFF TILL IT GOES ON
02CS 1056 C E17: CRT_ERR
02CB SA 0102 1057 C MOV OX,102H
02CE E8 06C8 R 105B C CALL ERR BEEP ; GO BEEP SPEAKER
0201 EB 06 1059 C JMP SHORT E18
0203 1060 C E16: NXT_LINE
0203 Bl 03 1061 C MOV CL,3 GET NEXT BIT TO CHECK
0205 02 EC 1062 C SHR AH,CL
0207 75 DE 1063 C JHZ E12 GO CHECK HORIZONTAL LINE
0209 1064 C £18: o I SPLAY_CURSOR:
0209 58 1065 C POP AX GET VIDEO SENSE SWS (AH)
02DA E8 3B 1066 C JMP SHORT P0014
1067
1068
1069
C
C
C
; --------------------------------------------------------- ---------------
THIS SUBROUTINE PERFORMS A READ/WRITE STORAGE TEST ON
1070 C A 16K BLOCK OF STORAGE.
1071 C ENTRY REQU I REMENTS:
1072 C ES == ADDRESS OF STORAGE SEGMENT BE I NG TESTED
1073 C OS == ADDRESS OF STORAGE SEGMENT BE I NG TESTED
1074 C WHEN ENTERING AT STGTST_CNT. CX MUST BE LOADED WITH
1075 C THE BYTE COUNT.
1076 C EXIT PARAMETERS:
1077 C ZERO FLAG = 0 I F STORAGE ERROR (DATA COMPARE OR PAR I TY CHECK.
1078 C AL == 0 DENOTES A PARITY CHECK. ELSE AL::XOR'ED BIT
1079 C PATTERN OF THE EXPECTED DATA PATTERN VS THE
1080 C ACTUAL DATA READ.
1081 C AX.BX.CX.DX,DI, AND SI ARE ALL DESTROYED.
1082 C ~TGTST--PROC----NEAR-----------------------------------------------------
020C 1083 C
020C B9 4000 1084 C MOV CX,4000H SETUP CNT TO TEST A 16K BLK
02DF 1085 C STGTST_CNT:
02DF FC 1086 C CLD SET DIR fLAG TO INCREMENT
02EO 88 09 1087 C MOV BX,CX SAVE CNT (4K fOR VIDEO OR 16K)
02E2 B8 AAAA 1088 C MOV AX,OAAAAH GET DATA PATTERN TO WRITE
02E5 BA FF55 1089 C MOV DX,OfF55H SETUP OTHER DATA PATTERNS TO USE
02E8 2B FF 1090 C SUB 01,01 01 = OFfSET 0 RELATIVE TO ES REG
02EA F3/ AA 1091 C REP STOSB WR I TE STORAGE LOCAT IONS
02EC 1092 C C3: STGOl
02EC 4F 1093 C OEC 01 PO I NT TO LAST BYTE JUST WR I TTEN
02EO FD 1094 C STO SET DIR FLAG TO GO BACKWARDS
02E£ 1095 C C4:
02££ BB F7 1096 C MOV SI,OI
02fO 88 CB 1097 C MOV CX,8X SETUP BYTE CNT
02F2 1098 C C5: I NNER TEST LOOP
02F2 AC 1099 C LODS8 READ OLD TEST BYTE [SI]+
02F3 32 C4 1100 C XOR AL,AH DATA READ AS EXPECTED ?
02F5 75 1E 1101 C JNE C7 NO - GO TO ERROR ROUTI NE
02F7 8A C2 1102 C MOV AL,OL GET NEXT DATA PATTERN TO WRITE
02F9 AA 1103 C STOSB WRITE INTO LOCATION JUST READ
02FA £2 f6 1104 C LOOP C5 OECREMENT COUNT AND LOOP CX
1105 C
02fC 22 E4 1106 C ANO AH,AH ENDING 0 PATTERN WRITTEN TO STG?
02FE 74 13 1107 C JZ C.X YES - RETURN TO CALLER WITH AL=O
0300 8A EO 1108 C MOV AH,AL SETUP NEW VALUE fOR COMPARE
0302 86 F2 1109 C XCHG DH,DL MOVE NEXT DATA PATTERN TO OL
0304
0306
0308
22
75
8A
£4
04
04
1"0
1111
1112
C
C
C
AND
JHZ
MOV
C.
AH,AH

DL,AH
READING ZERO PATTERN THIS PASS?
CONTI NUE TEST SEQUENCE TILL 0
ELSE SET 0 FOR END READ PATTERN
030A EB EO 1113 C JMP C3 AND MAKE fiNAL BACKWARDS PASS
030C 1114 C C6:
030C FC 1115 C CLD SET D I R FLAG TO GO FORWARO
0300
030E
0310
47
74 DE
4F
1116
1117
1118
C
C
C
INC
JZ
DEC
C,
01

01
SET POINTER TO BEG LOCATION
READ/WRlTE FORWARD IN STG
ADJ UST PO INTER
0311 E809 1119 C JMP C3 READ/WR I TE BACKWARD IN STG
0313 1120 C C6X:
0313 80 00 1121 C MOV AL,OOOH AL==O DATA COMPARE OK
0315 1122 C C7:
0315 FC 1123 C CLO SET DIRECTION FLAG BACK TO INC
0316 C3 1124 C RET
0317 1125 C STGTST ENDP
1126 C
1127 C
1128 C EGA CRT ATTACHMENT TEST
1129 C
1130 C 1. INIT CRT TO 40><25 - 8W ****SET TO MOOE****
1131 C 2. CHECK FOR VERTICAL AND VIDEO ENABLES, AND CHECK
1132 C TIMING OF SAME
1133 C 3. CHECK VERTICAL INTERRUPT
1134 C 4. CHECK RED, BLUE, GREEN, AND INTENSIFY DOTS

112 IBM Enhanced Graphics Adapter August 2, 1984

 1135 : 5. I NIT TO 40X25 - COLOR/MONO ****5ET TO MODE****
1136
1137
: -- ------------------------------------------------------
1138 ;----- NOMINAL TIME 15 B286H FOR ·60 HZ.
1139 ;----- NOMINAL TIME IS A2fEH fOR 50 HZ.
1140
= AOAC 1141 MAX_VERT_COLOR EQU OAOACH MAX T I ME fOR VERT/VERT
1142 (NOMINAL + 10%)
= C460 1143 M I N_VERT_COLOR EQU OC460H MIN TIME fOR VERT/VERT
1144 (NOMINAL - 10%)
= OOCS 1145 CENAB_PER_FRAME EQU 200 NUM Of ENA8LES PER FRAME
= S099 1146 MAX_VERT _MONO EQU 08D99H MAX T I ME FOR VERT/VERT
1147 (NOMINAL + 10%)
= 6862 1148 M I N_VERT_MONO EQU OB862H MIN TIME FOR VERT/VERT
1149 (NOMINAL - 10%)
= 015E 1150 EENAB_PER_FRAME EQU 350 ENHANCED ENABLES PER fRAME
= 015E 1151 MENA8_PER_FRAME EQU 350 NUM Of ENABLES PER fRAME
1152
= 0043 1153 EQU 043H 8253 T I MER CONTROL PORT
= 0040 1154 EQU 040H 8253 T I MER/CNTER 0 PORT
1155
0317 1156 POD14 PROC NEAR
0317 83 EC OA 1157 SUB SP,OAH RESERVE 5 WORDS ON STACK
031A 8B EC 1158 MOV BP,SP I NIT SCRATCH PAO POI NTER
1159
1160 ASSUME DS:ABSO, ES:ABSO
031C ES OCfE R 1161 CALL ODS
03H BO 30 1162 MOV AL, 0011 00008 SET T I MER 0 TO MODE 0
1163
0321 E6 43 1164 OUT TIM CTL.AL
0323 BO 00 "65 MOV AL,OOH
0325 E6 40 1166 OUT TlMERO,AL SEND fiRST BYTE TO T I MER
0327 f6 06 0487 R 02 1167 TEST INFO,2
032C
032E
74
E8
1f
016S R
1168 JZ
CALL
~~~~~_EGA_V SET UP I N MONOCHROME
1169
0331 C7 46 02 015E 1170 MOV WORO PTRIBP][2],MENAB_PER_fRAME NUM.OF FRAMES fOR MONO
0336 C7 46 04 S099 1171 MOV WORD PTRIBP][4J,MAX_VERT_MONO MAX T I ME fOR VERT/VERT
0336 c7 46 06 6862 1172 MOV WORD PTR[BP][6J,MIN_VERT_MONO MIN T I ME FOR VERT/VERT
0340 B2 B4 1173 MOV DL, CRTC_AOOR_B MONO CRTC REG
0342 B4 01 1174 MOV AH,C HRZ DSP HORIZ. TOTAL DIPLAY
0344 BO 27 '175 MOV AL,27H - TO 40 COL
0346 E8 0015 R 1176 CALL OUT OX
0349 62 6A 1177 MOV DL, INPUT STATUS B 'BA
0346 EB 2A 1178 JMP SHORT COMMON-
0340 1179 COLOR EGA V:
0340 E8 014S R 1180 - CALL ENV X SEl UP IN 40X25 COLOR
0350 E8 OE9A R 1181 CALL BRST_DET ENHANCED MODE
0353 73 11 1182 JNC COLOR V NO,40X25
0355 B2 04 1183 MOV OL, CRTC_ADOR BRST MODE ONLY!
0357 B4 01 1184 MOV AH, , HRZ DSP END
0359 BO 14 1185 MOV AL,20 MOD I FY FOR TEST ONLY
035B E8 0015 R 1186 CALL OUT OX
035E C7 46 02 015E 1187 MOV WORO PTR[BPJ[2J,EENAB_PERJRAME ; NUM. OF FRAMES FOR COLOR
0363 EB 06 90 1188 JMP BRST_COLOR_V
0366 1189 COLOR_V:
"90
0366 C7 46 02 00C8 1191 MOV WORD PTRI BP] [2 J. CENAB_PER_FRAME ; NUM. OF fRAMES fOR COLOR
036B 1192 BRST COLOR V:
036B C7 46 04 AOAC "93 - MOV WORD PTR[BP][4J,MAX_VERT_COLOR MAX TIME FOR VERT/VERT
0370 C7 46 06 C460 1194 MOV WORD PTR[BPJ[6].MIN_VERT_COLOR MIN T I ME FOR VERT /VERT
0375 B2 OA 1195 MOV DL, INPUT_STATUS SET ADDRESSING TO VIDEO
1196 ATTR STATUS
0377 1197 COMMON:
0377 B8 0500 1198 MOV AX,0500H ; SET TO VIDEO PAGE 0
037A
037C
CO 10
2B C9
1199
1200
INT
SUB
10"
CX,CX
1201
1202 ;----- LOOK FOR VERTICAL
1203
037E 1204 POD14_1 :
037E EC 1205 IN AL,OX GET STATUS
037F A8 08 1206 TEST AL, 0000 10008 VERT I CAL THERE YET?
0381 75 07 1207 JNE POD14_2 CONTINUE IF IT IS
0383 E2 f9 1208 LOOP POD14 1 KEEP LOOK I NG TILL COUNT
0385 B3 00 1209 MDV BL,OO- EXHAUSTED
0387 E9 0448 R 1210 JMP POD14_ERR NO VERTI CAL
1211
1212 ;----- GOT VERTICAL - START TIMER
1213
038A 1214 POD14_2:
038A 80 00 1215 MOV Al,O
03SC [6 40 1216 OUT TIMERO,AL SEND 2ND BYTE TO TIMER TO
1217 START IT
038E 2B DB 1218 SUB 6X, BX I NIT. ENABLE COUNTER
1219 ; ----- WA I T FOR VERT I CAL TO GO AWAY
0390 33 C9 1220 XOR CX,CX
0392 1221 POD14_25:
0392 EC 1222 IN AL,oX GET STATUS
0393 A8 08 1223 TEST AL,00001000B VERT I CAL ST 1LL THERE
0395 74 07 1224 JZ POD14_3 CONTINUE If IT'S GONE
0397 E2 F9 1225 LOOP POD14_25 KEEP LOOKING TILL COUNT
0399 83 01 1226 MOV BL,OlH EXHAUSTED
0398 E9 0448 R 1227 JMP POD14_ERR VERT I CAL STUCK ON
1228
1229 ;----- NOW START LOOKING FOR ENABLE TRANSITIONS
1230
039E 1231 POD14_3:
039E 2B C9 1232 SUB eX,ex
03AO 1233 POD14 4:
03AO EC 1234 - IN AL,DX GET STATUS
03Al A8 01 1235 TEST AL, 0000000 1B ENABLE ON YET?
03A3 74 15 1236 JE POD14 5 GOONIFITIS
03A5 A8 08 1237 T[ST AL, 0000 1OOOB VERT I CAL ON AGA I N?
03A7 75 23 1238 JNE POD14 75 CONTINUE IF IT IS
03A9 E2 F5 1239 LOOP POD14::::4 KEEP LOOK I NG I F NOT
03AB 83 02 1240 MOV BL,02H
03AD E9 0448 R 1241 JMP POD14_ERR ; ENABLE STUCK Off
03BO 1242 POD14_4A:
03BO B3 03 1243 MOV BL,03H
03B2 E9 0448 R 1244 JMP POD14_ERR ; VERT I CAL STUCK ON
03B5 1245 POD14_4B:
03B5 B3 04 1246 MOY BL,04H
03B7 E9 0448 R 1247 JMP POo14_ERR ; ENABLE STUCK ON
1248
1249 ;----- MAKE SURE VERTICAL WENT Off WITH ENABLE GOING ON
1250
03BA 1251 POD14_5:
03BA A8 08 1252 TEST AL, 00001 OOOB VERTI CAL Off?
03BC 75 F2 1253 JNZ P0014_4A GO ON If IT IS
1254 ; ----- NOW WAI T fOR ENABLE TO GO Off (ERROR I F NOT)
03BE 1255 POD14_6:
03BE EC 1256 IN AL,DX GET STATUS
03BF A8 01 1257 TEST AL,OOOOOOOlB ENABLE OFf YET?
03Cl E1 FB 1258 LOOPE POD14_6 KEEP LOOKING If NOT
03C3 E3 FO 1259 JCXZ POD14_4B , YET LOW
1260 ;----- ENABLE HAS TOGGLED, BUMP COUNTER AND TEST FOR NEXT VERTICAL

August 2, 1984 IBM Enhanced Graphics Adapter 113

03C5 1261 C POD14_7:
03C5 4' 1262 C INC BX BUMP ENABLE COUNTER
03C6 74 04 1263 C JZ POO14_75 I F COUNTER WRAPS,
1264 C SOMETH I NG I S WRONG
03C8 A8 08 1265 C TEST AL, 0000 1OOOB DID ENABLE GO LOW
1266 C BECAUSE OF VERT I CAL
03CA 74 02 1267 C JZ POD14_3 IF NOT, LOOK FOR ANOTHER
1268 C ENABLE TOGGLE
1269 C ; ----- HAVE HAD COMPLETE VERT I CAL-VERT I CAL CYCLE: NOW TEST RESULTS
03CC 1270 C P0014_15:
03CC eo 00 1271 C MOV AL,OO LATCH T I MERO
03CE E6 43 1212 C OUT TIM_CTl,AL
0300 3B 5E 02 1273 C CMP ex, WORD PTR! BP] (2] NUMBER Of ENABLES BETWEEN
1274 C VERTICALS O.K.?
0303 74 04 1275 c JE P0014 8
0305 B3 OS, 1276 C MOV BL,05H
0307 EB 6F 1277 C JMP SHORT POO14_ERR
0309 1278 C POO14_8:
0309 E4 40 1279 C IN AL, TIMERO ; GET TI MEA VALUE LOW
030B 8A EO 1280 C MOV AH,AL ; SAVE IT
0300 90 1281 C NOP
030E E4 40 1282 C IN AL, TlMERO ; GET TIMER HIGH
03EO 86 EO 1283 C XCHG AH,AL
03E2 90 1284 C NOP
03E3 90 1285 C NOP
03E4 3B 46 04 1286 C CMP AX, WORD PTAI SP][ 4] ; MAXIMUM VERTICAL TIMING
03£7 70 04 1287 C JGE POD14_9
03E9 B3 06 1288 C MOV BL,06H
03EB EB 5B 1289 C JMP SHORT POO14_ERR
03EO 1290 C POD14_9:
03Eo 3B 46 06 1291 C CMP AX, WORD PTR{ SP] (6] ; MINIMUM VERTICAL TIMING
03FO 7E 04 1292 C JLE P0014 10
03F2 B3 07 1293 C MOV SL,oiFi
03F4 EB 52 1294 C JMP SHORT POD14_ERR
1295 C
1296 C ;----- SEE I F RED, GREEN, BLUE AHO I NT ENS I FY DOTS WORK
1297 C
1298 C ;----- fiRST, SET A LINE OF REVERSE VIDEO, I NTENS I F I ED BLANKS INTO BUFFER
03F6 1299 C POO14_10:
03F6 B8 090S 1300 C MOV AX,090SH ; WRITE CHARS, BLANKS
03F9 BS OOOF 1301 C MOV BX,OOOFH PAGE 0, REVERSE VIDEO,
1302 C ; HIGH INTENSITY
03FC S9 0050 1303 C MOV CX,80 ; 80 CHARACTERS
03Ff CD 10 1304 C INT 10H
0401 EC 1305 C IN AL,oX
0402 52 1306 C PUSH OX ; SAVE I NPUT STATUS
0403 B2 CO 1307 C MOV OL,ATTR_WRITE ; ATTRIBUTE AOoRESSS
0405 B4 OF 1308 C MOV AH,OFH ; PALETTE REG' F'
0407 BO 3f 1309 C MOV AL,03FH ; TEST VALUE
0409 E8 0015 R 1310 C CALL OUT ox ; V IDEO STATUS MUX
040C B8 OOOF 1311 C MOV AX,OFH ; START WITH BLUE DOTS
040F 5A 1312 C POP OX
0410 1313 C POO14_13:
0410 50 1314 C PUSH AX ; SAVE
0411 52 1315 C PUSH OX ; SAVE I NPUT STATUS
0412 B2 CO 1316 C MOV OL, ATTR_WR I TE ; ATTA I BUTE AOoRESSS
0414 B4 32 1317 C MOV AH,32H ; COLOR PLANE ENABLE
0416 E8 0015 R 1318 C CALL OUT_OX ; VIDEO STATUS MUX
0419 5A 1319 C POP OX ; RECOVER I NPUT STATUS
041A 58 1320 C POP AX
0418 2B C9 1321 C SUB CX,CX
1322 C ; ----- SEE I F DOT COMES ON
0410 1323 C POO14_14:
01110 EC 1324 C IN AL,OX ; GET STATUS
041E A8 30 1325 C TEST AL, 0011 00008 ; DOT THERE?
0420 75 09 1326 C JNZ P0014_15 LOOK FOR DOT TO TURN OFF
0422 E2 F9 1327 C lOOP P0014 14 ; CONT I NUE TEST FOR DOT ON
0424 B3 10 1328 C MOV BL, lOti
0426 OA DC 1329 C OR BL,AH OR I N DOT BE I NG TESTED
0428 EB 1E 90 1330 C JMP POo14_ERR DOT NOT COM 1NG ON
1331 C ; ----- SEE I F DOT GOES OFF
0428 1332 C P0014_15:
042B 2B C9 1333 C SUB CX,CX
0420 1334 C POO14_16:
0420 EC 1335 C IN AL,oX ; GET STATUS
042E A8 30 1336 C TEST Al,00110000B IS DOT STILL ON?
0430 74 08 1337 C JE P0014_17 ; GO ON IF DOT OFF
0432 E2 F9 1338 C LOOP POD14_16 ; ELSE, KEEP WAITING FOR
1339 C ; DOT TO GO OFF
0434 B3 20 1340 C MOV BL,20H
0436 OA DC 1341 C OR Sl,AH ; OR I N DOT BE I NG TESTED
0438 EB OE 1342 C JMP SHORT POO14_ERR
1343 C
1344 C ; ----- ADJUST TO PO I NT TO NEXT DOT
1345 C
043A 1346 C POO14_17:
043A FE C4 1347 C INC AH
043C 80 FC 30 1348 C CMP AH,030H ; ALL 3 DOTS DONE?
043F 74 25 1349 C JE P0014 18 ; GO END
0441 80 CC OF 1350 C OR AH,OFH ; MAKE OF, If,2F
0444 8A C4 1351 C MOV AL,AH
0446 EB C8 1352 C JMP POO14_13 ; GO LOOK FOR ANOTHER DOT
0448 1353 C P0014_ERR:
0448 B9 0006 1354 C MOV CX,6
044B BA 0103 1355 C MOV DX,0103H ; ONE LONG AND THREE SHORT
044E E8 06C8 R 1356 C CALL ERR_BEEP
0451 83 C4 OA 1357 C ADD SP,OAH ; BALANCE STACK
0454 SO 36 1358 C MOV AL,00110110B ; RE-INIT TIMER 0
0456 E6 43 1359 C OUT TIM_CTL,AL
0458 2A CO 1360 C SUB AL,AL
045A E6 40 1361 C OUT TIMERO,AL
045C 90 1362 C NOP
0450 90 1363 C NOP
045E £6 40 1364 C OUT TIMERO,AL
0460 Bo 0001 1365 C MOV BP,l
0463 E9 0091 R 1366 C JMP SKI P
1367 C ASSUME OS:ABSO
0466 1368 C POO14_18:
0466 E8 OCFE R 1369 C CALL DDS
0469 88 0500 1370 C MOV AX,0500H SET TO VIDEO PAGE 0
046C CD 10 1371 C INT 10H
046E 80 36 1372 C MOV Al,00110110B RE-INIT TIMER 0
0470 E6 43 1373 C OUT TIM_CTL,AL
0472 2A CO 1374 C SUB AL,AL
0474 E6 40 1375 C OUT TIMERO,AL
0476 90 1376 C NOP
0477 90 1377 C NOP
0478 E6 40 1378 C OUT T1MERO,Al
047A 83 C4 OA 1379 C ADD SP,OAH ; REMOVE SCRATCH PAD
0470 SO 0000 1380 C MOV BP,O ; MAKE SP NON ZERO
0480 1381 C POO14 ENOP
1382 C
1383 C ; -~~-- TEST STORAGE
1384 C
0480 1385 C MEM_TEST:
0480 1E 1386 C PUSH OS

114 IBM Enhanced Graphics Adapter August 2, 1984

0481 E8 OCfE R 1387 CAll DDS
1388 ASSUME OS: ABSO
0484 f6 06 0487 R 02 1389 TEST INfO,2
0489 74 12 1390 JZ O_COlOR_M
048B 80 DE 0410 R 30 1391 OR EQUIP~LOW,030H
0490 88 OOOf 1392 MOV AX,OfH
0493 80 DE 0487 R 60 1393 OR INfO,060H
0498 88 OOOf 1394 MOV AX,OfH
049B fB 00 1395 JMP SHORT O~OUT~M
0490 1396 O~COlOR_M:
0490 80 26 0410 R Cf 1397 AND £QUIP_lOW,OCFH
04A2 80 OE 0410 R 20 1398 OR EQUIP_lOW,020H
04A7 B8 OOOE 1399 MOV AX,OEH I NTERNAL COLOR MODE
04AA 140O D_OUT_M: TEST I N COLOR
04AA CO 10 1401 INT 10M
04AC 83 EC 06 1402 SUB SP,6 RESERVE 3 WORDS ON STACK
04AF 88 EC 1403 MOV BP, SP SET BP
04Bl BB ACOO 1404 MOV AX,OAOOOH PUT BUFFER ADDRESS IN AX
1405 ASSUME OS: NOTH lNG, £S: NOTH I NG
04B4 8E 08 1406 MOV OS,AX SET UP SEG REGS TO POI NT
04B6 8E CO 1407 MOV ES,AX TO BUFFER AREA
04B8 C7 46 02 0000 1408 MOV WORD PTR[BP][2],0 INITIALIZE
04BO C7 46 04 0000 1409 MOV WORD PTR[BP][4],0 INITIALIZE
04C2 B6 03 1410 MOV DH,3
04C4 B2 C4 1411 MOV Dl, SEQ_ADOR
04C6 B8 0201 1412 MOV AX,0201H
04C9 E8 0015 R 1413 CAll OUT_OX
04CC B2 CE 1414 MOV Ol, GRAPH_AOOR ADDRESS READ MAP SELECT
04CE B8 0400 1415 MOV AX,0400H
0401 E8 0015 R 1416 CAll OUT_OX
0404 52 1417 PUSH OX
0405 B2 OA 1418 MOV Ol,ATTR_REAO SET UP ATTRIBUTE
0407 EC 1419 IN Al,OX
0408 82 CO 1420 MOV Ol,ATTR_WRlTE ATTRIBUTE WRITE ADDRESS
040A B8 3200 1421 MOV AX, 3200H
0400 E8 0015 R 1422 CALL OUT_OX
04EO E8 068F R 1423 CAll HOW BIG GO fINO AMOUNT OF MEMORY
04E3 80 FC 00 1424 CMP AH,O
04E6 74 03 1425 JZ AA1
04E8 E9 05CD R 1426 JMP EGA_MEM_ERROR
04EB 1427 AAl:
04EB E8 0509 R 1428 CAll MEMORY_OK GO TEST IT
04EE 80 FC 00 1429 • CMP AH,O
04Fl 74 03 1430 JZ AA2
04F3 E9 05CO R 1431 JMP EGA_MEM_ERROR
04F6 1432 AA2:
04F6 5A 1433 POP OX
OitF7 B2 C4 1434 MOV DL, SEQ_AOOR
04F9 68 0202 1435 MOV AX,0202H
04fC E8 0015 R 1436 CALL OUT OX
04ff 62 CE 1437 MOV Ol, GRAPH_AOoR ADDRESS OF READ MAP
0501 B8 0401 1438 MOV AX,0401H
0504 E8 0015 R 1439 CAll OUT_OX
0507 52 1440 PUSH OX
OS08 B2 DA 1441 MOV Ol,ATTR_READ SET UP ATTRIBUTE
050A EC 1442 IN Al,OX
050B B2 CO 1443 MOV Dl, ATTR_WR I TE ATTRIBUTE WRITE AOORESS
0500 B8 3200 1444 MOV AX, 3200H
0510 E8 0015 R 1445 CAll OUT_OX
0513 C7 46 04 0000 1446 MOV WORD PTR [BPj[4],0 INITIALIZE
0518 E8 068F R 1447 CAll HOW_BIG GO F I NO AMOUNT Of MEMORY
051B 80 FC 00 1448 CMP AH,O
051£ 74 03 1449 JZ AA3
0520 E9 OSCD R 1450 JMP EGA_MEM_ERROR
0523 1451 AA3:
0523 EB 0509 R 1452 CALL MEMORY_OK ; GO TEST IT
0526 80 FC 00 1453 CMP AH,O
0529 74 03 1454 JZ AA"
052B E9 05CD R 1455 JMP EGA_MEM_ERROR
052E 1456 AA4:
052E 5A 1457 POP OX
052F B2 C4 1458 MOV DL, SEQ....ADOR
0531 B8 0204 1459 MOV AX,0204H
0534 E8 0015 R 1460 CALL OUT_OX
0537 52 1461 PUSH OX
0538 B2 CE 1462 MOV DL, GRAPH_ADoR ADDRESS OF READ MAP
053A B8 0402 1463 MOV AX,0402H
0530 E8 0015 R 1464 CALL OUT_OX
0540 82 DA 1465 MOV ol, ATTR_READ SET UP ATTRIBUTE
0542 EC 1466 IN Al,DX
0543 82 CO 1467 MOV ol, ATTR_WR I TE ATTRIBUTE WRITE ADORESS
0545 B8 3200 1468 MOV AX, 3200H
0548 EB 0015 R 1469 CALL OUT OX
054B C7 46 04 0000 1470 MOV WORD PTR[BP1I4],0 INITIALIZE
0550 E8 068F R 1471 CALL HOW_BIG GO F I NO AMOUNT Of MEMORY
0553 80 FC 00 1472 CMP AH,O
0556 74 03 1473 JZ AA5
0558 EB 73 90 1474 JMP EGA_MEM_ERROR
055B 1475 AA5:
0558 E8 0509 R 1476 CAll MEMORY_OK GO TEST IT
055E 80 FC 00 1477 CMP AH,O
0561 74 03 1478 JZ AA6
0563 EB 68 90 1479 JMP EGA_MEM_ERROR
0566 1480 AA6:
0566 5A 1481 POP OX
0567 82 C4 1482 MDV Dl, SE'LADDR
0569 68 0208 1483 MOV AX,0208H
056C E8 0015 R 1484 CAll OUT_OX
056f 82 CE 1485 MOV Dl, GRAPH_AODR ; ADDRESS Of READ MAP
0571 B8 0403 1486 MOV AX,0403H
0574 E8 0015 R 1487 CALL OUT_OX
0577 52 1488 PUSH OX
0578 B2 DA 1489 MOV Ol,ATTR_READ SET UP ATTRIBUTE
057A EC 1490 IN Al,oX
057B 82 CO 1491 MOV DL,ATTR~WRJTE ATTRIBUTE WRITE ADDRESS
0570 B8 3200 1492 MOV AX,3200H
0580 E8 0015 R 1493 CAll OUT OX
0583 C7 46 04 0000 1494 MOV WORD PTR[ SP][ 4], 0 INITIALIZE
0588 E8 068F R 1495 CALL HOW BIG GO f r NO AMOUNT Of MEMORY
058B 80 Fe 00 1496 CMP AH,O
058E 75 3D 1497 JNZ EGA~MEM_ERROR
0590 E8 0509 R 1498 CAll MEMORY_OK GO TEST IT
0593 80 FC 00 1499 CMP AH,O
0596 75 35 1500 JNZ EGA_MEM_ERROR
0598 55 1501 PUSH BP SAVE SCRATCH PAD POINTER
0599 BO 0000 1502 MOV BP,O RESET BP FOR XT
059C 1503 EGA_MEM_EX IT:
059C 5E 1504 POP 51 RESTORE
0590 5A 1505 POP OX
059E E8 OCFE R 1506 CALL DDS SET DATA SEGMENT
1507 ASSUME oS:ABSO
05Al 36: 88 SC 02 1508 MOV BX,WORD PTR SS:[SI][2) GET EGA MEMORY SIZE
05A5 B1 06 1509 MOV Cl,06H DIVIDE BY 64 TO GET
05A7 03 EB 1510 SHR BX,Cl NUMBER OF 64KB BLOCKS
05A9 4B 1511 DEC BX
05AA B1 05 1512 MOV Cl,05H

August 2, 1984 IBM Enhanced Graphics Adapter 115

05AC D3 E3 1513 c SHL BX,CL
05A£ 80 £3 60 1514 c AND BL,01'00000B ISOLATE BITS SAND 6
1S15 c
05Bl 80 26 04B7 R 9F 1516 c AND INFO,100111'1B
1S17 c
05B6 08 1 £ 0487 R 1518 c OR I NFO,BL
1S19 c
05BA 80 DE 0487 R 04 1520 C OR INFO,00000100B ; 04H SET 3XX ACT I VE
05BF 8A 1 E 0488 R 1521 C MOV BL,INFO_3
05C3 £8 00F3 R 1522 C CALL MK ENV
05C6 83 C4 06 1523 C ADD SP-:-6 ; RESTORE STACK
05C9 lF 1524 C POP OS
05CA £9 0091 R 1525 C JMP SKI P ; GO TO END
05CO 1526 C EGA_MEM_ERROR:
05CO BA 0103 1527 C MOV DX,0103H ; ONE LONG AND THREE SHORT
05DO £8 06C8 R 1528 C CALL ERR BEEP
0503 55 1529 C PUSH BP - ; SAVE SCRATCH PAD POINTER
0504 BO 0001 1530 C MOV BP,l ; I NO I CA TE ERROR FOR XT
05D7 £B C3 1531 C JMP EGA_MEM_EXIT
1532 C
1533 C ;----- THIS ROUTINE FINDS AMOUNT OF MEMORY GOOD
1534 C
0509 1535 C MEMORY OK PROC NEAR
0509 BB AOOO 1536 C - MOV BX,OAOOOH SET PTR. TO BUFFER SEG
050C 8E DB 1537 C MOV DS,BX SET SEG. REG.
050E 8E C3 1538 C MOV ES,BX
05£0 8B 46 04 1539 C MOV AX,WORD PTR[BP)[4J ; SET COUNT FOR 32K WORDS
05E3 8A E8 1540 C MOV CH,AL ; SET AMOUNT OF 8UFFER
05£5 2A C9 1541 C SUB CL,CL , TO BE TESTED
05E7 01 E1 1542 C SHL CX,' ; MULTIPLY BY TWO
05E9 E8 05FB R 1543 C CALL POOSTG
OSEC 80 FC 00 1544 C CMP AH,O ; TEST FOR ERROR
OSEF 7S 09 1545 C JNZ MEMORY_OK_ERR ; IF ERROR GO PRINT IT
OSFl 1546 C MEMORY OK EX:
OSFl 88 46 04 1547 C - MOV AX,WORD PTR[BP1I4) ; AMOUNT OF MEMORY FOUND
OSF4 01 46 02 1548 C ADO WORD PTRIBP)[2I,AX ; AMOUNT OF MEMORY GOOD
OSF7 B8 0000 1549 C MOV AX,O
05FA 1550 C MEMORY OK ERR:
OSFA C3 1551 C - RET
OSFB 1552 C MEMORY_OK ENoP
1553 C
1554
1555
C
C
; ----------------------------------------------------------------
TH I S ROUTI NE PERfORMS A READ/WR I TE TEST ON A BLOCK OF STORAGE :
1556 C (MAX. SIZE'" 32KW). IF "WARM START", fiLL BLOCI< WITH 0000 AND:
1557 C RETURN. :
1558 C ON ENTRY:
1559 C ES = ADDRESS OF STORAGE TO BE TESTED
1560 C OS = ADDRESS OF STORAGE TO BE TESTED
1561 C CX = WORD COUNT Of STORAGE BLOCK TO BE TESTED
1562 C (MAX. '" BOOOH (32K WORDS))
1S63 C ON EXIT:
1564 C , ZERO FLAG'" OFF I f STORAGE ERROR
1565 C ; AX,BX,CX,DX,OI,SI ARE ALL DESTROYED.
1566 C ~ODS;:G--PROC----NEAR---------------------------------------------
OSFB 1567 C
OSFB S5 1568 C PUSH BP
05FC FC 1569 C CLO SET 0 I R TO INCREMENT
OSFD 26 FF 1570 C SUB 01,01 SET 01=0000 REL TO START
1571 C OF SEGMENT
05FF 26 CO 1572 C SUB AX,AX INITIAL DATA PATTERN FOR
1573 C OO-FF TEST
0601 E8 OCFE R 1574 C CALL DOS
1575 C ASSUME DS:ABSO
0604 86 1 E 0472 R 1576 C MOV BX, OS: RESET_FLAG ; WARM START?
0608 81 F6 1234 1577 C CMP BX,1234H
060C 8C C2 1578 C MOV OX,ES
060E 8E OA 1579 C MOV OS,OX RESTORE OS
0610 74 62 1580 C JE POOSTG_5 GO 00 FILL WITH 0000
1581 C I f WARM START
0612 81 FB 4321 1582 C CMP BX,4321H OCP WARM START?
0616 74 5e 1583 C JE PODSTG_5 00 fiLL IF SO
0618 1584 C PODSTG_' :
0618 88 05 1585 C MOV [01 J,AL ; WRITE TEST DATA
061A 8A 05 1586 C MOV AL,IOI} ; GET IT BACK
061C 32 C4 1587 C XOR AL,AH COMPARE TO EXPECTED
061E 7540 1588 C JNZ PODSTG ERRO ERROR EXIT If MISCOMPARE
0620 FE C4 1589 C INC AH - FORM NEW DATA PATTERN
0622 8A C4 1590 C MOV AL,AH
0624 7S F2 1591 C JNZ POOSTG_1 LOOP TILL ALL 256 DATA
1592 C PATTERNS DONE
0626 8B E9 1593 C MOV BP,CX SAVE WORD COUNT
0628 B8 AA55 1594 C MOV AX,OAA55H LOAD DATA PATTERN
0626 88 08 1595 C MOV ax,AX
0620 BA 55AA 1596 C MOV DX,055AAH LOAD OTHER DATA PATTERN
0630 F31 AS 1597 C REP STOSW FILL WORDS FROM LOW TO
1598 C HIGH WITH AAAA
0632 4F 1599 C DEC 01 PO I NT TO LAST WORD
0633 4F 1600 C DEC 01 WRITTEN
0634 FD 1601 C STO SET 0 I R FLAG TO GO DOWN
0635 86 F7 1602 C MOV SI,OI SET INDEX REGS. EQUAL
0637 8B CD 1603 C MOV CX,SP RECOVER WORD COUNT
0639 1604 C POOSTG_2: GO fROM HIGH TO LOW
0639 AD 1605 C LOOSW GET WORD FROM MEMORY
063A 33 C3 1606 C XOR AX,BX EQUAL WHAT S/8 THERE?
063C 75 22 1607 C JNZ PODSTG_ERRO GO ERROR EXIT I F NOT
063£ 86 C2 1608 C MOV AX, OX GET 55 DATA PATTERN AND
0640 A6 1609 C STOSW STORE IN LOC JUST READ
0641 E2 F6 1610 C LOOP POOSTG_2 LOOP TI LL ALL BYTES DONE
0643 8B CD 1611 C MOV CX,BP RECOVER WORD COUNT
0645 FC 1612 C CLD BACK TO INCREMENT
0646 46 1613 C INC $I ADJUST PTRS
0647 46 1614 C INC $I
0648 8B F£ 1615 C MOV OI,SI
064A 1616 C PODSTG 3: LOW TO HIGH DO I NG WORDS
064A AD 1617 C - LODSW GET A WORD
0646 33 C2 1618 C XOR AX,OX SHOULD COMPARE TO OX
0640 75 11 1619 C JNZ PODSTG_ERRO GO ERROR I F NOT
064F A6 1620 C STOSW WR I TE 0000 BACK TO LOC
1621 C JUST READ
0650 E2 F8 1622 C LOOP LOOP TILL DONE
1623 C
0652 FO 1624 C STD BACK TO DECREMENT
0653 4E 1625 C DEC $I ADJUST POINTER DOWN TO
1626 C LAST WORD WR I TTEN
0654 4E 1627 C DEC $I
0655 8B CD 1628 C MOV eX,BP ; GET WORD COUNT
0657 1629 C PODSTG_4:
0657 AD 1630 C LODSW , GET WORD
0658 06 CO 1631 C OR IV<,IV< ; '" TO 0000
065A 75 04 1632 C JNZ PODSTG ERRO ERROR I F NOT
065C E2 F9 1633 C LOOP PODSTG-4 LOOP TILL DONE
065E EB 11 1634 C JMP SHORT PODSTG_ERR2
0660 1635 C PODSTG_ERRO:
0660 8B C8 1636 C HOV ex, AX SAVE BITS I N ERROR
0662 32 E4 1637 C 'OR AH,AH
0664 OA ED 1638 C OR CH,CH HIGH BYTE ERROR?

116 IBM Enhanced Graphics Adapter August 2, 1984

0666 74 02 1639 JZ POOSTG_ERR1
0666 B4 01 1640 MOV AH,l SET HIGH BYTE ERROR
066A 1641 POOSTG_ERR1 :
066A OA C9 1642 OR CL,CL LOW BYTE ERROR?
066C 74 03 1643 JZ POOSTG_ERR2
066£ 60 C4 02 1644 ADD AH,2
0671 1645 POOSTG_ERR2:
0671 50 1646 POP BP
0672 FC 1647 CLD SET 0 I R FLAG BACK TO INC
0673 C3 1648 RET RETURN TO CALLER
0674 1649 POOSTG_5: SIMPLE FILL WITH 0000 ON
1650 WARM-START
0674 50 1651 PUSH AX SAVE
0675 52 1652 PUSH OX SAVE VALUE
0676 86 03 1653 MOV OH,3
0678 82 C4 1654 MOV OL,SEQ_AOOR SEQ_AOOR REG I STER
067A 88 020F 1655 MOV AX,020FH
0670 £8 0015 R 1656 CALL OUT_OX DO IT
0680 5A 1657 POP OX RESTORE
0681 58 1656 POP AX RESTORE
0682 F3/ A8 1659 REP STOSW
0684 £8 OCFE R 1660 CALL ODS
1661 ASSUME OS:ABSO
0687 89 1 E 0472 R 1662 MOV as: RESET_FLAG, BX
068B 8£ OA 1663 MOV as, OX ; RESTORE OS
0680 EB E2 1664 JMP POOSTG_ERR2 ; AND EXIT
068F 1665 POOSTG ENOP
1666
1667 ;----- DETERMINE SIZE OF BUffER
1668
068F 1669 HOW_BIG PROC NEAR
068F 8C OA 1670 MOV OX,OS SET PNTR TO BUffER LOC
0691 2B DB 1671 SUB BX,BX BAS I C COUNT Of OaK
0693 1672 FILL_LOOP:
0693 8E C2 1673 MOV ES,OX SET SEG. REG
0695 2B FF 1674 SUB 01,01
0697 B8 AA55 1675 MOV AX,OM55H TEST PATTERN
069A 8B C8 1676 MOV CX,AX
069C 26: 89 05 1677 MOV ES: [01 LAX SEND TO MEMORY
069F BO OF 1676 MOV AL,OfH PUT SOMETH I NG IN AL
06A1 26: 8B 05 1679 MOV AX,ES:[DI] GET PATTERN FROM MEMORY
06A4 33 C1 1660 XOR AX,ex COMPARE PATTERNS
06A6 75 14 1681 JHZ HOW_B I G_ENO GO END t f NO COMPARE
06A8 B9 2000 1682 MOV CX,2000H SET COUNT fOR 8K WORDS
OMB F3/ AB 1563 REP STOSW FILL 8K WORDS
06A0 81 C2 0400 1684 ADO OX,0400H POINT TO NEXT 16K BLOCK
06Bl 83 C3 10 1685 ADD BX,16 BUMP COUNT BY 161<B
06B4 80 FE BO 1686 CMP OH,DBOH
06B7 75 OA 1687 JNZ fiLL_LOOP AREA YET ? (BOOOOH)
06B9 EB 01 90 1688 JMP HOW_BIG_END
06BC 1689 HOW_BIG_END:
06BC 80 FE AO 1690 CMP OH,OAOH 1ST 16KB OK
06BF 74 06 1691 JZ HB_ERROR_EX I T
06C1 1692 RESUME:
06C1 01 5E 04 1693 ADD WORD PTR[ BP] [4], BX SAVE BUFFER FOUND
06C4 B8 0000 1694 MOV AX,O
06C7 1695 HB_ERROR_EX I T:
06C7 C3 1696 RET
06C8 1697 HOW_B I G ENOP
1698
1699
1700 ~ sUBRouTiNES -FOR-po~ER-oN-~i;~NosT i cs--~
1701
1702 ;;~~~- ;;;~~~~;~-~~~~-~;;~;- ;~;-~;~~- ;;~;-(;-;;~)-~~~-;~;-;;-------
1703 ;MORE SHORT TONES (1 SEC) TO INDICATE A fAILURE ON THE PLANAR
1704 ; BOARD ,A BAD RAM MODULE, OR A PROBLEM WITH THE CRT.
1705 ; ENTRY REQU I REMENTS:
1706 ; DH=NUMBER Of LONG TONES TO BEEP
1707 DL=NUMBER OF SHORT TONES TO BEEP.
1706 ~RR:BEEP---PROC----NE;R-------------------------------------------
06C8 1709
06C6 9C 1710 PUSHf SAVE FLAGS
06C9 FA 1711 CLI DISABLE SYSTEM INTS
06CA 1£ 1712 PUSH OS
06CB E8 OC FE R 1713 CALL ODS
1714 ASSUME OS: ABSO
06CE OA F6 1715 OR DH, DH ANY LONG TONES TO BEEP
0600 74 DB 1716 JZ G3 NO, DO THE SHORT ONES
0602 1717 G1 : LONG BEEP
0602 B3 06 1718 MOV BL,6 COUNTER FOR BEEPS
0604 £8 0020 R 1719 CALL BEEP DO THE BEEP
0607 1720 G2:
0607 £2 FE 1721 LOOP G2 DELAY BETWEEN BEEPS
0609 FE CE 1722 DEC DH ANY MORE TO DO
060B 75 F5 1723 JNZ G1 DO IT
0600 1724 G3:
0600 B3 01 1725 MOV BL,l COUNTER FOR A SHORT BEEP
060F £6 0020 R 1726 CALL BEEP 00 IT
06E2 1727 G4:
06E2 £2 FE 1728 LOOP G4 DELAY BETWEEN BEEPS
06E4 F£ CA 1729 DEC DL DONE WITH SHORT BEEPS
06E6 75 F5 1730 JNZ G3 00 MORE
06E8 1731 G5:
06E8 £2 FE 1732 LOOP G5 DELAY BEfORE RETURN
06EA 1733 G6:
06EA E2 F£ 1734 LOOP G6
06EC lF 1735 POP OS RESTORE CONTENTS OF OS
06ED 90 1736 POPF RESTORE FLAGS
06E£ C3 1737 RET
06EF 1736 ERR_BEEP ENOP
1739
1740 SUBTTL
1741
1742
06EF 1743 T2 LABEL WORD
06EF OEB3 R 1744 OW OffSET AHO MODE SET
06f1 10EF R 1745 OW OffSET AH1 SET CURSOR TYPE
06f3 1157 R 1746 OW OffSET AH2 SET CURSOR POS I T I ON
06F5 1186 R 1747 OW OffSET AH3 READ CURSOR POS I T I ON
06f7 1190 R 1748 OW OffSET AH4 READ Ll GHT PEN POS I T I ON
06F9 12A4 R 1749 OW OffSET AH5 ACT I VE 0 I SPLAY PAGE
06FB 150E R 1750 OW OffSET AH6 SCROLL DOWN
06FO 15BO R 1751 ow OffSET AH7 SCROLL UP
06Ff 1702 R 1752 ow OffSET AH8 READ CHAR/ATTR I BUTE
0701 1899 R 1753 OW OffSET AH9 WRITE CHAR/ATTRIBUTE
0703 1800 R 1754 OW OffSET AHA WR I TE CHARACTER ONLY
0705 1A75 R 1755 OW OFFSET AHB SET COLOR PALETTE
0707 lBCB R 1756 OW OFFSET AHC WRITE DOT
0709 lC9F R 1757 OW OFFSET AHO READ DOT
070B 1001 R 1756 OW OFFSET AHE WRITE TTY
0700 1085 R 1759 OW OFFSET AHF CURRENT VIDEO STATE
070f 10C5 R 1760 OW OFFSET AH10 SET PALETTE REGl STERS
0711 1F98 R 1761 OW OFFSET AH11 CHAR GENERATOR ROUT 1 NE
0713 20BF R 1762 OW OFFSET AH12 ALTERNATE SELECT
0715 2118 R 1763 OW OFFSET AH13 WR ITE STR I NG
== 0028 1764 T2L EQU $-T2

August 2, 1984 IBM Enhanced Graphics Adapter 117

 1765
1766 c INCLUDE VPARMS. INC
1767 C SUBTTL VPARMS. INC
1768 c PAGE
0717 1769 c VIDEO_PARMS LABEL BYTE
1710 C
1771 C STRUCTURE OF TH I STABLE
1772 C
1773 C COLUMNS, ROWS, PELS PER CHARACTER
1774 C PAGE LENGTH
1775 C SEQUENCER PARAMETERS
1776 C MI SCELLANEOUS REG I STER
1777 C CRTC PARAMETERS
1778 C ATTR I BUTE PARAMETERS
1779 C GRAPH I CS PARAMETERS
1780 C
'" 0000 1781 C BASE 1 EQU $ - V J DEO_PARMS
0717 1782 C BASC1_ L LABEL BYTE
1783 C
1784 C ;----- DEFAULT MODES
1785 C
1786 C ;--0--
0717 28 18 08 1787 C DB 400,240,080
071A 0800 1788 C OW 00800H
1789 C
= 0005 1790 c TFS_LEN EQU $ - BASE_1_L
1791 C
071C 1792 C SEQ_PARMS LABEL 8YTE
071C OB 03 00 03 1793 C DB OOBH, 003H, OOOH, 003H
'" 0004 1794 G M1 EQU $ - SEQ_PARMS
1795 C
0720 2' 1796 G DB 023H
1797 G
0721 1798 G CRT_PARMS LA8EL BYTE
0721 3727203731 1799 G DB 037H, 027H, 020H, 037H,031 H, 015H
0727 04 11 00 07 06 07
0720 00 00 00 00 El 24
" 1800
1801
G
G
DB
DB
004H, all H, OOOH, 007H, 006H, 007H
OOOH, OOOH, OOOH, OOOH, DEl H, 024H
0733 C7 14 08 EO FO A3 1802 C DB OC7H, 014H, 008H, OEOH, OFOH, OA3H
0739 FF 1803 G DB OFFH
= 0019 1804 C M4 EQU $-CRT_PARMS
1805 C
'" 0023 1806 C LN_4 EQU $ - BASE_l_L
1807 G
073A 1808 G ATTR_PARMS LABEL BYTE
073A 00 01 02 03 04 05 1809 C DB OOOH, 001 H, 002H, 003H,004H, 005H
0740 06 07 10 11 12 13 1810 G DB 006H, 007H, 010H, 01 1 H, 012H, 013H
0746 14 15 16 17 08 00 1811 G DB 014H, 015H, 016H, 017H, 008H, OOOH
074C OF 00 1812 G DB OOFH,OOOH
'" 0014 1813 C M, EQU $-ATTR_PARMS
1814 C
'" 0037 1815 C LN 2 EQU $ - BASE_'_L
074E 1816 C CRAPH_PARMS LABEL BYTE
074E 00 00 00 00 00 10 1817 G DB OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
0754 OE 00 FF 1818 C DB OOEH,OOOH,OFFH
'" 0009 1819 C M6 EQU $-GRAPH_PARMS
1820 G
'" 0040 1821 C M_ TBL__ .LEN EQU $ - BASE_l_L
1822 C
1823 C ;--1--
0757 28 18 08 1824 C DB 400,240,080
075A 0800 1825 C OW 00800H
1826 C
075C DB 03 00 03 1827 C DB 008H,003H, OOOH, 003H
1828 C
0760 2' 1829 C DB 023H
1830 C
0761 37 27 20 37 31 15 1831 C DB 037H, 027H, 020H, 037H, 031 H, 015H
0767 04 11 00 07 06 07 1832 G DB 004H, 01 1 H, OOOH, 007H,006H, 007H
0760 00 00 00 00 El 24 1833 c DB OOOH, OOOH, OOOH, OOOH, OEl H, 024H
0773 C7 14 08 EO Fa A3 1834 C DB OC7H, 01 4H, 008H, OEOH, OFOH, OA3 H
0779 FF 1835 C DB OFFH
1836 G
077A 00 01 02 03 04 05 1837 C DB OOOH, 001 H, 002H, 003H, 004H, 005H
0780 06 07 10 11 12 13 1838 C DB 006H, 007H, 010H, 011 H, 012H, 013H
0786 14 15 16 17 08 00 1839 C DB 014H, 015H, 016H, 017H, 008H, OOOH
078C OF 00 1840 C DB OOFH,OOOH
1841 G
078E 00 00 00 00 00 10 1842 G DB OOOH, OOOH, OOOH, OOOH, OOOH, 010H
0794 DE 00 Ff 1843 G DB OOEH,OOOH,OFFH
1844 C
1845 C ; --2--
0797 50 18 08 1846 C DB 800,240,080
079A 1000 1847 G OW 01000H
1848 C
079C 01 03 00 03 1849 C DB 001 H, 003H, OOOH, 003H
1850 C
07AO 2' 1851 C DB 023H
1652 G
07Al 70 4F 5C 2F SF 07 1653 C DB 070H, 04FH, 05CH, 02FH, 05FH, 007H
07A7 04 11 00 07 06 07 1854 C DB 004H, 011 H, OOOH, 007H, 006H, 007H
07AD 00 00 00 00 El 24 1655 C DB OOOH, OOOH, OOOH, OOOH, DEl H, 024H
0783 C7 28 08 EO FO A3 1856 G DB oe7H, 028H, 008H, OEOH, orOH, OA3H
0789 FF 1857 G DB OFFH
1858 C
078A 00 01 02 03 04 05 1859 c DB OOOH, 001 H, 002H, 003H, 004H, 005H
07CO 06 07 10 11 12 13 1860 G DB 006H, 007H, 010H, 01 1 H, 012H, 013H
07C6 14 15 16 17 08 00 1861 G DB 01 4H,015H, 016H, 01 7H, 008H, OOOH
07CC OF 00 1862 C DB OOFH,OOOH
1863 C
07CE 00 00 00 00 00 10 1864 C DB OOOH, OOOH, OOOH, OOOH,OOOH, 010H
0704 DE 00 FF 1865 C DB OOEH, OOOH, OFFH
1866 C
1867 C ;--3--
0707 50 18 08 1868 C DB 800,240,080
07DA 1000 1869 C OW 01000H
1870 C
01Qe 01 03 00 03 1871 C DB 001 H, 003H, OOOH, 003H
1872 C
07EO 23 1873 C DB 023H
1874 C
07El 70 4F 5C 2f 5F 07 1875 C DB 070H, 04FH, 05CH, 02FH, 05FH, 007H
07£7 04 11 00 07 06 07 1876 G DB 004H, 01 1 H, OOOH, 007H, 006H, 007H
07ED 00 00 00 00 El 24 18ff G DB OOOH, OOOH, OOOH, OOOH, DEl H, 024H
07F3 C7 28 08 EO fO A3 1878 C DB OC7H, 028H, 008H, OEOH, OFOH, OA3H
07F9 FF 1879 G DB OFFH
1880 C
07FA 00 01 02 03 04 05 1881 C DB OOOH, 001H, 002H, 003H, 004H, 005H
0800 06 07 10 11 12 13 1882 C DB 006H,007H, 010H, 011 H, 012H, 01 3H
0806 14 15 16 17 08 00 1883 C DB 014H,015H, 016H, 017H, 008H, OOOH
080C OF 00 1884 C DB OOFH,OOOH
1885 C
080E 00 00 00 00 00 10 1886 C DB OOOH, OOOH, OOOH, OOOH, OOOH, 010H
0814 DE 00 FF 1887 C DB OOEH,OOOH,OFFH
1888 C
1889 C ; --4--
0817 28 18 08 1890 C DB 400,240,080

118 IBM Enhanced Graphics Adapter August 2, 1984

08tA 4000 1891 C OW 04000H
1892 C
D81C DB 03 00 02 1893 C DB OOBH, 003H, OOOH, 002H
1894 C
0820 23 1895 C DB 023H
1896 C
0821 37 27 20 37 30 14 1897 C DB 037H,027H, 020H, 037H, 030H, 014H
0827 04 11 00 01 00 00 1896 C DB 004H, all H, OOOH, 001 H, OOOH, OOOH
0820 00 00 00 00 El 24 1899 C DB OOOH,OOOH, OOOH, OOOH, DEl H, 024H
0833 C7 14 00 EO FO A2 1900 C DB OC7H, 0 14H, OOOH, OEOH, OFOH, OA2H
0839 FF 1901 C DB OFfH
1902 C
063A 00 13 15 17 02 04 1903 C DB OOOH, 01 3H, 015H, 017H, 002H, 004H
0840 06 07 10 11 12 13 1904 C DB 006H, 007H, 010H, 011H, 012H, 013H
0846 14 15 16 17 01 00 1905 C DB 014H, 015H, 016H, 017H, 001 H, OOOH
084C 03 00 1906 C DB 003H,OOOH
1907 C
084E 00 00 00 00 00 30 1906 C DB OOOH, OOOH, OOOH, OOOH, OOOH, 030H
0854 Of 00 Ff 1909 C DB OOFH,OOOH,OfFH
1910 C
1911 C ; --5--
0857 26 18 08 1912 C DB 400,240,060
085A 4000 1913 C OW 04000H
1914 C
085C DB 03 00 02 1915 C DB OOBH, 003H, OOOH, 002H
1916 C
0660 23 1917 C DB 023H
1918 C
0861 37 27 20 37 30 14 1919 C DB 037H, 027H, 020H, 037H, 030H, 011~H
0867 04 11 00 01 00 00 1920 C DB 004H, 01 1 H, OOOH, 001H, OOOH, OOOH
0860 00 00 00 00 El 24 1921 C DB OOOH, OOOH, OOOH, OOOH, OEl H, 024H
0873 C7 14 00 EO FO A2 1922 C DB OC7H, 014H, OOOH, OEOH, OFOH, OA2H
0879 FF 1923 C DB OFfH
1924 C
087A 00 13 15 17 02 04 1925 C DB OOOH, 013H, 015H, 017H, 002H, 004H
0880 06 01 10 11 12 13 1926 C DB 006H, 007H, 01 OH, 011H, 012H,Ol 3H
0886 14 15 16 17 01 00 1927 C DB 014H, 015H, 016H, 017H, DOl H, OOOH
068C 03 00 1928 C DB 003H,000H
1929 C
088E 00 00 00 00 00 30 1930 C DB OOOH, OOOH, OOOH, OOOH, OOOH, 030H
0894 Of 00 ff 1931 C DB OOfH,OOOH,OfFH
1932 C
1933 C ; --6--
0897 50 18 08 1934 C DB 800,240,080
089A 4000 1935 C OW 04000H
1936 C
089C 01 01 00 06 1937 C DB 001 H, 001 H, OOOH, 006H
1938 C
08AO 23 1939 C DB 023H
1940 C
08Al 70 4f 59 20 5E 06 1941 C DB 010H, 04fH, 059H, 02DH, 05EH, 006H
08A7 04 11 00 01 00 00 1942 C DB 004H, 01 1 H, OOOH, 001 H, OOOH, OOOH
08AO 00 00 00 00 EO 23 1943 C DB OOOH, OOOH, OOOH, OOOH, OEOH, 023H
0883 ~~ 28 00 qf EF C2 1944 C DB OC7H, 026H, OOOH, ODfH, OEfH, OC2H
0689 1945 C DB OffH
1946 C
OBBA 00 17 17 17 17 17 1947 C DB OOOH, 01 7H, 017H, 017H, 017H, 017H
08CO 171717171717 1948 C DB 01 7H, 01 7H, 017H,017H, 017H, 017H
08C6 17 17 17 17 01 00 1949 C DB 017H, 01 7H, 017H, 017H, 001 H, OOOH
06CC 01 00 1950 C DB 001H,000H
1951 C
08CE 00 00 00 00 00 00 1952 C DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
0804 00 00 FF 1953 C DB OOOH,OOOH,OfFH
1954 C
1955 C ;--7--
0807 50 18 DE 1956 C DB 800,240,140
080A 1000 1957 C OW 01000H
1958 C
080C 00 03 00 03 1959 C DB OOOH, 003H, OOOH, 003H
1960 C
08EO A6 1961 C DB OA6H
1962 C
08El 60 4F 56 3A 51 60 1963 C DB 060H, 04fH, 056H, 03AH, 051H, 060H
08E1 70 1F 00 00 DB DC 1964 C DB 070H, 01 fH,OOOH,OOOH, OOBH, OOCH
08ED 00 00 00 00 5E 2E 1965 c DB OOOH, OOOH, OOOH, OOOH, 05EH, 02EH
08F3 50 28 00 5E 6E A3 1966 c DB 050H, 028H, OOOH, 05EH, 06£H, OA3H
08F9 FF 1967 C DB OFfH
1968 C
08fA 00 08 08 08 08 08 1969 C DB OOOH, 008H. 008H, 008H, 008H, 008H
0900 08 08 10 18 18 18 1970 C DB 008H,008H, 010H, 018H, 018H, 018H
0906 18 18 18 18 DE 00 1971 C DB o 18H, 0 18H, 01 8H, 018H, OOEH, OOOH
090C OF 08 1972 C DB 00FH,006H
1973 C
090E 00 00 00 00 00 10 1974 C DB OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
0914 OA 00 Ff 1975 C DB OOAH,OOOH,OFfH
1976 C
1977 c ; --8--
0917 28 18 08 1978 C DB 400,240,080
091A 4000 1979 C ow 04000H
1980 C
091C 00 00 00 03 1981 C DB OOOH, OOOH, OOOH, 003H
1982 C
0920 23 1983 C DB 023H
1984 C
0921 37 27 20 37 31 15 1985 c DB 037H, 027H, 02DH, 037H, 031H, 015H
0927 04 11 00 07 06 07 1986 C DB 004H, 01 1 H, 000H,007H, 006H, 007H
0920 00 00 00 00 E1 24 1967 C DB OOOH, OOOH, OOOH.OOOH, OElH, 024H
0933 C7 14 08 EO FO A3 1988 C DB OC7H, 014H, 008H,OEOH, OFOH. OA3H
0939 FF 1989 C DB OFFH
1990 C
093A 00 01 02 03 04 05 1991 C DB OOOH, 001 H, 002H,003H, 004H, 005H
0940 06071011 12 13 1992 C DB 006H,007H,010H, 011H, 012H, 013H
0946 14 15 16 17 08 00 1993 C DB 014H,015H,016H, 017H, 008H, OOOH
094C OF 00 1994 C DB OOFH,OOOH
1995 C
094£ 00 00 00 00 00 10 1996 C DB OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
0954 O£ 00 FF 1997 C DB OOEH,OOOH,OFFH
1998 C
1999 c ;. ~':I--

0957 28 18 08 2000 C DB I~OD,24D,v8U

095A 4000 2001 C DW 04000H
2002 C
095C 00 00 00 03 2003 C DB uOUH, ooutt, OOOH, 003H
2004 C
0960 23 2005 C DB 023H
2006 C
0961 37 27 20 37 31 15 2007 C DB 037H, 027H, 020H, 031H, 031H, 01 5H
0967 04 " 00 07 06 07 2008 C DB 004H, 011 H, 000H,007H, 006H, 007H
0960 00 00 00 00 E1 24 2009 C DB OOOH, OOOH, OOOH, OOOH, DEl H, 024H
0973 C7 14 08 EO FO A3 2010 C DB OC7H, 014H, 008H,OEOH, OFOH, OA3H
0979 ff 2011 C DB OFFH
2012 C
097A 00 01 02 03 04 05 2013 C DB OOOH, 001 H, 002H.003H, 004H, 005H
0980 06 07 10 11 12 13 2014 C DB 006H.007H,010H,011 H,012H,013H
0986 14 15 16 17 08 00 2015 C DB 014H, 015H, 016H, 017H, 008H, OOOH
098C OF 00 2016 C DB OOfH,OOOH

August 2, 1984 IBM Enhanced Graphics Adapter 119

 2017
098E 00 00 00 00 00 10 2018 DB OOOH, OOOH, OOOH, OOOH, OOOH, 0 1OH
0994 DE 00 FF 2019 DB OOEH,OOOH,OFFH
2020
2021 ; --A--
0997 28 18 08 2022 DB 400,240,080
099A 4000 2023 OW 04000H
2024
099C 00 00 00 03 2025 DB OOOH, OOOH, OOOH, 003H
2026
09AO 23 2027 DB 023H
2028
09Al 37 27 20 37 31 15 2029 DB 037H,027H, 020H, 037H, 031H, 015H
09A7 04 11 00 07 06 07 2030 DB 004H, 011 H, OOOH, 007H, 006H, 007H
09AD 00 00 00 00 El 24 2031 DB OOOH,OOOH, OOOH, OOOH, DEl H, 024H
09B3 C7 14 08 EO FO A3 2032 DB OC7H, 014H, 008H,OEOH, OFOH, OAlH
09B9 FF 2033 DB OFFH
2034
09BA 00 01 02 03 04 05 2035 DB OOOH, 001 H, 002H, 003H, 004H, 005H
09CO 06 07 10 11 12 13 2036 DB 006H, 007H, 010H, 011H, 012H, 013H
09c6 14 15 16 17 08 00 2037 DB 014H, 015H, 016H, 01 7H, 008H, OOOH
09CC OF 00 2038 DB OOFH,OOOH
2039
09CE 00 00 00 00 00 10 2040 DB OOOH, OOOH, OOOH, OOOH, OOOH, 010H
0904 DE 00 FF 2041 DB OOEH,OOOH,OFFH
2042
2043 ; --B--
0907 50 18 08 2044 DB 800,240,080
09DA 1000 2045 OW 01000H
2046
090C 01 04 00 07 2047 DB 001H, 004H, OOOH, 007H
2048
09EO 23 2049 DB 023H
2050
09El 70 4F 5C 2F 5F 07 2051 DB 070H, 04FH, 05CH, 02FH, 05FH, 007H
09E7 04 11 00 07 06 07 2052 DB 004H, 01 1 H, OOOH, 007H, 006H, 007H
09ED 00 00 00 00 E1 24 2053 DB OOOH, OOOH, OOOH, OOOH, DEl H, 024H
09F3 C7 28 08 EO FO A3 2054 DB OC7H, 028H, 008H, OEOH, OFOH, OA3H
09F9 FF 2055 DB OFFH
2056
09FA 00 00 00 00 00 00 2057 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OADO 00 00 00 00 00 00 2058 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OA06 00 00 00 00 00 00 2059 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OAOC OF 00 2060 DB OOFH,OOOH
2061
DADE 00 00 00 00 00 00 2062 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OA14 04 00 FF 2063 DB 004H, OOOH, OFFH
2064 ; --C--
OA17 50 18 DE 2065 DB 800,240,140
OAlA 1000 2066 OW OlOOOH
2067
OA1C 00 04 00 07 2068 DB OOOH, 004H, OOOH, 007H
2069
OA20 A6 2070 DB OA6H
2071
OA21 60 4F 56 3A 51 60 2072 DB 060H, 04FH, 056H, 03AH, 051 H, 060H
OA27 70 1F 00 00 DB DC 2073 DB 070H, 01 FH, OOOH, OOOH, OOBH, OOCH
OA2D 00 00 00 00 SE 2E 2074 DB OOOH, OOOH, OOOH, OOOH, 05EH, 02EH
OA33 50 28 00 5E 6E A3 2075 DB 050H, 028H, OOOH, 05EH, 06EH, OA3H
OA39 FF 2076 DB OFFH
2077
OA3A 00 00 00 00 00 00 2078 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OA40 00 00 00 00 00 00 2079 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OA46 00 00 00 00 DE 00 2080 DB OOOH, OOOH, OOOH, OOOH, OOEH, OOOH
OA4C OF 08 2081 DB 00FH,008H
2082
OA4E 00 00 00 00 00 00 2083 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OA54 04 00 FF 2084 DB 004H,000H,OFFH
2085 ; --0--
OAS7 28 18 08 2086 DB 400,240,080
OA5A 2000 2087 OW 02000H
2088
OA5C DB OF 00 06 2089 DB OOBH, OOFH, OOOH, 006H
2090
OA60 23 2091 DB 023H
2092
OA61 37 27 20 37 30 14 2093 DB 037H, 027H, 020H, 037H, 030H, 014H
0A67 041100000000 2094 DB 004H, 01 1 H, OOOH, OOOH, OOOH, OOOH
OA60 00 00 00 00 £1 24 2095 DB OOOH, OOOH, OOOH, OOOH, DEl H, 024H
OA73 C7 14 00 EO FO E3 2096 DB OC7H, 014H, OOOH, OEOH, OFOH, OE3H
OA79 FF 2097 DB OFFH
2098
OA7A 00 01 02 03 04 05 2099 DB OOOH, 001 H, 002H, 003H, 004H, 005H
OABO 06 07 10 11 12 13 2100 DB 006H, 007H, 010H, 011 H, 012H, 013H
0A66 14 15 16 17 01 00 2101 DB 014H, 015H, 016H, 017H, 001 H, OOOH
OA8C OF 00 2102 DB OOFH,OOOH
2103
OA8E 00 00 00 00 00 00 2104 DB OOOH, OOOH, OOOH, OOOH. OOOH, OOOH
OA94 05 OF FF 2105 DB 005H, OOFH, OFFH
2106 ; --E--
OA97 50 18 08 2107 DB 800,240,080
OA9A 4000 2108 OW 04000H
2109
OAgc 01 OF 00 06 2110 DB 001 H, OOFH, OOOH, 006H
2111
OAAO 23 2112 DB 023H
2113
OAAl 70 4F 59 20 5E 06 2114 DB 07DH, 04fH,OS9H, 02011, 05EH, 006H
OAA7 04 11 00 00 00 00 2115 DB 004H, 011 H, OOOH, OOOH, OOOH, OOOH
DMD 00 00 00 00 EO 23 2116 DB OOOH, OOOH, OOOH, OOOH, OEOH, 023 H
OAB3 C7 28 00 OF EF E3 2117 DB OC7H, 028H, OOOH, ODFH, OEFH, OE3H
OAB9 FF 2118 DB OFFH
2119
OABA 00 01 02 03 04 05 2120 DB OOOH, 001 H, 002H,003H, 004H, 005H
OACO 06071011 12 13 2121 DB 006H, 007H, 01 OH, 01 1 H, 012H, 013H
OAC6 14 15 16 17 01 00 2122 DB 01 4H, 015H, 016H, 017H, 001H, ODOH
DAce OF '00 2123 DB OOFH,OOOH
2124
DACE 00 00 00 00 00 00 2125 DB OOOH, OOOH, OOOH. OOOH, OOOH, OOOH
OA04 05 OF FF 2126 DB 005H,DOFH,OFFH
2127 ; --F--
OAD7 50 18 DE 2128 UB 800,240,140
DADA 8000 2129 OW 08000H
2130
OADC 05 OF 00 00 2131 DB 005H, 00 FH, OOOH, OOOH
2132
OAEO A2 2133 DB OA2H
2134
OAEl 60 4F 56 lA 50 EO 2135 DB 060H, 04FH, 056H, 0 1AH, 050H, OEOH
OAE7 70 1F 00 00 00 00 2136 DB 070H,01 FH, OOOH, OOOH, OOOH, OOOH
OAED 00 00 00 00 5E 2E 2137 DB OOOH, OOOH, OOOH, OOOH, 05EH, 02EH
OAF3 50 14 00 5E 6E 6B 2138 DB 05DH, 0 14H, OOOH, 05EH, 06EH, 08BH
OAF9 FF 2139 DB OFFH
2140
OAFA 00 08 00 00 18 18 2141 DB OOOH, 008H, OOOH, OOOH, 018H,018H
OBOO 00 00 00 08 00 00 2142 DB OOOH, OOOH, OOOH, 008H, OOOH, OOOH

120 IBM Enhanced Graphics Adapter August 2, 1984

OB06 00 18 00 00 OB 00 2143 DB OOOH, 018H, OOOH, OOOH, 009H, OOOH
OBOC as 00 2144 DB 005H,OOOH
2145
OBOE 00 00 00 00 00 10 2146 DB OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
OB14 07 Of FF 2147 DB 007H,OOFH,OFFH
2148 ; ~10~-
OB17 50 18 DE 2149 DB 80D, 240, 140
OB1A 8000 2150 DW 08000H
2151
OB1C 05 OF 00 00 2152 DB 005H,OOFH, OOOH, OOOH
2153
0820 '7 2154 DB OA7H
2155
0621 58 4F 53 17 50 8A 2156 DB 058H, 04FH, 053H, 017H, 050H, OBAH
0627 6C1FOOOOOOOO 2157 DB 06CH, 01 rH, OOOH, OOOH, OOOH, OOOH
OB20 00 00 00 00 5E 2B 2158 DB OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
0833 5D 14 OF 5f OA 88 2159 DB 050H,014H, OOFH, 05FH, OOAH, 08BH
0839 fF 2160 DB OFFH
2161
OB3A 00 01 00 00 04 07 2162 DB OOOH, DOl H, OOOH, OOOH, 004H, 007H
0640 00 00 00 01 00 00 2163 DB OOOH, OOOH, OOOH, 001H, OOOH, OOOH
OB46 04 07 00 00 01 00 2164 DB 004H, 007H, OOOH, OOOH, 001 H, OOOH
OB4C OS 00 2165 DB 005H,000H
2166
OB4E 00 00 00 00 00 10 2167 DB OOOH, OOOH, OOOH, OOOH, OOOH, 01 OH
OB54 07 OF FF 2168 DB 007H,OOFH,OFFH
2169
= 0440 2170 BASE_2 EQU S - VIOEO_PARMS
2171
2172 > 16K MODE VALUES
2173
2174 ;~~F~-

OBS7 50 18 DE 2175 DB 800,240,14D

OB5A 8000 2176 DW 08000H
2177
OB5C 01 OF 00 06 2178 DB 001H, OOFH, OOOH, 006H
2179
OB60 A2 2180 DB OA2H
2181
OB61 60 4F S6 3A 50 60 2182 DB 060H, 04FH, 056H, 03AH, 050H, 060H
OB67 70 1f 00 00 00 00 2183 DB 070H, 01 FH, OOOH, OOOH, OOOH, OOOH
OB60 00 00 00 00 5E 2E 2184 DB OOOH, OOOH, OOOH, OOOH, 05EH. 02EH
0873 50 28 00 5E 6E [3 2185 DB OSOH, 028H, OOOH, 05EH, 06EH, OE3H
0879 fF 2186 DB OFFH
2187
087A 00 08 00 00 18 18 2188 DB OOOH, 008H,000H, OOOH, 018H, 018H
OB80 00 00 00 08 00 00 2189 DB OOOH, OOOH, OOOH, 008H, OOOH, OOOH
OB86 00 18 00 00 DB 00 2190 DB OOOH, 018H, OOOH, OOOH, OOBH, OOOH
OB8C 05 00 2191 DB 005H,000H
2192
OB8E 00 00 00 00 00 00 2193 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OB94 os OF FF 2194 DB 005H,00FH,OFFH
2195
2196 ;~10-~

0897 SO 18 DE 2197 DB 800,240,140

OB9A 8000 2198 DW 08000H
2199
OB9C 01 OF 00 06 2200 DB 001 H, OOFH, OOOH, 006H
2201
OBAO A7 2202 DB OA7H
2203
OBAl 58 4F 53 37 52 00 2204 DB 05BH, 04FH, 053H, 037H, 052H, OOOH
OBA7 6C 1f 00 00 00 00 2205 DB 06CH, 01 FH, OOOH, OOOH, OOOH, OOOH
OBAo 00 00 00 00 5E 2B 2206 DB OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
OBB3 50 28 OF SF OA E3 2207 DB 050H, 028H, OOfH, 05 FH, OOAH, OE3H
OBB9 fF 2208 DB OFFH
2209
OBBA 00 01 02 03 04 05 2210 DB OOOH, 001H, 002H, 003H, 004H, OOSH
OBCO 14 07 38 39 3A 3B 2211 DB 014H, 007H, 038H, 039H, 03AH, 03BH
OBC6 3C 3D 3E 3F 01 00 2212 DB 03CH, 030H, 03EH, 03FH, 001 H, OOOH
OBCC OF 00 2213 DB OOFH, OOOH
2214
OBCE 00 00 00 00 00 00 2215 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OB04 05 OF ff 2216 DB 005H,OOFH,OFfH
2217
2218
= 04CO 2219 BASE_3 EQU S ~ VIOEO_PARMS
2220
2221 ;~~~~- HI RES ALTERNATE VALUES
2222
2223 ; --0--
OB07 28 18 DE 2224 DB 400,240,140
OBOA 0800 2225 DW 00800H
2226
OBOC OB 03 00 03 2227 DB 00BH,003H, OOOH, 003H
2228
OBEO '7 2229 DB OA7H
2230
OBEl 20 27 26 20 28 60 2231 DB 020H, 027H, 02BH, 020H, 028H, 060H
OBE7 6C 1F 00 00 06 07 2232 DB 06CH, 01 FH, OOOH, OOOH, 006H, 007H
OBED 00 00 00 DOSE 2B 2233 DB OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
OBF3 50 14 OF 5E OA A3 2234 DB 050H, 014H, OOFH, 05EH, OOAH, OA3H
OBF9 FF 2235 DB OFFH
2236
OBFA 00 01 02 03 04 05 2237 DB OOOH, 001 H, 002H, 003H, 004H, 005H
OCOO 14 07 38 39 3A 3B 2238 DB 014H, 007H, 038H, 039H, 03AH, 03BH
OC06 3C 3D 3E 3F 08 00 2239 DB 03CH, 03DH, 03EH, 03 FH, 008H, OOOH
OCOC OF 00 2240 DB OOFH,OOOH
2241
OCOE 00 00 00 00 00 10 2242 DB OOOH, OOOH, OOOH, OOOH, OOOH, 010H
OC14 DE 00 FF 2243 DB OOEH,OOOH,OFFH
2244
2245 ;~-1-~
OC17 28 18 DE 2246 DB 40D,240, 140
OCM 0800 2247 DW 00800H
2248
OC1C DB 03 00 03 2249 DB OOSH, 003H,OOOH, 003H
2250
OC20 '7 2251 DB OA7H
2252
OC2l 20 27 2B 20 28 60 2253 DB 02DH, 027H, 02BH, 020H, 028H, 060H
OC27 6ClfOOOD0607 2254 DB 06CH, 01 fH,OOOH, OODH, 006H, 007H
OC2D 00 00 00 00 5E 2B 2255 DB OOOH, OOOH, OOOH, OOOH, 05£H, 02BH
OCU 5D 14 OF 5E OA A3 2256 DB 050H, 014H, OOFH, 05£H, OOAH, OA3H
OC39 Ff 2257 DB OFFH
2258
OC3A 00 01 02 03 04 05 2259 DB OOOH, 001H, 002H, 003H, 004H, 005H
OC40 14 07 38 39 3A 38 2260 DB 014H, 007H,038H, 039H, 03AH, 03BH
OC46 3C 3D 3£ 3F 08 00 2261 DB 03CH, 030H,03£H, 03FH, 008H, OOOH
OC4C OF 00 2262 DB OOFH,OOOH
2263
OC4E 00 00 00 00 00 10 2264 DB OOOH, OOOH,OOOH, OOOH, OOOH, 010H
OC54 DE 00 FF 2265 DB OOEH,OOOH,OFFH
2266
2267 ; -~2~~

OC57 50 18 DE 2268 DB 800,240,140

August 2, 1984 IBM Enhanced Graphics Adapter 121

OC5A 1000 2269 C OW 01000H
2270 C
OC5C 01 03 00 03 2271 C DB DOl H, 003H, OOOH, 003H
2272 C
OC60 A7 2273 C DB OA7H
2274 C
OC61 5B 4F 53 37 51 5B 2275 C DB 05BH, 04FH, 053H, 037H, 051 H, 05BH
OC67 6C 1F 00 00 06 07 2276 C DB 06CH, 01 FH, OOOH, OOOH, 006H, 007H
OC60 00 00 00 DOSE 2B 2277 C DB OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
OC73 50 28 OF 5E OA A3 2278 C DB 050H, 028H, OOFH, 05EH, OOAH, OA3H
OC79 FF 2279 C DB OFFH
2280 C
OC7A 00 01 02 03 04 05 2281 C DB OOOH, DOl H, 002H, 003H, 004H, 005H
OC80 14 07 38 39 3A 3B 2282 C DB 014H, 007H, 038H, 039H, 03AH, 03BH
OC86 3C 30 3E 3F 08 00 2283 C DB 03CH, 030H, 03EH, 03 FH, 008H,000H
OC8C OF 00 2284 C DB OOFH,OOOH
2285 C
OC8E 00 00 00 00 00 10 2286 C DB OOOH, OOOH, OOOH, OOOH, OOOH, 010H
OC94 DE 00 FF 2287 C DB OOEH,OOOH,OFFH
2288 C
2289 C ; --3--
OC97 50 18 OE 2290 C DB 800,240,140
OC9A 1000 2291 C OW 01000H
2292 C
OC9C 01 03 00 03 2293 C DB DOl H, 003H, OOOH, 003H
2294 C
OCAO A7 2295 C DB OA7H
2296 C
OCAl 58 4F 53 37 51 58 2297 C DB 05BH,04FH, 053H, 037H, 051 H, 05BH
OCA7 6C 1F 00 00 06 07 2298 C DB 06CH, 01 FH, OOOH, OODH, 006H, 007H
OCAO 00 00 00 DOSE 2B 2299 C DB OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
OCB3 50 28 OF 5E OA A3 2300 C DB 050H, 028H, OOFH, 05EH, OOAH, OA3H
OCB9 FF 2301 C DB OFFH
2302 C
OCBA 00 01 02 03 04 05 2303 C DB OOOH, 001 H, 002H, 003H, 004H, 005H
OCCO 14 07 38 39 3A 3B 2304 C DB 014H, 007H, 038H, 039H, 03AH, 03BH
OCC6 3C 3D 3E 3F 08 00 2305 C DB 03CH, 030H, 03EH, 03FH, 008H, OOOH
OCCC OF 00 2306 C DB OOFH,aOOH
2307 C
aCCE 00 00 00 00 00 10 2308 C DB OOOH, OOOH, OOOH, OOOH, 000H,010H
OC04 DE 00 FF 2309 C DB OOEH,OOOH,OFFH
2310 C
2311 C
2312 C SUBTTL
2313
2314 ; ----- VECTOR INTO <AH> SPEC I F I ED FUNCT I ON
2315
OC07 2316 COMBO_VIOEO PROC NEAR
oe07 FB 2317 STI I NTERRUPTS ON
OG08 FC 2318 CLD SET D I REeT I ON FORWARD
OCD9 55 2319 PUSH BP SAVE THE REG I STER SET
OCOA 06 2320 PUSH ES
OCOB 1E 2321 PUSH OS
QGoe 52 2322 PUSH OX
oeoo 51 2323 PUSH CX
OGOE 53 2324 PUSH BX
DGOF 56 2325 PUSH SI
OGEQ 57 2326 PUSH 01
2327
OCEl 50 2328 PUSH AX ; SAVE AX VALUE
OCE2 8A C4 2329 MOY AL,AH ; GET I NTO LOW BYTE
OCE4 32 E4 2330 XOR AH,AH ; ZERO TO HIGH BYTE
OCE6 01 EO 2331 SAL AX, 1 ; * 2 FOR TABLE LOOKUP
OCE8 8B FO 2332 MOY SI,AX PUT INTO SI FOR BRANCH
OCEA 3D 0028 2333 CMP AX, T2L TEST FOR WITHIN RANGE
OGED 72 06 2334 JB M2 BRANCH AROUND BRANCH
OGEf 58 2335 POP AX RECOVER REG I STER
OCFO CD 42 2336 INT 42" PASS UNRECOGN IZEO CALL
OCF2 E9 219E R 2337 JMP V_RET RETURN TO GALLER
OCF5 2338 M2:
2339 ASSUME OS:ABSO
OCF5 E8 OCFE R 2340 CALL DDS
OCF8 58 2341 PDP AX RECOVER
OCF9 2E: FF A4 06EF R 2342 JMP WORD PTR CS:ISI + OFFSET T2] JMP TO AH,=O THRU AH=XX
2343
2344 ; ----- UT I L I TY ROUT I NES
2345
2346 ; ----- SET OS TO THE DATA SEGMENT
2347
OCfE 2348 DDS PROC NEAR
OCfE 50 2349 PUSH AX SAVE REG I STER
OCfF 2B CO 2350 SUB AX,AX
0001 8E 08 2351 MOY OS,AX
0003 5B 2352 POP AX RESTORE REG I STER
0004 c3 2353 RET
0005 2354 DDS ENOP
2355
0005 2356 WHAT_BASE PROC NEAR
2357 ASSUME OS:ABSO
0005 1E 2358 PUSH OS ;. SAVE DATA SEGMENT
0006 E8 OCFE R 2359 CALL DDS ; GET LOW MEMORY SEGMENT
0009 8B 16 0463 R 2360 MOY OX,AOOR_6845 ; GET CRTC ADDRESS
0000 80 E2 FO 2361 AND OL,OFOH ; STRI P Off LOW NIBBLE
0010 80 CA OA 2362 OR OL,OAH ; SET TO STATUS REGISTER
0013 IF 2363 POP OS
0014 C3 2364 RET
0015 2365 WHAT_BASE ENDP
2366
0015 2367 OUT_OX PROC NEAR ; AH"'INOEX,AL=OATA,DX"'PORT
0015 86 C4 2368 XCHG AL,AH ; GET I NOEX VALUE
0011 EE 2369 OUT DX,AL ; SET I NOEX REG
0018 42 2370 INC OX SET OX TO DATA REG
0019 86 C4 2371 XCHG AL,AH GET DATA VALUE
001B EE 2372 OUT OX,AL SET DATA REG
001C 4A 2373 DEC DX SET OX BACK TO I NO[X
0010 C3 2374 RET
001 E 2375 aU-I_DX ENOP
2376
2377 ;----- ROUTINE 10 ~OlJNlJ Bl[PlK
2378
OlllE 2379 BP_' PROC NEAR
001 E EE 2380 OUT aX,AL
OOlF C3 2381 RET
0020 2382 BP_' [NOP
2383
0020 2384 BEEP PROC NEAR
0020 52 2385 PUSH DX
0021 BA 0043 2386 MOY OX, TI MER+3
0024 BO B6 2387 MOY AL,101101108 ; SEL TIM 2,LSB,MSB,BINARY
0026 E8 DOlE R 2388 CALL BP 1 ; WR I TE THE T I MER MODE REG
0029 88 0533 2389 MOY AX-;-533H ; QIVISOR FOR 1000 HZ
Q02C 4A 2390 DEC DX
0020 E8 OOlE R 2391 CALL BP 1 ; WRITE TIMER 2 CNT - LSB
0030 SA C4 2392 MOY Al-;-AH
0032 [8 OOlE R 2393 CALL BP 1 ; WRITE TIMER 2 CNT - HS8
0035 BA 0061 2394 MOY OX-;-PORT_B

122 IBM Enhanced Graphics Adapter August 2, 1984

0036 EC 2395 IN AL,OX GET SETT I NG OF PORT
0039 8A EO 2396 MOV AH,Al SAVE THAT SETTING
003B OC 03 2397 OR Al,03 TURN SPEAKER ON
0030 E8 DOlE R 2398 eAll BP_l
0040 2B C9 2399 SUB ex,cx SET CNT TO WA 1T 500 MS
0042 2400 07:
0042 E2 FE 2401 lOOP 07 DELAY BEFORE TURNING OFF
0044 FE CB 2402 DEC Bl DELAY CNT EXP 1RED?
0046 15 FA 2403 JNZ 07 NO-CONT I NUE BEEP I NG SPK
0048 8A C4 2404 MDV Al,AH RECOVER VALUE OF PORT
004_" E8 DOlE R 2405 CALL BP_'
0040 5A 2406 PDP OX
004E C3 2407 RET RETURN TO CAllER
004F 2408 BEEP ENDP
2409
2410 ;----- FIND THE PARAMETER TABLE VECTOR I N THE SAVE TABLE
2411
004F 2412 SET_BASE PROC NEAR
2413 ASSUME DS:ABSO
004F E8 OCFE R 2414 CALL DDS
0052 C4 1E 04A8 R 21115 lES BX, SAVE_PTR GET PTR TP PTR TABLE
0056 26: C4 1F 2416 lES BX,DWORO PTR ES:[BX) GET PARAMETER PTR
0059 C3 2417 RET
OD5A 2418 SET_BASE ENDP
2419
2420 ;----- ESTABLISH ADDRESSING TO THE CORRECT MODE TABLE ENTRY
2421
OD5A 2422 MAKCBASE PROC NEAR
2423 ASSUME OS: ABSO
OD5A 51 2424 PUSH CX
0056 52 2425 PUSH OX
005C E8 OD4F R 2426 CAll SET BASE GET PARM TBl PTR
005F 8A 26 0449 R 2427 MOV AH,CRT_MOOE
0063 F6 06 0487 R 60 242B TEST INFO,060H TEST FOR BASE CARD
0068 74 16 2429 JZ B_M_1 MIN MEMORY
2430
2431 ;----- WE HAVE A MEMORY EXPANSION OPTION HERE
2432
OD6A 80 FC OF 2433 CMP AH,OFH
0060 75 07 2434 JNE B_M_2
OD6F 61 C3 0440 2435 ADD BX, BASE_2 - BASE_l
0073 EB 33 90 2436 JMP 8_M_OUT
0076 2437 8_M_2:
0076 80 FC 10 2438 CMP AH,OlOH
0079 75 07 2439 JNE B M 1
0078 81 C3 0480 2440 ADD BX, BASE_2 + M_ TBL_lEN - BASe 1
007F E8 27 90 2441 JMP B_M_OUT
0082 2442 B_M_1 :
0082 80 FC 03 2443 CMP AH,03H
0085 17 14 2444 JA B_M_3 SK I P ENHANCED PORT I ON
2445
2446 ;----- CHECK THE SWITCH SETTING FOR ENHANCEMENT
2447
0087 AD 0488 R 2448 MOV AL,INFO_3
OOSA 24 OF 2449 AND AL,OFH
008C 3C 03 2450 CMP AL,03H SECONDARY EMULATE SEll I NG
008E 74 07 2451 JE BRS
0090 3C 09 2452 CMP AL,09H PRIMARY EMULATE SETTING
0092 74 03 2453 JE BRS
0094 EB 05 90 2454 JMP B_M_3
2455
2456 ; ----- WE WI LL PERFORM ENHANCEMENT
2457
0097 2458 BRS:
0097 81 C3 04co 2459 ADD BX,8ASE_3 - BASE_ 1 ; VECTOR TO ENHANCEMENT TBL
0098 2460 B_M_3:
OD9B 8A DE 0449 R 2461 MDV Cl, CRT_MODE
009F 2A ED 2462 SUB CH,CH
OOAl E3 05 2463 JCXl B_M_4
2464
2465 ;----- THIS loOP Will MOVE THE PTR TO THE INDIVIDUAL MODE ENTRY
2466
00A3 2467 B_M_5:
ODA3 83 C3 40 2468 ADD BX, M_ TBl_lEN ; LENGTH OF ONE MODE ENTRY
00A6 E2 FB 2469 LOOP B_M_5
00A8 2470 B M 4:
00A8 2471 8=M=OUT:
OOM 5A 2472 PDP OX
ODA9 59 2473 PDP CX
OOAA C3 2474 RET
OOAB 2475 MAKE_BASE ENDP
2476
2477 ;----- PROGRAM THE EGA REGISTERS FROM THE PARAMETER TABLE
2478
OOAB 2479 SET_REGS PROC NEAR
2480 ASSUME os: ASSO, ES: NOTH I NG
2481
2482 ; ----- PROGRAM THE SEQUENCER
2483
OOAB E8 OD5A R 2484 CAll MAKE_BASE GET TABLE PTR
OOAE 83 C3 05 2485 ADD BX, TFS_LEN MODE TO SEQUENCER PARMS
OOBl B6 03 2486 MDV OH,3
00B3 B2 C4 2487 MDV Ol, SEQ_AOOR
00B5 B8 0001 2488 MOV AX,OOOlH RESET SEQUENCER
00B8 FA 2489 Cli ; 01 SABLE INTERRUPTS
00B9 E8 0015 R 2490 CALL OUT_OX
DOBC 26: 8A 07 2491 MOV AL,ES:[BXj ; GET SEQUENCER VALUE
DoeF FE. C4 2492 INC AH ; NEXT INDEX
00C1 E8 0015 R 2493 CALL OUT_OX SET IT
00C4 2494 01 :
00C4 FE C4 2495 INC AH NEXT I NOEX REG I sTm
00C6 43 2496 INC BX NEXT TABLE ENTRY
OOC7 26: 8A 07 2497 MDV AL,ES:[BXj
OOCA E8 0015 R 2498 CALL OUT_OX
OOCD 80 FC 05 2499 CMP AH,M1+1
DODO 72 F2 2500 JB 01
2501
0002 26: 8A 07 2502 MDV AL, ES: [BX)
0005 43 2503 INC BX
0006 B2 C2 2504 MDV Ol, MI SC_OUTPUT
0008 EE 2505 OUT OX,AL
0009 82 C4 2506 MDV Dl, SEQ_ADDR
OOOB B8 0003 2507 MDV AX,0003H
OODE E8 0015 R 2508 CAll OUT_OX START SEQUENCER
OOEl FB 2509 STI ENABLE INTERRUPTS
2510
2511 ; ----- PROGRAM THE CRT CONTROLLER
2512
ODE2 88 16 0463 R 2513 MDV OX, AOOR_6845 ; CRTC I NOEX REG' STER
00E6 2A E4 2514 SUB AH,AH ; COUNTER
00E8 2515 Xl:
00E8 26: 6A 07 2516 MDV AL, ES: I BX) ; GET VALUE FROM TABLE
ODE8 E8 0015 R 2517 CALL OUT_OX ; SET CRTC REG I STER
OOEE 43 2518 INC BX ; NEXT TABLE ENTRY
OOEF FE C4 2519 INC AH ; NEXT I NOEX VALUE
OOfl 80 FC 19 2520 CMP AH,M4 ; TEST REG I STER COUNT

August 2, 1984 IBM Enhanced Graphics Adapter 123

OOF4 7~ '2 2~21 JB Xl DO THE REST
ODF6 2(i: 68 47 Fl 2522 MOV AX. ES; (BX) (-OFH J GET CURSOR MODE
OOFA 86 EO
~~R~~R_MOOE, AX
2523 X,CHG
OoFC A3 0460 R 2524 MOV SET LOW RAM VALUE
2525
2526
2527
j----- PROGRAM THE ATTRIBUTE CHIP

OOFF 8B F3 2528 MOV ,SI,BX

OEOl E8 0005 R 2529 CALL WHAT_BASE
OE04 EC 2530 IN AL,OX
OE05 B2 CO 2531 MOY Pl, ATTR_WR I TE
OE07 2A E4 :;:532 SUB :<\H,AH I NOEX COUNTER
O£O9 2533 03:
OE09
~~: E8A 07 2534 !;tOY AL, ES: i BXJ GET DATA VALUE
bEaC 25:}5 XCHG AH,AL
tlE(lE EE ," 2,3. bUT
gw
", 86
E[
Eo 2537
2536
XCHG
our
QX,AL
~H;P.oL
aX,AL
~E12 43 ~539 INC ax NEXT OATA VALUE
FE c~
6~~
OE13 2540 AM NEXT INDEX VALUE
01::15 80 Fe 14 25~1 AH;M5 TEST REG I STER COUNT
OE18 72 EF 2542 Ja 03 DO THE REST
2543
OPA BO 00 2544 MPV AL,O
OE1C EE 2545 OUT OX,AL
2546
2547 j ---,.;:.. CHECk I F PALETTE REG I STER VALUES AR~ TO BE SAVED
2541:1
OE10 IE 2549 PUSH OS
tlE1E O. 2550 PUSH ES
OE1F C4 3E 04A8 R 2551 LES OI,SAVE_PTR GET TABLE PTR
OE23 26: C4 7[:\ 04 2552 LES OI,OWORO PTR ES:[01}(4) GET PALETTE PTR
gg~ 8C CO
OB C7
2553
2554
MOV
OR
AX,ES
AX,OI
OE2B 74 09 2555 JZ SAVE_OUT ; I F ZERO, NO SAVE OCCURS
2556
2557 ; ----- STORE AWAY THE PALETTE VALUES I N RAM SAVE AREA
2558
OE2D 1F 2559 pOp OS
OE2E IE 2560 pU.SH OS
OE2F B9 0010 2561 MOV,_ CX,160
0(32 F3/ A4 2562 REP MOVSB SAVE THE PALETTE REGS
004 4. 2563 INC, $1
ti~35 A4 2564 MOVSB SAVE THE OVERSCAN REG
OE36 2565 SAVE_OUT:
01::36 07 2566 PO~ ES
OE31 1F 2567 '0' OS
2568
256~ ;-~--- PROGRAM THE GRAPHICS CHIPS
2:170
OI::3~ B2 cc 2571 MCN ~t;gRAPH_l_POS
OE3A BO 00 2512 MOV
one EE 2573 OUT OX,AL
OEJP B2 cA 2574 Mdv qL, GRAPH_2_P05
OE3f B0 01 2575 MPV AL; 1
OE41 EE 257(j oUt OX,AL ,
~.~
OE42 2'377 MOY 0'-=; GRAPH AOOR
01::44 fij 2578 SUB AH,AH -
OE46 2579 04:
OE46 26: 8A 07 2580 MOV AL, ES: I BX] PARAMETER BYTE
OE49 E8 0015 R 2581 CALL OUT_OX SET IT
OE4C 43 2582 INC BX NEXT BYTE
OE40 FE C4 2583 IHe AH NEXT REG I STER
OE4F 80 FC 09 2584 CMP AH,M6
OE52 72 '2 2585 JB 04 CONTINUE
OE54 e3 2586 RET
OE55 2587 SET_REGS [NDP
2588
2589. ; --;,.-;. MODE SEt REGEN CLEAR ROUTI NE
2590
DES5 2591 BtMK PR()C, NEAR ; FILL RECEN WITH BLANKS
2592 ASSUME as: ABSO, ES: NOTH f NG
OE55 ~O 0487 R 259~ MOY AL;,INFO SEE IF .BLANK IS TO OCCUR
OE58 AS 80 2594 TEST AL,080H MODE SET HIGH BIT
OE5A 7$ 39 2595
g~;O~800H
JHZ 5K I P BLANK FOR, REGEN
OE5C !;iA B800 2596 MOV COLOR ,MODE REGEN ADDRESS
OE5F ~O 0449 R 2597 MOV AL,CRT_MOOE CURRENT MODE SET
01::62 3C 06 2598 CM' AL,,6 0-6 ARE COLOR MODES
0[64 76 OA 2599 JBE ceo
OE66 BA BOOO 2600 MOV OX,OBOOOH MONOCHROME REGEN ADDRESS
OE69 3C 07 2601 eM' AL,7 MONOCHROME MOOE
OE66 74 O~ 2602 JE CGO
(iE6P BA AOOO 2603 MOV OX,OAOOOH ; REMA I N I NG MODES
OE70 2604 CGO:
OE70 IJB (H2O 2605 MOV BX,onOH ALPHA ,BLANK 'vAulE
0E73 3C 04 2606 ALPHAMOOES 0;"3
OE75
0[77
72
3C
06
07
2607
~608
eM'
JB
eM'
ot1 4
Al; 7 ; ALPHA MODE
on9 74 02 2609 JE \/WI
OE7B 2B DB 2610 SU8 BX,BX ; GRAPH I CS BLANK VALUE
OE1D 26n WWl:
2612 SRLDAIl ES ; SET THE REGEN SEGMENT
onD 8E C2 2613 MOV ES,OX
OE7F 8B DE 044C R 2614 MOV CX,CRT_LEN
OE83 E3 10 2615 JCXZ QUT..:J, ,
OE85 89 8000 2f)16 MaY g".paODDH
OE88 FE AD <r~P
OE~B
80
,4 ()2
2611
2618 ;.I,E HHB~A~H
as
~m
40 2619 MOV CH,04ClH
~p::>,O ~tB*,:
0~8f
PE~j ~gn 2621
2622
MOY
~ua
Rt,
AX,~X
01 ;0,1 ~~~~ !~r~~(R
O~9~ F3/ AB 2623 STOSW CLEAR THE pAGE
OF':95 2624 6~+_1:
OE95 c, 2625 RET ; RETURN TO CALLER
OE96 26<;:6 BLANK ENOP
2621
PEQ6 2628 PH_5 PRPC NEAR
OE96 Ea lbBl R 262S! CAI,.L PAL_ON
d~99 C3 2$30 RET
OE9A 2631, PH_5 ENOP
~p32
g633 ; ----.; StE I F WE ARE to SUPPORT 640 x 350 ON A 640 x 200 MODE
OE9A ~~~~ BRST...:.DET PROC NEAR
~f=>3~
~~~~ME
OS:ABSO
g~;; 50
1E
2637
2638 pUSH
AX
OS
()E~C E8 OCFE R
~~ij~
Ci\!-L DDS
PE9f M 0488 R MOV AL, I NFO_3
OEA2 1F 2641 I;'OP OS
OEA3 24 QF 2642 AND AL,OFI1
OEAS 3C 03 2643 CMP AL,03H EMUt.ATE MODE
OEI\7 74 07 ~644 JE BYES
~e g~
QE~9 2645 eM' AI,09H EMULATE MODE
OEAB 2646 JE B_YES

124 IBM EnhllficM Graphics Adapter

DEAD ,a 2647 POP AX
DEAE fa 2648 CLC
DEAF
OEBO
c' 2649
2650 B_YES:
RET

OEBO
OEBl
'a
f.
2651
2652
POP
STC
AX

OEB2 C3 2653 RET

OEB3 ~654 BRST.:...OET ENOP
2655
g656 ; _~";M" MODE SET
2657
OEB3 2658 AHO:
2659 ASSUME OS:ABSO
OE83 fA 2660 CLI
OEB4 C7 06 OlOG R 0000 E 2661 MOY WORD PTR GRX_SET, OffSET CGDOOT
OEBA 8G OE OlOE R 2662 MOY WORD PTR GRX_SET+2, CS
DEBE fa 2663 STI
OEBf 80 26 0487 R F3 2664 AND INfO,11110011B TURN Off RETRACE BIT
2665 EGA ACTIVE BIT
OEC4 '0 2666 PUSH AX SAVE
OEG5 f6 06 0487 R 02 2667 TEST INFO,2
OECA 74 2C 2668 JZ ST 1 THERE I S NO MONOCHROME
OECC Al 0410 R 2669 MOY AX-:-EQU I P_FLAG THERE I S A MONOCHROME
OECF 24 30 2670 ~ND AL,030H j CI;iECK THE EQU I PMENT fLAG
OEDl 3C 30 2671 CMP ,b.L,030H fOR MONOCHROME CALL
OED3 74 48 2672
2673
JE ST_2 i 1t i S A MONOCHROME CALL

2674 ; --~-- FALL THROUGH => REGULAR COLOR CARD SETUP

2675
OED5 C6 06 0484 R 18 2676 ~OV RQWS, 0240
OEDA C7 06 0485 R 0008 2677 M9V POINTS,8
OEEO ,a 2678 PpP AX RECOVER
OEEl 80 DE 0487 R 08 2:679 OR I ~FO, 00001000B EGA NOT ACT I VE
OEE6 3C 01 2680 CMP AI,.; 1
OEE8 76 09 2681 JBE SL7 ; WA I T fOR, RETRACE ON
OEEA 3C 04 2682 CMP AL;4 ; MODES 2,3 ONLY
OEEC 73 05 2683 JAE ST_7
OEEE 80 OE 0487 R 04 2684 OR INFO,00000100B ; DO RETRACE
OH3 2685 ST_7:
OH3 CD 42 2686 INT 42H ; OTHER ADMtER MODE CALL
OEF5 E9 219E R 2687 JMP V_RET ; BACK TO CALLER
2688
2689 ;-~--;.. AT THis POINT THERE IS NO MONOCHROME ATTACHED TO THE ADAPTER
2690
OEF8 2691 ST_1 :
OEF8 Al 0410 R 2692 MOY AX, EQU I P_FLAG j TEST THE EQU I PMENT FLAo
OHB 24 30 2693 AND AL,030H ; TO SEE IF THIS IS A
OEFO' 3C 30 2694 CMP Al,030H ; MONOCHRQ~E SETUP CALL
OEfF 75 40 2695 JHE ST_3 ; MUST BE COLOR TO CARD
2696
~697 ; ----- fALL THROUGH "'> REGULAR MONOCHROME CARD SETUP
2698
OFOl C6 06 0"8" R 18 2699 MOY ftOWS,024D
OF06 C7 06 0485 R OOOE 2700 MOV POINTS,Ol"o
OFOC ,a 2701 POP AX RECOVER
OFOO CO "2 2702 ittr 42H OTHER ADAPTER MODE CALL
OFOF C7 06 0"60 R OBOC 2703 MO" CURSOR_MOOE,OBOCH F I X PLANAR VALUE
Of15 80 OE 0487 R 08 2704 OR I NFO,8 THE EGA I S NOT ACTIVE
OflA E9 219E R 2705 JMP V...;RET BACK TO CALLER
2706
27Q7 ; -~--~ MONOCHROME SETUP TO THE ADAPTER
2708
OF1D 27M ST_2:
OFlD ,a 2710 POP AX RECOVER
OFlE '0 2711 pU~H AX SAVE
OFlF B6 03 2712 MOY OH,3
Of21 24 80 2713 AND AL,080H PICK Off niE CLEAR BIT
Of23 80 26 0481 R 7F 2714 AND INfO,07fH MASK Off THE OTHER BITS
OF28
OF2C
OF20
,.
08

24
06 0"87 R

7F
2715
2716
2717
OR
POP
AND
INFO,AL
AX
AL, q7FH
SAVE REGEN GLEAR, BIT
~ECOVER TRUE CALL VALUE
ALREADY DEALT WITH 01
OF2F 3C OF 2718 CMP AL,OfH A MONOCHROME MODE
Of31 74 02 2719 JE ST 2A 00 THIS MODE
0f33 80 07 2120 MOV AL-:-7 REGULAR MONOCHROME
Of35 2721 ST_2A:
Of35 A2 0449 R 2722 MOV CRT_MODE,AL sAVE MODE VALUE
0f38 B2 B4 2723 MOY OL, CRTC~ADDR_B I T IS 3~B~X
OF3A 89 16 0463 R 2724 MOY ADDR~6845, OX SAVE CRTC ADDRESS
Of3E EB lC 90 2725 JMP QQl CaNT I NUE THE MODE SET
2726
2727 ; ~~~~~ COLOR SETUP TO THE ADAPTER
2728
OF"l 2729 ST_3:
OF41 5. 2730 POP AX RECOVER PARAMETER VALUE
Of42
Of43
'0
B6 03
2731
2732
PUSH
MOY
AX
DH,3
SAVE IT

OF45 24 80 2733 ANO ,o;L,08qH ISOLATE REGEN CLEAR BIT

Of47 &0 26 0487 R 7F 2734 AND INFO,07fH PREPARE 1NFO BYTE
Of4C 08 06 0487 R 2735 OR INFO,AL SET IT, o~ NOT
Of 50 ,a 2736 POP AX RECOVER TRUE MODE tALL
Of 51 24 7F 2737 AND AL,07FH DONE WITH D7
Of 53 A2 0449 R 2738 MOY CRT_MODE, AL SAVE TH I S MODE
Of 56 B2 04 2739 MOY DL, CRTC_ADOR 3~D-X
Of 58 89 16 0463 R 2740 MOY AOOR_6845, OX SAVE CRTC ADDRESS
Of5c 2741 QQ1:
OF5C C7 06 044E R 0000 2742 MOY CRT_START,O SAVE START ADDRESS
OF62 c6 06 0462 R 00 2743 MOY ACTtVE_PAGE,O RESET PAGE VALUE TO ZERO
2744 ASSUME ES: NOTH I NG
OF67 B9 000& 2745 MOY CX,~ : 8 pACES OF cLiRSOR VALUES
QF6A Bf 0450 R 2746 MOY o I, OffSET CURSOR.... POSN ; OffSET
OF6D IE 2747 PUSH OS ESTABLI SH
Of6E
i)FQF
OF71
07
28 CO
f3/ AS
2748
2749
2750
POP
SUB
REP
ES
AX,AX
STOSW
°
ADORESSINO
THOSE CuRSQR LOCATIONS
CLEAR OUT SAVED VALUES
2751
OFB E8 005A R 2752 CALL MAKE_BASE
2753
DF76 26: 8A 07 2754 MOY AL, ES: [BX) GET COLUMN COUNT
0f79 2A E4 2755 SUB AH,AH ZERO HI CH BYTE
Of7B A3 01j.4A R 2756 MOY CRT_COLS,AX STORE COLUMN VALUE

Df7E
Of82
26: sA 47 01
A2 0484 R
2757
2758
2759
2760
MOY
MOY
~L.ES:[BX][11
ROWS,AL ,
: GET ROW VALUE
STORE ROW VALUE

OF85 26: 8A 47 02 2761 MOY AL,ES:(BXJ(21 ; GET THE BYTES/CHAR

DF89 2A EIj. 2762 SUB AH,AH j ZERO HIGH BYTE
OF8B A3 0485 R 2763 MOY POINTS,AX ) STORE BYTES/CHAR
2764
OF8E 26: 8B 47 03 2765 MOY AX, ES: I BX) [3) ; GET PAGE SIZE
Df92 A3 044C R 2766 MOY CRT_LEN,AX ; STORE PAGE LENGTH
2767
OF95 28 DB 2766 SUB eX,BX ; ZERO
OF97 BO 01 2769 MOY AL j 1 : MONOCHROME ALJ:'HA CHAR GEN
Df99 8A 26 0449 R 2770 MOY AH, C;RT_MODE j GET CURRENT MODE
OF9D 80 fC 07 2771 CMP AH,7 ; I SIT MONOCHROME
OFAo 74 DC 2772 JE ENTRY_2 J 9X14 fONT

August 2, 1984 IBM Enhanced Graphics Adapter 125

OFAl 60 Fe 03 2773 CMP AH,03H
OFA5 77 35 2774 JA ENTRY_,
2775
OFA7 E8 OE9A R 2776
~~~~y~~T
CALL
OFAA 72 02 2777 JC
2778
DFAC 80 02 2779 MOV AL,2 ; COLOR ALPHA CHAR GEN
OfAE 2780 ENTRY_2:
OfAE E8 lEAE R 2781 CALL CH_GEN ; LOAD ALPHA CHAR GEN
OFBl [8 OCFE R 2182 CALL 005
OFB4 SA 26 0449 R 2783 MOV AH,CRT_MOOE ; GET CURRENT MODE
orBS 80 Fe 07 2784 CMP AH,7 IS I T MONOCHROME
orBB 74 03 2785 JE FOG_IT ; 9X14 fONT
OFBD EB 10 90 2786 JMP ENTRY_'
OFCO 2787 FOG IT:
OFCO BD 0000 E 2788
- MOV SP, OffSET CGHN_FoG ; TABLE POINTER
OfC3 BB OEOO 2789 MOV aX,OEOOH ; 14 BYTES PER CHAR
OfC6 2790 FOG:
OFC6 OE 2791 PUSH CS GET THE ROM SEGMENT
OFC7 07 2792 POP ES I NTD ES
OFca 26: 88 56 00 2793 MOV DX,ES:[BPj GET THE CHAR HEX CODE
OFCC DB 02 2794 OR OX,OX ZERO = NO MORE CHARS
OFCE 74,oc 2795 JZ ENTRY_' NO MORE
OFDO 89 0001 2796 MOV eX,l DO ONE CHAR AT A TIME
om3 45 2797 ING BP MOVE TO FIRST CODE PO I NT
OF04 E8 1EF6 R 2798 CALL oO_MAP2 STORE THE CODE POINT
OFo7 83 C5 OE 2799 ADO BP,014D ADJUST BP TO NEXT CODE
OFDA EB EA 2800 JMP FOG DO ANOTHER
OFDC 2801 ENTRY_1 :
OFDC £8 ODAB R 2802 CALL SET_REGS
OFDF E8 OE55 R 2803 CALL BLANK ; CLEAR OUT THE BUFFER
OfE2 £8 OE96 R 2804 CALL PH_5
2805
2806 ASSUME DS:ABSO
OFE5 E8 OCFE R 2807 CALL ODS
OFE8 80 3E 0449 R Of 2808 CMP CRT_MODE,OFH
OFED 72 06 2809 JB MS 1
OfEF C7 06 OlOC R 0000 E 2810 MOV WORD PTR GRX_SET • OFFSET CGMN
OFf5 2811 MS_l:
OFf5 80 3E 0449 R 07 2812 CMP CRT_MODE, 7
OHA 77 09 2813 JA SAVE_GRPH
OFFC 74 4B 2814 JE SAVE_ALPH
OffE 80 3E 0449 R 03 2815 GMP CRT_MODE,3
1003 76 44 2816 JBE SAVE_ALPH
1005 2817 SAVE_GRPH:
1005 C4 lE 04A8 R 2818 LES ax, SAVE_PTR
1009 83 C3 OC 2819 AOO BX,OCH
100C 26: C4 lF 2820 LES ax, aWORD 'fTR ES: [BX)
100F 8C CO 2821 Mav AX,ES
10'1 OB C3 2822 aR AX,BX
1013 74 32 2823 JZ J4J ; JMP AHO_DONE
1015 BE 0007 2824 Mav SI,07H
1018 2825 SG_l :
1018 26: 8A 00 2826 Mav AL,ES:[BX][SI}
1016 3C FF 2827 CMP AL,OFFH
1010 74 7A 2828 JE AHO_DONE
10lF 3A 06 0449 R 2829 CMP AL, CRT_MODE
1023 74 03 2830 JE SG_2
1025 46 2831 ING 51
1026 EB FO 2832 JMP SG_l
1028 2833 SO_2:
1028 FA 2834 GLI
1029 26: 8A 07 2835 Mav AL,6YTE PTR ES: I 6X]
102C fE C8 2836 OEG AL
102E A2 0484 R 2837 Mav ROWS,AL
1031 26: 86 47 01 2838 MOV AX,WORD PTR ES:[BXJ[l]
1035 A3 0485 R 2839 Mav POINTS,AX
1038 26: 86 47 03 2840 Mav AX,WORD PTR ES:[BXJ[3]
103C A3 OlOC R 2841 MOV WORD PTR GRX_SET ,AX
103F 26: 86 47 05 2842 MaV AX,WORD PTR ES:[BXJ[5[
1043 A3 OlOE R 2843 MOV WORD PTR GRX_SET + 2, AX
1046 FB 2844 STI
1047 2845 J4J:
1047 EB 50 2846 JMP SHORT AHO_DONE
1049 2847 SAVE_ALPH:
1049 C4 lE 04A8 R 2848 LES BX, SAVE_PTR
1040 83 C3 08 2849 Aao 6X,08H
1050 26: C4 I f 2850 LES BX,DWORD PTR ES: I BX]
1053 8C CO 2851 MOV AX,ES
1055 06 C3 2852 OR AX,BX
1057 74 40 2853 JZ AHO_DONE
1059 BE 0006 2854 MOV SI,OBH
105C 2855 SA_l:
105C 26: 8A 00 2856 Mav AL,ES:(BXllSI]
105F 3c FF 2857 GMP AL,OffH
1061 74 36 2858 Jf AHO_DONE
1063 3A 06 0449 R 2859 eMP AL,CRT_MODE
1061 14 03 2860 JE SA_2
1069 46 2861 INC 51
106A E6 fO 2862 JMP SA_'
106C 2863 SA_2:
106C 26: 8A 27 2864 Mav AH, ES: I ax]
106F 26: 8A 47 01 2865 Mav AL,ES:IBXj(l]
1013 26: 8B 4f 02 2866 MOV CX,ES:[BX1!2j
1077 26: 8B 57 04 2867 MOV DX,ES:(BXJ[4]
1076 26: 8B 6F 06 2868 Mav BP,ES:(BX1!6]
101f 26: 8E 47 08 2869 Mav ES,ES:(BXJ[e]
1083 53 2870 PUSH BX
1084 88 08 2871 Mav BX,AX
1086 B8 1110 2812 Mav AX,1"OH
1089 CD 10 2873 I NT 10M
108B 5B 2814 POP BX
108C 26: 8A 47 OA 2815 MOV AL,ES:(BX](OAH]
1090 3C FF 2876 CMP AL,OFFH
1092 74 05 2877 JE AHO_DONE
1094 FE C8 2818 DEC AL
1096 A2 0484 R 2819 Mav ROWS,AL
2880
2881 ;~-~-~ SET THE LOW RAM VALUES FOR COMPATIBILITY {JD8 AND 309 SAVE BYTES)
2882
1099 2883 AHO_DONE:
1099 E8 OCFE R 2884 CALL ODS
109C 80 3E 0449 R 07 2885 eMP CRT_MOOE,7
10Al 71 lE 2886 JA DNDCS
lOA3 BB 10ce R 2887 Mav BX,OfFSET COMPAT_MODE
10A6 AO 0449 R 2888 Mav AL,CRT_MODE
10A9 2A E4 2889 SUB AH,AH
10AB 03 08 2890 ADD BX,AX
lOAD 2E: 8A 07 2891 MOV AL,CS:(BX]
lOBO A2 0465 R 2892 MOV CRT_MODE_SET ,AL
10B3 BO 30 2893 Mav AL,030H
10B5 80 3E 0449 R 06 2894 eMP CRT_MODE,6

~~~~~~H
10BA 75 02 2895 JNE
10BC BO 3F 2896 Mav
lOBE 2897 DO_PAL:
lOBE A2 0466 R 2898 Mav CRT_PALETTE, AL

126 IBM Enhanced Graphics Adapter August 2, 1984

10Cl 2899 DNDCS:
10Cl 8B DE 0460 R 2900 MOY CX1 CURSOR_MODE
10C5 EB 28 90 2901 JMP AHI
2902
10C8 2903 COMPAT_Mg~E LABEL BYTE
10ca 2C 28 2D 29 2A 2E 2904 02CH, 028H, 02DH, D29H, 02AH, 02EH
10CE IE 29 2905 DB 01EH,029H
2906
2907 C INCLUDE Vl-,. INC
2908 C SUBHl Vl-,.INC
2909 C PAGE
2910 C
1000 2911 g CAlC_CUR~~~UME PROC NEAR
2912 DS:ABSO
1000 80 FO 00 2913 C CMP CH,O CHECK FOR FULL HEIGHT
2914 C JNE NORMAL CHECK
1003
1005
75
FE
0'"
Cl 2915 C INC g~_' ADJUST END VALUE
1007 EB OA 2916 C JMP SHORT
1009 2917 C
1009 FE Cl 2918 C INC eL ADJUST FOR EGA REG I STERS
100B 3A OE 0485 R 2919 C eMP CL, BYTE PTR PO I NTS WI LL IT WRAP
100F 72 02 2920 JB NO, ITS OK
10El 2A C9 2921
C
C SUB g~~gIOUT EGA METHOD FOR CURSOR END
10E3 2922 C CAlC_OUT~USH
10E3 51 2923 C ex SAVE CURSOR TYPE VALUE
10E4 2A CO 2924 C SUB CL,CH ENO - START
10E6 80 F9 10 2925 C CMP CL,010H LOW NIBBLE EQUAL
10E9 59 2926 C PDP cx RESTORE
tOEA 75 02 2927 C JNE COMP_4
10EC FE Cl 2928 C INC eL ADO 1 FOR CORRECT CURSOR
10EE 2929 C
10EE C3 2930 C BACK TO CALLER
10EF 2931 C ENOP
2932 C
2933 C ~ -SET:CT;;~-----S~T-~~~;~~-T;;E----------------------------------
2934 e
2935 C ; THIS ROUTINE SETS THE CURSOR VALUE
2936 C ; INPUT
2937 e ; (CX) HAS CURSOR VALUE CH-START LINE, CL-STOP LINE
2938 e ; OUTPUT
2939 e .; NONE
'" 0004
2940
2941
C
C
; ----------------------------------------------------------------
EOU
10EF 2942 e AH1:
2943 C ASSUME DS:ABSO
10EF 8'" OA 2944 e MDV AH,C_CRSR_START CRTC REG FOR CURSOR SET
10F1 89 OE 0"'60 R 2945 C MOV CURSOR_MOOE, ex SAVE IN DATA AREA
10F5 F6 06 0"'87 R 08 2946 e TEST INFO,8 EGA ACTIVE BIT
10FA 75 33 2947 e JHZ DO_SET 0=EGA 1=OLD CARDS
1
2948 e
2949 e ;----- THIS SECTION WILL EMULATE CURSOR OFF ON THE EGA
2950 e
10FC 8A C5 2951 e MOV AL,CH GET START VALUE
10FE 2'" 60 2952 e AND AL,060H TURN OFF CURSOR?
1100 3C 20 2953 e eMP AL,020H TEST THE BITS
1102 75 05 e
~~:O~EOOH
2954 JNE SK I P CURSOR Off
1104 89 lEOO 2955 e MOV EMULATE CURSOR OFF
1107 EB 26 2956 e JM' SHORT DO_SET
2957 e
2958 e ;----- THIS SECTION: ADJUST THE CURSOR AND TEST FOR ENHANCED OPERATION
2959 C
"09 2960 e
1109 F6 06 0487 R 01 2961 e TEST INFO,l CURSOR EMULATE BIT
e
g~'f~~DE,3
110E 75 1F 2962 JHZ O=EMULATE, 1=VALUE AS-IS
1110 80 3E 0449 R 03 2963 e CMP POSS I BlE EHULA T I ON
e
i~~~;DET
1115 77 15 2964 JA NO, SET THE CURSOR TYPE
1117 E8 OE9A R 2965 e CALL SEE I F EMULATE MODE
",A 73 10 2966 e JHC NOT EMULAT I NG
l11C 80 FO 04 2967 e CMP CH,CUT_OFF TEST START
111F 76 03 2968 e JBE AH1_B SKI P ADJUST
1121 80 C5 05 2969 e ADD CH,5 ADJUST
1124 2970 e
1124 80 F9 04 2971 e CMP CL,CUT_OFF TEST END
1127 7603 2972 e JBE AH1_S SKI P ADJUST
1129 80 Cl 05 2913 e ADD CL,5
112C 2974 C
112C E8 1000 R 2975 e CALL CALC_CURSOR ; ADJUST END REGISTER
112F 2976 e
112F E8 1135 R 2977 e CALL MI. OUTPUT CX REG
1132 E9 219E R 2978 e JMP V_RET RETURN TO CALLER
2979 e
2980 e ; ----- TH I S ROUT I HE OUTPUTS THE ex REG I STER TO THE CRTC REGS NAMED IN AH
2981 e
1135 2982 C M16:
1135 88 16 0463 R 2983 e MOV OX, AOOR_6845 ADDRESS REG I STER
1139 8A C5 2984 e MOV AL,CH DATA
113B E8 0015 R 2985 e CALL ~~T_OX OUTPUT THE VALUE
113E FE C4 2986 e INC NEXT REGISTER
1140 8A Cl 2987 e MOV AL,CL SECOND DATA VALUE
1142 E8 0015 R 2988 e CALL OUT_OX OUTPUT THE VALUE
1145 C3 2989 e RET ALL DONE
2990 e
2991 e ; ----------------------------------------------------------------
2992 e POSITION
e ~ r~~~E~~R~~C~ ~~~~!~iE~A~~U~~E:L~~~ ~~g~N BUFFER
2993 C
2994
2995 e ; INPUT
2996 C ; AX = ROW, COLUMN POSITION
2997 e ; OUTPUT
2998 e ; AX = OFFSET OF CHAR POSITION IN REGEN BUFFER
2999 e f,OSiTioN--------;~~~----NEA~----------------------------- .. -------
1146 3000 e
1146 53 3001 e PUSH BX ; SAVE REG I STER
1147 88 OS 3002 C MOV BX,AX
1149 8A C4 3003 C MeV AL,AH ROWS TO AL
114B F6 26 044A R 3004 e ~g~ :~;~H PTR CRT_COlS DETERMINE BYTES TO ROW
114F 32 fF 3005 e ZERO OUT
1151 03 C3 3006 e ADD AX, BX ADD I N COLUMN VALUE
"53 01 EO 3007 e SAL AX, 1 * 2 FOR AlTR I BUTE BYTES
1155 5B 3008 e POP BX RESTORE REG I STER
1156 C3 3009 e RET
1157 3010 C POSITION ENDP
3011
3012
3013
e
C
C
; -_ .. _--------------_ .. _------_ .. __ .. _----------_ .... _----_.-----------
SET_CPOS SET CURSOR POSITION
3014 e THIS ROUTINE SETS THE CURRENT CURSOR POSITION TO THE
3015 e NEW X-Y VALUES PASSED
3016 C INPUT
3017 C OX .. ROW,COLUMN OF NEW CURSOR
3018 C : : OUTPUTBH - DISPLAY PAGE OF CURSOR
3019 e
3020 e CURSOR IS SET AT CRTC IF DISPLAY PAGE IS CURRENT
3021 e DISPLAY

"57
3022
3023
e
e iH2;-------------------------------------------------------------
1157 E8 1150 R 3024 C CALL

August 2, 1984 IBM Enhanced Graphics Adapter 127

'1SA E9 219E R 3025 c JMP
3026 e
1150 3027 e SET_CPOS~OV
1150 8A CF 3028 e CL,BH
11SF 32 ED 3029 e XOR CH,CH ; ESTABl I SH LOOP COUNT
1161 01 £1 3030 e SAL CX,l ; WORD OFfSET
1163 8B Fl 3031 e MOV SI,CX ; USE I NOEX REG I STER
1165 89940450 R 3032 e MOV [SI+OffSET CURSOR_POSNI,OX ; SAVE THE PO INTER
1169 38 3£ 0462 R 3033 e eMP ACTIVEJAGE,BH
1160
116F
7505
8B C2
3034
3035
e
e
JNZ
MOV
"17
AX,DX
SET_CPOS_RETURN
GET ROW/COLUMN TO AX
1111 £8 1115 R 3036 e CALL M18 CURSOR_SET
1114 3037 e M17: SET_CPOS_RETURN
1174 C3 3038 e RET
3039 c
3040 e ;-~~.- SET CURSOR POSITION, AX HAS ROW/COLUMN FOR CURSOR
3041 c
1175 3042 C M18 PROC NEAR
1175 £81146 R 3043 e CALL pas IT I ON ; DETERMt NE LOC I N REGEN
1178 88 (;8 3044 e MOV CX,AX
i11A 03 OE 044E R 3045 e ADD eX,CRT_START ; ADO I N THE START ADOR
3046 e fOR TH I S PAGE
117E 01 F9 3047 e SAR eX,l / 2 FOR CHAR ONLY COUNT
11M 84 ot 3048 e HOV AH, C_CRSR_LOC_HGH REG I STER NUMBER FOR CURSOF
1182 E8 1135 R 3049 e CALL H16 SET VALUE TO CRTC
11 85 C3 3050 e RET
1166 3051 C M18 ENOP
3052
3053
e
c ; -_ ...... _-_ ............ ...... _.. _--_ ............ __ .. _-----_ ........ _.... --_ .... _--- -------
~-

READ_C¥~~~R ROUT I NE
3054 C
3055 e ; READS THE CURRENT CURSOR VALUE f=ROM
3056 e :,', I NPUT MEMORY AND SENDS IT BACK TO THE CALLER
3057 e
3058 e BH - PAGE OF CURSOR
3059 e ":, OUTPUT
3060
3061
e
e : ~3~RE~~Lg~~sg~ ~~~ECURRENT CURSOR POS I T ION
g~

1186
3062
3063
c
e
iHi;-.. -.. -.... -............. -.. --.. .. -.. ------.. -.. -.. --.... ---..
~- .... -.... -.. -
------~---

1186 8A DF 3064 e MOV BL, BH ; PAGE VALUE

1188 32 FF 3065 e xoR BH,BH ; ZERO UPPER BYTE
118A 01 t:I 3066 e SAL eX.1 ; WORD OFFSET
118C 8B 97 0450 R 3067 e HOV DX,I ex + OFFSET CURSOR_POSN I ; GET CURSOR FOR TH I S PAGE
1190 sa OE 0460 R 3066 e HOV cx. CURSOR~MODE ; GET THE CURSOR MOOE
1194 SF 3069 e 'OP 01
11~5 5£ e POP
1196
1197
1198
S13
58
58
3070
3071
3072
3073
e
e
e
'OP
POP "ox
AX
AX
; DISCARD CX
; DISCARD OX
'OP
1199 1F 3074 e POP OS
119A 01 3075 e POP ES
119B 50 3076 e POP BP
119C CF 3071 e IRET
3078 e
3019 e ; ........ - READ LIGHT PE:N POSITION
3080 e
1190 3081 e AH4:
1190 AO 0449 R 3082 e MOV AL,CRT_MODE
llAO 3G 07 3083 e OMP AL,07H
11A2 77 37 3084 e JA REAO_LPEN
3085 e
11 A4 F6 06 0487 R 02 3086 e TEST I NFO,2
l1A9 74 07 3087 e JZ EGA~I S_COLOR
3088 e
3089 e ; ----- MONOCHROME HERE (MONoe BIT 1)
3090 e
llAB 3C 07 3091 e eMP AL,07H
llAO 742C 3092 e JE REAO_.LPEN
llAF EB as 90 3093 e JHP OLD_LP
3094 c
3095 e ;---- .. EGA IS COLOR HERE (MONOC BIT 0)
3096 c
l1B2 3097 e EGA_I S_COLOR:
l1B:? 3006 3098 e eMP AL,06H
119& 1625 3099 e J.E REAO_LPEN
1186 3100 e
l1B6 CO 42 3101 e INT 42" ; CALL EX I ST I NG CODE
1188 SF g102 e POP 01
11M 5E 3103 C POP 51
ilM 63 e4 06 3104 c AOD SP,6 ; DISCARD SAVED BX,eX,DX
liat! 1F 3105 c PoP OS
1113E 07 3106 e POP
l1BF 50 ]107 e "
-"
'OP
llca ct 3108 e IRtT
3109
3110
3111
e
e ; ...... " . ..... -....
e LIGHT PEN
~ -~- ~~ - - -
.. -........ .................. .............. -.. .. .. .. _...................... _--
-~

3112 e THIS ROUTINE TESTS THE LIGHT PEN SWITCH AND THE LIGHT
3113 e PEN TitIGOER. Ir ~orH ARE SET, THE LOCATION OF THE LIGHT
3114 e ~, r~~0~~A~T6~R7~N~fDE~rH£RwISE, A RETURN WITH NO
3115 e
3116 e ON E:xn
3117 o , (AHl '" 0 IF NO LICHT PEN INf'ORMATION IS AVAILABLE
3118 e ; BX, CX, oX ARE: otSTROYED
e
(AH) '" 1 nH~br~T,/~~W!~ot~~~L~~L~URRENr LIGHT PEN
3119
3120 e :,:
3121 e POSIT I ON
3122 o (CH) '" I\ASTE:R POS I T I ON (OLD MODES)
3123
3124
e
e ; {........ - --_ - l~~l ~ :~~+E~u~~~lr+O~I~~[WH~~?i~~TAL
-- -_ ....
...... ...... ........ - ............ _.......... -...... _.... __ _.. _...... _..POSITION
_...... -----
3125 c
3126 e ASSUME CS: CODE, DS:ABSO
3127 e ;-........ SUBTRACT_TABLE
l1el 3128 o V1 LABEL BytE
l1Cl 06060707 05 05 3129 e Os OQ6H, 006H, D07H, OD7H, D05H, 005H ; 0-5
l1C7 040$ 00 00 00 00 3130 e DB 004H, D05H, OOOH, OOOH, OOOH, OOOH ; 6 .. B
'1eo 0() 05 06 04 04 04 3131 c DB 0001'1, 005H, 006H,004H, 001lH, 004H ; e .. l1
1103 040606040704 3132 e DB 001lH, 006H, 006H, OD4H, 007H, 004H ; 12-11
1109 07 04 3133 e DB 007H,004H J 18-19
3134 e
110B 3135 e PROC NEAR
3136 e
3137 e ; .. ~ .. - .. WAIT FOR LIGHT PEN TO BE DEPRESSED
3138 e
110B sa 16 01163 R 3139 e HOV OX, ADDR_6845 GET BASE ADDRESS OF 6845
110r 83 C2 06 3140 e ADD DX 6 j PO I NT TO STATUS REG I STER
11 E2 EC 3141 e IN AL,OX GET STATUS REGISTER
11E3 A8 04 3142 e TEst AL,4 ; TEST LIGHT PEN SWITCH
11E5 B4 00 3143 e MOV AH,O J SET NO LIGHT PEN RETURN
l1E7
11E9
14
E9
03
1291 R
3144
3145
e
e
JZ
JMP
v.
v6
; CODE
J NOT SET. RETURN
3146 e
3147 e ;-_ ...... NOW TEST fOR LIGHT PEN TRIGGER
3148 e
l1EC 3149 C V9:
11EC A8 02 3150 e lEST AL.2 J rEST L I CHi PEN TR I GGER

128 IBM Enhanced Graphics Adapter August 2, 1984

llEE 75 03 3151 C JNZ V7A REf URN WITHOUT RESETTING
3152 C TRIGGER
lHO E9 129B R 3153 C JMP V7 EX 1T LI OHT PEN ROUT] NE
3154 C
3155 C ;_~M __ TRIGGER HAS BEEN SET .. READ THE VALUE 1N
3156 C
lH3 3157 C V1A:
,
l1F3 84 10 3158
3159
3160
3161
C
C
e
,.. _.. _. MOV AI-!, 16 II OHT PEN REG I STERS
INPUT REGS pOiNTED TO BY AH, AND CONVERT Ttl ROW COLUMN IN OX
e
lH5 88 16 0463 R
8A 04
316~ e MOV ox,AODlC6845 ADDRESS REG I STER
l1F9 3163 0 MOV AL,AH REG I STER TO READ
lHB
l1FC
lHD
4.
EE

,0
3164
3165
3166
0
C
C
OUT
INC
PUSH
DX,AL
OX
AX
SET IT UP
DATA REGISTER
1HE EO 3167 C IN AL,DX GET THE VALUE
llFF SA [8 3168 C MOV CH,AL SAVE IN CX
1201 5. 3169 C POP AX
1202 4A 3170 C OEC OX ; ADDRESS REG I STER
1203
1205
1207
FE C4
8A C4
EE
3171
3112
3173
C
C
C
INC
MOV
OUT
AH
AL,AH
DX,AL
, SECOND OAtA REGI aIER
1208 42 3174 C INC OX J POINT TO DATA REGISTER
1209 EC 3175 C IN AL,DX J on THE 2ND DATA VALUE
120A 8A E5 3176 C MOV AH,CH I AX HAS I NPUT VALUE:
3177 C
3178 C ; --_ .... AX HAS THE VALUE READ I N FROM tHE 6845
3179 C
120C 8A lE 0449 R 3180 e MOV BL, CRT_MODI::
1210 2A FF 3181 e SUB BH,8H MODE VALUE TO ax
1212 2E: 8A 9F l1Cl R 3182 C MOV BL,CS:V1IBXI AMOUNT TO SUBTRACT
1217 28 C3 3183 C SUB AX,BX TAKE I T AWAY
1219 8B 1E 044E R 3184 C MOV BX,CRT_START SGREEN At:)D~ESs
1210 01 EB 3185 C SH. BX,l DiviDE BV 2
121F 2B C3 3186 C SUB AX, ax ADJUST Tt) ZERO START
1221 79 02 3187 C JNS V2 IF POSITIVE, GET MOOE
1223 2B CO 3188 C SUB AX,AX <0 PLAYS AS 0
3189 G
3190 e 1-........ DETERMINE MODE OF OPERATION
3191 C
1225 3192 C V2: DETERM I NE MODE
1225 Bl 03 3193 C MOV CL,3 SET *8 SHIFT COUNT
1227 80 3E 0449 R 04 3194 C eMP CRT_MODE,4 , GRAPH I cs OR ALpHA
122C 72 40 3195 C JB V4 i ALPHA_PEN
122E 80 3E 0449 R 07 3196 C CMP CRT_MODE,7
1233 7446 3191 C JE V4 i ALPHA_liEN
3198 C
1235 80 3E 0449 R 06 3199 C CMP CRT~MODE; 06H
123A 77 28 3200 C JA VO
123C 7S 02 3201 C JNE VO'
123E 01 f8 3202 e SH. AX,1
3203 G
3204 C ; - ....... OLD GRAPH I CS MODES
3205 G
1240 3206 G VflX;
1240 B2 28 3207 C MOY DL j 40 DIVISOR FOR GRAPHICS
1242 F6 F2 3208 e OIV DL ROW(Al) AND GiJLUMN(AH}
3209 C AL RANGE 0-99;
3210 e AH RANGE 0"'39
3211 e ,"---" DETERMINE GRAPHIC ROW POSiTION
3212 e
1244 8A f8 3213 e MOY CH,AL SAVE ROW VALUE iNCH
1246 02 ED 3214 C AOO CH,CH *2 FOR EVEN/ODD FIELD
1248 8A DC 321~ e MOV BL,AH COLUMN VALUE TO BX
124A 2A ff 3216 e SUB BH,BH *8 FOR MED I UM RES
124C 80 3E 0449 R 06 3217 e eMP CRT_MODE, 6 MEDIUM OR HIGH RES
1251 75 04 3218 C JNE V3 NOT~HIGH_RES
1253 B1 04 3219 C MOV CL,4 SH I FT VALUE FOR HIGH RES
1255 DO E4 3220 C SAL AH,1 COLUMN VALUE *2 FOR HIGH RES
1257 3221 G V3: NOT _H I GH_RES
1257 D3 f3 3222 C SHL BX,CL *16 FOR HIGH RES
3223 C
3224 C ; ----- OETERM I NE ALPHA CHAR POSIT ION
3225 C
1259 8A 04 3226 C MOV DL,AH ; COLUMN VALUE FOR RETURN
125B 8A FO 3227 C MOV DH,AL : ROW YALUE
1250 DO EE 3228 e SH' DH,1 ; DIVJOE BY.4
125F DO EE 3229 C SH. DH,l ; FOR VALUE: iN 0-24 RANGE
1261 EB 2C 90 3230 G JMP V5 ; LIGHT_PEtLRETURN_SET
1264 3231 C V8:
3232 C
3233 G ;----- NEW GRAPHICS MODES
3234 e
1264 99 3235 e CWO PREPARE TO 0 I V I DE
1265 F7 36 044A R 3236 e DIV CRT .COLS AX "" ROW. ox "" COLUMN
1269 fl8 DA 3231 C MOV BX,OX SAVE REMA I NOEA.
126B 03 E3 3238 G SAL aX,CL p[L COLUMN
126D 88 c8 3239 e MOV eX,AX PEL ROW
126F 52 3240 e PUSH OX SAVE FROM i1lVIDE
1270 99 3241 e CWO PREPARE: TO blVIDE
1271 F7 36 0485 R 3242 C OIV Po I NTS 01YIDE BY BYTES/CHAR
1275 3243
~~X~X~~ER
5A e POP OX
1276 8A FO 3244 C MOV DH,AL ROW
1278 EB 15 90 3245 G JMP V5
3246 e
3247 G ; --'--- ALPHA MODE ON LI GHT PEN
3248 C
1278 3249 C V4: ; ALPHA PEN
127B f6 36 044A R 3250 C OIV BYTE PTR CRT_COLS ; ROW,COLUMN VALUE
127r SA fO 3251 C MOV DH,AL ; ROWS TO DH
1281 8A D4 3252 C MOV DL,AH ; COLS TO DL
1283 flA DC 3253 C MOV BL,AH ; COLUMN VALUE
1285 32 Ff 3254 C XO. BH,BH ; 10 BX
1287 03 E3 3255 C SAL BX,CL
1289 F6 26 0485 R 3256 C MUL BYTE PTR PO I NTS
1280 fiB C8 3257 C MOV CX,AX
128F 3258 C V5: LJ GHT rEN iH:TUR~ _SET
128F B4 01 3259 C MOV AH,l INDICATE EYERt~ING SEt
§~e~TRt¥~ft~E~~~~E
1291 3260 C V6:
1291 52 3261 e PUSH DX
3262 G IN CASE _
1292 8B 16 0463 R 3263 e MOV DX.At)iJR 6845
1296 83 C2 07 3264 e ADO (lX; 7 -
1299 EE 3265 e OUT ox.Al
3266 e
129A 5A 3261 G POP OX
129B 3~68 G V11
129B 5F 3269 C POP 0;
129C 5E 3270 C POP 51
1290 113 C4 06 3271 C ADD sl>,6 OiSCARD SAVED ex,cx,ox
12AO
12A1
12A2
"
07
50
Of
3272
3273
3214
C
C
C
POP
'0'
pOP
OS
ES
S.
12A3 3215 (j I RET
12A4 3276 C REAO.... lPEN lSNDfi

August 2, 1984 IBM Enhanced Graphics Ad.apter 129

 3217
3278
3279 ;-;m:O,sp:PAGE---------sELEcT-AcTlvE-OI5PLAY-PAGE---------------
3280 ; THIS ROUTINE SETS THE ACTIVE DISPLAY PAGE, ALLOWING
3281 ; FOR MULTIPLE PAGES OF DISPLAYED VIDEO.
3282 ; INPUT
3283 , Al HAS THE NEW ACTIVE DISPLAY PAGE
3284 ; DUTPUT
; THE CRTC IS RESET TO DISPLAY THAT PAGE
12A4
3285
3286
3287
itt;:;-------------------------------------------------------------
12A4 A2 0462 R 3288 MOY ACT I VE_PAGE, Al ; SAVE ACT I VE PAGE VALUE
12A7 8B OE 044C R 3289 MOY ex, CRT_lEN ; GET SAVED LENGTH OF
3290 ; REGEN BUfFER
12AB 98 3291 CBW ; CONVERT AL TO WORD
lZAC 50 3292 PUSH AX ; SAVE PAGE VALUE
12AD F7 E1 3293 MUl CX ; DISPLAY PAGE TIMES
3294 ; REGEN LENGTH
12AF A3 044E R 3295 MOV CRT_START, AX ; SAVE START ADDRESS FOR
3296 ; LATER REQU I REMENTS
1282 8B C8 3297 MOV CX,AX ; START ADDRESS TO CX
1284 8A 1E 0449 R 3298 MOV Bl, CRT_MODE
1288 80 F8 07 3299 CMP Bl,7 DO NOT DIVIDE BY TWO
12BB 17 02 3300 JA AOP_'
12BD 3301
12BD 01 F9 3302 SAR CX,1 ; ! 2 FOR CRTC HANDL I NG
12Bf 3303
12BF 84 DC 3304 MOV AH, C_STRT_HGH ; REG FOR START ADDRESS
12C1 E8 1135 R 3305 CAll M16
12C4 58 3306 POP 8)( ; RECOVER PAGE VALUE
12C5 01 E3 3307 SAL BX,1 ; *2 FOR WORD OFFSET
12C7 88 87 0450 R 3308 MOV AX,{BX + OFFSET CURSO~POSN] ; GET CURSOR FOR TH I S PAGE
12CB E8' 175 R 3309 CAll M18 ; SET THE CURSOR POSITION
12CE E9 219E R 3310 JMP V_RET
3311
3312 SUBHl
3313
3314 INCLUDE VSCROll.INC
3315 SUBHl VSCROll. INC
3316 PAGE
3317
1201 3318 FlTA PROC NEAR CHECK FOR SCROll COUNT
1201 50 3319 PUSH AX
1202 8A E6 3320 MOV AH,DH lOWER ROW
1204 2A E5 3321 SUB AH,CH UPPER ROW
1206 FE C4 3322 INC AH NUMBER TO SCROLL
1208 3A EO 3323 CMP AH,Al SAME AS REQUESTED
120A 58 3324 POP AX
12DB 75 02 3325 JNE LTA
1200 2A CO 3326 SUB Al,Al ; YES, SET TO 0 FOR BLANK
120F 3327 lTA:
12DF C3 3328 RET
12ED 3329 FlTA ENoP
3330
12EO 3331 CRANK PROC NEAR ; MOVE ROWS OF PELS UP
12ED 53 3332 PUSH BX
3333 ASSUME oS:A8S0
12Et lE 3334 PUSH OS ; SAVE DATA SEGMENT
12E2 E8 OCFE R 3335 CAll ODS ; SET DATA SEGMENT
12E5 8B tE 044A R 3336 MOV 8X,CRT_COlS
12E9 If 3337 POP OS
12EA 3338 CRANK_A:
12EA 51 3339 PUSH CX ; SAVE MOVE COUNT
12E8 8A CA 3340 MOV Cl,OL ; COLUMN COUNT
12ED 2A ED 3341 SUB CH,CH ; CLEAR HIGH BYTE
12EF 56 3342 PUSH 81 ; SAVE POINTERS
12FO 57 3343 PUSH 01
12F1 F3! A4 3344 REP MOVS8 MOVE THAT ROW
12F3 5F 3345 POP 01 RECOVER PO INTERS
12F4 5E 3346 POP SI
12F5 03 F3 3347 AOO SI,BX NEXT ROW
12F7 03 FB 3348 AOO DI,BX NEXT ROW
12f9 59 3349 POP CX REGOVER ROW COUNT
12FA E2 EE 3350 LOOP CRANK_A DO MORE
12FC 5B 3351 POP ax
12FD C3 3352 RET RETURN TO CAllER
12fE 3353 CRANK ENOP
3354
12FE 3355 CRANK_4 ~~~ NEAR ; MOVE ROWS OF PELS DOWN
12FE 53 3356 ax
3357 ASSUME DS:A8S0
12FF lE 3358 PUSH OS ; SAVE DATA SEGMENT
1300 E8 OCFE R 3359 CALL DDS ; SET DATA SEGMENT
1303 8B lE 044A R 3360 MOV BX, CRT_COlS
1307 1F 3361 POP OS
1308 3362 CRANILB:
1308 51 3363 PUSH CX ; SAVE MOVE COUNT
1309 8A CA 3364 MOV Cl,DL ; COLUMN COUNT
130B 2A ED 3365 SUB CH,CH ; CLEAR HIGH BYTE
1300 56 3366 PUSH SI ; SAVE POINTERS
130E 57 3367 PUSH 01
'30F F3! A4 3368 REP MOVSB ; MOVE THAT ROW
1311 5F 3369 POP 01 ; RECOVER PO INTERS
1312 5E 3370 POP SI
1313 2B F3 3371 SUB SI,BX ; NEXT ROW
1315 2B FB 3372 SUB ~,BX ; NEXT ROW
1317 59 3373 POP ; RECOVER ROW COUNT
1318 E2 EE 3374 lOOP CRANK_B ; DO MORE
131A 5B 3375 POP . ax
131B C3 3376 RET ; RETURN TO CALLER
131C 3377 CRANK_4 ENDP
3378
131C 3379 PART_' PROC NEAR ; FilL ROW AFTER SCROLL
13tC 52 3380 PUSH OX
1310 B6 03 3381 MOV DH,3
131F B2 C4 3382 MOV Dl,SEQ..ADDR ; SEQUENCER
1321 B8 020F 3383 MOV AX,020FH ; MAP MASK
1324 E8 0015 R 3384 CALL g~T_DX ; All MAPS ON
1327 5A 3385 POP
1328 2B CO 3386 SUB AX,AX ; ZERO
132A 8A CA 3387 MOV Cl,Dl ; COLUMN COUNT
132C 2A ED 3388 SUB CH,CH
132E 57 3389 PUSH 01 ; SAVE POINTER
132F F3! AA 3390 REP STOSB ; CLEAR ONE ROW OF PELS
1331 5F 3391 POP 01 ; RECOVER PO INTER
1332 8A C6 3392 MOV Al,DH ; GET COLOR VALUE
1334 52 3393 PUSH OX
1335 86 03 3394 MOV OH,3
1337 B2 C4 3395 MOV DL,SEQ..AODR ; SEQUENCER
1339 84 02 3396 MOV AH,02H ; MAP MASK
133B E8 0015 R 3397 CALL g~T_DX ; SET TH E COLOR
133E 5A 3398 POP
133f eo H 3399 MOV Al,OFFH ; ALL BITS ON
1341 8A CA 3400 MOV Cl,Ol ; COLUMN COUNT
1343 57 3401 PUSH 01 ; SAVE POINTER
1344 F3! AA 3402 REP STOSB ; TURN ON THOSE BITS IN

130 mM Enhanced Graphics Adapter August 2, 1984

 3403 C ENABLED PLANES
1346 ,F 3404 C POP 01 RECOVER PO INTER
1341 C3 3405 C RET RETURN TO CALLER
1348 3406 C ENDP
3407 C
1348 3408 C PROC NEAR
1348 86 03 3409 C MOV OH,3
134A 82 C4 3410 C MOV DL, SEQ_ADoR ; SEQUENCER
134C 88 020F 3411 C MOV AX,020FH ; MAP MASK, ALL MAPS
134F E8 0015 R 3412 C CALL OUT_OX , ENABLE THE MAPS
1352 C3 3413 C RET ; RETURN TO CALLER
1353 3414 C EHOP
3415 C
1353 3416 C PROC NEAR BLANK FOR SCROLL UP
1353 1E 3417 C PUSH OS SAVE DATA SEGMENT
3418 C ASSUME DS:ABSO
1354 E8 ceFE R 3419 C CALL DDS ; GET LOW MEMORY SEGMENT
1351 8A F7 3420 C MOV DH,BH ; ATTRIBUTE FOR BLANK LINE
1359 2A FF 3421 C SUB BH,BH ; CLEAR HIGH BYTE
135B 50 3422 C PUSH AX ; SAVE
135C 52 3423 C PUSH OX ; SAVE BECAUSE OF MULTI PLY
1350 8B C3 3424 C MOV AX,ex ; ROW COUNT
135F f7 26 0485 R 3425 C MUL POINTS ; CHARACTER HEIGHT
1363 8B D8 3426 C MOV BX,AX ; NET VALUE TO BX
1365 5A 3427 C POP OX ; RECOVER
1366 58 3428 C POP AX
3429 C
1367 1F 3430 C POP OS
3431 C ASSUME OS: NOTH I NG
1368 3432 C 513:
1368 E8 131C R 3433 C CALL BLANK OUT ROW WITH COLOR
3434 C ASSUME
136B 1E 3435 C PUSH SAVE SEGMENT
136C E8 OCFE R 3436 C CALL LOW MEMORY SEGMENT
136F 03 3E 044A R 3437 C ADD , NEXT ROW
1373 1F 3438 C POP ; RECOVER
1374 4B 3439 C DEC ; NEXT
1375 75 Fl 3440 C JNZ ; DO MORE
1377 E8 1348 R 3441 C CALL
137A C3 3442 C RET ; RETURN TO CALLER
137B 3443 C ENOP
3444 C
137B 3445 C BLNIC4 • PROC NEAR ; BLANK FOR SCROLL DOWN
1378 1E 3446 C PUSH OS ; SAVE DATA SEGMENT
3447 C ASSUME DS:A8S0
137C E8 OCFE R 3448 C CALL DDS ; GET LOW MEMORY SEGMENT
137F 8A F7 3449 C MOV DH,BH ; ATTR I BUTE FOR BLANK LI NE
1381 2A FF 3450 C SUB BH,BH ; CLEAR HIGH BYTE
1383 50 3451 C PUSH AX ; SAVE
1384 52 3452 C PUSH OX ; SAVE BECAUSE OF MULTI PLY
1385 8B C3 3453 C MOV AX,BX ; ROW COUNT
1387 F7 26 0485 R 3454 C MUL POINTS ; CHARACTER HEIGHT
138B 8B D8 3455 C MOV BX,AX ; NET VALUE TO BX
1380 5A 3456 C POP ox ; RECOVER
138E 58 3457 C POP AX
3458 C
138F 1F 3459 C POP OS
3460 C ASSUME OS: NOTH I NG
1390 3461 C
1390 E8 131C R 3462 C CALL ; BLANK OUT ROW WITH COLOR
3463 C ASSUME
1393 1E 3464 C PUSH ; SAVE SEGMENT
1394 E8 OCFE R 3465 C CALL ; LOW MEMORY SEGMENT
1397 2B 3£ 044A R 3466 C SUB ; NEXT ROW
139B 1F 3467 C POP ; RECOVER
139C 4B 3468 C DEC ; NEXT
1390 75 Fl 3469 C JNZ ; DO MORE
139F E8 1348 R 3470 C CALL
13A2 C3 3471 C RET ; RETURN TO CALLER
13A3 3472 C ENoP

- -:-:::::-::-::::::~:::-::------
3473 C
3474 C
3475
3476
C
C ~ -SCROLL~~ r:-:::~ ~:: ::~::
3477 C ON THE SCREEN
3478 C
3479 C : : :. INPUT (AH) = CURRENT CRT MODE
3480 C (AL) = NUMBER OF ROWS TO SCROLL
3481 C (CX) = ROW/COLUMN OF UPPER LEFT CORNER
3462 C (OX) = ROW/COLUMN OF LOWER RIGHT CORNER
3483 C IBH) = ATTRIBUTE TO BE USED ON BLANKED LINE
3484
3485
3486
C
C
C
;
; OUTPUT
I~~ ~ ~ ~~~~N S~~~~~~ SEGMENT

3487
3486
C
C
; W~._~. _________________________
N014E -- THE REGEN BUFFER · _______ · _____ · _________ _
IS MODIFIED

3489 C ASSUME CS:CODE# DS:ABSO, ES: NOTHI NG

13A3 3490 C SCROL~UP PROC NEAR
13A3 8A DB 3491 C MOV BL,AL SAVE LI NE COUNT IN BL
13A5 E8 16EB R 3492 C CALL MK_ES
13AB 80 FC 04 3493 C CMP AH,4 TEST fOR GRAPH I CS MODE
13AB 72 06 3494 C JB Nl HANDLE SEPERATELY
13AD 80 Fe 07 3495 C CMP AH,7 TEST FOR BW CARD
13BO 74 03 3496 C JE Nl
13B2 E9 1474 R 3497 C JMP GRAPHICS_UP
13B5 3498 C Nl: ; UP_CONTINUE
13B5 53 3499 C PUSH BX ; SAVE fiLL ATTR IN BH
MeV
~R~~POSITION
13B6 8B Cl 3500 C ; UPPER LEFT POSITION
13B8 E8 13F2 R 3501 C CALL ; DO SETUP FOR SCROLL
138B 74 31 3502 C JZ N7 ; BLANK_F I ELD
13BO 03 FO 3503 C ADD SI,AX , FROM ADDRESS
13BF 8A E6 3504 C MOV AH,DH ; # ROWS I N BLOCK
13Cl 2A E3 3505 C SUB AH,BL ; # ROWS TO BE MOVED
13C3 3506 C N2: ; ROW_LOOP
13C3 E8 1432 R 3507 C CALL Nl0 ; MOVE ONE ROW
13C6 03 F5 3508 C ADD SI,BP
13C8 03 FO 3509 C ADD OI,BP ; NEXT LINE IN BLOCK
13CA FE CC 3510 C DEC AH ; COUNT OF LINES TO MOVE
13CC 75 F5 3511 C JNZ N2 ; ROW_LOOP
13CE 3512 C N3: ; CLEAR_ENTRY
13CE 56 3513 C POP AX ; RECOVER ATTR I BUTE IN AH
13CF BO 20 3514 C MDV AL, • • FILL WITH BLANKS
1301 3515 C N4: ; CLEAR_LOOP
1301 £8 143B R 3516 C CALL N11 ; CLEAR THE ROW
1304 03 FO 3517 C ADD OI#BP , POINT TO NEXT LINE
1306 FE CB 3518 C DEC BL ; LI NES TO SCROLL
1308 75 F7 3519 C JNZ N4 ; CLEAR_LOOP
13DA 3520 C N5: ; SCROLL_END
130A E8 OCFf R 3521 C CALL DDS
'300 80 3E 0449 R 07 3522 C CMP CRT_MODE,7 , IS THIS THE B/W CARD
13E2 74 07 3523 C JE N6 ; SKI P THE MODE RESET
13E4 AD 0465 R 3524 C MOV Al,CRT_MOoE..SET ; GET THE MODE SET
13E7 SA 0308 3525 C MOV oX,D3DSH ; ALWAYS SET COLOR CARD
13EA EE 3526 C OUT OX,AL
13EB 3527 C N6: ; VIDEO_RET_HERE
nEB E9 219E R 3528 C JMP V_RET

August 2, 1984 IBM Enhanced Graphics Adapter 131

BEE C
~~N ~O~ t a~eNT
3529 N7:
13EE SA DE 3530 C BL,OH
13FO EB DC 3531 C N3 GO CLEAR THAT AREA
13F2 3532 C ENDP
3533 C
3534 C ;.---- HANDLE COMMON SCROLL SET UP HERE
3535 C
13F2 3536 C SCROLL_pas I T ION PROC NEAR
13F2 F6 06 0481 R 04 3537 C TEST INFO,4
13F7 14 12 3538 C JZ N9
3539 C
3540 C ; ----- 80X25 COLOR CARD SCROLL
3541 C
13F9 52 3542 C PUSH OX
13FA B6 03 3543 C MOV DH,3
13FC B2 DA 3544 C MOV OL,ODAH ; COLOR CARD HERE
13FE 50 3545 C PUSH AX
13FF 3546 C N8: ; WAIT_DISP_ENABLE
13FF EC 3541 C IN AL,DX
1400 A8 08 3548 C TEST AL,8 WAI T FOR VERT RETRACE
1402 74 FB 3549 C JZ NB WAI T_O I SP_ENABLE
1404 BO 25 3550 C MOV AL,25H
1406 B2 08 3551 C MOV DL,OD8H OX'" 308
1408 EE 3552 C OUT DX,AL TURN OFF VIDEO
1409 58 3553 C POP AX OUR I NG VERT I CAL RETRACE
140A 5A 3554 C POP OX
140B 3555 C N9:
140B E8 1146 R 3556 C CALL POSITION CONVERT TO REGEN PO INTER
140E 03 06 044E R 3557 C ADD AX, CRT_START OFFSET OF ACT I VE PAGE
1412 8B F8 3558 C MOV OI,AX TO ADDRESS FOR SCROLL
1414 86 FO 3559 C MOV SI,AX FROM ADDRESS FOR SCROLL
1416 2B 01 3560 C SUB DX,CX OX = #ROWS, HGOLS
1418 FE C6 3561 C INC DH
141A FE C2 3562 C INC DL INCREMENT FOR 0 ORIGIN
141C 32 ED 3563 C XOR CH,CH ZERO HIGH BYTE OF COUNT
141E 86 2E 044A R 3564 C MOV SP,CRT_COLS NUM OF COLS IN 0 I SPLAY
1422 03 EO 3565 C ADD SP, BP TIMES 2 FOR ATTR BYTE
1424 8A C3 3566 C MOV Al,BL GET LINE COUNT
1426 F6 26 044A R 3567 C MUL BYTE PTR CRT COlS OffSET TO FROM ADDRESS
142A 03 CO 3568 C AOD AX,AX - *2 FOR ATTR I BUTE BYTE
142C 06 3569 C PUSH ES ESTABl I SH ADDRESS I NG
1420 1F 3570 C pOP OS FOR BOTH PO INTERS
142E 80 F8 00 3571 C CMP SL,D a MEANS BLANK FIELD
1431 C3 3572 C RET RETURN WITH FLAGS SET
1432 3573 C SCROLL_POS I T I ON ENDP
3574 C
3575 C
3576 C
1432 3577 C N10 PROC NEAR
1432 8A CA 3578 C MOV Cl,DL ; GET # Of COLS TO MOVE
1434 56 3579 C PUSH 51
1435 51 3580 C PUSH 01 , SAVE START ADDRESS
1436 F3j A5 3581 C REP MOVSW ; MOVE THAT LINE ON SCREEN
1438 5F 3582 C POP 01
1439 5E 3583 C POP 51 ; RECOVER ADDRESSES
143A C3 3584 C RET
143B 3585 C N1D ENDP
3586 C
3587 C
3588 C
143B 3589 C Nll PROC NEAR
143B 8A CA 3590 C MOV CL,DL ; GET H COLUMNS TO CLEAR
1430 57 3591 C PUSH 01
143E F3j AB 3592 C REP STOSW ; STORE THE FILL CHARACTER
1440 5F 3593 C POP 01
1441 C3 3594 C RET
1442 3595 C Nl1 ENOP
3596
3597
3598
C
C
C
; -----------------
SCROLL_DOWN
-- ------------------.------------------
3599 C 1H I S ROUT I NE MOVES THE CHARACTERS WITH I N A
3600 C DEFINED BLOCK DOWN ON THE SCREEN, FILLING THE
3601 C TOP LINES WITH A DEFINED CHARACTER
3602 C INPUT
3603 C (AH) = CURRENT CRT MODE
3604 C (AL) "" NUMBER OF LINES TO SCROLL
3605 C (CX) = UPPER LEFT CORNER OF REGION
3606 C (OX) = LOWER RIGHT CORNER Of REGION
3607 C (BH l = fiLL CHARACTER
3608 C (OS) = DATA SEGMENT
3609 C (ES) = REGEN SEGMENT
3610 C OUTPUT
3611 C NONE -- SCREEN IS SCROLLED
3612 C ~~ROLL=~O~;j-----;ROC----NEAR---------------H~~~~-~---~~R_
1442 3613 C
1442 FD 3614 C STD SCROLL DOWN
1443 8A 08 3615 C MOV BL,AL II NE COUNT TO BL
1445 E8 16E8 R 3616 C CALL MK ES
1448 53 3617 C PUSH BX- SAVE ATTRIBUTE IN BH
1449 8B C2 3618 C MOV AX, OX lOWER RIGHT CORNER
1448 E8 13F2 R 3619 C ~~ll ~~~OLLJOS JT I ON ; GET REGEN LOCATION
144E 14 20 3620 C
1450 28 FO 3621 C SUB SI,AX SI I S fROM ADDRESS
1452 8A E6 3622 C MOV AH,DH GET TOTAL # ROWS
1454 2A E3 3623 C SUB AH, BL COUNT TO MOVE I N SCROLL
1456 3624 C N13:
1456 E8 1432 R 3625 C CALL N10 ; MOVE ONE ROW
1459 28 F5 3626 C SUB SI,BP
1458 28 FD 3627 C SUB DI.BP
1450 FE CC 3628 C OEC AH
145F 15 F5 3629 C JNZ N13
1461 3630 C N14:
1461 58 3631 C POP AX ; RECOVER ATTRIBUTE IN AH
1462 BO 20 3632 C MOV AL, '
1464 3633 C N15:
1464 E8 1438 R 3634 C CALL N11 CLEAR ONE ROW
1467 2B FO 3635 C SUB DI,BP GO TO NEXT ROW
1469 FE CB 3636 C DEC BL
146B 75 F7 3637 C JNZ N15
1460
1410
1470
E9

8A DE
13DA R 3638
3639
3640
C
C
C
N16:
MOV
JMP
N'
BL,DH
1412 E6 ED 3641 C JMP N1'
1474 3642 C SCROLL_DOWN ENOP
3643
3644
3645
C
C
C
; ----------------
SCROLL UP
--~--------------------------- ------------------
3646 C THIS ROUTINE SCROLLS UP THE INFORMATION ON THE CRT
3647 C ENTRY
3648 C CH,CL"" UPPER LEFT CORNER OF REGION TO SCROLL
3649 C DH,DL'" LOWER RIGHT CORNER OF REGION TO SCROLL
3650 C BOTH Of THE ABOVE ARE IN CHARACTER POSITIONS
3651 C BH = fiLL VALUE fOR BLANKED LI NES
3652 C Al = # LINES TO SCROLL (AL=O MEANS SLANl( THE ENTIRE
3653 C FI ELO)
3654 C DS = DATA SEGMENT

132 IBM Enhanced Graphics Adapter August 2, 1984

 3655 ES = REGEN SEGMENT
3656
3657 ; EXIT NOTHING, THE SCREEN IS SCROLLEO
3658 b~~;Hics=u;-----;~OC----NE~R---------------·---------------------
147l1. 3659
1474 8A 08 3660 MOV BL,AL • SAVE LINE COUNT IN BL
1476 88 C1 3661 MOY AX,CX ; GET UPPER LEFT POSITION
3662 ; INTO AX REG
3663
3664 ; ----- USE CHARACTER SUBROUT I NE FOR POS I T I ON I NG
3665 ;----- ADDRESS RETURNED IS MULTIPLIED BY 2 FROM CORRECT VALUE
3666
1478 E8 16A7 R 3667 CALL GRAPHJOSN
147B 8B F8 3668 MOV OI,AX SAVE RESULT AS
3669 DEST I NAT I ON ADDRESS
3670
3671 ;----- DETERMINE SIZE OF WINDOW
3672
1470 28 01 3673 SUB OX,CX
147F 81 C2 0101 3674 ADO OX,101H ADJUST VALUES
1483 DO E6 3675 SAL OH,1 MULTIPLY H ROWS BY 4
3676 SINCE 8 VERT DOTS/CHAR
1485 DO E6 3677 SAL DH,1 AND EVEN/ODD ROWS
3678
3679 ;----- DETERMINE CRT MODE
3680
1487 60 3E 0449 R 06 3681 CMP TEST FOR MED IUM RES
148C 73 04 3682 JNC F I NO_SOURCE
3683
3684 ;----- MEDIUM RES UP
3685
148E DO E2 3686 SAL OL,l • 2,
1490 01 E7 3687 SAL 01,1 SINCE 2 BYTES/CHAR
3688
3689 ;----- DETERMINE THE SOURCE ADDRESS IN THE BUFfER
3690
1492
1492 06
3691
3692
R7:
PUSH ES ~t~Os~g~~~~s BOTH
1493 1F 3693 POP OS PO I NT I NG TO REGEN
1494 2A ED 3694 SUB CH,CH o TO HIGH OF COUNT REG
1496 DO E3 3695 SAL BL,1 NUMBER OF LI NES *4
1498 DO [3 3696 SAL BL,1
149A 74 20 3697 JZ Rl1 IF 0, BLANK ENTIRE FIELD
149C SA C3 3698 MOV AL,BL NUMBER OF LINES IN AL
149E 84 50 3699 MOV AH,80 80 BYTES/ROW
14AO f6 E4 3700 MUL AH OffSET TO SOURCE
14A2 8B F7 3701 MOV SI,OI SET UP SOURCE
14A4 03 FO 3702 ADD SI,AX ADD I N OFFSET TO IT
14A6 8A £6 3703 MOV AH,OH NUMBER OF ROWS IN FIELD
14A8 2A E3 3704 SUB AH,BL OETERM I NE NUMBER TO MOVE
3705
3706 ;----- LOOP THROUGH, MOVING ONE ROW AT A TIME, BOTH EVEN AND ODD FIELDS
3707
14AA
14AA £8 14CO R
3708
3709
R8:
CALL R17 ~g~{g~; ROW
14AO 81 EE 1 FBO 3710 SUB S I, 2000H-80 MOVE TO NEXT ROW
14B1 81 EF 1 FBO 3711 SUB 01,2000H-80
14B5 FE CC 3712 DEC AH NUMBER OF ROWS TO MOVE
14B7 75 F1 3713 JNZ R8 CONT I NUE TILL ALL MOVED
3714
3715 ;-~--- FILL IN THE VACATED LlNE(S)
3716
14B9 3717 R9: ; CLEAR_ENTRY
1489 8A C7 3718 C MOV AL,BH ; ATTRIBUTE TO FILL WITH
1488 3719 C R10:
1488 E8 14E6 R 3720 C CALL Rl. CLEAR THAT ROW
148E 81 EF 1 FBO 3721 C SUB 01,2000H-80 PO I NT TO NEXT LI NE
14C2 FE CB 3722 C DEC BL NUMBER OF LINES TO FILL
l4c4 75 F5 3723 C JNZ RIO CLEAR.LOOP
14C6 £9 219E R 3724 C JMP V_RET
14C9 3725 C Rll: BLANK FIELD
14C9 8A DE 3726 C MOV BL,OH SET BLANK COUNT TO
3727 C EVERYTH I NG I NFl ELO
14CB EB EC 3728 C JMP R9 CLEAR THE FIELD
14CO 3729 C GRAPHICS_UP ENOP
3730 C
3731 C ;----- ROUTINE TO MOVE ONE ROW OF INFORMATION
3732 C
14CO 3733 C R17 PROC NEAR
14CO SA CA 3734 C MOV CL,OL NUM OF BYTES I N THE ROW
14CF 56 3735 C PUSH 51
1400 57 3736 C PUSH 01 SAVE PO INTERS
1401 F3/ A4 3737 C REP MOYSB MOVE THE EVEN FIELD
1403 5F 3738 C POP 01
1404 5E 3739 C POP 51
1405 Sl C6 2000 3740 C ADO SI,2000H
1409 81 C7 2000 3741 C ADD 01,2000H POINT TO THE ODD FIELD
1400 56 3742 C PUSH 51
140E 51 3743 C PUSH 01 SAVE THE PO INTERS
140F 8A CA 3744 C MOV CL,OL COUNT BACK
14E1 F3/ A4 3745 C REP MOVS8 MOYE THE ODD FIELD
14£3 5F 3746 C POP 01
14E4 5E 3747 C POP 51 PO I NTERS BACK
14£5 C3 3748 C RET RETURN TO CALLER
14E6 3749 C R17 ENOP
3750 C
3751 C ; ----- CLEAR A 51 NGLE ROW
3752 C
14E6 3753 C R18 PROC NEAR
14E6 8A CA 3754 C MOV CL,OL NUMBER OF BYTES IN FIELD
14E8 57 3755 C PUSH 01 SAVE PO INTER
14E9 f3/ AA 3756 C REP STOSB STORE THE NEW VALUE
14EB 5F 3757 C POP 01 POINTER BACK
14EC S1 C7 2000 3758 C ADO 0l,2000H POINT TO 000 FIELD
14FO 57 3759 C PUSH 01
14F1 8A CA 3760 C MOV CL,OL
14F3 F3/ AA 3761 C REP STOSB FILL THE ODD FIELD
14F5 SF 3762 C POP 01
14F6 C3 3763 C RET RETURN TO CALLER
14F7 3764 C R18 ENOP
3765 C
14F7 3766
3767
C
C MEM_DEl ~~~~ME NEAR
OS;ABSO
14F7 50 3768 C PUSH AX
14F8 lE 3769 C PUSH OS
14F9 E8 OCFE R 3770 C CALL ODS
14FC 8A 26 0487 R 3771 C MOV AH,INFO
1500 80 E4 60 3772 C AND AH,060H
1503 1F 3773 C POP OS
1504 58 3774 C POP AX
1505 74 02 3775 C JZ MIN
1507 F9 3776 C 5TC
1508 C3 3777 C RET
1509 3778 C MIN:
1509 F8 3779 C CLC
150A C3 3780 C RET

August 2, 1984 IBM Enhanced Graphics Adapter 133

150B 3781 e HEM_OET ENDP
3782 e
3783 e ;----~ SCROLL ACTIVE PAGE UP
3784 e
150B 3785 e SC_2:
150B E9 13A3 R 3786 e JMP SCROLL_UP
3787 e
150E 3788 e AH6:
3789 e ASSUME DS:ABSO
150E E8 1201 R 3790 e CALL FLTA
15" 8A 26 0449 R 3791 e MOV AH. CRT_MODE GET CURRENT MODE
1515 80 FC 07 3792 e eMP AH.07H
1518 76 F1 3793 e JBE SC_2 ANY OF THE OLD MODES
151A 80 FC OD 3794 e eMP AH.ODH
1510 7317 3795 e JAE GRAPHICS_UP_2 NEW GRAPHICS MODES
151F E9 219E R 3796 e JMP V_RET NOT A RECOGN I ZED MODE
3797 e
1522 3198 e GR_ST_' PROC NEAR
1522 SA AOOO 3799 e MOV DX.OAOOOH REGEN BUFFER
1525 BO 051' 3800 e MOV BP.0511H GRAPHICS WRITE MODE
1528 80 FC OF 3801 e eMP AH.OFH
1528 72 08 3802 e JB W1
1520 E8 14F1 R 3803 e CALL MEM_OET
1530 73 03 3804 e JNe W1
1532 BO 0501 3805 e MOV BP,0501H GRAPH I CS WR I TE MODE
1535 3806 e VV1:
1535 e, 3807 C RET
1536 3808 e GR_ST_1 ENDP
3809 C
1536 3810 C GRAPH I CSA~~U~E PROC NEAR
3811 e DS:ABSO
1536 52 3812 e PUSH OX
1537 E8 1522 R 3813 e CALL GR_ST_' SET SEGMENT. WR I TE MOOf
3814 e SRLOAD ES SET REGEN
153A 8E C2 3815 e+ MOV ES,DX
153C SA 3816 e POP OX
153D 8A D8 3817 e MOV BL.AL NUMBER OF LINES
153F 8B Cl 3818 C MOV AX,CX UPPER LEFT CORNER
1541 5' 3819 e PUSH BX
1542 8A 3E 0462 R 3820 e MOV BH.ACTIVE]AGE ; ACT IVE PAGE FOR SCROLL
1546 E8 16C6 R 3821 e CALL GR>CPSN ; ADDRESS I N REGEN
1549 5B 3822 e PDP BX
154A 8B F8 3823 C MOV DI,AX l SET POINTER
154C 2B D1 3824 e SUB DX,CX ; DETERMINE WINDOW
154E 81 C2 0101 3825 C ADD DX,0101H ; ADJUST
1552 2A E4 3826 e SUB AH,AH ; ZERO HIGH BYTE
1554 8A C3 3827 e MOV AL,BL ; LI NE COUNT
1556 52 3828 e PUSH OX
1557 F7 26 0485 R 3829 C MUL POINTS BYTES PER CHARACTER
155B F7 26 044A R 3830 e MUL CRT_COLS COLUMNS
155F 8B F7 3831 e MOV 51,01 SET UP SOURCE INDEX
1561 03 FO 3832 e ADD SI.AX ADJUST
3833 e ASSUME DS:NOTHING
1563 00 3834 e PUSH ES
1564 1F 3835 e POP OS
1565 5A 3836 e POP OX
1566 OA DB 3837 C OR BL.BL LINE COUNT
1568 74 3F 3838 e JZ AR9
156A 8A CE 3839 C MOV CL.DH
156C 2A CB 3840 e SUB CL.BL
156E 2A ED 3841 e SUB CH,CH
3842 e
3843 e ASSUME DS:ABSO
1570 1E 3844 e PUSH OS
1571 E8 OCFE R 3845 e CALL DDS LOW MEMORY SEGMENT
1574 50 3846 c PUSH AX
1575 52 3847 C PUSH OX
1576 8B C1 3848 C MOV AX.CX
1578 F7 26 0485 R 3849 c MUL POINTS BYTES PER CHAR
157C 8B C8 3850 e MOV CX.AX SET THE COUNT
157E 5A 3851 C POP DX
157F 5. 3852 e POP AX
3853 e ASSUME OS:NOTHING
1580 1F 3854 e POP OS
3855 e
1581 52 3856 e PUSH OX
1582 8B C5 3857 C HOV AX,BP
1584 B6 03 3858 C HOV DH,3
1586 B2 CE 3859 C HOV DL.GRAPH_ADDR GRAPH ICS
1588 £8 0015 R 3860 C CALL OUT_OX
1588 B2 C4 3861 e HOV DL.SEQ....ADOR SEQUENCER
1580 B8 020F 3862 C HOV AX.020FH ENABLE ALL MAPS
1590 E8 OD15 R 3863 C CALL OUT_OX
1593 5A 3864 C POP OX
1594 E8 12EO R 3865 C CALL CRANK SCROLL THE SCREEN
3866 C
1597 52 3867 C PUSH OX
1598 40 3858 C DEC BP
1599 8B C5 3869 e HOV AX,BP
159B 86 03 3870 C HOV DH,3
1590 82 CE 3871 C MOV DL, GRAPH_ADDR
159F E8 0015 R 3872 C CALL OUT_OX
15A2 5A 3873 C POP OX
lSA3 3874 C ARlO:
15A3 E8 1353 R 3875 C CALL 8LNK_3
15A6 E9 219E R 3876 C JHP V_RET
15A9 3877 C AR9:
lSA9 8A DE 3878 C MOV BL.DH BLANK ENTIRE WINDOW
15A8 EB F6 3879 C JHP ARlO
15AD 3880 C GRAPHICS_UP_2 ENDP
3881 C
3882 C ;----- SCROLL ACTIVE DISPLAY PAGE DOWN
3883 C
15AD 3884 C SC_3:
l~AD E9 1442 R 3885 C JHP SCROLL_DOWN
3886 C
15BO 3887 C AH7:
3888 C ASSUME DS:ABSO
1"580 E8 1201 R 3889 e CALL FLTA
15B3 8A 26 0449 R 3890 e HOV AH,CRT_MOOE
1587 80 FC 03 3891 e CHP AH,03H OLD COLOR ALPHA
15BA 76 F1 3892 C JBE SC_'
158C 80 FC 07 3893 C eMP AH.07H MONOCHROME ALPHA
158F 74 EC 3894 e JE SC_3
3895 C
15Cl 80 FC 00 3896 e eHP AH.ODH NEW GRAPH I CS MODES
15C4 73 DC 3897 e JAE GRAPH I CS_DN_2
15C6 80 FC 06 3898 e eHP AH.06H OLD GRAPH I CS MODES
15C9 77 04 3899 C JA H_O
15CB B4 07 3900 e HOV AH.07H
15CD CD 42 3901 e 'NT 42H
15CF 3902 C "_0:
15CF E9 219E R 3903 e JHP V_RET
3904 C
15D2 3905 C GRAPH I CS_DN_2 PROC NEAR
1502 Fo 3906 C STo DIRECTION TO DECREMENT

134 IBM Enhanced Graphics Adapter August 2, 1984

1503 8A D8 3907 C MOV Bl,AL LINE COUNT
1505 52 3908 C PUSH ox SAVE LOWER RIGHT
1506 E8 1522 R 3909 C CAll ~~_ST_'
3910 C SRLOAD SET REGEN SEGMENT
1509 8E C2 3911 C+ MOV ES,DX
150B 5A 3912 C POP ox
150C 88 C2 3913 C MOV AX,OX
150E F'E Clf 3914 C INC AH ; HOV CHAR ROW UP BY ONE
15EO 53 3915 C PUSH ox
15E1 8A 3E 0462 R 3916 C MOV BH.ACTIVE_PAGE
15E5 E8 16C6 R 3917 C CAll GR>t.PSN ; ADDRESS I N REGEN
15E8 58 3918 C POP BX
15E9 28 06 044A R 3919 C SUB AX,CRT_COLS ; ONE SCAN OVERSHOOT
15EO 88 Fa 3920 C MOV 01 ,AX.
15EF 28 01 3921 C SUB DX,ex ; CALCULATE WI NDOW
15Fl 81 C2 0101 3922 C AOD DX,010'H ; ADJUST COUNT
15F5 2A E4 3923 C SUB AH,AH
15F7 8A C3 3924 C MOV AL,BL
15F9 52 3925 C PUSH DX
15FA F7 26 0485 R 3926 C MUl POINTS BYTES PER CHAR
15F'E F7 26 044A R
1602 88 f7
3921
3928
C
C
MUl
MOV ~~;j'jTOLS BYTES PER ROW

1604 28 fO 3929 C SUB SI,AX

3930 C ASSUME os:NOTH ING
1606 06 3931 C PUSH ES SET OS TO
1607 1F 3932 C POP DS THE REGEN SEGMENT
1608 5A 3933 C POP DX
1609 OA DB 3934 C OR BL,BL SCROLL COUNT
160B 74 40 3935 C JZ DXR9 BLANK ENT I RE WI "DOW
1600 8A CE 3936 C MOV CL.DH
160F 2A CB 3937 C SUB CL,BL
1611 2A ED 3936 C SUB CH,CH
3939 C
3940 C ASSUME DS:A8S0
1613 lE 3941 C PUSH OS
1614 E8 OCFE R 3942 C CALL 005
1617 50 3943 C PUSH AX
1618 52 3944 C PUSH ox
1619 88 C1 3945 C MOV AX.CX
161B F7 26 0485 R 3946 C MUl POINTS BYTES PER CHAR
161F 88 C8 3941 C "OV ex,AX
1621 SA 3948 C POP ox
1622 58 3949 C POP AX
3950 C ASSUME DS:NOTHING
1623 1F 3951 C POP OS
3952 C
1624 52 3953 C PUSH ox
1625 88 C5 3954 C "OV AX,BP
1627 B6 03 3955 C MOV DH,3
1629 82 CE 3956 C MOV DL, GRAPH_ADDR ; GRAPHICS
162B E8 0015 R 3957 C CALL OUT_OX
162E 82 e4 3958 C MOV DL, SECLADDR SEQUENCER
1630 88 020F 3959 C MOV AX,020FH E"ABLE ALL MAPS
1633 E8 0015 R 3960 C CALL g~T_DX
1636 5A 3961 C POP
1637 E8 12FE R 3962 C CALL CRANIL4 SCROLL THE SCREEN
3963 C
163A 52 3964 C PUSH DX
163B 40 3965 C DEC BP
163C 8B C5 3966 C MOV AX,BP
163E 86 03 3967 C MOV OH,3
1640 82 CE 3968 C MOV DL, GRAPH_ADDR
1642 E8 0015 R 3969 C CALL OUT_OX
1645 5A 3970 C POP DX
16116 3971 C DXR10:
1646 E8 137B R 3972 C CAll BLNK_4
16119 FC 3973 C ClO
164A £9 219E R 3974 C JMP V_RET
1640 3915 C DXR9:
164D 8A DE 3976 C MOV BL,OH BLANK ENT I RE WINDOW
16l1F EB F5 3977 C JMP DXR10
1651 3978 C GRAPH I CS_ON_2 ENDP
3979 C
3980 C SUBTTL
3981
3982 C INCLUDE VGRW.INC
3983 C SUBTTL VGRW. INC
3984 C PAGE
3985 C
3986 C ASSUME DS:ABSQ
1651 3987 C f I ND_POS IT I 0" PROC NEAR
1651 8A CF 3988 C MOV CL,BH ; DISPLAY PAGE TO CX
1653 32 ED 3989 C XOR CH,CH
1655 8B fl 3990 C MOV Sl,ex ; MOVE TO S I fOR INDEX
1657 01 E6 3991 C SAL SI .. ' ; * 2 fOR WORD OFFSET
1659 88 811 0450 R 3992 C MOV AX. I S I + OffSET CURSOR_POSH] ; ROW/COLUMN Of THAT PAGE
1650 33 DB 3993 C XOR BX,ax ; SET START ADDRESS TO 0
165F E3 06 3994 C JCXZ P5 ; NO_PAGE
1661 3995 C P4: ; PAGE_LOOP
1661 03 1E 044C R 3996 C AOO BX,CRT_LEN ; LENGTH Of BUFFER
1665 E2 fA 3997 C lOOP P. ; NO_PAGE
1667 3998 C P5:
1667 E8 1146 R 3999 C CALL POSITION ; DETERMINE LOC IN REGEN
166A 03 08 4000 C AOD ax, AX ; ADD TO START OF REGEN
166C C3 4001 C RET
1660 4002 C fiND_POSITION ENOP
4003 C'
4004 C :--------------------------------------------------------

~ ~:. :::::Dr~!~-~~ri~~ ~~P~~D~E~~~T~~

4005
4006
4007 I 2 8 I TS IN BL TO
4008
4009 C BL '" COLOR TO BE USED ( LOW 2 BITS I
4010 C EXIT
4011 g ~ ~XCOL~L~~T~OIBE USED ( 6 REPLICATIONS Of THE
4012
1660
4013
4014 g ~,9-----PROc----NEAR-------------------------------------
1660 80 E3 03 4015 C AND BL,3 ISOLATE THE COLOR BITS
1670 8A C3 4016 C NOV AL, BL COPY TO AL
1672 51 4017 C PUSH CX SAVE REG I STER
1673 B9 0003 4018 C HOV CX.. 3 NUMBER OF TIMES
1676 4019 C 520:
1676 DO EO 4020 C SAL AL .. 1
1678 DO EO 4021 C SAL AL,l ; LEFT SHIFT BY 2
167A OA DB 4022 C OR BL,AL ; ANOTHER COLOR VERSION
4023 C .. INTO BL
167C E2 F8 4024 C LOOP 520 ; FILL ALL OF BL
167E 8A Fe 4025 C MOV BH,BL ; FILL UPPER PORTION
1680 59 4026 C POP ex ; REG I STER BACK
1681 C3 4027 C RET ; ALL DONE
1682 4028 C S19 ENDP

g ~ -EXPAND;~nE:::~~::-~::::-~::-:~~:-~:-::-:::-:::::::----
4029
4030
4031
4032 C; ALL OF THE BITS, TURNING THE 8 BITS INTO

August 2, 1984 IBM Enhanced Graphics Adapter 135

 4033 e 16 BITS. THE RESULT IS LEFT IN AX
4034 e ~2;-----PRO;;----~EAR-------------------------------------
1682 4035 e
1682 52 4036 e PUSH OX ; SAVE REG I STERS
1683 51 4037 e PUSH CX
1684 53 4038 e PUSH BX
1685 2B 02 4039 e SUB OX,DX RESULT REG I STER
1681 B9 0001 4040 e MOV CX,l MASK REG I STER
168A 4041 e S22:
168A 8B 08 4042 e MOV BX,AX BASE I NTO TEMP
168C 23 09 4043 e AND BX,CX USE MASK TO EXTRACT BIT
168E DB 03 4044 e OR OX,BX PUT I NTO RESULT REG I STER
1690 01 EO 4045 e SHL AX,'
1692 01 E1 4046 e SHL CX,l SH I FT BASE AND MASK BY 1
1694 8B DB 4047 e MOV BX,AX BASE TO TEMP
1696 23 09 4048 e AND BX,CX EXTRACT THE SAME BIT
1698 08 03 4049 e OR DX,BX PUT I NTO RESULT
169A 01 E1 4050 e SHL CX,l SHI FT ONLV MASK NOW,
4051 e MOV I NG TO NEXT BASE
169C 73 EC 4052 e JNe 522 USE MASK BIT COMING OUT
4053 e TO TERMINATE
169E 88 C2 4054 e MOV AX,DX RESULT TO PARM REGISTER
16AO 58 4055 e POP BX
16A1 59 4056 e POP ex RECOVER REG I STERS
16A2 SA 4057 e POP ox
16A3 C3 4058 e RET ; ALL DONE
16A4 4059 C S21 ENOP
4060 e
16A4 4061 C S26 PROC NEAR
16A4 At 0450 R 4062 e MOV AX, CURSOR_POSN ; GET CURRENT CURSOR
16A7 4063 e GRAPH_PO~~SH LABEL NEAR
16A7 53 4064 e BX SAVE REG I STER
16A8 8B 08 4065 e MOV BX,AX SAVE A COPY Of CURSOR
16M 8A C4 4066 e MOV AL,AH GET ROWS TO AL
16AC F6 26 044A R 4067 e MUL BYTE PTR CRT_eOLS MULTI PLY BY BYTES/COLUMN
16BO 01 ED 4068 e SHL AX,1 *4 SINCE 4 ROWS/BYTE
16B2 01 EO 4069 e SHL AX,l
16B4 2A fF 4070 e SUB BH.6H , ISOLATE COLUMN VALUE
16B6 03 C3 4071 e ADD AX,BX ; DETERMINE OFFSET
16B8 5B 4072 e POP BX ; RECOVER POINTER
16B9 C3 4073 e RET ; ALL DONE
16BA 4074 C S26 ENDP
4075 e
4076
4077
e
e
~ -GR=CUR ------------ ------------ ---- ------- --- -- ------ -----------
4078 e ; ENTRY BH == DI SPLAY PAGE:
4Q79 e
/.j080 e ; EXIT
4081 e AX == CURSOR POSITION FOR REQUESTED PAGE

16BA
4082
4083
e
e
6R=CUR;----------------------------------------------------------
4084 e ASSUME OS: ABSO
16BA 53 4085 e PUSH BX , SAVE REG I STER
16BB 8A OF 4086 e MOV BL, BH ; GET TO LOW BYTE
16BO 2A FF 4087 e SUB BH, BH ; ZERO HIGH BYTE
16Bf 01 (3 4068 e SAL BX.1 ; *2 FOR WORD COUNT
16C1 8B 81 0450 R 4069 e MOV AX, I BX + OFFSET CURSOR_POSN 1 ; CURSOR, REQUESTED PAGE
16c5 5B 4090
4091
4092
4093
e
e
e
e
; POP
-~~~;~s~- -------------------------------------------------------
8X ; _RECOVER REG I STER

4094 e AX '" CURSOR POS I T I ON I N DES I RED PAGE

4095 e BH == DES I RED PAGE
4096 e EXIT
4097 e AX '" BYTE OFFSET I NTO REGEN
4098 e 6R~=PS~-PROC----NEAR---------------------------------------------
16C6 4099 e
16C6 53 4100 e PUSH BX SAVE
16C7 51 4101 e PUSH CX SAVE
16c8 52 4102 e PUSH OX SAVE
16C9 2A ED 4103 e SUB CH, CH ZERO
16CB 8A Cf 4104 e MOV
_ ~M
CL, BH _PAGE NUMBER
16CD 8B 08 4105 e MOV BX,AX ROW, COLUMN
16CF SA C4 4106 e
1601 F6 26 044A R 4107 e MUL BYTE PTR CRT_COlS ROW * COLUMNS/ROW
16D5 F7 26 0485 R 4108 e MUL PO I NTS BYTES PER ROW
16D9 2A Ff 4109 e SUB BH, BH ZERO TO LEAVE COL VALUE
1606 03 C3 4110 e ADD AX, BX ADO I N COLUMN
1600 8B lE 044C R 4"1 e MOV BX,CRT_LEN PAGE LENGTH
16El E3 04 4112 e JCXZ GP_2 NO PAGE OFFSET
16E3 4113 e
16E3 03 C3 4114 e ADO AX,BX ; ADO I N THE PAGE LENGTH
16E5 E2 FC 4115 e LOOP GP_3 ; 00 FOR NUMBER OF PAGES
16E7 4116 e
16E7 5A 4117 e POP ox RECOVER
16E8 59 4118 e POP ex RECOVER
16E9 5B 4119 e POP BX RECOVER
16EA C3 412Q e RET
16EB 4121 e GRX_PSN ENOP
4122 e
16EB 4123 e
16EB BE B800 4124 e MOV SI,OB800H
16EE 88 3E 0410 R 4125 e MOV OI,EQUiP_FLAG
16F2 81 E7 0030 4126 e AND 01,030H
16F6 83 Ff 30 4127 e eMP 01,030H
16F9 75 03 4128 e JNE P6_A
16FB BE BODO 4129 e MOV SI,OBOOOH
16fE 4130 e
16FE 8E C6 4131 e MOV ES,SI
1700 C3 4132 e RET
4133 e
e
~ ~ ~§
e ; -READ=A~; ?~R=~~~~:: -:::::-~:: -: ~~: ~ ::~: -:::-:::~~:~:: ---
e
4136
4137 e AT THE CURRENT CURSOR POSITION AND RETURNS THEM
413~ C , TO THE CALLER
4139 C : INPUT
41'tO e (AH) '" CURRENT CRT MODE
4141 e ) (BH) :::: t11SPLAY PAGE ( ALPHA MODES ONLY)
4142 e (OS) ::: DATA SEGMENT
4143
4144
e
e ; OUTPUT (ES) =
REGEN SEGMENT
e
~ !:~l ~ ~~~~1:5~~
4145
e
4146
4141
4148
e
c
; -------- -------------------------------------------
ASSUME
READ

CS: CODE, OS:ABSO, ES: NOTH i NG

----:;
e F'~OC
gg~ E~
4,49 REAO_AC_CURRENT NEAR
16[8 R 4150 e CALL M~_ES
1704 E8 1.651 R 4151 e CALL FIND_POSITION
1707 8B F3 4152 e MOV SI,BX ; ADDRESSING IN 51
4153 e
1 709 ~B 1.6 0463 R 4154 C 1II0V Ox, ADOR_6S45 ; GET BASE ~DORESS
1700 83 C2 d6 4155 e Abo ox, 6 ; POINT AT STATUS PORT
4156 e
1710 F6 iJ6 0467 R 04 4157 e INfO.4
4158 e

136 IBM Enhanced Graphics Adapter August 2, 1984

1715 06 4159 C PUSH ES
1716 lF 4160 C POP OS SEGMENT FOR QU I CK ACCESS
4161 C
1717 74 OB 4162 C JZ PlA
4163 C
4164 C ;~~-~~ WAIT FOR HORIZONTAL RETRACE
4165 C
1719 4166 C P2: WA I T FOR RETRACE LOW
1719 EC 4167 C IN AL,D~ GET STATUS
171A A6 01 4168 C TEST AL,1 IS HORZ RETRACE LOW
171C 75 FB 4169 C JNZ P2 WAIT UNTIL IT IS
ll1E FA 4170 C CLI NO MORE INTERRUPTS
171F 4171 C P3: WAIT FOR RETRACE HIGH
171F EC 4172 C IN AL,DX GET STATUS
1720 A6 01 4173 C TEST AL,l IS IT HIGH
1722 74 FB 4174 C JZ P3 WAIT UNTIL IT IS
1724 4175 C P3A:
1724 AO 4176 C LODSW ; GET THE CHAR/ATTR
1725 E9 219E R 4177 C JMP V RET
1726 4178 C READ_AC_CURRENT ENDP
4179 C
4180 C i~MEO=REAO=~;TE~---~~~-----------------------------------
4181 C
4182 C TH I S ROUT I NE WILL TAKE 2 BYTES FROM THE REGEN
4183 C BUFFER, COMPARE AGA I NST THE CURRENT FOREGROUND
4184 C COLOR, AND PLACE THE CORRESPONDING ON/OFF BIT
4185 C PATTERN INTO THE CURRENT POSITION IN THE SAVE
4186 C AREA
4187 C ENTRY
4188 C S I, as '" PO I NTER TO REGEN AREA Of INTEREST
4189 C BX '" EXPANDED FOREGROUND COLOR
4190 C BP '" POINTER TO SAVE AREA
4191 C EXIT
4192 C BP I S I NCREMENT AFTER SAVE
4193 C ~23-----PROC----NEAR----~--------------------------------
1726 4194 C
1728 6A 24 4195 C MOV AH,(SII GET FIRST BYTE
172A 8A 44 01 4196 C MOV AL, (SI +1 I GET SECOND BYTE
1720 89 COOO 4197 C MOV CX, OCOOOH 2 BIT MASK TO TEST
4198 C THE ENTR I ES
1730 82 00 4199 C NOV DL,O RESULT REG I STER
1732 4200 C S24:
1732 85 C1 4201 C TEST AX,CX IS, THIS 8ACKGROUND?
1734 F6 4202 C Cle CLEAR CARRY I N HOPES
4203 C THAT IT IS
1735
1737
74 01
F9
4204
4205
C
C
JZ
STC
S2,
~rs~~ T ~ T sb Ss~~C~~~~~ND
1736 4206 C S25:
1738 DO 02 4207 C RCl DL,1 MOVE THAT BIT INTO THE
173A 01 E9 4208 C SHR eX,1 RESULT
173C 01 E9 4209 C SHe eX,l MOVE THE MASK TO THE
RIGHT BY 2 BITS
~~~~
C
173E 73 F2 C JNC S2' DO IT AGAIN IF MASK
4212 C DIDN'T FALL OUT
17tj.(i 88 56 00 4213 C MOV [BPJ,DL STORE RESULT I,N SAVE
1743 45 4214 C IHC BP ADJUST PO INTER
1744 C3 4215 C RET ALL DONE
1745 4216 C S23 ENDP
4217 C
4218 C
1745 4219 C GRAPHICS_READ PROC NEAR
1745 E8 16EB R 4220 C CALL MK ES
1748 E8 16A4 R 4221 C CALL S26 CONVERTED TO OFFSET
1748 8B FO 4222 C MOV SI,AX SAVE IN SI
1740 83 EC 08 4223 C SUB SP,8 ALLOCATE SPACE TO SAVE
4224 C THE READ CODE PO I NT
1750 8B EC 4225 C MOV BP,SP PO I NTER TO SAVE AREA
4226 C
4227 C ;~--~~ DETERMINE GRAPHICS MODES
4228 C
1752 80:iE 0449 R 06 4229 C CMP CRT_MODE,6
1757 06 4230 C PUSH ES
1758 1J; 4231 C POP OS PO I NT TO REGEN SEGMENT
1759 72 lA 4232 C JC S13P MEO I UM RESOLUT I ON
4233 C
4234 C ;----~ HIGH RESOLUTION READ
4235 C
4236 C ;~--~- GET VALUES FROM REGEN BUFFER AND CONVERT TO CODE POINT
4237 C
H5B B6 04 4238 C MOV DH,4 NUMBER OF PASSES
175D 4239 C
175D 8A 04 4240 C MOV AL, [SI J GET FIRST BYTE
175F 88 46 00 4241 C MOV (BPj,AL SAVE I N STORAGE AREA
1762 45 4242 C IHC BP NEXT LOCATION
1763 6A 84 2000 4243 C MOV AL,[SI+2000Hl GET LOWER REG I ON BYTE
1767 88 46 00 4244 C MOV (BP],AL ADJUST AND STORE
176A 45 4245 C INC BP
1768 63 C6 50 4246 C ADO SI,60 PO I NTER I NTO REGEN
176E FE CE 4247 C DEC DH LOOP CONTROL
1770 75 EB 4248 C JHZ S12P 00 I T SOME MORE
1772 EB 17 90 4249 C JMP S15P GO MATCH THE SAVED CODE
4250 C POINTS
4251 C
4252 C ;----- MEDIUM RESOLUTION READ
4253 C
1775 4254 C S13P:
1775 01 E6 4255 C SAL Sl,l
1177 B6 04 4256 C MOV DH,4
1779 4257 C S14P:
1779 E8 1728 R 4258 C CALL S23 GET PA I R BYTES
4259 C INTO SINGLE SAVE
177C 61 C6 2000 4260 C ADD SI,2000H GO TO LOWER REG I ON. c
1780 E8 1726 R 4261 C CALL S23 GEl; THIS PAIR INTO SAVE
1783 81 EE HBO 4262 C SUB S I ,2000H-80 ADJUST PO I NTER BACK INTO
1787 FE CE 4263 C DEC DH UPPER ,
1789 75 EE 4264 C JHZ S14P kEEP GO I NG UNT I L 8 DONE
4265 C
4266 C ;----.:. SAVE AREA HAS CHARACTER IN IT, MATCH IT
4267 C
178B 4266 C S15P:
118B 4269 C PUSH OS
H6C 4270 C CALL DDS _ ,
n8F 4211 C I,.t~ DI,GRX_SET ESTABLISH ADDRESSINd
1193 4272 C eo:p DS
1794 4273 C SUB BP,8 ADJUST. POI NfER TO , ,
4274 C 8EG I NN I NG OF SAVE AREA
1797 88 F5 4275 C HOV SI,BP
1799 4276
~a~~~~T 0 ~~6~T ~g~ NT
FC C ClO
lt9A BO 00 4277 C MOV AL,O BE I NG
179C 4276 C S16P: MATCHED ,.,
179C 16 4279 C PUSH SS AOpRESSING TO,.,STACK_
1790 1F 42$0 C POP DS FOR THE STRING COMPA6E
179E BA 0080 428,1 C NOV DX,128 NUMBER TO TEST AGA I NST
HAl 4282 C S17P:
c
11~1
171\2
sCi
51
42$3
4284 t
PUSH
PUSH
51
01 ~~~ ~~~~ ;~~~f~~iihER

August 2, 1984 IBM Enhanced Graphics Adapter 13'1

 NUMBER Of BYTES TO MATCH
g~P~B
17A3 89 0008 4285 G MOV
17A6 f3/ A6 4286 G REPE COMPARE THE 8 BYTES
17A8 SF 4287 G POP 01 RECOVER THE POINTERS
17A9 5E 4288 G POP SI
17M 74 10 4289 G JZ S18P I f ZERO FLAG SET,
4290 G THEN MATCH OCCURRED
17AC FE CO 4291 G ING AL NO MATCH, MOVE TO NEXT
17AE 83 C7 08 4292 G ADD 01,8 NEXT CODE PO I NT
17Bl 4A 4293 G DEG OX LOOP CONTROL
17B2 75 ED 4294 G JNZ S17P DO ALL OF THEM
4295 G
4296 C ;----- CHAR NOT MATCHED, MIGHT BE IN USER SUPPLIED SECOND HALF
4297 G
17B4 3C 00 4298 G GMP AL,O ; AL <> 0 IF ONLY 1ST
4299 C HALF SCANNED
17B6 74 11 4300 G JE S18P IF == 0, THEN ALL HAS
4301 G BEEN SCANNED
4302 G ASSUME DS:ABSO
17B8 E8 OCFE R 4303 G CALL DDS
17BB C4 3E 007C R 4304 G LES DI,EXT_PTR GET POINTER
17BF 8C CO 4305 G MOV AX,ES SEE I F THE PNTR EXISTS
17Cl DB C7 4306 G OR AX,D! If ALL 0, DOESN'T EXIST
l7C3 74 04 4307 G JZ S16P NO SENSE LOOKING
l7C5 BO 80 4308 G MDV AL,128 OR I GIN FOR SECOND HALF
17C7 EB 03 4309 G JMP S16P GO 8ACK AND TRY FOR IT
4310 G
4311 G ; ----- CHARACTER I S FOUND ( AL=O I F NOT FOUND )
4312 G
17C9 4313 C
17C9 83 C4 08 4314 G ADD SP,8 ; READJUST THE STACK,
4315 G ; THROW AWAY SAVE
17CC E9 219E R 4316 G JMP ; ALL DONE
17CF 4317 G GRAPH I CS_READ
4318 G
4319 G
4320 G ; ----- READ CHARACTER/ATTR I BUTE AT CURRENT CURSOR POS I T I ON
4321 G
17Cf 4322 G AH8S:
17Cf E9 1701 R 4323 G JMP
4324 G
1702 4325 G AH8:
4326 G ASSUME DS:ABSO
1702 8A 26 0449 R 4327 C MOV AH , CRT_MODE ; GET THE CURRENT MODE
1706 80 fC 07 4328 G GMP AH,07H
1709 74 F4 4329 G JE AH8S
170B 80 FC 03 4330 G GMP AH,03H
170E 76 EF 4331 G JBE AH8S
17EO 80 FC 06 4332 G GMP AH,06H
17E3
17E5
77 03
E9 1745 R
4333
4334
G
C
JA
JMP
Z_'
GRAPH I CS_READ
17E8 4335 G
17E8 80 FC OF 4336 C GMP AH,OFH
17EB 72 52 4337 G JB GRX_RD2
17ED E8 14F7 R 4338 G CALL MEM_DET
17fO 72 40 4339 G JG GRX_R02
17F2 EB OA 4340 G JMP SI-fORT GRX_RD1
17F4 80 FC 00 4341 G GMP AH,OOH RANGE TEST
17F7 73 46 431t2 G JAE GRX R02 FOUR MAP READ
17F9 BO 00 4343 G MOV AL,a
17FB E9 219E R 4344 G JMP V_RET
4345 G
17FE 1t346 G GRX ROl PROC NEAR
1t347 G - ASSUME DS:ABSO
431t8 G SRLOAD ES,OAOOOH REGEN SEGEMNT
17FE BA ADOO 431t9 G+ MOV OX,OAOOOH
1801 8E C2 4350 G+ MOV ES,DX
1803 £8 16BA R 1t351 G CALL GR CUR BYTE OFFSET INTO REGEN
1806 8B FO 4352 G MOV SI-;-AX SAVE IN SI
1808 8B lE 0485 R 1t353 G MOV BX, POINTS BYTES PER CHARACTER
l80C 2B E3 4354 C SUB SP,BX ALLOCATE SPACE TO SAVE
4355 G THE READ CODE PO I NT
l80E 8B EC 1t356 G MOV BP, SP PO I NTER TO SAVE AREA
1t357 G
4358 C ; ----- GET VALUES FROM REGEN BUffER AND CONVERT TO CODE PO I NT
4359 G
1810 53 1t360 G PUSH BX SAVE BYTES PER CHARACTER
1811 24 01 1t361 G AND AL,l ODD OR EVEN BYTE
1813 8A C8 1t362 C MOV CL,AL USE FOR SH I FT
1815 80 05 4363 G MOV AL,5 COLOR COMP VALUE (CO-C2)
1817 02 EO 4364 G SHL AL,CL (Cl-C3) I F ODD BYTE
1819 84 07 4365 G MOV AH,G_COLOR COLOR COMPARE REG! STER
1818 86 03 4366 G MOV DH,3
1810 82 CE 4367 G MOV DL, GRAPH_ADOR
181F E8 0015 R 11368 G CALL OUT_OX SET GRAPH I CS CH I P
1822 88 0518 4369 G MOV AX,518H READ MODE
1825 E8 0015 R 4370 G CALL OUT_OX SET GRAPH! CS CH I P
1828 4371 G
1828 26: 8A 04 4372 G MOV AL,ES:(Slj GET FIRST BYTE
1828 F6 DO 4373 G NOT AL
1820 88 46 00 1t371t C MOV S5: [BPj,AL SAVE I N STORAGE AREA
1830 45 4375 C I NG BP NEXT LOCATION
1831 03 36 044A R 4376 C AOD ~~,CRT_COLS POI NTER I NTO REGEN
1835 48 4377 C DEG LOOP CONTROL
1836 75 fO 4376 C JNZ 512 1 DO I T SOME MORE
1838 58 4379 G POP BX - RECOVER BYTES PER CHAR
1839 88 0510 4380 G MOV AX,51OH UNDO READ MODE
la3c E8 32 90 4381 C JMP GRX_RECG CHAR REGONTION ROUTINE
183F 4382 G GRX_R01 ENOP
4383 G
183F 4384 G GRX_R02 PROC NEAR
4385 G ASSUME DS:ABSO
4386 G SRLOAO ES,OAOOOH REGEN SEGMENT
183F BA ADOO 4387 G+ MOV OX,OAOOOH
1842 8E C2 4388 c+ MOV ES,DX
1844 E8 168A R 4389 G CALL GR CUR BYTE OffSET I NTO REGEN
1847 88 FO 4390 G MOV SI-;-AX SAVE IN SI
1849 88 1E 0485 R 4391 c MOV BX, POI NTS BYTES PER CHARACTER
1840 28 E3 4392 c SUB SP,BX ALLOCATE SPACE TO SAVE
4393 c THE READ CODE PO I NT
184F 88 EC 4394 C MOV BP, SP PO I NTER TO SAVE AREA
4395 G
4396 C ;----- GET VALUES FROM REGEN BUFFER AND CONVERT TO CODE POINT
4397 G
1851 B6 03 4398 G MOV DH,3
1853 82 CE 4399 G MOV DL, GRAPH_ADOR GRAPHICS CHIP
1855 88 0508 4400 G MOV AX,50BH COLOR COMPARE
1858 E8 0015 R 4401 G CALL OUT OX SET THE REG I STER
1858 53 4402 G PUSH BX - SAVE BYTES PER CHARACTER
l85C 4403 G 512:
l65C 26: 8A 04 4404 G MOV AL,E5:(Slj GET COLOR COMPARED BYTE
185F F6 00 4405 G NOT AL ADJUST
1861 86 46 00 4406 G MOV 5S; [BPj,AL SAVE I N STORAGE AREA
1664 45 4407 G ING BP NEXT LOCAT I ON
1865 03 36 044A R 4408 G ADD SI,CRT_COlS PO I NTER I NTO REGEN
1869 4B 4409 G DEG BX LOOP CONTROL
186A 75 FO 4410 G JNZ S'2 DO I T SOME MORE

138 IBM Enhanced Graphics Adapter August 2, 1984

186C 58 4411 C POP BX RECO¥ER BYTES PER CHAR
1860 88 0500 4412 C MO¥ AX,500H UNDO READ MODE
1870 4413 C GRX_R02 ENOP
4414 C
1870 4415 C
4416 C
4417 C j----- SAVE AREA HAS CHARACTER IN IT, MATCH IT
4418 C
1870 E8 0015 R 4419 C CALL OUT OX SET READ MODE BACK
1873 C4 3E 010C R 4420 C LES DI,GRX_SET GET FONT DEFINITIONS
1877 28 EB 4421 C SUB BP,BX ADJUST POINTER TO
4422 C BEG I NN I NG OF SAVE AREA
1879 8B F5 4423 C MOV SI, BP
1878 FC 4424 C ClD ; ENSURE 0 I RECT I ON
187C BO 00 4425 C MOV AL,O CODE POINT BEING MATCHED
187E 16 4426 C PUSH SS ADDRESSING TO STACK
187F 1F 4427 C POP DS FOR THE STR I NG COMPARE
1880 6A 0100 4428 C MOV OX, 2560 NUM8ER TO TEST AGA I NST
1883 4429 C
1883 56 4430 C PUSH SI SAVE SAVE AREA PO INTER
1884 57 4431 C PUSH DI SAVE CODE PO INTER
1885 86 CB 4432 C MOV CX,BX NUMBER OF BYTES TO MATCH
1887 F3/ A6 4433 C REPE CMPSB COMPARE THE 8 BYTES
1889 5F 4434 C POP DI RECOVER THE POINTERS
18BA 5£ 4435 C POP SI
1888 74 07 4436 C JZ S18_5 IF ZFL SET, THEN MATCH
4437 C OCCURRED
1880 FE CO 4438 C INC Al NO MATCH, ON TO NEXT
188F 03 FB 4439 C ADD DI,BX NEXT CODE POINT
1891 4A 4440 C DEC DX LOOP CONTROL
1892 75 EF 4441 C JNZ S17_5 DO ALL OF THEM
1894 4442 C AL"CHAR, 0 I F NOT FOUND
1894 03 E3 4443 C ADD SP,BX READJUST THE STACK
1896 £9 219£ R 4444 C JMP V_RET
4445 C
4446 C ;----- WRITE CHARACTER/ATTRIBUTE AT CURRENT CURSOR POSITION
4447 C
4448
4449
C
C
;-wRi TE~AC~CURRENT -------------------------------
4450 C TH I 5 ROUT I NE WR I TES THE ATTR I BUTE
4451 C AND CHARACTER AT THE CURRENT CURSOR
4452 C POS I T I ON
4453 C INPUT·
4454 C (AH) = CURRENT CRT MODE
4455 C (SH) " DISPLAY PAGE
4456 C (CX) " COUNT OF CHARACTERS TO WRITE
4457 C (AL) " CHAR TO WRITE
4458 C (BLI " ATTR I BUTE OF CHAR TO WR I TE
4459 C (OS) = DATA SEGMENT
4460 C ( ES) = REGEN SEGMENT
4461 C OUTPUT
4462 C NONE

1899
4463
4464
C
C
1;;9 ----------------------------------- ----------
~

4465 C ASSUME OS:ABSO

1899 £8 OCFE R 4466 C CALL DDS
189C 8A 26 0449 R 4467 C MDV AH, CRT_MODE
4468 C
18AO 80 FC 04 4469 C CMP AH,4 IS THIS GRAPHICS
18A3 72 08 4470 C JC P6
18A5 80 FC 07 4471 C CMP AH,7 IS THIS BW CARO
18AS 74 03 4472 C JE P6
18AA £8 74 90 4473 C JMP GRAPHICS_WRITE
18AD 4474 C P6: j WR I TE~AC_CONT I NUE
18AD E8 16E8 R 4475 C CAll MK ES
18BO 8A E3 4476 C MOV AH-:-BL GET ATTRIBUTE TO AH
1882 50 4477 C PUSH AX SAVE ON STACK
1883 51 4478 C PUSH CX SAVE WR I TE COUNT
1884 £8 1651 R 4479 C CALL F I NO_pas I T I ON
1887 8B FB 4480 C MDV OI,BX ADDRESS TO D I REG I STER
1889 59 4481 C PDP CX WR I TE COUNT
18BA 58 4482 C PDP BX CHARACTER IN BX REG
l8BB 88 16 0463 R 4483 C MOV ox, ADOR_6845 GET BASE ADDRESS
188F 83 C2 06 4484 C ADD OX,6 POINT AT STATUS PORT
4485 C
4486 C j----- WAIT FOR HORIZONTAL RETRACE
4487 C
18C2 4488 C P7:
18C2 F6 06 0487 R 04 4489 C TEST INFO,4
l8C7 74 OB 4490 C JZ P9A
18C9 4491 C P8:
18C9 EC 4492 C IN Al,DX GET STATUS
18CA A8 01 4493 C TEST AL,l IS IT LOW
l8CC 75 FB 4494 C JNZ PB WAIT UNTIL IT IS
l8CE FA 4495 C ell NO MORE INTERRUPTS
l8CF 4496 C P9:
18CF EC 4497 C IN AL,DX j GET STATUS
1800 A8 01 4498 C TEST AL,l IS IT HIGH
1802 74 FB 4499 C JZ P9 WAIT UNTIL IT IS
1804 4500 C P9A:
1804 88 C3 4501 C MOV AX,BX RECOVER THE CHAR/ATTR
1806 A8 4502 C STOSW PUT THE CHAR(ATTR
1807 F8 4503 C STI I NTERRUPTS BACK ON
1808 E2 [6 4504 C lOOP AS MANY TIMES
180A E9 219E R 4505 C JMP
4506 C
4507 C j----- WRITE CHARACTER ONLY AT CURRENT CURSOR POSITION
4508 C
4509 C
4510 C WR I TE C CURRENT
4511 C ~THIS ROUTINE WRITES THE CHARACTER AT
4512 C THE CURRENT CURSOR POSITION, ATTRIBUTE
4513 C UNCHANGED
4514 C INPUT
4515 C (AH) " CURRENT CRT MODE
4516 C (BH) " DISPLAY PAGE
4517 C (CX) " COUNT OF CHARACTERS TO WRITE
4518 C (AL) " CHAR TO WRITE
4519 C (OS) = DATA SEGMENT
4520 C ( ES) " REGEN SEGMENT
4521 C OUTPUT
4522 C NONE
4523 C
180D 4524 C
4525 C ASSUME DS:ABSO
1800 £8 OCFE R 4526 C CALL DDS
18£0 8A 26 0449 R 4527 C MDV AH, CRT_MODE
4528 C
18E4 80 FC 04 4529 C CMP AH,4 IS THIS GRAPHICS
18E7 72 08 4530 C Je PlD
18E9 80 FC 07 4531 C CMP AH.7 IS THIS BW CARD
18EC 74 03 4532 C JE PlD
4533 C
18EE EB 30 90 4534 C JMP GRAPH I CS_WR I TE
18fl 4535 C P10:
18Fl E8 16EB R 4536 C CALL MK_ES

August 2, 1984 IBM Enhanced Graphics Adapter 139

18F4 50 4537 C PUSH AX ; SAVE ON STACK
18F5 51 4538 C PUSH CX l SAVE WR I TE COUNT
18F6 f8 1651 R 4539 C CALL F I NO_pas IT I ON
18F9 8B FB 4540 C MOV OI,BX ; ADDRESS TO 0 I
18FB 59 4541 C POP ex ; WR I TE COUNT
18FC 5B 4542 C POP BX ; Bl HAS CHAR TO WR I TE
4543 C
4544 C ;----- WAIT FOR HORIZONTAL RETRACE
4545 C
18FD 8B 16 0463 R 4546 C HOV ox, ADDR_6845 GET BASE ADDRESS
1901 83 C2 06 4547 C ADO OX,6 PO I NT AT STATUS PORT
1904 4548 C Pl1:
1904 F6 06 0487 R 04 4549 C TEST INFO,4
1909 74 OB 4550 C JZ P13A
190B 4551 C P12:
190B fC 4552 C IN AL,DX ; GET STATUS
190C A8 01 4553 C TEST AL, , ; IS IT LOW
190E 75 FB 4554 C JNZ P12 ; WAIT UNTIL IT IS
1910 FA 4555 C CLI i NO MORE INTERRUPTS
1911 4556 C P13:
1911 EC 4557 C IN AL,DX ; GET STATUS
1912 A8 01 4558 C TEST AL,1 ; IS IT HIGH
1914 74 FB 4559 C JZ P13 ; WAIT UNTIL IT IS
1916 4560 C P13A:
1916 8A C3 4561 C HOV AL,BL RECOVER CHAR
1918 AA 4562 C STOSB PUT THE CHAR/ATTR
1919 FB 4563 C STI I NTERRU PTS BACK ON
191A 47 4564 C INC BUMP PO I NTER PAST ATTR
191B E2 E7 4565 C LOOP AS REQUESTED
1910 [9 2l9E R 4566 C JHP
4567 C
4568
4569
C
C
; -G~APHics-WRi;:E-------------------------------------------------
4510 C THIS ROUTINE WRITES THE ASCII CHARACTER TO THE
4571 C ; CURRENT POSITION ON THE SCREEN.
4572 C ; ENTRV
4573 C AL = CHARACTER TO WR ITE
4574 C BL = COLOR ATTR I BUTE TO BE USED FOR FOREGROUND COLOR
4575 C I F BIT 7 IS SET, THE CHAR IS XOR'D INTO THE REGEN
4576 C BUffER (0 IS USED FOR THE BACKGROUND COLOR)
4577 C CX = NUMBER OF CHARS TO WRITE
4578 C OS = DATA SEGMENT
4579 C ES = REGEN SEGMENT
4580 C ; EXIT
4581 C NOTH I NG I S RETURNED
4582 C
4583 C GRAPH I CS READ
4584 C THIS ROUTINE READS THE ASCII CHARACTER AT THE CURRENT
4585 C CURSOR POSITION ON THE SCREEN BY MATCHING THE DOTS ON
4586 C THE SCREEN TO THE CHARACTER GENERATOR CODE PO I NTS
4587 C ENTRY
4588 C NONE (0 IS ASSUMED AS THE BACKGROUND COLOR)
4589 C EXIT
4590 C AL = CHARACTER READ AT THAT POSITION (0 RETURNED IF
4591 C NONE FOUND)
4592 C
4593 C ; FOR COMPATIBILITY ROUTINES, THE IMAGES USED TO FORM CHARS ARE;
4594 C CONTAINED IN ROM FOR THE 1ST 128 CHARS. TO ACCESS CHARS
4595 C IN THE SECOND HALF, THE USER MUST INITIALIZE THE VECTOR AT
4596 C INTERRUPT lFH (LOCATION 0007CH) TO POINT TO THE USER
4597 C SUPPLlEO TABLE OF GRAPHIC IMAGES (8X8 BOXES).
4598 C FAILURE TO DO SO WILL CAUSE IN STRANGE RESULTS
4599
4600
C
C
;----------------------------------------------------------------
ASSUME CS: CODE, DS:ABSO, ES: NOTH I NG
1920 4601 C GRAPHICSc~~ITE :~?~ NEAR
1920 80 FC 07 4602 C
1923 72 03
~=P ~~X~WRT
4603 C
1925 E9 1901 R 4604 C
1928 4605 C
1928 E8 16EB R 4606 C CALL
192B B4 00 4607 C MOV ; 0 TO HIGH OF CODE POINT
192D 50 4608 C PUSH ; SAVE CODE PO I NT VALUE
4609 C
4610 C ;----- DETERMINE POSITION IN REGEN BUFFER TO PUT CODE POINTS
4611 C
192E E8 16A4 R 4612 C CALL .26 LOC I N REGEN BUFFER
1931 8B F8 4613 C MOV DI,AX REGEN POINTER IN 01
4614 C
4615 C ;----- DETERMINE REGION TO GET CODE POINTS FROM
4616 C
1933 58 4617 C POP AX RECOVER CODE PO I NT
1934 3C 80 4618 C CMP AL,80H , I S IT I N SECOND HALF
1936 73 06 4619 C JAE 51 ; YES
4620 C
4621 C IMAGE IS IN FIRST HALF, CONTAINED IN ROM
4622 C
1938 C5 36 OlOC R 4623 C LOS SI,GRX_SET
193C E8 06 4624 C JMP SHORT S2 DETERM I NE_MODE
4625 C
4626
4627
C
C
;----- IMAGE IS IN SECOND HALF, IN USER RAM
193E 4628 C S1:
193E 2C 80 4629 C SUB AL,80H
1940 C5 36 007C R 4630 C LOS SI,EXT_PTR
4631 C
4632 C ;----- DETERMINE GRAPHICS MODE IN OPERATION
4633 C
1944 4634 C S2: ; DETERM I NE_MODE
1944 Dl EO 4635 C SAL AX,l ; MULTIPLY CODE POINT
1946 01 EO 4636 C SAL AX,l ; VALUE BY 8
1948 D1 EO 4637 C SAL AX,l
194A 03 Fa 4638 C ADO SI,AX S I HAS OFFSET OF
194C 1E 4639 C PUSH OS DES I RES CODES
1940 E8 OCFE R 4640 C CALL O~S
1950 80 3E 0449 R 06 4641 C CMP CRT_MODE,6
1955 IF 4642 C POP OS
1956 72 2C 4643 C JC 57 ; TEST FOR MEDIUM RES MODE
4644 C
4645 C ;----- HIGH RESOLUTION HaDE
4646 C
~e~-~~~~N
1958 4647 C 53:
1958 57 4648 C PUSH 01 PO INTER
1959 56 4649 C PUSH 51 SAVE CODE PO INTER
195A B6 04 4650 C MOV DH,4 NUMBER OF TIMES THROUGH
195C 4651 C 54: LOOP
195C AC 4652 C LODSB GET BYTE FROM CODE PO I NT
1950 F6 C3 80 4653 C TEST BL,80H SHOULD WE USE THE
1960 75 16 4654 C JHZ 56 FUNCT I ON TO PUT CHAR IN
1962 AA 4655 C STOSB STORE I N REGEN 8UFFER
1963 AC 4656 C LODSB
1964 4657 C 55:
1964 26: 88 85 lFFF 4658 C MOV ES: [0 1+2000H-1 J.AL STORE I N SECOND HALF
1969 83 C7 4F 4659 C ADO 01,79 MOVE TO NEXT ROW I N REGEN
196C FE CE 4660 C DEC OM DONE WI TH LOOP
196E 75 EC 4661 C JNZ 54
1970 5E 4662 C POP 51

140 IBM Enhanced Graphics Adapter August 2, 1984

1971 5F 4663 C POP 01 ; RECOVER REGEN PO INTER
1972 47 4664 C INC 01 ; POINT TO NEXT CHAR pas
1973 E2 E3 4665 C lOOP 53 ,; MORE CHARS TO WRITE
1975 E9 219E R 4666 C JMP V_RET
1978 4667 C S6:
1978 26: 32 05 4668 C XOR Al, ES: I Dt J ,; XOR WITH CURRENT
1978 AA 4669 C STOSB ,; STORE THE CODE PO I NT
197C AC 4670 C lODS8 ; AGAIN FOR 000 FIELD
1970
1982
26: 32 85 1 FFF
EB EO
4671
4612
4673
C
C
C
XOR
JMP 5,
Al, ES: I DI+2000H-l J
; BACK TO MAINSTREAM

4674 C ;----- MEDIUM RESOLUTION WRITE

4675 C
1984 4616 C S7: ,; MED_RES_WRITE
1984 8A 03 4677 C MOV DL,Bl ; SAVE HIGH COLOR BIT
1986 01 £7 4678 C SAL 01,1 ; OFFSET*2, 2 BYTES/CHAR
1988 E8 1660 R 11-679 C CALL 51' ; EXPAND Bl TO FUll WORD
1988 4680 C S8: ; OF COLOR
198B 57 4681 C PUSH 01 ; SAVE REGEN POINTER
198C 56 4682 C PUSH 51 ; SAVE THE CODE POINTER
1980 B6 04 4683 C MOV DH,4 ; NUMBER OF lOOPS
198F 4684 C S9:
198F AC 4685 C loose eET CODE POINT
1990 E8 1682 R 4686 C CAll 521 DOUBLE UP All THE BITS
1993 23 C3 4687 C AND AX,BX CONVERT THEM TO FORE-
4688 C GROUND COLOR (0 BACK)
1995 F6 C2 80 4689 C TEST DL,80H IS THIS XOR FUNCTION
1998 74 07 4690 C JZ 510 NO, STORE IT IN AS IT IS
199A 26: 32 25 4691 C XOR AH,ES:[DIJ 00 FUNCT I ON WITH HALf
199D 26: 32 45 01 4692 C XOR Al,ES:IDI+1J AND WITH OTHER HALF
19A1 4693 C S10:
STORE FIRST BYTE
~~;lg:ll~~Al
19A1 26: 88 25 4694 C MOV
19A4 26: 88 45 01 4695 C HOV STORE SECOND BYTE
19A8 AC 4696 C Loose GET CODE PO I NT
19M E8 1682 R 4697 C CAll 521
19AC 23 C3 4698 C AND AX,8X CONVERT TO COLOR
19AE F6 C2 80 4699 C TEST Dl,80H IS THIS XOR FUNCTION
1981 74 OA 4100 C JZ 511 NO, JUST STORE THE VALUE
19B3 26: 32 A5 2000 4701 C XOR AH, ES; I D I +200DH J FUNCT I ON WITH FIRST HALF
19B8 26: 32 85 2001 4702 C XOR Al, ES: I D 1+2001H J AND WITH SECOND HALF
19BO 4703 C S11:
19BD 26: 88 A.5 2000 4704 C MOV ES: [01+2000HJ,AH
19C2 26: 88 85 2001 4705 C MOV ES: [01 +2000H+l J,Al STORE I N SECOND PORT I ON
19C7 83 C7 50 4706 C ADD 01,80 POINT TO NEXT LOCATION
19CA
19CC
19CE
FE CE
75 Cl
5E
4707
4708
4709
C
C
C
DEC
JNZ
POP
5,
DH

51
KEEP GOING
RECOVER CODE paNTER
19CF 5F 4710 C POP 01 RECOVER REGEN PO INTER
1900 47 4711 C INC 01 PO I NT TO NEXT CHAR
1901 47 4712 C INC 01
1902 E2 87 4713 C lOOP 58 ; MORE TO WR ITE
1904 E9 219E R 4714 C JMP V_RET
1907 4715 C GRAPH I CS_WR I TE ENDP
4716 C
4717 C
4718
4719
C
C I. -ENTRY-i~-~-~i~~~~:i~~!:::----------·--------------------------
4720 C
4721 C
4722 C CX '" COUNT OF CHARS TO WR ITE

1907
4723
4724
4725
C
C
C
bRX=WRj-:~~~::--~~~::::~-::~~:~::::------------------------------
1907 80 FC OF 4726 C CMP AH, OFH 640X350 GRAPH t cs
190A 72 DE 4721 C J8 NO_ADJl
190C E8 14F7 R 4728 C CAll MEM_DET BASE CARD

~~D :~~~g~~010'8
190F 72 09 4729 C
19E1 80 E3 65 4730 C 85H, XOR C2 CO MASK
19E4 8A E3 4131 C MOV AH,8l
19E6 DO E4 4732 C SHl AH,1 EXPAND CO TO Cl, C2 TO C3
19E8 OA DC 4733 C OR Bl,AH BUilD ?(80H) + (O,3,C,n
19EA 4734 C NO_ADJ1 :
19EA 2A E4 4735 C SUB AH,AH ; ZERO
19EC F7 26 0485 R 4736 C MUL POINTS ,; OFFSET FONT TABLE BASE
19FO 50 4737 C PUSH AX ; FONT TABLE DISPLACEMENT
19F1 E8 16BA R 4738 C CAll GR_CUR ; GET OFFSET I NTO REGEN
19F4 8B F8 4739 C MOV DI,AX , INTO DESTI NATION
19F6 88 2E 0485 R 4740 C HOV BP,POINTS ; ByTES PER CHAR
"741 C SRlOAO ES,OAOOOH ; REGEN SEGEMNT
19FA BA AQOO 4742 C+ MOV DX,OAOOOH
19FD 8E C2 4743 C+ MOV ES,DX
19FF C5 36 010C R 4744 C LOS SI,GRX_SET ; ADDRESS I NG TO FONTS
lA03 58 4745 C POP AX ; RECOVER OF fSET
lA04 03 FO 4746 C ADD SI,AX ; CHARACTER I N TABLE
1A06 86 03 4747 C MOV DH,3
lA08 4748 C S20A:
lA08 F6 C3 80 4749 C TEST Bl,080H ; TEST FOR XOR
lA08 74 08 4750 C JZ NO_XOR ; NO XOR
lAOD 82 CE 4751 C MOV OL, GRAPH_ADOR
lAOF 88 0318 4752 C MOV AX,0318H GRAPH I CS CH I P XOR
1A12 E8 0015 R 4753 C CAll OUT_OX SET REG I STER
1A15 E8 lE 90 4754 C JMP '.2 SKIP BLANK
lA18 4755 C NO_XOR: BLANK BOX FOR CHAR
1A18 57 4756 C PUSH 01 SAVE REGEN PO INTER
1A19 82 C4 4757 C MOV Dl, SEILADDR
1A18 88 020F 4758 C MOV AX,020FH ENABLE ALL MAPS
lA1E E8 0015 R 4759 C CAll OUT_OX
1A21 28 CO 4760 C SUB AX,AX ; STORE ZERO
1A23 51 4761 C PUSH ex ; SAVE CHARACTER COUNT
1A24 88 CD 4762 C MOV CX,BP ; GET ByTE COUNT
lA26 1E 4763 C PUSH OS
lA27 E8 OCFE R 4764 C CALL DDS
lA2A 4765 C S13A:
1A2A AA 4766 C STOSB ,; ZERO REGEN 8YTE
lA28 03 3E 044A R 4767 C ADD OI,CRT_COlS ; NEXT BVTE OF BOX
lA2F 4f 4768 C DEC 01 ; ADJUST
1A30 E2 F8 4769 C lOOP 513A ; NEXT BYTE
1A32 lF 4770 C POP OS
lA33 59 4771 C POP ex RECOVER CHARACTER COUNT
lA34 5f 4772 C POP 01 RECOVER REGEN POINTER
lA35 4773 C
lA35 82 CII- 4774 C HOV Dl,SEQ_ADOR
lA37 84 02 4775 C MOV AH,02H SET MAP MASK
lA39 8A C3 4776 C HOV Al,8l FOR COLOR
lA38 E8 0015 R 4777 C CALL OUT_OX SET THE CHIP
lA3E 57 4778 C PUSH 01 SAVE OFFSET I N REGEN
lA3F 53 4779 C PUSH BX SAVE COLOR VALUE
1A40 51 4780 C PUSH CX SAVE CHACTER COUNT
lA41 88 DO 4781 C MOV 8X,BP LOOP CONTROL, BYTES/CHAR
lA43 1E 4782 C PUSH OS SAVE FONT SEGMENT
lA44 E8 OCFE R 4783 C CAll DDS SET LOW RAM SEGMENT
4784 C ASSUME DS:ABSQ
lA47 88 OE 044A R 4785 C MOV CX,CRT_COlS ; GET COLUMN COUNT
lA48 lF 4786 C POP OS ; RESTORE FONT SEGMENT
4787 C ASSUME DS:NOTHING
lA4C 4788 C SlK: ; WRITE OUT THE CHARACTER

August 2, 1984 mM Enhanced Graphics Adapter 141

lA4C 8A 04 4789 MOV AL,OS:ISlj CODE POINT

~~:f~i\~U
lA4E 26: 8A 25 4790 MOV LATCH DATA
lASl 26: 88 05 4791 MOV WR ITE ONE BYTE OF FONT
lAS4 46 4792 INC 51 NEXT FONT PO I NT
lASS 03 F9 4793 ADO OI,CX ONE ROW BELOW LAST PO I NT
lAS7 4B 4794 DEC BX BYTES PER CHAR COUNTER
lAS8 75 F2 4795 JNZ SlK DO NEXT ROW OF CHARACTER
4796
lASA 59 4797 POP CX ; CHARACTER COUNT
lA5B 5B 4798 POP BX ; COLOR VALUE
lA5C 2B FS 4799 SUB SI, BP ; ADJUST PTR TO FONT TABLE
lA5E 5F 4800 POP 01 ; REGEN PO INTER
lA5F 47 4801 INC 01 ; NEXT CHAR POSN I N REGEN
lA60 E2 A6 4802 LOOP S20A ; WR ITE ANOTHER CHARACTER
4803
lA62 82 CE 4804 MOV Dl, GRAPH_ADDR
lA64 B8 0300 4805 MOV AX,0300H NORMAL WR I TE, NO ROTATE
lA67 E8 0015 R 4806 CAll OUT_OX SET THE CHI P
lA6A 82 C4 4807 MOV DL, SEQ_AODR
lA6C B8 020F 4808 MOV AX,020FH ENABLE ALL MAPS
lA6F E8 0015 R 4809 CALL OUT_OX SET THE CHI P
lA72 E9 219E R 4810 JMP V_RET
lA7S 4811 GRX_WRT ENOP
4812
4813 SUBTTL
4814
4815 ;----- SET COLOR PALETTE
4816
lA7S 4817 AHB:
4818 ASSUME DS:ABSO
lA75 80 3E 0463 R B4 4819 CMP BYTE PTR AODR_684S,OB4H
lA7A 74 09 48'20 JE M21_B ; CALL VAll 0 ONLY FOR COLOR
lA7C F6 06 0487 R 02 4821 TEST INFO,2 ; SEE I FITS THE OLD COLOR CARD
lA81 74 05 4822 JZ M21_A I F NOT, HANDLE I THERE
lAS3 CO 42 4823 INT 42H ; OLD CODE CALL
lA85 4824 M21_B:
lA85 E9 219E R 4825 JMP V_RET ; BACK TO CALLER
lAS8 4826 M21_A:
lAS8 2B CO 4827 SUB AX,AX
lA8A 8B E8 4828 MOV BP,AX
lA8C C4 3E 04A8 R 4829 LES DI,SAVE_PTR
lA90 83 C7 04 4830 ADD 01,4
lA93 26: C4 30 4831 LES DI,OWORD PTR ES:IDlj
lA96 8C CO 4832 MOV AX,ES
lA98 DB C7 4833 OR AX,OI
lA9A 74 01 4834 JZ NOT4AHB
lA9C 45 4835 INC BP
lA90 4836 NOT4AHB:
lA90 E8 lOCO R 4837 CALL PAL INIT
lAAO OA FF 4838 OR BH,SH
1AA2 75 65 4839 JNZ M20
4840
4841 ; ----- HANDLE BH == 0 HERE
4842 ALPHA MODES => BL == OVERSCAN COLOR
4843 GRAPHICS "'> BL == OVERSCAN AND BACKGROUND COLOR
4844
4845 ;----- MOVE INTENSITY BIT FROM 03 TO 04 FOR COMPATIBILITY
4846
lAA4 8A FB 4847 MOV BH, BL
lAM AD 0466 R 4848 MOV AL, CRT_PALETTE
lAA9 24 EO 4849 AND AL,OEOH
lAAB 80 E3 1 F 4850 AND BL, 01 FH
lAAE OA C3 4851 OR AL,BL
lABO A2 0466 R 4852 MOV CRT_PALETTE,AL
lAB3 8A OF 4853 MOV BL,BH
lABS 80 E7 08 4854 AND BH,08H
lAB8 DO E7 4855 SHL BH,1
lABA 8A E8 4856 MOV CH,AL
lABC 80 E5 EF 4857 AND CH,OEFH
lABF OA ED 4858 OR CH, CH
1AC1 80 E3 OF 4859 AND BL.OFH
lAC4 8A F8 4860 MOV SH,BL
lAC6 DO £3 4861 SHL BL,l
lAC8 80 E3 10 4862 AND Bl,010H
lACB 80 E7 07 4863 AND BH,07H
lACE OA OF 4864 OR BL,BH
4865
lADO AO 0449 R 4866 MOV AL, CRT_MODE
lAD3 3C 03 4867 CMP AL,3
lAD5 76 OE 4868 JBE M21
4869
4870 ; ----- GRAPH I CS MODE DONE HERE (SET PALETTE 0 AND OVERSCAN)
4871
lAD7 B4 00 4872 MOV AH,O
lAD9 8A C3 4873 MOV AL,BL
lADB E8 109F R 4874 CALL PAL_SET
4875
lADE OB ED 4876 OR BP, BP
lAEO 74 03 4877 JZ M21
lAE2 26: 88 10 4878 MOV ES:(DI],BL
4879
4880 ;----- ALPHA MODE DONE HERE (SET OVERSCAN REGISTER)
4881
lAE5 4882 M21:
lAE5 80 3E 0449 R 03 4883 CMP CRT_MODE,3 ; CHECK FOR AN ENHANCED MODE
lAEA 77 05 4884 JA SET OVRSC ; NO CHANCE
lAEC E8 OE9A R 4885 CALL BRST DET ; SEE I F WE ARE ENHANCED
1AEF 72 07 4886 JC SKI P=OVRSC ; THERE I S NO BORDER
lAF1 4887 SET_OVRSC:
1AF1 64 11 4888 MOV AH,OllH ; OVERSCAN REG I STER
1AF3 8A C3 4889 MOV AL,BL
lAF5 E8 lD9F R 4890 CALL PAL_SET ; SET THE BORDER
lAF8 4891 SKIP~OVRSC:
lAF8 OB ED 4892 OR BP, SP
lAFA 74 04 4893 JZ M21Y
lAFC 26: 88 50 10 4894 MOY ES:(DI )(16Dj,BL
lBOO 4895 M21Y:
lBOO 8A DO 4896 MOV BL,CH
1B02 80 E3 20 4897 AND BL,020H
lB05 S1 05 4898 MOV CL,5
1807 02 EB 4899 SHR BL,CL
4900
4901 HANDLE BH = 1 HERE
4902 ALPHA MODES ==> NO EFFECT
4903 GRAPH I CS ==> LOW 81 T OF BL == 0
4904 PALETl E 0 == BACKGROUND
4905 PALETTE 1 == GREEN
4906 PALETTE 2 '" RED
4907 PALETTE 3 '" BROWN
4908 => LOW B IT OF BL == 1
4909 PALETTE 0 == BACKGROUND
4910 PALETTE 1 == CYAN
4911 PALETTE 2 == MAGENTA
4912 PALETTE '3 = WH I TE
4913
4914

142 IBM Enhanced Graphics Adapter August 2, 1984

1809 4915 H2O:
1809 80 3E 0449 R 03 4916 CMP CRT_MODE,3
lBOE 76 4A 4917 JBE MBO
4918
1810 AO 0466 R 4919 MOV AL,CRT_PALETTE
1813 24 OF 4920 AND AL,OOFH
lB15 80 E3 01 4921 AND BL,1
lB18 74 02 4922 JZ M22
lB1A oe 20 4923 OR AL,020H
lBle 4924 M22:
lBle
lB1F
A2
24
0466 R
10
4925
4926
MOV
AND ~~~O~~~ETTE,AL
lB21 oe 02 4927 OR AL,2
lB23 OA 08 4928 OR BL,AL
lB25 B4 01 4929 MOV AH,l
1B27 SA C3 4930 MOV Al,BL
1B29 E8 lD9F R 4931 CALL PAL_SET
4932
182e OB ED 4933 OR 8P,BP
lB2E 74 04 4934 JZ M22Y
1830 26: 88 50 01 4935 MOV ES:[DI][l],BL
lB34 4936 M22Y:
4937
1834 FE C3 4938 INC BL
1B36 FE C3 4939 INC BL
lB38 B4 02 4940 MOV AH,2
lB3A 8A C3 4941 MOV AL,BL
lB3C E8 109F R 4942 CALL PAL_SET
4943
lB3F DB EO 4944 OR BP,8P
lB41 74 04 4945 JZ M27Y
1 B43 26: 88 50 02 4946 MOV ES: (01 J[2].BL
1847 4947 M27Y:
4948
1847 FE C3 4949 INC BL
lB49 FE C3 4950 INC BL
lBilB 84 03 4951 MOV AH,3
lB40 SA C3 4952 MOV AL, BL
lB4F E8 lD9F R 4953 CALL PAL_SET
4954
lB52 OB ED 4955 OR BP, BP
lB54 74 04 4956 JZ M80
1 B56 26: 88 50 03 4957 MOV ES:[DIJ[3],BL
4958
lB5A 4959 M80:
1B5A E8 lDB7 R 4960 CALL
lB5D E9 219E R 4961 JMP
4962
4963 e INCLUDE vaoT. INC
4964 e SUBTTL VDOT. I Ne
4965 e PAGE
4966 e : ----------- ... ------------------------------------
4967 e ENTRY
4968 e OX = ROW
4969 e CX = COLUMN
4970 e BH = PAGE
4971 e EXIT
4972 e BX = OFFSET I NTO REGEN
4973 e AL = BIT MASK FOR COLUMN BYTE
4974 e b~;=;up=~-------PROC----NEAR---------------------
lB60 4975 e
4976 e
4977 e ; ----- OFFSET'" PAGE OFFSET + ROW * BYTES/ROW + COLUMN/8
4978 e
1 B60 F7 26 044A R 4919 e MUL ~~RD PTR CRT_COlS ROW * BYTES/ROW
1B64 51 4980 e PUSH SAVE COLUMN VALUE
lB65 al E9 4981 e SHR CX,l DIVIDE BY EIGHT TO
lB67 al E9 4982 e SHR CX.1 DETERM I NE THE BYTE THAT
1869 01 E9 4983 e SHR CX,l THIS DOT IS IN
4984 e (8 BITS/BYTE)
186B 03 Cl 4985 e ADD AX, ex BYTE OFFSET I NTO PAGE
lB60 8A OF 4986 e MOV BL,BH GET PAGE INTO BL
lB6F 2A FF 4987 e SUB BH,BH ZERO
1871 88 CB 4988 e MOV cX,ax COUNT VALUE
lB73 88 1E 044C R 4989 e MOV BX,CRT_LEN LENGTH OF ONE PAGE
lB77 E3 04 4990 e JeXl DS_2 PAGE ZERO
lB79 4991 e
lB79 03 C3 4992 e ADD AX,BX BUMP TO NEXT PAGE
1878 E2 FC 4993 e LOOP DS_3 DO FOR THE REST
1870 4994 e
1870 59 4995 e POP ex RECOVER COLUMN VALUE
187E 8B 08 4996 e MOV BX,AX REGEN OFFSET
lB80 80 El 07 4997 e ANO CL,07H SH I FT COUNT FOR 8 I T MASK
lB83 BO 80 4998 e MOV AL,080H MASK BIT
lB85 02 E8 4999 e SH' AL,CL POSITION MASK BIT
1887 C3 5000 e RET
lB88 5001 e DOT_SUP_l ENOP
5002 e
5003 e
5004 e ; -;iii;-;UBROUTi NE-DET ERM i HE; -TttE-~EGEN-B;TE- ~OCAT i ON -----
5005 e ; OF THE INDICATED ROW COLUMN VALUE IN GRAPHICS MODE.
5006 e ; ENTRY --
5007 e ; OX = ROW VALUE (0-1991
5008 e ; CX'" COLUMN VALUE (0-639)
5009 e ; EXIT --
5010 e ; SI '" OFFSET INTO REGEN BUFFER FOR BYTE OF INTEREST
5011 e ; AH = MASK TO STRI P OFF THE BITS OF INTEREST
5012 e ; CL'" BITS TO SHIFT TO RIGHT JUSTIFY THE MASK IN AH
5013 e ; DH = # 8ITS IN RESULT

1888
5014
5015
e
e k;------PROC----NEAR-------------------------------------
lB88 53 501~ e PUSH BX SAVE BX DURING OPERATION
lB89 50 5017 e PUSH AX WILL SAVE AL DURING OPERATION
5018 e
5019 e ;----- DETERMINE 1ST BYTE IN IDICATED ROW BY MULTIPLYING ROW VALUE BY 40
5020 e ;----- ( LOW BIT OF ROW DETERMINES EVEN/aDO, 80 BYTES/ROW
5021 e
lB8A BO 28 5022 e MOV AL,40
lB8C 52 5023 e PUSH ox SAVE ROW VALUE
lB8D 80 E2 FE 5024 e AND DL,OFEH STR I P OFF ODD/ EVEN BIT
1890 F6 E2 5025 e MUL DL AX HAS ADDRESS OF 1 ST BYTE
5026 e OF INDICATED ROW
lB92 5A 5027 e POP ox RECOVER IT
1893 F6 C2 01 5028 e TEST DL,l TEST FOR EVEN/ODD
1896 74 03 5029 e JZ R4 JUMP I F EVEN ROW
1898 05 2000 5030 e ADD AX,20aOH OFFSET TO LOCATION OF ODD ROWS
lB98 5031 C R4: EVEN_ROW
1B98 88 FO 5032 e MOV SI,AX MOVE POINTER TO SI
1890 58 5033 e POP AX RECOVER AL VALUE
lB9E 88 01 5034 e MOV oX,ex COLUMN VALUE TO D?(
5035 e
5036 e ; ----- DETERM IHE GRAPH I CS MODE CURRENTLY I N EFFECT
5037 e
5038 e ; -SET-UP-;HE -REG i ;TERS-ACCORDING-TO -;HE-MODE---------------------
5039 e
5040 e CH ;; MASK FOR LOW OF COLUMN ADDRESS ( 7/3 FOR HI GH/MED RES)

August 2, 1984 IBM Enhanced Graphics Adapter 143

 5041 C , CL = # OF ADDRESS BITS I N COLUMN VALUE ( 3/2 FOR HIM)
5042 C ; BL = MASK TO SELECT BITS fROM POINTED BYTE (BOH/COH FOR HIM)
5043 C ; BH = NUMBER OF VALID BITS IN POINTED BYTE ( 1/2 FOR HIM)
5044 C • - ----------- - - - - - ----------------- ---------------------- - --- ----
5045 e
lBAO BB 02CO 5046 e MOV BX.2COH
lBA3 B9 0302 5047 e MOV CX,302H SET PARMS fOR MED RES
lBA6 SO 3E 0449 R 06 5048 e eMP CRT_MODE, 6
lBAB 12 06 5049 e Je R5 HANDLE I F MED ARES
1BAD BB 0180 5050 e MOV BX,180H
1 BBO B9 0103 5051 e MOV CX,703H SET PARMS FOR HIGH RES
5052 e
5053 e ; ----- DETERM I HE BIT OfFSET I N BYTE FROM COLUMN MASK
5054 e
lBB3 5055 C R5:
lBB3 5056 e AND CH,OL ; ADDRESS OF PEL WITHIN BYTE TO CH
5057 e
5058 e ; ----- DETERM I NE BYTE OFFSET FOR TH I S LOCAT I ON I N COLUMN
5059 e
lBB5 03 EA 5060 e SHR DX,CL SH I FT BY CORRECT AMOUNT
lBB1 03 F2 5061 e ADO 51 ,OX I NCREMENT THE PO INTER
lBB9 8A F1 5062 e MOV OH,SH GET THE # Of BITS IN RESULT TO DH
5063 e
5064 e ;----- MULTIPLY BH (VALID BITS IN BYTE) BY CH (BIT OFfSET)
5065 e
lSBB 2A C9 5066 e SUB CL,CL ; ZERO INTO STORAGE LOCATION
lBBD 5067 C R6:
lBBO 00 C8 5068 e ROR AL,l LEFT JUSTIFY THE VALUE
5069 e IN AL (FOR WRITE)
lBBF 02 CD 5070 C ADO CL,CH AOD I N THE BIT OFFSET VALUE
lBCT FE CF 5071 e DEC BH LOOP CONTROL
lBC3 75 F8 5072 e JNZ R6 ON EXIT. CL HAS SHI FT COUNT
5013 e TO RESTORE BITS
lBC5 8A £3 5014 e MOV AH,BL GET MASK TO AH
lBC7 02 EC 5075 e SHR AH,CL MOVE THE MASK TO CORRECT LOCATION
1 BC9 5B 5076 e POP BX RECOVER REC
TBCA C3 5077 e RET RETURN WITH EVERYTHING SET UP
lBCB 5078 e R3 ENOP
5079 e
5080
50S1
e
e
; ----------------------------------------------------------------
READ DOT -- WRITE DOT
5082 e THESE ROUTINES WILL WRITE A DOT, OR READ THE DOT AT
5083 e THE INDICATED LOCATION
5084 C ENTRY --
5085 e OX'" ROW {0-199) {THE ACTUAL VALUE DEPENDS ON THE MODE)
5086 e CX == COLUMN ( 0-639) ( THE VALUES ARE NOT RANGE CHECKED)
5087 e AL = DOT VALUE TO WRITE (1,2 OR 4 BITS DEPENOING ON MODE,
5088 e REQ'D FOR WRITE DOT ONLY, RIGHT JUSTIFIED)
5089 e BIT 1 OF AL=l INDICATES XOR THE VALUE INTO THE LOCATION
5090 e OS = DATA SEGMENT
5091 e ES = RECEN SEGMENT
5092 e
5093 e
e
.------------------------------------------------------------ ----
5094 ; EXIT AL = DOT VALUE READ, RIGHT JUSTIFIED, READ ONLY
5095 e
5096 e
5097 e ; ----- WR I TE DOT
5098 e
lBCB 5099 e AHC:
5100 e ASSUME OS:ABSO
lBCB 80 3£ 0449 R 07 5101 e eMP CRT_MODE,1
lBOO 77 2A 5102 e JA WR I TE_DOT_2
5103 e
lBD2 5104 e WRITE_DOT PROC NEAR
5105 e ASSUME OS: ABSO, ES: NOTH I NG
1B02 52 5106 e PUSH OX
5101 C SRLOAD ES,OB800H
lBD3 SA B800 5108 c+ MOV DX,OB800H
1 BD6 8E C2 5109 c+ MOV ES,DX
lBD8 SA 5110 C POP OX
1 B09 50 5111 C PUSH AX SAVE DOT VALUE
lBOA 50 5112 C PUSH AX TWICE
lBOB £8 lB88 R 5113 e CALL R3 DETERMINE BYTE POSITION OF THE DOT
lBOE 02 E8 5114 C SHR AL,CL SHIFT TO SET UP THE BITS fOR OUTPUT
lBEO 22 C4 5115 e AND AL,AH STR I P OFf THE OTHER BITS
lB£2 26: 8A DC 5116 e MOV CL,ES:(Sll GET THE CURRENT BYTE
18£5 58 5117 e POP BX RECOVER XOR FLAG
1BE6 f6 C3 80 5118 e TEST BL,80H IS IT ON
lBE9 75 00 5119 e JNZ R2 YES, XOR THE DOT
lBEB f6 04 5120 e NOT AH SET THE MASK TO REMOVE THE
lBEO 22 CC 5121 e AND CL,AH INDICATED BITS
lBEf OA C1 5122 e OR AL,CL OR I N THE NEW VALUE OF THOSE BITS
lBFl 5123 C Rl: FIN ISH_DOT
lBFl 26: 88 04 5124 e MOV ES: (SI ],AL RESTORE THE BYTE I N MEMORY
lBF4 58 5125 e POP AX
l8F5 E9 219E R 5126 e JMP V_RET
lBF8 5127 C R2: XOR_DOT
lBF8 32 Cl 5128 C XOR AL,CL EXCLUSIVE OR THE DOTS
lBFA
TBFC
EB F5 5129
5130
C
e
JMP
WRITE_DOT
R'ENDP FINISH UP THE WRITING

5131 e
lBFC 5132 C WRITE DOT 2 PROC NEAR
lSFC 80 3£ 0449 R Of 5133 e ~ CMP CRT _MOOE, 0 FH
lCOl 72 00 5134 C JB NO_ADJ2
lC03 E8 14F1 R 5135 C CALL MEM_DET ; BASE CARD
1C06 72 08 5136 C JC NO_AOJ2
lC08 24 85 5137 C AND AL,10000101B ; 85H, XOR C2 CO MASK
lCOA 8A EO 5138 C MOV AH,AL
lCOC DO E4 5139 C SHL AH,l EXPAND CO TO Cl, C2 TO C3
lCOE OA C4 5140 C OR AL,AH BUILD ?(80H) + (0,3,C,F)
lClO 5141 C NO ADJ2:
lC10 50 5142 C - PUSH AX
lCll 8B C2 5143 e MOV AX,OX ROW VALUE
lCB £8 1B60 R 5144 e CALL OOT_SUP_l BX=OFFSET, AL=B IT MASK
lCl6 B6 03 5145 C MOV DH,3
lC1S B2 CE 5146 e MOV OL, GRAPH_AODR GRAPHICS CHIP
lC1A B4 08 5147 C MOV AH,G_BIT_MASK BIT MASK REG I STER
lC1C E8 0015 R 5148 C CALL OUT_OX SET BIT MASK
lCl F 52 5149 e PUSH OX
5150 e SRLOAD ES,OAOOOH REGEN SEGMENT
1C20 BA AOOO 5151 e+ MOV OX,OAOOOH
lC23 8E C2 5152 e+ MOV ES,OX
lC25 5A 5153 C POP OX
1C26 58 5154 C POP AX RECOVER COLOR
1C27 8A E8 5155 C MOV CH,AL SAVE COLOR
1C29 F6 C5 80 5156 C TEST CH,080H SEE IF XOR
1C2C 74 OA 5157 C JZ WD_A NO XOR
lC2E B4 03 5158 C MOV AH,G_OATA_ROT DO XOR
lC30 BO 18 5159 e MOV AL,018H XOR FUNCTt ON
lC32 E8 0015 R 5160 C CALL OUT_OX SET THE REG I STER
lC35 EB 12 90 5161 e JMP WD_B SK I P THE BLANK
lC38 5162 e BLANK THE DOT
lC38 B2 C4 5163 e MOV DL,SE<LAOOR SEQUENCER
lC3A B4 02 5164 e MOV AH,S_MAP MAP MASK
lC3C BO FF 5165 e MOV AL,OfFH ENABLE ALL MAPS
lC3E E8 0015 R 5166 e CALL OUT_OX SET THE REG I STER

144 IBM Enhanced Graphics Adapter August 2, 1984

lC4l 26: 8A 07 5167 c MOV AL, ES: [BX] LATCH DATA
lC44 2A CO 5168 c SUB AL,AL ZERO
lC46 26: 88 07 5169 c MOV ES: [BX],AL BLANK THE DOT
lC49 5170 C WD_B: SET THE COLOR MAP MASK
lC49 B2 C4 5171 C MOV DL, SEQ_AODR SEQUENCER
lC4B B4 02 5172 C MOV AH, S_MAP MAP MASK REG' STER
lC4D 8A C5 5173 C MOV AL,CH COLOR VALUE
lC4F 24 OF 5174 C ANO AL,OFH VALUES 0-15
lC51 E8 0015 R 5175 C CALL OUT_OX SET IT
lC54 26: 8A 07 5176 C MOV AL, ES: [6X] LATCH DATA
1C57 80 FF 5177 C MOV AL,OFFH WRITE VALUE
lC59 26: 88 07 5178 C MOV ES:(BX],AL SET THE DOT
5179 C
5180 C ;----- NORMALIZE THE ENVIRONMENT
5181 C
lC5C £8 0015 R 5182 C CALL OUT OX ALL MAPS ON
lC5F 82 CE 5183 C MOV DL, GRAPH_ADDR GRAPH I CS CH I PS
lC61 84 03 5184 C MOV AH,G_oATA_ROT XOR REG I STER
lC63 2A CO 5185 C SUB AL,AL NORMAL WR I TES
lC65 £8 0015 R 5186 C CALL OUT_OX SET IT
lC68 84 08 5187 C MOV AH,G_BIT_MASK BIT MASK
lC6A BO FF 5188 C MOV AL,OFFH ALL BITS ON
lC6C E8 0015 R 5189 C CALL OUT OX SET IT
lC6F E9 219E R 5190 C JMP V_RET WR I TE DOT DONE
lC72 5191 C WR I TE_DOT_2 ENoP
5192 C
lC72 5193 C PROC NEAR
5194 C ASSUME oS:ABSO
lC72 50 5195 C PUSH AX
le73 52 5196 C PUSH OX
5197 C SRLOAD ES,OAOOOH
lC74 BA AOOO 5198 c+ MOV OX,OAOOOH
lC77 8E C2 5199 c+ MOV ES,DX
lC79 5A 5200 C POP OX
lC7A 58 5201 c POP AX
lC7B 8B C2 5202 c MOV AX,DX
lC7D E8 1660 R 5203 c CALL 00T_SUP_1
lC80 85 07 5204 c MOV CH,7
lC82 2A E9 5205 c SUB CH,CL
1C84 26 02 5206 c SUB OX,OX
lC86 BO 00 5207 c MOV AL,O
lC88 C3 5208 c RET
lC89 5209 c ENDP
5210 c
lC89 5211 c PROC NEAR
1C89 8A CO 5212 c MOV CL,CH
lC8B B4 04 5213 c MOV AH,4
lC8D 52 5214 c PUSH OX
lC8E B6 03 5215 c MOV DH,3
lC90 B2 CE 5216 c MOV OL, GRAPH_ADDR
lC92 E8 0015 R 5217 c CALL OUT OX
lC95 5A 5218 c POP OX -
1C96 26: 8A 27 5219 c MOV AH, ES: I BX]
1C99 02 [C 5220 c SHR AH,CL
lC9B 80 E4 01 5221 c AND AH,1
lC9E C3 5222 c RET
lC9F 5223 c ENOP
5224 c
5225 c ; ----- READ DOT
5226 C
lC9F 5227 C AHD:
5228 C ASSUME OS:ABSO
lC9F 80 3£ 0449 R 07 5229 C eMP CRT MODE,7
lCA4 77 18 5230 C JA R_l-
5231 C
lCA6 5232 C READ_DOT PROC NEAR
5233 C ASSUME OS: ABSD, ES: NOTH I NG
lCA6 52 5234 C PUSH OX
5235 C SRLOAD ES,OB8DDH
lCA7 BA B800 5236 C+ MOV OX,OBBDOH
lCAA 8E C2 5237 C+ MOV ES,DX
1CAC SA 5238 C POP OX
lCAO E8 1 B88 R 5239 C CALL R3 DETERMINE BYTE POSITION OF DOT
lCBO 26: 8A 04 5240 C MOV AL,ES:[Slj GET THE BYTE
lCB3 22 C4 5241 C ANO AL,AH MASK OFF THE OTHER BITS IN THE BYTE
lCB5 02 EO 5242 C SHL AL,CL LEFT JUSTI FY THE VALUE
lCB7 8A CE 5243 C MOV Cl,DH GET NUMBER OF BITS IN RESULT
lCB9 02 CO 5244 C ROL AL,CL RIGHT JUSTIFY THE RESULT
lCBB E9 219E R 5245 C JMP V_RET
lCBE 5246 C READ_DOT ENDP
5247 C
lCBE 5248 C
lCBE 80 3E 0449 R OF 5249 C CMP CRT MODE,DFH
lCC3 72 25 5250 C JB READ DOT 2
lCC5 E8 14F7 R 5251 C CALL MEM_DET -
lCC8 72 20 5252 C JC READ_DOT_2
5253 C
lCCA 5254 C READ_DOT_' PROC NEAR 2 MAPS
5255 C ASSUME DS;ABSO, ES: NOTH I NG
lCCA £8 lC72 R 5256 C CALL RD_S
lcca E8 lC89 R 5257 C CALL RD_1S
lcao OA 04 5258 C OR Ol,AH
lC02 DO E4 5259 C SHL AH,l
lC04 OA 04 5260 C OR DL,AH
lCD6 BO 02 5261 C MOV AL,2
lCD8 E8 lC89 R 5262 C CALL RO lS
lCOB DO E4 5263 C SHL AH-;-l
lCoD DO E4 5264 C SHL AH,l
lCDF OA 04 5265 C OR OL,AH
lCEl DO E4 5266 C SHL AH,l
lCE3 OA 04 5267 C OR OL,AH
lCE5 8A C2 5268 C MOV AL,DL
lcn E9 219E R 5269 C JMP V_RET
lCEA 5270 C READ_00T_1 ENOP
5271 C
lCEA 5272 C READ_00T_2 PROC NEAR 4 MAPS
5273 C ASSUME DS:ABSO, ES:NOTHING
1CEA E8 lC72 R 5274 C CALL RD_S
lCED 5275 C
lCED E8 1C89 R 5276 C CALL RD_1S
lCFO 8A C8 5277 C MOV CL,AL
lCF2 02 E4 5278 C SHL AH,CL
lCF4 OA 04 5279 C OR DL,AH
lCF6 FE CO 5280 C INC AL
lCF8 3C 03 5281 C CMP AL,3
lCFA 76 Fl 5282 C JBE RD_2A
lCFC SA C2 5283 C MOV AL,DL
lCFE E9 219E R 5284 C JMP V RET
1001 5285 C READ_DOT_2 ENDP
5286 C
5287 C
5288 C WRITE TTY WRITE TELETYPE TO ACTlVE PAGE
5289 C -THIS INTERFACE PROVlOES A TELETYPE LIKE INTERFACE TO THE VIDEO
5290 C CARD. THE INPUT CHARACTER IS WRITTEN TO THE CURRENT CURSOR
5291 C POSt T ION, AND THE CURSOR I S MOVED TO THE NEXT POS IT ION. • F THE
5292 C CURSOR LEAVES THE LAST COLUMN OF THE FIELD, THE COLUMN IS SET

August 2, 1984 IBM Enhanced Graphics Adapter 145

 5293 TO ZERO, AND THE ROW VALUE IS INCREMENTED. If THE ROW VALUE
5294 LEAVES THE FIELD, THE CURSOR IS PLACED ON THE LAST ROW, fiRST
5295 COLUMN, AND THE ENTIRE SCREEN IS SCROLLED UP ONE LINE. WHEN
5296 THE SCREEN IS SCROLLED UP, THE ATTRIBUTE FOR FILLING THE NEWLY
5297 BLANKED LINE IS READ FROM THE CURSOR POSITION ON THE PREVIOUS
5298 LINE BEFORE THE SCROLL, IN CHARACTER MODE. IN GRAPHICS MODE,
5299 THE 0 COLOR IS USED.
5300 ENTRY
5301 (AH) '" CURRENT CRT MODE
5302 (AL) = CHARACTER TO BE WRITTEN
5303 NOTE THAT BACK SPACE, CAR RET, BELL AND LI NE FEED ARE HANDLED
5304 AS COMMANDS RATHER THAN AS DISPLAYABLE GRAPHICS
5305 (BL) FOREGROUND COLOR FOR CHAR WRITE IF CURRENTLY IN A
5306 GRAPH I CS MODE
5307 EXIT
5308 ALL REG I STERS SAVED
5309
1001 5310
5311 ASSUME CS: CODE, DS:ABSD
1001 50 5312 PUSH AX SAVE REG I STERS
1002 SA 3E 0462 R 5313 MOV BH,ACTIVE_PAGE GET THE ACTIVE PAGE
1006 53 5314 PUSH BX SAVE
1007 8A OF 5315 MOV Bl,BH GET PAGE TO BL
1009 32 FF 5316 XOR BH,BH CLEAR HIGH BYTE
100B 01 E3 5317 SAL BX,1 *2 FOR WORD OFFSET
1 DOD 8B 97 0450 R 5318 MOV ox, [BX + OFFSET CURSOR_POSN 1 CURSOR, ACT I VE PAGE
1011 5B 5319 POP BX RECOVER
5320
5321 ox NOW HAS THE CURRENT CURSOR POS I T I ON
5322
1012 3C OU 5323 eMP AL,OOH IS IT CARRIAGE RETURN
1014 74 5C 5324 JE U9 CAR_RET
1016 3C OA 5325 eMP AL,OAH IS IT A LINE FEED
1018 745C 5326 JE Ul0 II NE_FEED
lOlA 3C 08 5327 eMP AL,D8H I SIT A BACKSPACE
lOlC 74 4C 5328 JE U8 BACK_SPACE
101 E 3C 07 5329 eMP Al,07H IS IT A BELL
1020 74 5C 5330 JE U" BELL
5331
5332 ; ----- WR ITE THE CHAR TO THE SCREEN
5333
1022 B4 DA 5334 MOV AH,10 WRITE CHAR ONLY
1024 89 0001 5335 MOV CX,l ONLY ONE CHAR
1027 CO 10 5336 INT 10H WR I TE THE CHAR
5337
5338 POSITION THE CURSOR FOR NEXT CHAR
5339
1029 FE C2 5340 INC DL
102B 3A 16 044A R 5341 CMP OL, BYTE PTR CRT_COLS TEST fOR COLUMN OVERFLOW
102F 75 35 5342 JNZ U7 SET_CURSOR
1031 2A 02 5343 SUB DL,DL COLUMN FOR CURSOR
1033 3A 36 0484 R 5344 CMP DH, ROWS
1037 75 2B 5345 JNZ U6 SET_CURSOR_I NC
5346
5347 ; ----- SCROLL REQU I RED
5348
1039 5349 Ul :
1039 E8 1150 R 5350 ; SET THE CURSOR
5351
5352 ;----- DETERMINE VALUE TO FILL WITH DURING SCROLL
5353
103C AD 0449 R 5354 MOV AL, CRT_MODE ; GET THE CURRENT MODE
103F 3C 04 5355 CMP AL,4
1041 72 06 5355 JB U2 READ-CURSOR
1043 2A FF 5357 SUB BH, BH fiLL WITH BACKGROUND
1045 3C 07 5358 CMP AL,7
1047 75 06 5359 JNE U3 SCROLL-UP
1049 5360 U2: READ-CURSOR
1049 B4 08 5361 MOV AH,8
l04B CO 10 5362 INT 10H READ CHAR/ATTR
1040 8A FC 5363 MOV BH,AH STORE IN BH
1041'" 5364 U3: SCROLL-UP
104F B8 0601 5365 MOV AX,6D1H SCROLL ONE LINE
1052 2B C9 5366 SUB CX,CX UPPER LEfT CORNER
1054 8A 36 0484 R 5367 MOV DH, ROWS lOWER RIGHT ROW
1058 8A 16 044A R 5368 MOV DL, BYTE PTR CRT_CDlS LOWER RIGHT COLUMN
105C FE CA 5369 DEC OL
105E 5370 U4: V I OED-CALL-RETURN
105E CO 10 5371 INT 10N SCROLL UP THE SCREEN
1060 5372 U5: TTY-RETURN
1060 58 5373 POP AX RESTORE THE CHARACTER
1061 E9 219E R 5374 JMP V_RET RETURN TO CALLER
1064 5375 U6: SET-CURSOR-! NC
1064 FE C6 5376 INC DN NEXT ROW
1066 5377 U7: SET-CURSOR
1066 B4 02 5378 MOV AH,2
1068 EB F4 5379 JMP U4 ESTABl I SH THE NEW CURSOR
5380
5381 ; ----- BACK SPACE fOUND
5382
106A 5383 U8:
106A OA 02 5384 OR ALREADY AT END OF LINE
106C 74 F8 5385 JZ SET CURSOR
106E FE CA 5386 DEC NO -- JUST MOVE IT BACK
1070 EB F4 5387 JMP SET_CURSOR
5388
5389 ; ----- CARRIAGE RETURN FOUND
5390
1072 5391 U9:
1072 2A 02 ~392 SUB MOVE TO FIRST COLUMN
1074 EB fa 5393 JMP SET_CURSOR
5394
5395 ; ----- LI NE fEED fOUND
5396
1076 5397 Ul0:
l076 3A 36 0484 R 5398 , CMP DH,ROWS BOTTOM OF SCREEN
l07A 75 E8 5399 JNE U6 YES, SCROLL THE SCREEN
107C EB BB 5400 JMP Ul NO, JUST SET THE CURSOR
5401
5402 ; ----- BELL FOUND
5403
l07E 5404 U11 :
107E 83 02 5405 MOV BL,2 SET UP COUNT FOR BEEP
1080 E8 0020 R 5406 CALL BEEP SOUND THE POD BELL
1083 EB DB 5407 JMP U5 TTY_RETURN
5408
5409
5410 ;----- CURRENT VIDEO STATE
5411
1085 5412 AHF:
5413 ASSUME OS:ABSO
1085 8A 26 044A R 5414 MOV AH,BYTE PTR CRT_COLS GET NUMBER Of COLUMNS
1089 8A 3E 0462 R 5415 MOV BH,ACT IVE_PAGE
1080 AD 0487 R 5416 MOV AL,INFO
1090 24 80 5417 AND AL,08DH
1092 OA 06 0449 R 5418 OR AL,CRCMODE

146 IBM Enhanced Graphics Adapter August 2, 1984

1096 5f 5419 POP 01
1091 5E 5420 POP 51
109.
1099
5.
5. '421
5422
POP
POP
ex
ex
DISCARD ex
,09A 5A 5423 POP OX
109B 1F 5424 POP os
10ge 07 5425 POP ES
1090 5. 5426 POP
IRET
BP
lO9E CF 5427
5428
5429 SUBTTL
5430
5431
lD9F 5432 PAL_SET PRoe NEAR
lO9F 50 5433 PUSH AX
lOAD £8 0005 R 5434 CALL WHAT_BASE
lOA3 FA 5435 CLI
10M 5436 VR:
lOAlf EC 5437 IN AL.DX
lOAS AS O. 5438 TEST AL.OSH ; VERT I CAL RETRACE
lOA7 14 FB 5439 JZ VR
10A9 5. 5440 POP AX
10M 82 CO 5441 MOV DL. ATTR_WR I TE
'OAG 86 e4 5442 XCHG AL.AH
lOAE EE 5443 OUT DX.AL
lOAF 86 e4 5444 XCHG AL.AH
10Bl EE 5445 OUT DX,Al
1082 BO 20 5446 MOV AL,020H
1084 EE 5447 OUT DX,AL
lOB5 FB 5448 511
10B6 C, 5449 RET
10B7 5450 PAL_SET ENOP
5451
10B7 5452 PAL_ON PRoe NEAR
lOB7 E8 lOCO R 5453 CALL PAL_INIT
1 DBA 82 CO 5454 MOV DL. A TTR_WR I TE
lOBC BO 20 5455 MOV AL,020H
lOBE EE 5456 OUT OX.AL
lDSF c, 5457 RET
lOCO 5458 PA,--ON ENOP
5459
lOCO 5460 PAL..INIT PRoe NEAR
lOCO E8 0005 R 5461 CALL WHAT_BASE
10C3 EC 5462 IN AL,OX
10C4 C, 5463 RET
10C5 5464 PAL_INIT ENOP
5465
5466 ; ----- SET PALETTE REG I STERS
5467
10C5 5468 AH10:
5469 ASSUME DS:ABSO
10C5 F6 06 0487 R 02 5470 TEST INFO,2
1 DCA 75 07 5471 JNZ 8M_OK I N MONOCHROME MODE
5472
5473 ; ----- HERE THE EGA I SIN A COLOR MODE
5474
lOCC 80 3E 0463 R B4 5475 CMP BYTE PTR AOOR_6845,OB4H
1001 74 33 5476 JE BM_OUT
1003 5477 BM.-OK:
1003 8A EO 5478 MOV AH,AL
1005 010 E4 5479 OR AH,AH
1007 75 30 5480 JNZ 9M_'
5481
5482 ; ----- SET I NO I V I DUAL REG I STER
5483
1009 2B ED 5484 SUB BP,BP
100B C4 3E 04A8 R 5485 LES 01 , SAVE_PTR
100F 83 C7 04 5486 ADD 01,4
lOE2 26: C4 3D 5487 LES OI,DWORD PTR ES:[OI]
10E5 8C co 548. MOV AX,ES
10E7 OB C7 5489 OR AX,DI
10E9 74 01 5490 JZ TLO_l
lOEB 45 5491 INC BP
10EC 5492 TLO_' :
5493
10EC E8 lOCO R 5494 CALL PAL_I NIT
lOfF 8A E3 5495 MOV AH,BL
10Fl 8A C7 5496 MOV AL,BH
lOF3 E8 109F R 5497 CALL PAL_SET
10F6 E8 10B7 R 5498 CALL PAL_ON
'OF9 08 ED 5499 OR BP,BP
10FB 74 09 5500 JZ BM_OUT
lOFO 8A C7 5501 MOV AL,8H
lOFF 2A Ff 5502 SUB BH,BH
lEOl 03 FB 5503 ADD OI,BX
lE03 26: 88 05 5504 MOV ES:IDIJ,AL
lE06 5505 8M_OUT:
1E06 E9 219E R 5506 JMP V_RET
5507
1E09 5508 BM_':
1E09 FE CC 5509 DEC AH
lEOB 75 20 5510 JNZ BM_2
5511
lEOD 2B ED 5512 SUB BP,BP
lEOF C4 3E 04A8 R 5513 LES OI,SAVE_PTR
lE13 83 C7 04 5514 ADO 01,4
lE16 26: C4 3D 5515 LES OI,OWORD PTR ES:[OI)
lE19 8e co 5516 MOV AX,ES
lE18 OB C7 5517 OR AX,OI
lEl0 74 01 5518 JZ TLO_2
lE1F 45 5519 INC BP
lE20 5520 TLO_2:
5521
5522 ; ----- SET OVERSCAN REG I STER
5523
lE20 E8 lOCO R 5524 CALL PAL_I NIT
1E23 B4 11 5525 MOV AH,011H
1E25 8A C7 5526 MOV AL,BH
lE27 E8 109F R 5527 CALL PAL_SET
lE2A E8 10B7 R 5528 CALL PAL_ON
5529
lE20 DB ED 5530 OR BP,BP
lE2F 74 05 5531 JZ BM_OUT
lE31 83 C7 " 5532 ADD Ol,Ol1H
1E34 26: 88 3D 5533 MOV ES:lol1.BH
5534
lE37 E9 219E R 5535 JMP V_RET
5536
lE3A 5537 8M_2:
lE3A FE CC 5538 DEC AH
lE3C 75 40 5539 JNZ BM_3
5540
5541 ;----- SET 16 PALETTE REGISTERS AND OVERSCAN REGISTER
5542
lE3E 1E 5543 PUSH OS
lE3F 06 5544 PUSH ES

August 2, 1984 mM Enhanced Graphics Adapter 147

 5545
lE40 C4 3E 04A8 R 5546 LES 01, SAVE_PTR
1 E44 83 C7 04 5547 ADD 01,4
1 E47 26: C4 30 5548 LES OI,DWORD PTR ES:[Dlj ES:DI PTR TO PAL SAVE AREA
lE4A 8C CO 5549 MOV AX,ES
lE4C OB C7 5550 OR AX,DI
lE4E 74 09 5551 JZ TLO_3
5552
lE50 lf 5553 POP OS PARAMETER ES
lE51 1£ 5554 PUSH OS
1E52 88 F2 5555 MOV SI,OX PARAMETER OffSET
1E54 B9 0011 5556 MOV CX,17D
1 E57 F3/ A4 5557 REP MOVSB
5558
1 E59 5559 TLO_3:
1 E59 07 5560 POP ES
lE5A 1F 5561 POP OS
5562
1 E5B 8B DA 5563 MOV BX,DX
1 E50 E8 lOCO R 5564 CALL PAL_INIT
1 E60 2A E4 5565 SU8 AH,AH
1 E62 5566 BM_2A:
1 E62 26: 8A 07 5567 MOV AL, ES: [SX]
lE65 EB lD9F R 5568 CALL PAL_SET
lE68 FE C4 5569 INC AH
lE6A 43 5570 INC 8X
1E6B 80 FC 10 5571 CMP AH,010H
1 E6E 72 F2 5572 J8 BM_2A
lE70 FE C4 5573 INC AH
lE72 26: 8A 07 5574 MOV AL, ES: [BX]
1 E75 E8 lD9F R 5575 CALL PAL_SET
1 E78 E8 lDB7 R 5576 CALL PAL_ON
1 E7B E9 219E R 5577 JMP V_RET
5578
1 E7E 5579 BM_3:
lE7E FE CC 5580 DEC AH
lE80 75 29 5581 JNZ BM_4
5582
5583 ; ----- TOGGLE INTENSifY/BLINKING BIT
5584
1E82 53 5585 PUSH 8X
lE83 E8 OD5A R 5586 CALL MAKE_BASE
lE86 83 C3 33 5587 ADD aX,010H + LN_4
1 E89 26: 8A 07 5588 MOV AL. ES: I BX}
lE8C 58 5589 POP 8X
5590
1 E80 OA DB 5591 OR BL,BL
lE8F 75 OA 5592 JNZ BM_6
5593
5594
5595
; ----- ENABLE INTENSIFY

1 E91 80 26 0465 R DF 5596 AND CRT_MODE_SET, 110111 1 1 B

, E96 24 F7 5597 AND Al,OF7H
1 E98 EB DC 90 5598 JMP BM_7
, E9B 5599 BM_6:
1 E9B FE CB 5600 DEC 8L
lE90 75 07 5601 JNZ BM_7
5602
5603 ENABLE BLI NK
5604
1 E9f 80 DE 0465 R 20 5605 OR CRT_MODE_SET,020H
lEA4 OC 08 5606 OR Al,08H
lEA6 5607 BM_7:
lEA6 B4 10 5608 MOV AH, P_MOOE
lEA8 EB 109f R 5609 CALL PAL_SET
lEAS 5610 BM_4:
lEAB E9 219E R 5611 JMP V_RET
5612
5613 C I NCLUOE VCHGEN. INC
5614 C SUBTTL VCHGEN.INC
5615 C PAGE
5616
5617
C
C
------------------------------------------------
ENTRY
5618 C AL'" 0 USER SPEC I F I EO fONT
5619 C 1 8 X 14 FONT
5620 C 2 8 X 8 DOUBLE DOT
5621 C BL = BLOCK TO LOAD

lEAE
5622
5623
C
C
------------------------------------------------
CH_GEN:
lEAE 50 5624 C PUSH AX ; SAVE THE I NVOLVEO REGS
lEAF 55 5625 C PUSH 8P
1 ESO 53 5626 C PUSH 8X
1 EBl 51 5627 C PUSH CX
lE82 52 5628 C PUSH OX
lEB3 DO 5629 C PUSH ES
5630 C
5631 C ASSUME OS:ABSO
1 E84 E8 OCFE R 5632 C CALL ODS SET DATA SEGMENT
1 EB7 AO 0449 R 5633 C MOV AL,CRT_MODE GET THE CURRENT MODE
lEBA 50 5634 C PUSH AX SAVE IT
lEBB 3C 07 5635 C CMP AL,7 I S TH I S MONOCHROME
1 EBD 74 07 5636 C JE H14 MONOCHROME VALUES
1 E8F C6 06 0449 R OS 5637 C MOV CRT_MODE,OBH COLOR VALUES
lEC4 EB 05 5638 C JMP SHORT H15 SKI P
1 EC6 5639 C H14:
1 EC6 C6 06 0449 R OC 5640 C MOV CRT_MODE,OCH ; MONOCHROME VALUES
1 ECB 5641 C H15:
1 ECB E8 ODAB R 5642 C CALL SET_REGS
1 ECE E8 OCFE R 5643 C CALL ODS RESET THE DATA SEGMENT
lEDl 58 5644 C POP AX RECOVER OLD MODE VALUE
lED2 A2 0449 R 5645 C MOV CRT_MOOE, AL RETURN TO lOW MEMORY
5646 C
1 ED5 07 5647 C POP ES RESTORE REGS THAT WERE
lED6 5A 5648 C POP OX USED BY THE MODE SET
lE07 59 5649 C POP CX ROUTINES
lE08 5. 5650 C POP 8X
lED9 50 5651 C POP 8P
lEDA 58 5652 C POP AX
5653 C
lEDB OA CO 5654 C OR AL,AL SET FLAGS
1 EDO 74 17 5655 C JZ 00_MAP2 USER SPEC I f I ED FONT
lEDF DE 5656 C PUSH CS SET SEGMENT TO
1 EEO 07 5657 C POP ES THI S MODULE
1 EEl 2B 02 5658 C SU8 OX,OX ZERO OUT START OFFSET
, EEJ B9 0100 5659 C MOV CX,02560 CHAR COUNT (FUll SET)
lEE6 FE C8 5660 C DEC AL WHICH PARAMETER
1 EE8 75 07 5661 C JNZ H7 MUST BE ONE
lEEA B7 OE 5662 C MOV BH,014D BYTES PER CHARACTER
lEEC BO 0000 E 5663 C MOV BP, OFFSET CGMN 8 X 14 TABLE OFFSET
lEEF E8 05 5664 C JMP SHORT DO_MAP2 STORE IT
lEF1 5665 C H7:
lEfl B7 08 5666 C MOV BH,8 8 X 8 FONT
lEF3 BD 0000 E 5667 C MOV BP, offSET CGDDOT ROM 8 X 8 DOUBLE DOT
5668
5669
5670
C
C
C
; ------------------------------------------
ALPHA CHARACTER GENERATOR LOAD
------

148 IBM Enhanced Graphics Adapter August 2, 1984

 5671 C
5672 C ENTRY
5673 C ES:BP - POINTER TO TABLE
5674 C cx - COUNT OF CHARS
5675 C OX - CHAR COUNT OFFSET I NTO MAP 2
5676 C BH - BYTES PER CHARACTER
5677 C BL - MAP 2 BLOCK TO LOAD
5678 C 60=MAP2~-------·---------------------------------
1 EF6 5679 C
1 EF6 06 5680 C PUSH ES FONT TABLE SEGMENT
1 Ef7 1F 5661 C POP OS ; ADDRESSING TO TABLE
lEF8 52 5682 C PUSH OX SAVE REG I STER
5683 C SRLOAD ES, DAOOOH ; ADDRESS I NG TO MAP 2
1Ef9 BA AOOO 5684 C+ MOV OX,DAOOOH
lEFC 8E C2 5685 C+ MDV ES,DX
1EfE 5A 5686 C POP OX RECOVER REG I STER
lEFF 51 5687 C PUSH CX MULTIPLY BY 020H SINCE
HOO 61 05 5688 C MOV CL,5 MAX I MUM BYTES PER
H02 03 E2 5689 C SHL DX,CL CHARACTER IS 320:=020H
H04 59 5690 C PDP CX RECOVER
H05 OA DB 5691 C OR BL,8L WH I CH 16K 8LOCK TO LOAD
lF07 74 08 5692 C JZ H3 BLOCK lERO
H09 5693 C H4:
H09 81 C2 4000 5694 C ADD DX,04000H INCREMENT TO NEXT BLOCK
HOD FE CB 5695 C DEC BL ANY MORE
HOf
H11
75 F8 5696
5697
C
C H3:
JNZ
H' DO ANOTHER

BYTES PER CHARACTER

1 fll 8A C7 5698 C MOV AL, BH
lF13 2A E4 5699 C SUB AH,AH lERO
H15 8B fA 5700 C MOV OI,OX OFFSET INTO MAP
lF17 88 f5 5701 C MOV SI,SP OFFSET INTO TABLE
H19 E3 00 5702 C JCXZ LD_OVER CHARACTER COUNT
lF1B 5703 C LO:
lF1B 51 5704 C PUSH CX SAVE CHARACTER COUNT
lF1C 88 C8 5705 C MOV CX,AX ONE ENT I RE CHARACTER
lFlE F3/ A4 5706 C REP MOVSB AT A TIME
1F20 2B f8 5707 C SUB DI,AX ADJUST DFFS£T
lF22 83 C7 20 5708 C ADD 0l,020H NEXT CHARACTER POS I T I ON
lF25 59 5709 C POP CX RECOVER CHARACTER COUNT
1F26 E2 F3 5710 C LOOP LO DO THE REST
1F28 5711 C LD_OVER:
H28 C3 5712 C RET
5713 C
H29 5714 C BRK_1:
5715 C ASSUME DS:ABSO
H29 E8 OCFE R 5716 C CALL DDS SET LOW MEMORY SEGMENT
H2C A3 0485 R 5717 C MOV POINTS,AX GET BYTES/CHARACTER
H2F 88 16 0463 R 5718 C MOV OX, AOOR_6845 CRTC REG I STER
H33 80 3E 0449 R 07 5719 C CMP CRT_MODE,7
1f38 75 05 5720 C JNE HllA
H3A 84 14 5721 C MOV AH, C_UNOERLN_LOC R14H
lF3C E8 0015 R 5722 C CALL OUT_OX SET THE UNDERLINE LOC
1 f3F 5723 C HllA:
1f3F FE C8 5724 C DEC AL POINTS - 1
1 F41 B4 09 5725 C MOV AH, C_MA>CSCAN_LN R09H
1f43 E8 0015 R 5726 C CALL OUT_OX SET THE CHARACTER HE I GHT
H46 FE C8 5727 C DEC AL POINTS - 2
5728 C
H48 8A E8 5729 C MOV CH,AL CURSOR START
H4A 8A C8 5730 C MOV CL,AL CURSOR END
H4C FE C1 5731 C INC CL ADJUST END
H4E B4 01 5732 C MOV AH,l SET C TYPE B t OS CALL
H50 CD 10 5733 C INT 10H SET THE CURSOR
5734 C
H52 8A lE 0449 R 5735 C MOV BL,CRT_MODE GET THE CURRENT MODE
H56 B8 015E 5736 C MOV AX, 3500 MAX SCANS ON SCREEN
1f59 80 fB 03 5737 C CMP BL,3 640X200 ALPHA MODES
H5C 77 08 5738 C JA H11 MUST BE 350
H5E E8 OE9A R 5739 C CALL BRST_DET
1f61 72 03 5740 C JC H11
H63 B8 00C8 5741 C MOV AX, 2000 SET FOR 200
H66 5742 C Hll :
1F66 99 5743 C CWO PREPARE TO DIVIDE
1F67 F7 36 0485 R 5744 C DIV POINTS MAX ROWS ON SCREEN
lF6B '8 5745 C DEC AX ADJUST
1F6C A2 0484 R 5746 C MOV ROWS,AL SAVE ROWS
1F6F FE CO 5747 C INC AL READJUST
1F71 2A E4 5748 C SU8 AH,AH CLEAR
1F73 F7 26 0485 R 5749 C MUL POINTS ROWS*BYTES/CHAR
1F77 .8 5750 C DEC AX ADJUST
1F78 8B 16 0463 R 5151 C MOV DX,ADDR_6845 CRTC ADDRESS
1F7C B4 12 5752 C MOV AH, C_VRT_DSP _END SCANS 0 I SPLAYED
1F7E E8 0015 R 5753 C CALL OUT_OX SET IT
lF8l AD 0484 R 5754 C MOV AL,ROWS GET CHARACTER ROWS
1F84 FE CO 5755 C INC AL ADJUST
1F86 F6 26 044A R 5756 C MUL BYTE PTR CRT_COLS ROWS*COLUMNS
lF8A 01 EO 5757 C SHL AX,l *2 FOR ALPHA MODE
HBC 05 0100 5758 C ADD AX,2560 SPACE BETWEEN PAGES
H8F A3 044C R 5759 C MOV CRT_LEN,AX BYTES PER PAGE
1F92 E8 OE96 R 5760 C CALL PH_S VIDEO ON
1f95 E9 219E R 5761 C JMP V_RET RETURN TO CALLER
5762 C
5763 C ; ---~. LOADABLE CHARACTER GENERATOR ROUT I NES
5764 C
H98 5765 C AH11:
1f98 3C 10 5766 C CM' AL,010H CHECK PARAMETER
H9A 73 37 5767 C JAE AHll_ALPHA1" NEXT STAGE
5768 C
5769 c ;----- ALPHA MODE ACTIVITY HERE
5770 C
1f9C 3C 03 5771 C CM' AL,03H RANGE CHECK
1F9E 73 17 5772 C JAE H1 NEXT STAGE
HAD E8 lEAE R 5773 C CALL CH_GEN SET THE CHAR GEN
HA3 E8 ODAB R 5774 C CALL SET_REGS
HA6 E8 0[96 R 5775 C CALL PH_5 VIDEO ON
5776 C ASSUME DS:ABSO
HA9 E8 OCFE R 5777 C CALL DDS SET THE DATA SEGMENT
HAC 8B DE 0460 R 5778 C MOV CX, CURSOR_MODE GET THE MODE
HBO B4 01 5779 C MOV AH,l SET C TYPE
lFB2 CD 10 5780 C INT 10H EMULATE CORRECT CURSOR
lFB4 E9 219E R 5781 C JMP V_RET RETURN TO CALLER
5782 C
5783 C ; ----- SET THE CHARACTER GENERATOR BLOCK SELECT REG I STER
5784 C
HS7 5785 C H1:
HS7 75 17 5786 C JNE H2 NOT IN RANGE
lFB9 B6 03 57B7 C MOV DH,3
1 FBB B2 C4 5788 C MOV DL, SEQ_AODR SEQUENCER
5789 C
HBD B8 0001 5790 C MOV AX,1 AH:=S_RESET, AL"'l
HeQ E8 0015 R 5791 C CALL OUT_OX
5792 C
HC3 84 03 5793 C HOV AH,S_CGEN CHAR BLOCK REGI STER
HC5 8A C3 5794 C HOV AL,BL GET THE VALUE
He7 E8 0015 R 5795 C CALL OUT_OX SET IT
5796 C

August 2, 1984 IBM Enhanced Graphics Adapter 149

lFCA 68 0003 5797 e MOY AX,3 ; AH=S_RESET, AL=3
HCO E8 0015 R 5798 e CALL OUT_OX
HOD 5799 e H2:
HOD E9 219E R 5800 e JMP V_RET ; RETURN TO CALLER
5801 e
H03 5802 e AH11_ALPHA 1 :
5803 e ASSUME OS:ABSO
H03 3C 20 5804 e eMP AL,020H
H05 73 26 5805 e JAE AH1'_GRAPHICS
5806 e
5807 e ;----- ALPHA MODE ACTIVITY HERE
5808 e
1 F07 2C 10 5809 e SUB AL,010H ; ADJUST TO 0 - N
1 F09 3C 02 5810 e eMP AL,02H RANGE CHECK
1 FOB 77 F3 5811 e JA H2 1NVALI 0 CALL
1 FOO 50 5812 e PUSH AX SAVE
HOE 53 5813 e PUSH BX
lFOF E8 lEAE R 5814 e CALL CH_GEN LOAD THE CHAR GEN
HE2 E8 OOAB R 5815 e CALL SET_REGS
HE5 5B 5816 e POP BX
lFE6 5B 5817 e POP AX ; RESTORE
lFE7 8A EO 5818 e MOY AH,Al ; CALL I NG PARAMETER
HE9 OA E4 5819 e OR AH,AH ; USER MODE
HEB 8A C7 5820 e MOY AL, BH
HED 74 09 5821 e JZ H13 ; DO NOT SET BYTES/CHAR
lFEF BO 08 5822 e MOY AL,8 ; 8 X 8 FONT
1Hl 80 FC 01 5823 e eMP AH,1 I S THE CALL FOR MONoe
lFF4 75 02 5824 e JNE H13 ; NO, LEAVE IT AT 8
lFF6 80 DE 5825 e MOY AL,140 ; MONOC SET
IH8 5826 e H13:
lFF8 2A E4 5827 e SUB AH,AH ; CLEAR UPPER BYTE
lFFA E9 lF29 R 5828 e JMP BRK_1 ; CONTINUE
5829 e
5830 e ;----- GRAPHICS MODE ACTIVITY HERE
5831 e
lFFO 5832 e AH11_GRAPHICS:
5833 e ASSUME OS:ABSO
HFO 3C 30 5834 e eMP AL,030H
lFFF 73 6A 5835 e JAE AH11 _INFORM
2001 2C 20 5836 e SUB AL,020H
2003 75 11 5837 e JNZ f10
5838 e
5839 e ;----- COMPATIBILITY, UPPER HALF GRAPHICS CHARACTER SET
5840 C
5841 e ASSUME OS:ABSO
5842 e SRLOAO OS,O
2005 2B 02 5843 e+ SUB OX,OX
2007 8E OA 5844 e+ MOY OS,OX
2009 FA 5845 e ell
200A 89 2E 007C R 5846 e MOY WORD PTR EXT_PTR , BP
200E 8e 06 007E R 5847 e MOY WORD PTR EXT_PTR + 2 , ES
2012 FB 5848 e S71
2013 5849 e F11 :
2013 E9 219E R 5850 e JMP V_RET
2016 5851 e FlO:
5852 e ASSUME OS:ABSO
2016 52 5853 e PUSH OX
5854 e SRLOAO OS,O
2017 2B 02 5855 e+ SUB OX,OX
2019 8E OA 5856 e+ MOY OS,OX
201B 5A 5857 e POP OX
201C 3C 03 5858 e eMP AL,03H ; RANGE CHECK
201E 77 F3 5859 e JA f11
2020 FE C8 5860 e OEe Al
2022 74 14 5861 e JZ f19
2024 OE 5862 e PUSH es
2025 07 5863 e POP ES
2026 FE C8 5864 e OEe Al
2028 75 08 5865 e JNZ f13
202A B9 OOOE 5866 e MOY CX,140
202U BU UUOO E 5867 e MOY BP,OFFSET CGMN ; ROM 8 X 14 CHARACTER SET
2030 EB 06 5868 e JMP SHORT F19
2032 5869 e F13:
2032 89 0008 5870 e MOY CX,8
2035 BO 0000 E 5871 e MOY BP, OFFSET CGDOOT ; ROM 8 X 8 DOUBLE DOT
2038 58n e F19:
2038 FA 5873 e ell
2039 89 2E 010C R 5874 e MOY WORD PTR GRX_SET , BP
2030 8C 06 alOE R 5875 e MOY WORD PTR GRX_SET + 2 , ES
2041 FB 5876 e S71
5877 e ASSUME OS:ABSO
2042 E8 OCfE R 5878 e CALL OOS
2045 89 DE 0485 R 5879 e MOY pOINTS,CX
2049 8A C3 5880 e MOY AL,BL
204B B8 2067 R 5881 e MOY ex, OffSET RT
204E OA CO 5882 e OR AL,AL
2050 75 05 5883 e JNZ OR 3
2052 8A C2 5884 e MaY AL-:-Ol
2054 EB 09 90 5885 e JMP OR_'
2057 5886 e OR_3:
2057 3C 03 5887 e eMP AL,3
2059 76 02 5888 e JBE OR 2
2058 BO 02 5889 e MOY AL-:-2
2050 5890 e OR_2:
2050 2E: 07 5891 e XLAT CS:RT
205F 5892 e OR_' :
205F FE C8 5893 e OEe Al
2061 A2 0484 R 5894 e MOY ROWS,AL
2064 E9 219E R 5895 e JMP V_RET
5896 e
2067 5897 e RT LABEL BYTE
2067 00 OE 19 2B 5898 e OB 000,140,250,430
5899 e
5900 e
5901
5902
e
e
;----- INFORMATION RETURN DONE HERE

206B 5903 e AH11 _INFORM:

5904 e ASSUME OS:ABSO
206B 3C 30 5905 e eMP AL,030H
2060 74 03 5906 e JE F6
206F 5907 e F5:
206F E9 219E R 5908 e JMP V,-RET
2072 5909 C F6:
2072 8B OE 0485 R 5910 e MOY CX, POINTS
2076 8A 16 0484 R 5911 e MOY OL,ROWS
207A 80 fF 07 5912 e eMP BH,7
2070 77 FO 5913 e JA F5
207F 80 FF 01 5914 e eMP BH,l
2082 77 18 5915 e J' F7
5916 e
5917 e ASSUME OS:ABSO
2084 52 5918 e PUSH OX
5919 e SRLOAD OS,O
2085 2B 02 5920 e+ SUB OX,DX
2087 8E OA 592' e+ MOY OS,DX
2089 5A 5922 e POP OX

150 IBM Enhanced Graphics Adapter August 2, 1984

208A OA FF 5923 OK BH,BH
208C 75 07 5924 JNL F'
208E C4 2E 007C R 5925 LES BP, EXT_PTR
2092 EB lA 90 5926 JMP INFORM_OUT
2095 5927 F9:
2095 C4 2E OlOC R 5928 LES BP,GRX_SET
2099 EB 13 90 5929 JMP INFORM_OUT
5930
5931 ; ----~ HANDLE BH = 2 THRU BH ;:: 5 HERE RETURN ROM TABLE PO INTERS
5932
209C 5933 F7:
5934 ASSUME DS:ABSO
209C 80 EF 02 5935 SUB BH,2
209F 8A OF 5936 MOV BL,BH
20Al 2A FF 5937 SUB BH,BH
20A3 01 £3 5938 SAL ex,1
20A!) 81 C3 20B7 R 5939 ADD BX,OFFSET TBL_5
20A9 2E: 88 2F 5940 MDV 8P,CS: I BX]
20AC OE 5941 PUSH CS
20AD 07 5942 POP ES
5943
20AE 5944 INfORM_OUT:
20AE 5F 5945 POP 01
20AF 5E 5946 POP SI
20BO 5B 5947 POP BX
20Bl 58 5948 POP AX 01 SCARO SAVED CX
20B2 58 5949 POP AX 01 SCARO SAVED OX
2063 1F 5950 POP OS
20B4 58 5951 POP AX 01 SCARO SAVED ES
2085 58 5952 pOP AX DISCARD SAVED BP
20B6 eF 5953 fRET
5954
5955 ;----- TABLE OF CHARACTER GENERATOR OFFSETS
5956
2087 5957 TBL_5 LABEL WORD
20B7 0000 E 5958 OW OFFSET CGMN
20B9 0000 E 5959 ow OFfSET CGDDOT
20BB 0000 E 5960 ow OffSET INT_lF_'
20BD 0000 E 5961 OW OffSET CGMN_FDG
5962
5963 SUSfTL
5964
5965 ;~---- AL1£RNATE SELECT
5966
20BF 5967 AH12:
5968 ASSUME DS:ABSO
20BF 80 FB 10 5969 eMP BL,010H ; RETURN ACT I VE CALL
20C2 72 51 5970 JB ACT_1
20C4 74 1B 5971 JE ACT_3
20c6 80 FB 20 5972 eMP BL,020H ; ALTERNATE PRINT SCREEN

e:~E~
20C9 74 03 5973 JE
20CB E9 219E R 5974 JMP INVALID CALL
20CE 5975 ACe2: ; NEW PR I NT SCREEN
5976 SRLOAD DS,O
20CE 2B 02 5977 SU8 DX,DX
2000 8E DA 5978 MOV DS,OX
2002 FA 5979 eLi
2003 C7 06 0014 R 21"7 R 5980 MOV WORD PTR INT5_PTR, OffSET PRINT_SCREEN
2009 8C DE 0016 R 598' MOV WORD PTR I NT5_PTR+2, CS
2000 F8 5982 STI
20DE E9 219E R 5983 JMP V_RET
20E' 5984 ACI"_3:
20£1 8A 3E 0487 R 5985 MOV BH,INFO LOOKING FOR MONOC BIT
20E5 80 E7 02 5986 AND BH,2 ; ISOLATE
20E8 DO EF 5987 SH' BH,l ; ADJUST
5988
20EA AO 0487 R 5989 MOV AL,INFO LOOK I NG FOR MEMORY
20EO 24 60 5990 AND AL.01100000B ; MEMORY BITS
20EF B1 05 5991 MOV CL,5 ; SH I fT COUNT
20Ft 02 E8 5992 SH. AL,CL ; ADJUST MEM VALUE
20F3 8A 08 5993 MOV BL,AL ; RETURN REGISTER
5994
20F5 8A DE 0488 R 5995 MOV CL.INFO_3 FEATURE/SWI TCH
20F9 8A E9 5996 MDV CH,CL DUPLICATE IN CH
20FB 80 E1 OF 5997 AND CL.OFH MASK Off SWITCH VALUE
20FE DO ED 5998 SH' CH,l MOVE fEATURE VALUE
2100 DO ED 5999 SH' CH.l
2102 DO ED 6000 SHR CH,l
2104 DO ED 6001 SHR CH.l
2106 80 E5 OF 6002 AND CH.OfH MASK IT
6003
2109 5F 6004 PDP 01
210A 5E 6005 POP SI
210B 5A 6006 POP DX DISCARD BX
210C 5A 6007 POP ox DISCARD ex
2100 5A 6008 POP ox
210E 1F 6009 POP OS
210F D7 6010 POP ES
2110 50 6011 POP BP
2111 eF 6012 IRET
2112 6013 AH12_X:
2112 E9 219E R 6014 JMP V_RET RETURN TO CALLER
2115 6015 ACT_' :
2115 6016 STR_OUTZ:
2115 E9 219E R 6017 JMP V_RET RETURN TO CALLER
6018
6019 ;---~- WRITE STRING
6020
2118 6021 AH13:
2118 3C 04 6022 eMP AL.04 RANGE CHECK
211A 73 F9 6023 JAE STR_OUTZ I NVALI 0 PARAMETER
211C E3 F7 6024 JCXZ STR_OUTZ
211E 53 6025 PUSH BX SAVE REGISTER
21lF 8A OF 6026 MOV BL.BH GET PAGE TO LOW BYTE
2121 2A FF 6027 SUB BH,BH
2123 01 E3 6028 SAL BX,1 *2 FOR WORD OffSET
2125 8B 87 0450 R 6029 MOV Sl,lBX + OffSET CURSOR_POSN] GET CURSOR POSITION
2129 58 6030 POP BX RESTORE
212A 5. 6031 PUSH SI CURRENT VALUE ON STACK
6032
2128 50 6033 PUSH AX
212C BB 0200 6034 MOV AX,0200H SET THE CURSOR POSITION
212F CD 10 6035 INT 10H
2131 58 6036 POP AX
2132 6031 STR_l :
2132 51 6038 PUSH ex
2133 53 6039 PUSH BX
2134 50 6040 PUSH AX
2135 86 EO 6041 XCHG AH,AL
2137 26: 8A 46 00 6042 MOV AL,ES:[BP] GET THE CHAR TO WR ITE
213B 45 6043 INC 8P
213C 3C OD 60lf.4 eMP AL,ODH CARR I AGE RETURN
213E 74 3D 6045 JE STR_CR_lf
2140 3C OA 6046 CMP AL,OAH LINE FEED
2142 74 39 6047 JE STR_CR_lf
2144 3C 08 6048 CHP AL,D8H BACKSPACE

August 2, 1984 mM Enhanced Graphics Adapter 151

2146 74 35
2148 3C 07
6049
6050
JE
eMP !r~o~:-LF ; BELL
214A 74 31 6051 JE STR_CR_LF
214C B9 0001 6052 NOV CX,1 COUNT OF CHARACTERS
214F 80 FC 02 6053 eMP AH,2 CHECK WHERE ATTR IS
2152 72 05 6054 JB OO_STR NOT IN THE STRING
2154 26: 8A 5E 00 6055 MOV BL, ES: I BPI GET THE ATTRIBUTE
2158 45 6056 INC BP NEXT ITEM IN STRING
2159 6057
2159 84 09 6058 MOV AH,09H ; WRITE THE CHAR/ATTR
215B CD 10 6059 INT 10H
2150 FE C2 6060 INC DL NEXT CURSOR POSITION
215F 3A 16 044A R 6061 eMP OL, BYTE PTR CRT_COLS COLUMN OVERFLOW
2163 72 11 6062 JB STR_2 NOT YET
2165 3A 36 0484 R 6063 eMP OH, ROWS
2169 75 07 6064 JNE STR_3
216B B8 OEOA 6065 MOV AX,OEOAH
216E CD 10 6066 INT lDH
2170 FE CE 6067 DEC DH
2172 6068
2172 FE C6 6069 INC DH NEXT ROW
2174 2A 02 6070 SUB OL,DL COLUMN ZERO
2176 6071
2176 B8 0200 6072 MOV AX,0200H ; SET THE CURSOR
2179 CD 10 6073 INT 10H
217B EB OE 6074 JMP SHORT STR_4
2170 6075 STR_CR_L~bv
2170 84 OE 6076 AH,OEH
217F CO 10 6077 INT 10H
2181 SA OF 6078 MOV BL,BH ; GET PAGE TO LOW BYTE
2183 2A FF 6079 SUB BH,BH
2185 01 E3 6080 SAL BX,1 *2 FOR WORD OFFSET
2187 88 97 0450 R 6081 MOV OX,I BX + OFFSET CURSOR_POSN I GET CURSOR pas I T I ON
2188 6082
2188 58 6083 POP AX
218C 58 6084 POP ax
2180 59 6085 POP CX
218E E2 A2 6086 LOOP STR_'
6067
2190 5A 6068 POP ox RECOVER CURSOR POSITION
6089 FROM PUSH S I ABOVE
2191 3C 01 6090 eMP AL,1
2193 74 09 6091 JE STR_OUT
2195 3C 03 6092 eMP AL,3
JE
~~Og~~H
2197 74 05 6093
2199 B8 0200 6094 MOV ; SET CURSOR POSITION
219C CD 10 6095 INT lOH
219E 6096 STR_OUT:
6097 ; ALLOW FALL THROUGH
6098
6099
219E 6100 V_RET PROC NEAR ; VIDEO BIOS RETURN
219E 5F 6101 POP 01
219F 5E 6102 POP SI
21AO 58 6103 POP BX
21A1 59 6104 POP CX
21A2 5A 6105 POP OX
21A3 lF 6106 POP OS
21A4 07 6107 POP ES
21A5 50 6108 POP BP
21M CF 6109 I RET
21A7 6110 V_RET ENDP
6111
21M 6112 COMBO_VIDEO ENOP
6113
6114 INCLUDE VPRSC.INC
6115 SUBTTL VPRSC.INC
6116 PAGE
6117
6118
; ------------------------------------------------------------------------
INTERRUPT 5
6119 THIS LOGIC WILL BE INVOKED BY INTERRUPT 05H TO PRINT THE
6120 SCREEN. THE CURSOR POSITION AT THE TIME THIS ROUTINE IS INVOKED
6121 WILL BE SAVED AND RESTORED UPON COMPLETION. THE ROUTINE IS
6122 INTENDED TO RUN WITH INTERRUPTS ENABLED. IF A SUBSEQUENT
6123 'PRINT SCREEN' KEY IS DEPRESSED DURING THE TIME THIS ROUTINE
6124 IS PRINTING IT WILL BE IGNORED.
6125 ADDRESS 50:0 CONTAINS THE STATUS OF THE PRINT SCREEN:
6126
6127 50:0 =0 EITHER PRINT SCREEN HAS NOT BEEN CALLED
6128 OR UPON RETURN FROM A CALL THIS INDICATES
6129 A SUCCESSFUL OPERATION.
6130 =1 PR I NT SCREEN I SIN PROGRESS
6131 =255 ERROR ENCOUNTERED OUR I NG PR I NT I NG
6132 ; ----------------------------------~-~---~-------------------------------
6133 ASSUME CS: CODE, OS: ABSO
21A7 6134 PRINT_SCREEN PROC FAR
21A7 F8 6135 STI MUST RUN WITH I NTS ENABLED
21A8 1E 6136 PUSH 05 MUST USE 50:0 fOR DATA
21A9 50 6137 PUSH AX AREA STORAGE
21M 53 6138 PUSH BX
21A8 51 6139 PUSH ex USE THIS LATER FOR CURSOR LlMITS
21AC 52 6140 PUSH ox WILL HOLD CURRENT CURSOR POS
21AD E8 OCFE R 6141 CALL ODS
21BO 80 3E 0500 R 01 6142 eMP STATUS_BYTE, 1 ; SEE IF PR I NT ALREADY I N PROGRESS
2185 74 63 6143 JZ EXIT ; JUMP IF PR I NT I N PROGRESS
2187 C6 06 0500 R 01 6144 MOV STATUS_BYTE,1 ; I NO I CATE PR I NT NOW I N PROGRESS
21BC 84 OF 6145 MOV AH,15 ; WI LL REQUEST THE CURRENT MODE
218E CD 10 6146 INT 10H ; IAL}=MODE (NOT USED)
6147 ; [AH]=NUMBER COLUMNS/LINE
6148 ; _____________________________________ ~ __
; a_~ _ _ _ _ _IBHI=VISUAL
_ ~_a_a _ _ _ _ _ _
PAGE
___ _

6149
6150 AT THIS POINT WE KNOW THE COLUMNS/LlNE ARE IN
6151
6152
6153
; 0
~:~ I D~~~~~~, ~~~~X I ~U~~~~~ Cf!t~ ~S I I b~~ JMOri~E STACK
; ----------------~-----------------------------------------------
21CO 8A CC 6154 MOV CL,AH ; WI LL MAKE USE OF ICX] REG TO
21C2 8A 2E 0484 R 6155 HOV CH,ROWS CONTROL ROW &: COLUMNS
21C6 FE C5 6156 INC CH ADJUST
21C8 E8 2220 R 6157 CALL CRLf CAR RETURN Ll NE fEED ROUTI NE
21C8 51 6158 PUSH CX SAVE SCREEN BOUNDS
21CC B4 03 6159 MOV AH,3 WILL NOW READ THE CURSOR.
21CE CD 10 6160 INT 10H AND PRESERVE THE POSITION
2100 59 6161 POP CX RECALL SCREEN BOUNDS
2101 52 6162 PUSH OX RECALL IBH]=VISUAL PAGE
2102 33 02 6163 XOR DX,oX SET CURSOR POS IT I ON TO 10,0 I
6164
6165
6166
6167
6168
2104 6169
2104 B4 02 6170 MOV AH,2 TO INDICATE CURSOR SET REQUEST
2106 CO 10 6171 INT 10H NEW CURSOR POS ESTABL I SHED
2108 8408 6172 MOV AH,8 TO I NO I CATE READ CHARACTER
21DA CD 10 6173 INT 10H CHARACTER NOW IN IALI
210C OA CO 6174 OR AL,AL SEE I F VAll 0 CHAR

152 IBM Enhanced Graphics Adapter August 2, 1984

210E 75 02 6175 JNZ PRI15 JUMP IF VALID CHAR
21EO 80 20 6176 MOV Al, ' ; MAKE A BLANK
21E2 6177 PR115:
21E2 52 6178 PUSH OX SAVE CURSOR POSITION
21E3 33 02 6179 XOR OX,OX INDICATE PRINTER 1
21E5 32 E4 6180 XOR AH,AH TO INDICATE PRINT CHAR IN (All
21£7 CO 17 6181 I NT 17H PR I NT THE CHARACTER
21E9 5A 6182 POP ox RECAll CURSOR POS I T I ON
21EA F6 C4 29 6183 TEST AH,029H TEST FOR PR I NTER ERROR
21EO 75 21 6184 JNZ ERR10 JUMP I f ERROR DETECTED
21£F FE C2 6185 INC OL ADVANCE TO NEXT COLUMN
21 F1 3A CA 6186 CMP Cl,Ol SEE I F AT END OF LINE
21F3 75 OF 6187 JNZ PRll0 I F NOT PROCEED
21 F5 32 02 6188 XOR OL,OL BACK TO COLUMN 0
21F7 8A E2 6189 MOV AH,OL (AHl=O
21 F9 52 6190 PUSH OX SAVE NEW CURSOR POS I T I ON
21 FA E8 2220 R 6191 CALL CRLF LI NE FEED CARR I AGE RETURN
21 FO 5A 6192 POP OX RECALL CURSOR POS I T I ON
21FE FE C6 6193 INC OH ADVANCE TO NEXT LINE
2200 3A EE 6194 CMP CH,DH FINISHED?
2202 75 DO 6195 JNZ PRI10 I F NOT CONT I NUE
6196
2204 5A 6197 POP OX RECALL CURSOR POS I T I ON
2205 134 02 6198 MOV AH,2 TO INDICATE CURSOR SET REQUEST
2207 CO 10 6199 INT 10H CURSOR POS I T I ON RESTORED
2209 C6 06 0500 R 00 6200 MOV STATUS_BYTE,O INDICATE FINISHED
220E EB OA 6201 JMP SHORT EX I T EXIT THE ROUTINE
2210 6202 ERRlO:
2210 5A 6203 POP OX Gf.T CURSOR POS I T I ON
2211 13402 6204 MOV AH,2 TO REqUEST CURSOR SET
2213 CD 10 6205 INT lOH CURSOR POS I T I ON RESTORED
2215 C6 06 0500 R FF 6206 MOV STATUS_BYTE,OFFH INOICATE ERROR
221A 6207 EXIT:
221A 5A 6208 POP OX RESTORE ALL THE REG I STERS USED
22113 59 6209 POP CX
221C 513 6210 POP BX
2210 58 6211 POP AX
221E 1F 6212 POP OS
221F CF 6213 I RET
2220 6214 PR I NT_SCREEN ENDP
6215
6216 ; ------ CARR I AGE RETURN, LI NE FEED SUBROUT I NE
6217
2220
2220
2222
33 02
32 E4
6216
6219
6220
CRlF PROC
XOR
XOR
NEAR
OX, OX
AH,AH
PRINTER °
WILL NOW SENO INITIAL CR, LF
6221 TO PR INTER
2224 130 00 6222 MOV AL,OOH eR
2226 CD 17 6223 INT 17H SEND THE LI NE fEED
2228 32 E4 6224 XOR AH,AH NOW FOR THE CR
222A 80 OA 6225 MOV AL,OAH IF
222C CD 17 6226 INT 17H SEND THE CARRIAGE RETURN
222E C3 6227 RET
222F 6228 CRLF ENDP
6229
6230 SUBTTL
6231
222F 6232 COOE ENDS
6233 ENO

1 PAGE,120
2 SUBTTL MONOCHROME CHARACTER GENERATOR
0000 3 COOE SEGMENT PUBL t C
4 PUBLi C CGMN
0000 5 CGMN LABEL BYTE
6 BW 8*14 PATTTERN
0000 00 00 00 00 00 00 7 08 OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH TOP_HALF _00
00 00 8
0008 00 00 00 00 00 00 9 08 OOOH, OOOH, OOOH, OOOH, OOOH, OOOH BOTTOM_HALF 00
OOOE 00 00 7E 81 A5 81 10 08 OOOH,OOOH, 07EH, 081 H, OASH, 081 H, 081H,OBOH TH_01
81 BO
0016
OOlC
99
00
81
00
7E 00 00 00
7E FF DB FF
"
12
13
013
DB
099H,081H,07EH,000H,000H,OOOH ,
000H,000H,07EH,OHH,00BH,OFFH,OFFH,OC3H ;
BT 01
TH::::02
FF C3 14
0024 E7 FF 7E 00 00 00 15 DB OE7H,OFFH,07EH,000H,000H,000H , BT 02
002A 00 00 00 6C FE FE 16 DB 000H,000H,000H,06CH,OFEH,OFEH,OFEH,OFEH ; TH::::03
FE FE 17
0032 7C 38 10 00 00 00 18 DB 07CH, 038H, 01 OH, OOOH, OOOH, OOOH , BT 03
0038 00 00 00 10 38 7C 19 OB OOOH, OOOH, OOOH, 010H, 038H, 07CH, OFEH, 07CH ; TH::::04
FE 7C 20
0040 38 10 00 00 00 00 21 DB 038H,010H,000H,000H,000H,000H , BT 04
0046 00 00 18 3C 3C E7 22 DB OOOH,000H,018H,03CH,03CH,OE7H,0E7H,OE7H ; TH::::05
E7 E7 23
004E 18 18 3C 00 00 00 24 DB 018H,018H,03CIl,000H,000H,000H ; BT_05
0054 00 00 18 3C 7E FF 25 DB OOOH, OOOH, 01 8H, 03CH, 07EH, OF FH, OFFH, 07EH ; TH_06
FF 7E 26
005C 18 18 3C 00 00 00 27 DB 018H,018H,03CH,000H,OOOH,000H , BT_06
0062 00 00 00 00 00 18 28 DB OOOH, OOOH, OOOH, OOOH, OOOH, 018H, 03CH,03CH ; TH_07
3C 3C 29
006A 18 00 00 00 00 00 30 DB 018H,OOOH,000H,000H,000H,OOOH BT 07
0070 FF FF FF FF FF E7 31 DB OfFH, OFFH, OFFH, OFFH, OFFH, OE7H,OC3H,OC3H TH::::08
C3 C3 32
0078 E7 FF FF FF FF FF 33 DB OE7H,OFFH,OFFH,OFFH,OFFH,OFFH BT 08
007E 00 00 00 00 3C 66 34 DB OOOH, OOOH, OOOH, OOOH, 03GH, 066H, 042H, 042H TH::::09
42 42 35
0086 66 3C 00 00 00 00 36 DB 066H, 03CH, OOOH, OOOH, OOOH, OOOH BT 09
008C FF FF FF FF C3 99 37 DB OHH, OFFH, OFFH, OFFH, OC3H, 099H,OBOH,OBDH TH::::OA
130 BO 38
0094 99 C3 FF FF FF FF 39 DB 099H,OG3H,OFFH,OFFH,OFFH,OFFH , BT OA
009A 00 00 1E OE 1A 32 40 DB 000H,000H,01EH,00EH,01AH,032H,078H,OCCH ; TH::::OB
78 CC 41
00A2 CC CC 78 00 00 00 42 DB OCCH, OCCH, 076H, OOOH, OOOH, OOOH BT 013
00A8 00 00 3C 66 66 66 43 DB OOOH, OOOH, 03CH, 066H, 066H, 066H, 03CH, 018H TH::::OC
3C 18 44
OOBO 7E 18 18 00 00 00 45 DB 07EH,018H,018H,000H,00QH,OQOH BT OC
OOB6 00 00 3F 33 3F 30 46 DB OOOH, OOOH, 03FH, 033H, 03FH, 030H, 030H, 030H TH::::OD
30 30 47
OOBE 70 FO EO 00 00 00 48 DB 070H,OFOH,OEOH,OOOH,000H,OOOH , BT 00
OOC4 00 00 7F 63 7F 63 49 DB 000H,000H,07FH,063H,07FH,063H,063H,063H ; TH::::OE
63 63 50
OOCC 67 E7 E6 CO 00 00 51 DB 067H,OE7H,OE6H,OCOH,OOOH,000H , BT_OE
0002 00 00 18 18 DB 3C 52 DB 000H,000H,018H,018H,ODBH,03CH,0E7H,03CH ; TH_OF
E7 3C 53
OODA DB 18 18 00 00 00 54 08 OOBH, 01 8H, 018H, OOOH, OOOH, OOOH
55
OOEO 00 00 80 CO EO F8 56 DB 000H,000H,080H,OCOH,OEOH,OF8H,OFEH,OF8H ; TH_l0
FE F8 57
00E8 EO CO 80 00 00 00 58 DB OEOH, OCOH, 080H, OOOH, OOGH, OOOH BT 10
OOEE 00 00 02 06 OE 3E 59 DB OOOH, OOOH, 002H, 006H, OOEH, 03EH, OFEH,03EH TH::::11
FE 3E 60
OOF6 DE 06 02 00 00 00 61 DB OOEH, 006H, 002H, OOOH, OOGH, OOOH BT 11
OOFC 00 00 18 3C 7E 18 62 DB OOOH, OOOH, 018H,03CH, 07EH, 018H,018H,018H TH::::12
18 18 63
0104 7E 3C 18 00 00 00 64 DB 07EH, 03CH, 018H, OOOH, OOGH, OOOH BT 12
OlOA 00 00 66 66 66 66 65 DB OOOH, OOOH, 066H, 066H, 066H, 066H,066H, 066H TH=-'3

August 2, 1984 IBM Enhanced Graphics Adapter 153

 66 66 66
0112 006666000000 67 OB OOOH,066H,066H,OOOH,OOOH,OOOH , 8T_13
0118 0000 7F DB DB DB 68 08 OOOH,OOOH,07FH,00BH,ODBH,ODBH,07BH,01BH ; TH_14
7B lB 69
0120 18 1B 1B 00 00 00 70 DB 01BH,01BH,01BH,000H,000H,000H , BT 14
0126 00 7C C6 60 38 6C 71 08 OOOH, 07CH, OC6H, 060H, 038H, 06CH, OC6H, OC6H ; TH=15
C6 C6 72
012E 6C 38 DC C6 7C 00 73 08 06CH,038H,00CH,OC6H,07CH,OOOH 8T 15
0134 00 00 00 00 00 00 74 DB GOOH, OOOH, OOOH, OOOH, OOGH, OOOH, OOGH, OOOH TH=16
00 00 75
013C FE FE FE 00 00 00 76 DB GFEH,OFEH,OF£H,OOOH,OOOH,OOOH , BT 16
0142 00 00 18 3C 7E 18 77 DB OOOH,000H,018H,03CH,07EH,018H,018H,018H ; TH=17
18 18 78
014A 7E 3C 18 7E 00 00 79 DB 07EH,03CH,018H,07£H,000H,OOOH , BT 17
0150 00 00 18 3C 7E 18 80 DB OOOH,000H,018H,03CH,07EH,018H,018H,018H ; TH=,8
18 18 81
0158 18 18 18 00 00 00 82 08 018H, 018H, 018H, OOOH, OOOH, OOOH BT_ 18
015E 00 00 18 18 18 18 83 08 OOOH, OOOH, 018H, 018H, 018H, 018H, 018H, 018H TH_19
18 18 84
0166 7E 3C 18 00 00 00 85 DB 07EH,03CH,018H,000H,000H,000H BT 19
016C 00 00 00 00 18 DC 86 DB OOOH, OOOH, OOOH, OOOH, 018H, OOCH, OFEH, OOCH TH=,A
FE DC 87
0174 18 00 00 00 00 00 88 DB 018H,000H,OOOH,OOOH,OOOH,000H BT lA
017A 00 00 00 00 30 60 89 DB OOOH, OOOH, OOOH, OOOH, 030H, 060H, OF£H, 060H TH= 1B
FE 60 90
0182 30 00 00 00 00 00 91 DB 030H,OOOH,000H,OOOH,OOOH,OOOH , BT 18
0188 00 00 00 00 00 CO 92 08 OOOH,OOOH,OOOH,OOOH,OOOH,OCOH,OCOH,OCOH ; TH=,C
CO CO 93
0190 FE 00 00 00 00 00 94 DB OFEH,OOOH,OOOH,OOOH,OOOH,OOOH 8T lC
0196 00 00 00 00 28 6C 95 DB OOOH,OOOH,OOOH,000H,028H,06CH,OFEH,06CH ; TH=,0
FE 6C 96
019E 28 00 00 00 00 00 97 DB 028H, OOOH, OOOH, OOOH, OOOH, OOOH BT_1D
01A4 00 00 00 10 38 38 98 DB OOOH, OOOH, OOOH,010H, 038H, 038H, 07CH, 07CH TH_l £
7C 7C 99
01AC FE FE 00 00 00 00 100 DB OFEH,OFEH,OOOH,OOOH,OOOH,OOOH , BT_1E
01B2 00 00 00 FE FE 7C 101 DB OOOH,000H,000H,OFEH,OFEH,07CH,07CH,038H ; TH_' F
7C 38 102
01BA 38 10 00 00 00 00 103 DB 038H, 010H, OOOH, OOOH, OOOH, OOOH
104
01CO 00 00 00 00 00 00 105 DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH ; TH_20 SP
00 00 106
01C8 00 00 00 00 00 00 107 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH BT 20 SP
01CE 00 00 18 3C lC 3C 108 DB OOOH, OOOH, 018H, 03CH, 03CH, 03CH, 018H, 018H TH=21!
18 18 109
0106 00 18 18 00 00 00 110 DB OOOH,018H,018H,OOOH,000H,000H , BT 21 !
010C 00 66 66 66 24 00 111 DB 000H,066H,066H,066H,024H,OOOH,000H,OOOH ; TH=22 "
00 00 112
01E4 000000000000 113 DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH , BT 22 It
OlEA 00 00 6C 6C FE 6C 114 DB OOOH,000H,06CH,06CH,OFEH,06CH,06CH,06CH ; TH=23 II
6C 6C 115
01 F2 FE 6c 6C 00 00 00 116 08 OF£H,06CH,06CH,OOOH,000H,000H BT_23 II
01V8 18 18 7C C6 C2 CO 117 08 018H, 018H, 07CH, OC6H, OC2H, OCOH, 07CH, 006H TH_24 S
7C 06 118
0200 86 C6 7C 18 18 00 119 DB 086H,OC6H,07CH,018H,018H,000H BT 24 S
0206 00 00 00 00 C2 C6 120 08 OOOH, OOOH,OOOH, OOOH, OC2H, OC6H, OOCH, 018H TH=25 '%'
DC 18 121
020E 30 66 C6 00 00 00 122 DB 030H,066H,OC6H,000H,000H,OOOH , BT_25 '%'
0214 00 00 38 6C 6C 38 123 08 OOOH,000H,038H,06CH,06CH,038H,076H,00CH ; TH_26 &:
76 DC 124
021C CC CC 76 00 00 00 125 08 OCCH,OCCH,076H,000H,000H,000H BT_26 &:
0222 00 30 30 30 60 00 126 08 OOOH, 030H, 030H, 030H, 060H, OOGH, OOOH, OOOH TH_27 ,
00 00 127
022A 00 00 00 00 00 00 128 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH BT 27
0230 00 00 OC 18 30 30 129 08 OOOH, OOOH, OOCH, 01 8H, 030H, 030H, 030H, 030H TH_28 (
30 30 130
0238 30 180C 00 00 00 131 08 030H,018H,00CH,000H,000H,000H BT_28 (
023E 00 00 30 180C DC 132 08 OOOH, OOOH, 030H, 018H, OOCH, OOCH, OOCH, OOCH TH_29)
OC oc 133
0246 OC 18 30 00 00 00 134 08 OOCH,018H,030H,000H,000H,000H BT_29 )
024C 00 00 00 00 66 3C 135 08 OOOH, OOOH, OOOH, OOOH, 066H, 03CH, OFFH, 03CH TH_2A *
FF 3C 136
0254 66 00 00 00 00 00 137 DB 066H,000H,OOOH,000H,OOOH,000H BT 2A *
025A 00 00 00 00 18 18 138 DB 000H,OOOH,000H,OOOH,018H,018H,07EH,018H TH::::2B +
7E 18 139
0262 18 00 00 00 00 00 140 DB 018H,000H,000H,000H,000H,000H BT 2B +
0268 00 00 00 00 00 00 141 DB OOOH,OUOH,OOOH,OOOH,OOOH,OOOH,OOOH,OGOH TH=2C,
00 00 142
0270 18 18 18 30 00 00 143 08 018H,018H,018H,030H,OOOH,OOOH BT_2C ,
0276 00 00 00 00 00 00 144 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OFEH, OOOH TH_2D-
FE 00 145
027E 00 00 00 00 00 00 146 DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH 8T 20 -
0284 00 00 00 00 00 00 147 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOGH TH=2E
00 00 148
028C 00 18 18 00 00 00 149 DB OOOH,018H,018H,000H,000H,000H BT 2E ,
0292 00 00 02 06 OC 18 150 DB OOOH,OOOH,002H,006H,OOCH,018H,030H,060H TH::::2F I
30 60 151
029A co 80 00 00 00 00 152 08 OCOH, 080H, OOOH, OOOH, OOOH, OOOH BT_2F I
02AO 00 00 7C C6 CE OE
153
154 DB OGOH, OOOH, 07CH, OC6H. OCEH, ODEH, OF6H, OE6H ; TH_30 °
02A8
02AE
F6
c6
00
E6
C6
00
7C 00 00 00
18 38 78 18
155
156
157
DB
DB
OC6H, OC6H, 07CH, OOOH, OOOH, OOOH
OOOH, OOOH, 018H, 038H, 078H, 018H, 018H, 018H
BT_30
TH_31 1
°
18 18 158
02B6 18 18 7£ 00 00 00 159 DB 018H,018H,07EH,000H,OOOH,000H BT 31 1
02BC 00 00 7C c6 06 oc 160 DB OOOH,000H,07CH,OC6H,006H,OOCH,018H,030H TH=322
18 30 161
02c4 60 C6 FE 00 00 00 162 DB 060H,OC6H,OFEH,000H,000H,000H 8T 32 2
02CA 00 00 7C C6 06 06 163 DB OOOH, OOOH, 07CH, OC6H, 006H, 006H, 03CH, 006H TH=33 3
3C 06 164
0202 06 C6 7C 00 00 00 165 DB 006H,OC6H,07CH,000H,OOOH,000H , BT_33 3
0208 00 00 DC lC 3C 6C 166 DB 000H,OOOH,00CH,01CH,03CH,06CH,OCCH,OF£H ; TH_34 4
CC FE 167
02EO OC OC 1E 00 00 00 168 DB OOCH, OOCH, 01 EH,OOOH, OOOH, OOOH BT 34 4
02E6 00 00 FE CO CO CO 169 08 000H,000H,OFEH,OCOH,OCOH,OCOH,OFCH,006H TH=355
FC 06 170
02££ 06 C6 7C 00 00 00 171 08 006H,OC6H,07CH,000H,000H,000H 8T 35 5
02F4 00 00 38 60 CO CO 172 08 OOOH,000H,038H,060H,OCOH,OCOH,OFCH,OC6H TH=366
FC C6 173
02FC C6 C6 7C 00 00 00 174 08 OC6H, OC6H, 07CH, OOOH, OOOH, OOOH BT_36 6
0302 00 00 FE C6 06 DC 175 08 OOOH, OOOH, OFEH, OC6H, 006H, OOCH, 018H, 030H TH_37 7
18 30 176
030A 30 30 30 00 00 00 177 08 030H,030H,030H,000H,OOOH,000H , BT_37 7
0310 00 00 7C C6 C6 C6 178 DB OOOH, OOOH, 07CH, OC6H, OC6H, OC6H, 07CH, OC6H ; TH_38 8
7C C6 179
0318 C6 C6 7C 00 00 00 180 DB OC6H,OC6H,07CH,000H,OOOH,OOOH , BT 38 8
031£ 00 00 7C C6 C6 C6 181 DB 000H,000H,07CH,OC6H,OC6H,OC6H,07£H,006H ; TH=39 9
7£ 06 182
0326 06 OC 78 00 00 00 183 08 006H, OOCH, 078H, OOOH, OOOH, OOOH 8T_39 9
032C 00 00 00 18 18 00 184 08 OOOH, OOOH, OOOH, 018H, 018H, OOOH, OOOH, OOOH TH_3A:
00 00 185
0334 18 18 00 00 00 00 186 08 018H, 018H, OOOH, OOOH, OOOH, OOOH BT 3A :
OHA 00 00 00 18 18 00 187 08 OOOH, OOOH, OOOH, 018H, 018H, OOOH, OOOH, OOOH TH=3B;
00 00 188
0342 18 18 30 00 00 00 189 08 018H,018H,030H,000H,OOOH,OOOH • BT_3B ;
0348 00 00 06 OC 18 30 190 08 OOOH, OOOH, 006H, OOCH, 018H, 030H, 060H, 030H ; TH_3C <
60 30 191

154 IBM Enhanced Graphics Adapter August 2, 1984

0350
0356
18
00
OC
00
06 00 00 00
00 00 00 7E
192 O.
08
018H,OOCH,006H,000H,OOOH,OOOH
OOOH. OOOH, OOOH, OOOH. OOOH, 07EH, OOOH, OOOH
BT_3C <
TH_3D ==
193
00 00 194
035E 7E 00 00 00 00 00 195 o. 07EH, OOOH, OOOH, OOOH, OOOH, OOOH ; BT_3o ==
0364 00 00 60 30 18 DC 196 o. 000H,000H,060H,030H,018H,00CH,006H,00CH ; TH_3E >
06 OC 197
036C 18 30 60 00 00 00 198 o. 018H, 030H, 060H, OOOH, OOOH, OOOH BT _3E >
0372 00 00 7C C6 C6 DC 199 O. 000H,OOOH,07CH,OC6H,OC6H,00CH,018H,018H TH_3F"
18 18 200
037A 00 18 18 00 00 00 201 DB 000H,018H,018H,OOOH,000H,OOOH BT_3F"
202
0380 00 00 7C C6 C6 OE 203 08 OOOH,000H,07CH,OC6H,OC6H,00EH,OOEH,ODEH ; TH_40 @
DE DE 204
0388 DC CO 7C 00 00 00 205 O. ODCH,OCOH,07CH,000H,OOOH,000H , BT 40 @
038E 00
C6
00
FE
10 38 6C C6 206 O. 000H,OOOH,010H,038H,06CH,OC6H,OC6H,OFEH ; TH=41 A
207
0396 C6 c6 C6 00 00 00 208 08 OC6H,OC6H,OC6H,OOOH,000H,000H BT 41 A
039C 00 00 FC 66 66 66 209 08 OOOH,000H,OFCH,066H,066H,066H,07CH,066H TH=42 8
7C 66 210
03A4 66 66 FC 00 00 00 211 o. 066H,066H,OFCH,OOOH,OOOH,OOOH BT 42 B
03M 00 00 3C 66 C2 CO 212 O. 000H,000H,03cH,066H,OC2H,OCOH,OCOH,OCOH TH=43 C
CO CO 213
03B2 C2 66 3C 00 00 00 214 08 OC2H,066H,03CH,OOOH,000H,000H BT_43 C
03B8 00 00 F8 6C 66 66 215 08 OOOH,OOOH,OF8H,06cH,066H,066H,066H,066H TH_44 0
66 66 216
03CO 66 6C F8 00 00 00 217 08 066H,06CH,OF8H,OOOH,OOOH,000H , BT 44 0
03C6 00 00 FE 66 62 68 218 08 OODH,OOOH,OFEH,066H,062H,068H,078H,068H ; TH=45 E
78 68 219
03CE 62 66 FE 00 00 00 220 08 062H,066H,OFEH,000H,OOOH,OOOH BT_45 E
0304 00 00 FE 66 62 68 221 06 OOOH, OOOH, OFE~!, 066H, 062H, 068H, 078H, 068H TH_46 F
78 68 222
030C 60 60 FO 00 00 00 223 O. 060H,060H,OFOH,000H,000H,000H BT~46 F
03E2 00 00 3C 66 C2 CD 224 DB OOOH,OOOH,03CH,066H,OC2H,OCOH,OCOH,ODEH TH_47 G
CO DE 225
03EA C6 66 3A 00 00 00 226 D. OC6H,066H,03AH,000H,OOOH,OOOH , BT 47 G
03FO 00 00 C6 C6 C6 C6 227 D. OOOH, OOOH, OC6H, OC6H, OC6H, OC6H, OFEH, OC6H ; TH=48 H
FE C6 228
03F8 C6 C6 C6 00 00 00 229 08 OC6H,OC6H,OC6H,OOOH,000H,OOOH , BT_48 H
03FE 00
18
00
18
3C 18 18 18 230
231
O' OOOH,OOOH,03CH,018H,018H,018H,018H,018H ; TH_49 !

0406 18 18 3C 00 00 00 232 08 018H,018H,03CH,OOOH,OOOH,000H , BT_49 I

040C 00 ~OlE DC DC DC 233 08 OOOH,OOOH,OlEH,OOCH,OOCH,OOCH,OOCH,OOCH ; TH_4A J
DC DC 234
0414 CC CC 78 00 00 00 235 08 OGCH,OCCH,078H,000H,OOQH,OOOH ; BT 4A J
041A 00 00 E6 66 6C 6c 236 08 OOOH,OOOH,OE6H,066H,06CH,06CH,078H,06CH TH=4B K
78 6C 237
0422
0428
6C
00
66 E6 00
00 FO 60
00 00
60 60
238
239
O'
DB
06CH,066H,OE6H,000H,OOOH,000H
OOOH, OOOH, OFOH, 060H, 060H, 060H, 060H, 060H
8T 4B K
TH=4C L
60 60 240
0430
0436
62
00
66 FE 00
00 C6 EE
00 00
FE FE
241 O. 062H,066H,OFEH,000H,OOOH,000H , BT_4C L
242 06 OOOH,000H,OC6H,OEEH,OFEH,OFEH,OD6H,OC6H ; TH_40 M
06 c6 243
043E c6 C6 C6 00 00 00 244 08 OC6H,OC6H,OC6H,OOOH,000H,000H , BT_4D M
0444 00 00 C6 E6 F6 FE 245 08 OOOH,OOOH,OC6H,OE6H,OF6H,OFEH,OoEH,OCEH ; TH_4E N
DE CE 246
044C C6 C6 C6 00 00 00 247 08 OC6H,OC6H,OC6H,OOOH,OOOH,OOOH , BT_4E N
0452 00
C6
00 38 6C
C6
C6 C6 248
249
O' OOOH, OOOH, 038H, 06CH, OC6H, OC6H, OC6H, OC6H ; TH_ 4F 0

045A C6 6C 38 00 00 00 250 D. OC6H, 06CH, 038H, OOOH, OOOH, OOOH

251
0460 00
7C
00
60
FC 66 66 66 252
253
O' 000H,OOOH,OFCH,066H,066H,066H,07CH,060H ; TH_50 P

0468
046E
60
00
60
00
FO 00 00 00
7C C6 C6 C6
254
255
O'
O.
060H,060H,OFOH,OOOH,OOOH,000H
000H,OOOH,07CH,OC6H,OC6H,OC6H,OC6H,OD6H
BT 50 P
TH=51 Q
C6 06 256
0476 DE 7C OC OE 00 00 257 O. ODEH,07CH,OOCH,OOEH,OOOH,000H , BT_51 Q
047C 00
7C
00
6C
FC 66 66 66 258 O. OOOH, OOOH, OFCH, 066H, 066H, 066H, 07CH, 06CH ; TH_52 R
259
0484 66 66 E6 00 00 00 260 08 066H,066H,OE6H,OOOH,OOOH,OOOH BT_52 R
048A 00
38
00
DC
7C C6 c6 60 261 O. OOOH,OOOH,07CH,OC6H,OC6H,060H,038H,OOCH TH_53 S
262
0492 C6 C6 7C 00 00 00 263 O. OC6H,OC6H,07CH,000H,OOOH,000H , BT_53 S
0498 00
18
00
18
7E 7E 5A 18 264
265
O' OOOH,OOOH,07EH,07EH,05AH,018H,018H,018H ; TH_54 T
04AO 18 18 3C 00 00 00 266 O. 018H,018H,03CH,OOOH,000H,000H , BT_54 T
04A6 00
C6
00
C6
C6 C6 C6 C6 267 O. 000H,OOOH,oc6H,OC6H,oc6H,oc6H,OC6H,OC6H ; TH_55 U
268
04AE C6 C6 7C 00 00 00 269 O. OC6H,OC6H,07CH,OOOH,OOOH,OOOH BT_55 U
04B4 00
C6
00
C6
C6 C6 C6 C6 270 O. OOOH, OOOH, OC6H, OC6H,OC6H, OC6H, OC6H, OC6H TH_56 V
271
04BC 6c 38 10 00 00 00 272 O' 06CH,038H,010H,OOOH,OOOH,000H , BT_56 V
04C2 00
06
00
06
C6 C6 C6 C6 273
274
O' OOOH,000H,OC6H,OC6H,OC6H,OC6H,OD6H,OD6H ; TH_57 W

04CA
0400
FE
00
7C
00
6C 00 00 00
C6 C6 6C 38
275
276
O.
08
OFEH, 07CH, 06CH, OOOH, DOOH, OOOH , BT 57 W
OOOH, OOOH, OC6H, OC6H, 06CH, 038H, 038H, 038H ; TH=58 X
38 38 277
0408 6C C6 C6 00 00 00 278 08 06CH, OC6H, OC6H, OOOH, OOOH, OOOH , BT _58 X
04DE 00 00 66 66 66 66 279 08 OOOH, OOOH, 066H, 066H, 066H, 066H, 03CH, 018H ; TH_59 y
3C 18 280
04E6 18 18 3C 00 00 00 281 D. 018H,018H,03CH,000H,000H,000H , BT_59 y
04EC 00 00 FE C6 8C 18 282 O. OOOH,000H,OFEH,OC6H,08CH,018H,030H,060H ; TH_5A Z
30 60 283
04F4 C2 C6 FE 00 00 00 284 o. OC2H,OC6H,OFEH,000H,000H,000H BT 5A Z
04FA 00 00 3C 30 30 30 285 o. OOOH, OOOH, 03CH, 030H, 030H, 030H, 030H, 030H TH=5B [
30 30 286
0502 30 30 3C 00 00 00 287 O' 030H, 030H, 03CH, OOOH, OOOH, OOOH BT 58 [
0508 00
38
00
1C
80 CO EO 70 288
289
O' OOOH, OOOH, 080H, OCOH, OEOH, 070H, 038H, OtCH TH=5C
0510
0516
DE
00
06
00
02 00 00 00
3C DC OC OC
290
291
0'
o. 00EH,006H, 002H, OOOH, OOOH, OOOH
000H,OOOH,03CH,OOCH,00CH,00CH,OOCH,OOCH
BT 5C
TH=5D 1
DC DC 292
051E DC DC 3C 00 00 00 293 o. 00cH,aocH,03CH,OOOH,000H,000H BT_50 1
0524 10
00
38
00
6C C6 00 00 294
295
O' 010H, 038H, 06CH, OC6H, OOOH, OOOH, oaoH, OOOH TH_5E

052C 00 00 00 00 00 00 296 D. OOOH, OOOH, OOOH, OOOH, OOOH, OOOH , BT_5E

0532 00 00 00 00 00 00 297 O' OOOH,OOOH, OOOH,OOOH, OOOH, OOOH, OOOH, OOOH ; TH_5F _

053A
00
00
00
00 00 00 FF 00
298
299
300
O. OOOH, OOOH, OOOH"OOOH, °
FFH, OOOH
0540 30 30 18 00 00 00 301 o. 030H, 030H, 018H, OOOH, OOOH, OOOH, OOOH, OOOH ; TH_60
00 00 302
0548 00 00 00 00 00 00 303 08 OOOH, OOOH, OOOH, OOOH, OOOH, OOOH , BT 60
054E 00 00 00 00 00 78 304 OS OOOH,OOOH, OOOH, OOOH, OOOH, 078H,00CH,07CH ; nC61 LOWER_CASE A
OC 7C 305
0556 CC CC 76 00 00 00 306 O. OCCH,OCCH,076H,000H,OOOH,000H , BT_61 LOWER_CASE A
055C 00 00 EO 60 60 78 307 08 000H,000H,OEOH,060H,060H,078H,06CH,066H ; TH_62 L.C, B
6C 66 308
0564 66 66 7C 00 00 00 309 O' 066H,066H,07CH,000H,OOOH,OOOH , BT_62 L,C. B
056A 00
C6
00 00 00
CO
00 7C 310
311
O' OOOH, OOOH, OOOH, OOOH, OOOH, 07CH, OC6H, OCOH ; TH_63 L, C, C

0572
0578
CO
00
C6 7C 00
00 1C DC
00 00
DC 3C
312
313
O'
o.
OCOH,OC6H, 07CH, OOOH, OOOH, OOOH ,
000H,OOOH,01CH,OOCH,OQCH,03CH,06CH,OCCH ;
BT_63 L. C,
TH_64 L.C.
6C CC 314
0580 CC CC 76 00 00 00 315 o. OCCH,OCCH,076H,000H,000H,000H , BT_64 L,C.
0586 00 00 00 00 00 7C 316 o. OOOH, OOOH, OOOH, OaOH, OOOH, 01CH, OC6H, OFEH ; TH_65 L. c.
C6 FE 317

August 2, 1984 IBM Enhanced Graphics Adapter 155

058E co c6 7C 00 00 00 318 08 OCOH.OC6H,07CH,OOOH.000H.000H ; Bl_65 L.C o E
0594 00 00 38 6C 64 60 310 OB 000H,OOOH,038H,06CH,064H,060H,OFOH.060H ; TH_66 L.C. F
FO 60 320
059C 60 60 FO 00 00 00 321 DB 060H.060H,OFOH,OOOH,OOOH,OOOH , 81_66 L.C. F
05A2 00 00 00 00 00 76 322 DB 000H.000H,OOOH,OOOH,OOOH,076H,OCCH,OCCH ; TH_67 L.C. G
CC CC 323
05AA CC 7C DC CC 78 00 324 DB OCCH,07CH,OOCH,OCCH,078H,OOOH , BT_67 L.C. G
05BO 00 00 EO 60 60 6C 325 DB 000H.000H.OEOH,060H,060H,06cH,076H,066H ; TH_68 L.C. H
76 66 326
05B8 66 66 E6 00 00 00 327 DB 066H.066H,OE6H,OOOH,OOOH,OOOH , BT_68 L.C. H
05BE 00 00 18 18 00 38 328 DB 000H.000H,018H,018H,OOOH.038H,018H,018H ; TH_69 L.C. I
18 18 320
05c6 18 18 3C 00 00 00 330 DB 018H.018H,03CH,OOOH,OOOH,OOOH , BT_69 L.C. I
05CC 00 00 06 06 00 DE 331 DB 000H,OOOH,006H.006H,OOOH,OOEH,006H.006H ; TH_6A. L.C. J
06 06 332
0504 06 06 66 66 3C 00 333 DB 006H,006H,066H,066H,03CH,OOOH ; 8T_6A L.C. J
05DA. 00 00 EO 60 60 66 334 DB 000H.000H,OEOH,060H,060H,066H,06cH,078H ; TH_6B L.C. K
6C 78 335
05E2 6C 66 E6 00 00 00 336 DB 06CH,066H,OE6H.000H,OOOH,OOOH , BC6B L.C. K
05E8 00 00 38 18 18 18 337 DB 000H,OOOH,038H.018H.018H,018H,018H,018H ; TH_6c L.C. L
18 18 338
05FO 18 18 3C 00 00 00 33. DB 018H.018H,03CH.000H.000H .. 000H ; Bl_6c L.C. L
05F6 00 00 00 00 00 EC 340 DB 000H,OOOH,OOOH.000H.000H,OECH,OFEH,006H ; TH_60 L.C. M
FE 06 341
05FE 06 06 c6 00 00 00 342 DB 006H.006H.OC6H.000H,000H,000H • BT_6D L.C. M
0604 00 00 00 00 00 DC 343 DB 000H.000H,OOOH,000H,OOOH,00CH,066H,066H ; TH_6E LoCo N
66 66 344
060C 66 66 66 00 00 00 345 DB 066H,066H,066H,OOOH,OOOH,OOOH ; BT_6E L.C o N
0612 00 00 00 00 00 7C 346 DB 000H,OOOH,OOOH,000H.000H,07CH.OC6H,OC6H ; TH_6F L.C. 0
C6 C6 347
061A C6 C6 7C 00 00 00 348 DB OC6H, OC6H, 07CH, OOOH. OOOH, OOOH
340
0620 00 00 00 00 00 DC 350 DB 000H,OOOH,OOOH,000H,000H,OOCH,066H,066H ; IH_70 L.C. P
66 66 351
0628 66 7C 60 60 FO 00 352 DB 066H.07CH,060H,060H,OFOH,OOOH • BT_70 L.C.
062E 00 00 00 00 00 76 353 DB OOOH, OOOH, OOOH,OOOH,OOOH, 076H,OCCH, OCCH ; TH_71 L. C.
CC CC 354
0636 CC 7C DC OC 1E 00 355 DB OCCH, 07CH, OOCH,OOCH,Ol EH, OOOH , BT_71 L. C.
063C 00 00 00 00 00 DC 356 DB 000H,OOOH,OOOH,OOOH,OOOH,ODCH,076H,066H ; TH_72 L.C.
76 66 357
0644 60 60 Fa 00 00 00 358 DB 060H.060H,OFOH,000H,000H,OOOH , BT_72 L.C. R
064A 00 00 00 00 00 7C 350 DB 000H,OOOH,OOOH,000H,000H,07CH,OC6H,070H ; TH_73 L.C. S
C6 70 360
0652
0658
1C
00
C6
00
7C 00 00 00
10 30 30 FC
3.'
3.2
DB
DB
01CH,OC6H,07CH,OOOH,OOOH,OOOH ; BT_73 L.C.
OOOH, OOOH, 010H,030H,030H, OFCH,030H, 030H ; IH_74 L. C.
30 30 3.3
0660
0666
30
00
36
00
1C 00 00 00
00 00 00 CC
3.'
3.5
DB
DB
030H, 036H,01CH, OOOH,OOOH, OOOH ; BT_74 L. C.
OOOH,OOOH,OOOH#OOOH,OOOH,OCCH,OCCH,OCCH ; IH_75 L.C.
CC CC 3 ••
066E CC CC 76 00 00 00 3.7 DB OCCH,OCCH,076H,000H .. 000H,OOOH ; BT_75 L.C. U
0674 00 00 00 00 00 66 3.8 DB 000H,000H,OOOH,000H,OOOH,066H.066H,066H ; TH_76 L.C. V
66 66 3 ••
067C 66 3C 18 00 00 00 370 DB 066H,03CH,018H,OOOH,OOOH,OOOH ; BT_76 L.C. V
0682 00 00 00 00 00 C6 371 DB 000H,OOOH,OOOH,OOOH,OOOH,OC6H,OC6H,006H ; IH_77 L.C o W
e6 06 372
068A 06 FE 6e 00 00 00 373 OB 006H,OFEH,06CH,OOOH,OOOH,000H ; BT_77 L.C. W
0690 00 00 00 00 00 C6 374 DB 000H,000H,OOOH,OOOH,OOOH,OC6H,06CH,038H ; TH_78 L.C. X
6e 38 375
0698 38 6C C6 00 00 00 37. OB 038H,06CH,OC6H,OOOH,OOOH,000H ; BT_78 L.C o x
069E 00 00 00 00 00 e6 377 DB 000H,OOOH,OOOH,OOOH,OOOH,OC6H,OC6H,OC6H ; TH_79 LoCo Y
C6 e6 378
06A6 C6 7E 06 DC F8 00 370 DB OC6H,07EH,006H,OOCH,OF8H,OOOH ; BT_79 L.C. Y
06AC 00 00 00 00 00 FE 380 DB 000H,000H#000H,OOOH,OOOH,OFEH,OCCH,018H ; IH_7A L.C. Z
CC 18 381
06B4 30 66 FE 00 00 00 382 DB 030H.066H,OFEH,OOOH .. 000H,OOOH , BT_7A L.C. Z
06BA 00 00 DE 18 18 18 383 DB 000H,000H.00EH,018H,018H,018H,070H,018H ; TH_7B L 8RAK
70 18 38'
06C2
06C8
18
00
00
18
00
18
DE 00 00 00
18 18 18 18
385
386
387
DB
DB g~g~:g~g~:g~~~:g~g~:g~g~:g~g~.000H.018H ~ ~~=i~ r BRAK
0600 18 18 18 00 00 00 388 DB 018H,018H,018H,OOOH,OOOH.000H • BT_7C I
0606 00 00 70 18 18 18 380 DB 000H,000H.070H,018H,018H,018H,OOEH,018H ; TH_7D R BRAK
DE 18 300
06DE 18 18 70 00 00 00 301 DB 018H,018H,070H,OOOH,OOOH,OOOH ; 8T_7D R BRAK
06E4 00 00 76 DC 00 00 3,2 DB 000H,OOOH,076H,ODCH,OOOH,OOOH,000H.000H ; TH_7E TILDE
00 00 393
06EC 00 00 00 00 00 00 39' DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH ; 8T_7E TILDE
06F2 00 00 00 00 10 38 3.5 DB 000H,OOOH,000H,OOOH,010H,038H,06CH,OC6H ; TH_7F DELTA
6C C6 30.
06FA C6 FE 00 00 00 00 307 DB OC6H, OFEH, OOOH, OOOH# OOOH, OOOH
308
0700 00 00 3C 66 C2 co 300 DB OOOH,000H,03CH,066H,OC2H,OCOH,OCOH.OC2H ; TH_80
CO C2 400
0708 66 3C DC 06 7C 00 401 DB 066H,03CH,00CH,006H,07CH,OOOH ; BT_80
070E 00 00 CC CC 00 CC '02 DB OOOH,OOOH,OCCH,OCCH,OOOH.OCCH.OCCH .. OCCH ; TH_81
CC CC '03
0716 CC CC 76 00 00 00 40' DB OCCH,OCCH,076H,000H,OOOH,OOOH ; BT_81
071C 00 DC 18 30 00 7C 405 OB 000H,OOCH,018H,030H,OOOH,07CH,OC6H,OFEH ; TH_82
C6 FE 40.
0724 CO C6 7C 00 00 00 407 DB OCOH,OC6H,07CH,000H,000H,OOOH ; BT_82
072A 00 10 38 6C 00 78 408 DB 000H,010H,038H,06CH,OOOH, 078H,OOCH, 07CH ; TH_83
OC 7C 400
0732 CC CC 76 00 00 00 410 DB OCCH,OCCH,076H,OOOH,OOOH,000H ; 8T_83
0738 00 00 CC CC 00 78
0740
OC
CC
7C
CC 76 00 00 00 '"
"2
413
DB
DB
000H,000H,OCCH,OCCH,OOOH,078H,00CH,07CH ; IH_84
OCCH,OCCH,076H,OOOH,OOOH,OOOH ; BT_84
0746
074E
00
OC
CC
60
7C
CC
30 18 00 78
76 00 00 00
'"'15
".
DB
DB
000H,060H,030H,018H,OOOH,078H,00CH,07CH ; TH_85
OCCH,OCCH,076H,OOOH,OOOH.000H ; BT_85
0754 00
DC
38
7C
6c 38 00 78 '17
"8
DB 000H,038H,06CH,038H#000H, 078H,00CH, 07CH ; TH_86

ggg~:ggg~:g~g~:ggg~:g~g~:ggg~.060H,066H ~~=g~
075C CC CC 76 00 00 00 410 DB
0762 00 00 00 00 3C 66 420 DB ;
60 66 '21
ggg~:g~g~:g~g~:g~g~:ggg=:g~g~.OC6H,OFEH ~ ~~=g~
076A 3C DC 06 3C 00 00 '22 DB
0770 00 10 38 6C 00 7C '23 DB
C6 FE '24
co
ggg~:ggg~:g~g~:ggg~:ggg~:g~g~,OC6H,OFEH ~ ~~=:;
0778 C6 7C 00 00 00 425 DB
077E 00 00 CC CC 00 7C 42. DB
C6 FE 427
0786 co C6 7C 00 00 00 428 DB OCOH,OC6H.07CH,000H,000H,OOOH ; BT_89
078C 00 60 30 18 00 7C 42' DB 000H,060H,030H,018H,OOOH,07CH,OC6H,OFEH ; IH_SA
co FE 430
ggg~:ggg~:g~~~:ggg~:ggg=:g~g=,018H,018H ~ ~~=:~
0794 CO C6 7C 00 00 00 431 DB
079A 00 00 66 66 00 38 432 DB
07A2
18
18
18
18 3C 00 00 00
'33 DB
07Ae 00 18 3C 66 00 38
'34
435 DB g~g=:g~:=:g~g=:ggg=:ggg=:g~g=,018H,018H ; ~~:g~
18 18 43.
g~g=:gJg=:g~g=:g~g=:ggg=:ggg=,018H,018H ~ ~~:gg
07BO 18 18 3C 00 00 00 '37 DB
07B6 00 60 30 18 00 38 '38 DB
18 18 430
g~g=:g~=:g~=:g~g=:g~g=:ggg=,0C6H,OC6H ~~:g~
07BE 18 18 3C 00 00 00 440 DB
07C4 00 C6 C6 10 38 6C 441 DB ;
co C6 442
07CC FE C6 C6 00 00 00 443 DB OFEH, OO6H, OO6H, OOOH, OOOH, OOOH

156 mM Enhanced Graphics Adapter August 2, 1984

0702 38 6c 38 00 38 6C 444 D8 038H.06CH.038H.000H.038H,06CH,OC6H,OC6H ; TH_8F
c6 c6 445
070A FE C6 C6 00 00 00 446 DB OFEH, 006H, OC6H, OOOH, OOOH, OOOH
447
07E0 18 30 60 00 FE 66 448 DB 018H, 030H, 060H,OOOH,OFEH, 066H, 060H, 07CH ; TH_90
60 7c 449
ggg~: ggg~: g~5~:ggg~:ggg~: g~g~, 036H, 07EH ~~:g~
07E8 60 66 FE 00 00 00 450 D8
07EE 00 00 00 00 CC 76 451 DB ;
36 7E 452
ggg~; ggg~:gg~~;ggg~:ggg~; ggg~, OFEH, OCCH ~~:~~
07F6 08 08 6E 00 00 00 453 DB
07FC 00 00 3E 6C CC CC 454 DB ;
FE CC 455
0804 CC CC CE 00 00 00 456 DB OCCH,OCCH,OCEH .. OOOH,OOOH.OOOH ; 8T_92
080A 00 10 38 6c 00 7C 457 DB 000H,010H, 038H,06CH,OOOH, 07CH, OC6H, OC6H ; TH_93
C6 C6 458
gg8~: gg8~:g~~~:gg~~:ggg~: g~g~, OC6H, OC6H ~~:~~
0812 C6 C6 7C 00 00 00 459 DB
0818 00 00 C6 C6 00 7C 460 D8 ;
C6 C6 461
ggg~: g~g~: g~g~:g~g~:ggg~: g~g~, OC6H, OC6H ~~:~~
0820 C6 C6 7C 00 00 00 462 DB
0826 00 60 30 18 00 7C 463 DB ;
C6 C6 464
ggg~:g~8~:g~~~;ggg~:ggg~:ggg~,occH,ocCH ~~:g~
082E C6 C6 7C 00 00 00 465 D8
0834 00 30 78 CC 00 CC 466 D8 ;
CC CC 467
ggg~:g~g~:g~8~:g~g~:ggg~:ggg~.occH,occH ~~:~~
083C CC CC 76 00 00 00 468 D8
0842 00 60 30 18 00 CC 469 DB ;
CC CC 470
ggg~:ggg~:g~~~:gg~~:ggg~:ggg~,oc6H,0C6H ~~:~~
084A CC CC 76 00 00 00 471 DB
0850 00 00 C6 C6 00 C6 472 DB ;
C6 C6 473
ggg~:g~~~:gg~~:g~~~:g~~~:ggg~,oc6H,0C6H ~~:~;
0858 C6 7E 06 DC 78 00 474 DB
085E 00 C6 C6 38 6C C6 475 D8 ;
C6 C6 476
ggg~;g~~~:g~~~;ggg~:ggg~:ggg~,oc6H,0C6H ~~:~~
0866 C6 6C 38 00 00 00 477 D8
086C 00 C6 C6 00 C6 C6 478 D8 ;
C6 C6 479
ggg~:g~g~: g1~~:g~g~: g~g~: ggg~, 060H, 066H ~~:~~
0874 C6 C6 7C 00 00 00 480 DB
087A 00 18 18 3C 66 60 481 D8 ;
60 66 482
ggg~:g~g~: gJ~~:g~g~:g~g~:g~g~,060H, 060H ~~:~~
0882 3C 18 18 00 00 00 483 D8
0888 00 38 6C 64 60 FO 484 D8 ;
60 60 485
0890 60 E6 FC 00 00 00 486 DB 060H,OE6H,OFCH,000H,000H,000H , BT_9C
0896 00 00 66 66 3C 18 487 D8 000H,000H,066H,066H,03CH,018H,07EH,018H ; TH_90
7E 18 488
089E 7E 18 18 00 00 00 489 D8 07EH,018H,018H,OOOH,OOOH,000H ; BT_90
08A4- 00 F8 CC CC F8 C4 490 D8 000H,OF8H, OCCH,OCCH, OF8H, OC4H,OCCH, ODEH ; TH_9E
CC DE 491
ggg~:gg~~:g~~~:g~g~:g~g~:g~g~,07EH,018H ~~:~~
08AC CC CC C6 00 00 00 492 D8
0882 00 DE 18 18 18 18 493 D8 ;
7E 18 494
08BA 18 18 18 08 70 00 495 D8 018H, 01 8H, 01 8H, 008H, 070H, OOOH
496
08CO 00 18 30 60 00 78 497 DB 000H,018H,030H,060H, 000H,078H .. 00CH, 07CH ; TH_AO
DC 7C 498
ggg~:ggg~:g1~~:g~g~:ggg~:g~g~,018H,018H j ~~:!~
08C8 CC CC 76 00 00 00 499 D8
OSCE 00 DC 18 30 00 38 500 DB
18 18 501
g~~~:g~g~:g~g~:ggg~:ggg~:g~g~,OC6H,OC6H ~~:~J
0806 18 18 3C 00 00 00 DB
080C 00
C6
18
C6
30 60 00 7C
502
503
504
DB i
08E4 C6 C6 7C 00 00 00 505 DB OC6H, OC6H,07CH, OOOH,OOOH, OOOH ; BT_A2
08EA 00 18 30 60 00 CC 506 D8 000H,018H,030H, 060H,OOOH, OCCH,OCCH,OCCH ; TH_A3
CC CC 507
08F2 CC CC 76 00 00 00 508 DB OCCH,OCCH,076H,OOOH,000H,OOOH , BT_A3
08F8 00 00 76 DC 00 DC 509 DB OOOH, OOOH, 076H,00CH, OOOH,OOCH, 066H, 066H ; TH_A4
66 66 510
0900 66 66 66 00 00 00 511 DB 066H, 066H, 066H,OOOH, OOOH,OOOH ; BT_A4
0906 76 DC 00 C6 E6 F6 512 DB 076H,OOCH,OOOH,OC6H,OE6H,OF6H,OFEH,OOEH ; TH_A5
FE DE 513
090E OE C6 C6 00 00 00 514 DB
0914 00 3C 6C 6C 3E 00 515 DB
7E 00 516
ggg~:g~~~:ggg~:ggg~:g~~~:ggg~,07CH,OOOH ~~:~~
091C 00 00 00 00 00 00 517 DB
0922 00
7C
38
00
6C 6C 38 00 518
519
DB i
092A 00 00 00 00 00 00 520 DB
0930 00 00 30 30 00 30 521 DB ggg~;ggg~:g~g~:g~g~:ggg~:g~g~,030H,060H ; ~~:~~
30 60 522
ggg~:ggg~:g~g~:ggg~:ggg~:ggg~,OFEH,OCOH ~~:~;
0938 C6 C6 7C 00 00 00 523 DB
093E 00 00 00 00 00 00 524 DB ;
FE CO 525
0946 CO CO 00 00 00 00 526 DB OCOH,OCOH,OOOH,OOOH,OOOH,OOOH , BT_A9
094c 00 00 00 00 00 00 527 DB 000H,000H,OOOH,000H,OOOH,000H,OFEH,006H ; TH_M
FE 06 528
0954 06 06 00 00 00 00 529 DB 006H,006H,OOOH,OOOH~000H,OOOH ; BT.-AA
095A 00 CO CO C6 CC 08 530 DB 000H .. OCOH,OCOH,OC6H,OCCH,0D8H,030H,060H ; TH_AB
30 60 531
0962 DC 86 DC 18 3E 00 532 DB 00CH,086H,00CH,018H~03EH,OOOH ; ST_AB
0968 00 CO CO C6 CC 08 533 DB 000H,OCOH,OCOH,OC6H,OCCH,0D8H,030H,066H ; TH_AC
30 66 534
0970 CE 9E 3E 06 06 00 535 D8 OCEH,09EH,03EH,006H .. 006H,00QH ; BT_AC
0976 00 00 18 18 00 18 536 DB 000H,OOOH,018H,018H~000H,018H,018H,03CH ; TH_AD
18 3C 537
097E 3C 3C 18 00 00 00 538 DB 03CH,03CH.018H,000H~000H,000H ; ST_AD
0984 00 00 00 00 36 6c 539 DB 000H,OOOH .. 000H,000H .. 036H,06CH,008H,06CH ; TH_AE
08 6C 540
098C 36 00 00 00 00 00 541 DB 036H,OOOH,OOOH,OOOH,OOOH,OooH , BT_AE
0992 00 00 00 00 DB 6C 542 D8 OOOH,OOOH,OOOH, 000H,OD8H, 06CH, 036H,06CH ; TH_AF
36 6c 543
099A DB 00 00 00 00 00 544 D8 008H, OOOH, OOOH, OOOH .. OOOH, OOOH
545
09AO " 44 11 44 11 44 546 D8 011H,044H,011H,044H,011H,044H,011H,044H ; TH_80
" 44 547
09A8 " 44 11 44 11 44 548 D8 011H,044H,011H,044H,011H,044H , BT_80
09AE 55 AA 55 AA 55 AA 549 D8 055H, OAAH, 055H, OMH, 055H, OAAH. 055H, OMH ; TH_81
55 AA 550
0986 55 AA 55 AA 55 AA 551 D8 055H,OAAH,055H,OMH,055H,OAAH ; 8T_81
098C DO 77 DO 77 DO 77 552 D8 000H,077H, OODH, 077H,00DH, 077H .. 000H,077H ; TH_B2
DO 77 553
09C4 DO 77 DD 77 DO 77 554 D8 OOOH,077H,OOOH,077H,OODH,077H , 8T_B2
09CA 18 18 18 18 18 18 555 D8 018H,018H,018H,018H,018H,018H,018H,018H ; 1H_83
18 18 556
0902 18 18 18 18 18 18 557 D8 018H,018H,018H,018H,018H,018H , BT_83
0908 18 18 18 18 18 18 558 D8 018H,018H,018H,018H,018H,018H,018H,OF8H ; TH_84
18 F8 559
09EO 18 18 18 18 18 18 560 D8 018H,018H,018H,018H,018H,018H ; BT_84
09E6 18 18 18 18 18 F8 561 D8 018H,018H,018H,018H,018H,OF8H,018H,OF8H ; TH_B5
18 F8 562
09EE 18 18 18 18 18 18 563 D8 018H,018H,018H,018H,018H,018H ; 8T_85
09F4 36 36 36 36 36 36 564 D8 036H, 036H, 036H, 036H, 036H, 036H, 036H, OF6H ; TH_86
36 F6 565
09rc 36 36 36 36 36 36 566 DB 036H,036H,036H,036H,036H,036H ; 8T_86
OA02 00 00 00 00 00 00 567 DB OOOH,OOOH,OOOH,OOOH~OOOH,OOOH,OOOH.OFEH ; TH_87
00 FE 568
OADA 36 36 36 36 36 36 569 DB 036H!0l.6H, 036H, 036H,036H, 036H

August 2, 1984 mM Enhanced Graphics Adapter 157

OA10 00 00 00 00 00 F8 570 DB 000H,OOOH,OOOH,OOOH,OOOH,OF8H,018H,OF8H ; TILB8
18 F8 571
OA18 18 18 18 18 18 18 572 08 018H,018H,018H.018H,018H,018H ; BT_B8
DAlE 36 36 36 36 36 F6 57' DB 036H, 036H, 036H,036H,036H, OF6H,006H,OF6H ; TH_B9
06 F6 574
OA26 36 36 36 36 36 36 575 D8 036H, 036H, 036H,036H,036H, 036H ; BT_B9
OA2C 36 36 36 36 36 36 576 DB 036H. 036H. 036H,036H,036H, 036H,036H,036H ; TH_BA
36 36 577
OA34 36 36 36 36 36 36 578 D8 036H,036H.036H,036H,036H,036H ; BT_BA
OA3A 00 00 00 00 00 FE 57. D8 OOOH, OOOH, OOOH,OOOH,OOOH,OFEH, 006H,OF6H ; TH_BB
06 F6 580
OA42 36 36 36 36 36 36
g~g~:g~g~:g~g~:g~g~:gig~:g~g~, 006H,OFEH ~~=:~
581 DB
OA48 36 36 36 36 36 F6 582 DB ;
06 FE 58'
OA50
0A56
00
36
36
00
36
FE
00 00 00 00
36 36 36 36
58.
585
586
08
D8 g~g~: g~g~:g~g~:g~~~: g~~~:g~g~, 036H,OFEH i ~~=:g
OASE
0A64
00
18
18
00
18
F8
00 00 00 00
18 18 18 F8
587
588
58.
DB
DB g~g~;g~g~;g~g~:g~g~:g~g~:g~g~,018H,OF8H ; ~~::~
ggg~;ggg~:ggg~:ggg~:ggg~:ggg~,OOOH,Of8H ; ~~::~
OA6C 00 00 00 00 00 00 590 DB
OA12 00 00 00 00 00 00 591 DB
00 F8 592
OA1A 18 18 18 18 18 18 59' DB 018H, 018H, 018H, 018H, 018H, 018H
594
OA80 18 18 18 18 18 18 595 DB 018H,018H,018H,018H,018H,018H,018H, 01 FH ; TH_CO
18 1F 596
OAB8
OA8E
00
18
18
00
18
FF
00 00 00 00
18 18 18 18
597
598
599
DB
DB g~g~:g~g~:g~g~:g~g~:g~g~:g~g~,018H,OFFH ; ~~=g~
OA96
OA9C
00
00
00
00
00
FF
00 00 00 00
00 00 00 00
600
601
602
DB
DB ggg~:ggg~:ggg~:ggg~:ggg~:ggg~,OOOH,OFFH ; ~~:g~
g~~~:g~~~:g~~~:g~~~:g~:~: g~~~,018H~01 FH ~~:g~
OAA4 18 18 18 18 18 18 60' DB
DAM 18 18 18 18 18 18 604 DB ;
18 1F 605
OAB2 18 18 18 18 18 18 606 DB 018H,018H,018H,018H,018H,018H ; BT_C3
OAB8 00 00 00 00 00 00 607 DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OFFH ; TH_C4
00
OACO
OAC6
00
18
FF
00
18
00 00 00 00
18 18 18 18
608
609
610
DB
DB
OOOH,OOOH~OOOH,OOOH,OOOH~OOOH BT_C4
018H,018H.018H,018H,018H,01BH,018H,OFFH ; TH_C5
;
18 FF 611
DACE 18 18 18 18 18 18 612 DB 018H,018H,018H,018H.018H.018H ; BT_C5
OA04 18 18 18 18 18 1F 613 DB 018H,O'8H~ 018H,018H, 018H.01 FH, 018H,01 FH ; TH_C6
18 1F 614
OAOC 18 18 18 18 18 18 615 DB 018H,018H,018H,018H,018H.018H ; BT_C6
OAE2 36 36 36 36 36 36 616 DB 036H,036H~ 036H,036H,036H~036H, 036H,037H ; TH_C7
36 37 617
OAEA 36 36 36 36 36 36 618 DB 036H,036H,036H,036H,036H,036H ; BT_C7
OAf0 36 36 36 36 36 31 619 DB 036H, 036H, 036H,036H,036H~037H, 030H,03FH ; TH_C8
30 3F 620
OAF8
OAFE
00
00
00
00
00 00 00 00
00 00 00 3F
621
622
DB
DB
OOOH,OOOH~OOOH,OOOH,OOOH.OOOH ;
BT_C8
OOOH, OOOH, OOOH,OOOH, OOOH, 03FH, 030H,031H ; TH_C9
30 37 62'
0806 36 36 36 36 36 36 624 DB 036H, 036H, 036H,036H, 036H,036H , BT_C9
OBOC 36 36 36 36 36 F7 625 DB 036H,036H,036H,036H,036H,0F7H,OOOH,OFFH ; TH_CA
00 FF 626
OB14 00 00 00 00 00 00 627
ggg~:ggg~:ggg~:ggg~:ggg~;g~~~,OOOH,OF1H ~ ~~:g~
DB
OB1A 00 00 00 00 00 FF 628 DB
00 F7 62'
OB22 36 36 36 36 36 36 6'0 DB 036H,036H,036H,036H.036H,036H , BT_CB
OB28 36 36 36 36 36 37 631 D8 036H, 036H,036H,036H, 036H,037H.030H. 031H ; TH_CC
30 37 6'2
gJg~: gJg~:g~g~:g~g~: gJg~;g~~~, OOOH, OFfH ~ ~~:gg
OB30 36 36 36 36 36 36 633 DB
OB36 00
00
00
fF
00 00 00 FF 6"
635
DB

OB3E 00 00 00 00 00 00 6'6
gg~~:gg~~:g~~~:gg~~:gg~~:g~~~,OOOH,OF7H ~ ~~:g~
DB
OB44 36 36 36 36 36 F1 6'7 DB
00 F1 6'8
gi:~:gi:~: gi~~:gi~~:gi:~;g~~~,OOOH,OFFH ~~=g~
OB4C 36 36 36 36 36 36
OB52 18 18 18 18 18 FF
6"
6'0
DB
DB i
00 FF 6"
OB5A
OB60
00
36 36
00 00 00 00 00
36 36 36 36
6.,
6'2
6 ••
DB

DB
OOOH, OOOH, OOOH, OOOH. OOOH, OOOH
036H, 036H. 036H,036H. 036H,036H.036H, OFFH ; TH_OO
36 FF 6'5
OB68 00 00 00 00 00 00
ggg~:ggg~:ggg~:ggg~:ggg~:g~~~,OOOH, OFFH ~~=g~
646 DB
OB6E 00 00 00 00 00 FF 6'7 DB ;
00 FF 6'8
OB76 18 18 18 18 18 16
gJg~: gJg~: gJg~:gJg~: gJg~:gJg~,OOOH, OFFH ~~:g~
6 •• DB
OB7C 00 00 00 00 00 00 650 DB ;
00 FF 651
gig~: gig~:g~g~:g~g~: g~g~:g~~~,036H. 03FH ~~:g~
OB84 36 36 36 36 36 36 652 DB
OB8A 36 36 36 36 36 36 653 DB ;
36 3F
OB92
OB98
00 00
18 18
00 00 00 00
18 18 18 IF
65.
655
656
DB
DB
OOOH,OOOH~OOOH,OOOH.OOOH.OOOH BT_03
018H,018H,018H,018H.018H,01FH,018H.OlFH ; TH_04
;
18 1F 657
OBAO
OBA6
00 00
00 00
18 1F
00 00 00 00
00 00 00 1F
658
65.
660
DB
DB ggg~:ggg~:ggg~:ggg~:ggg~:g~~~,018H,01FH ; ~~:g;
gJg~:gJg~:gJg~:gJg~: gJg~:gJg~,OOOH, 03FH ~~:g~
OBAE 18 18 18 18 18 18 661 DB
08B4 00 00 00 00 00 00 662 DB ;
00 3F 66'
OBBC 36 36 36 36 36 36 664 DB 036H,036H,036H,036H,036H,036H ; BT_06
OBC2 36 36 36 36 36 36 665 DB 036H,036H.036H,036H.036H,036H,036H,OFfH ; TH_07
36 FF 666
oeCA 36 36 36 36 36 36 667 DB 036H, 036H, 036H,036H, 036H,036H ; 8T_01
0800 18 18 18 18 18 FF 668 DB 018H,018H,018H,018H,018H,OFFH,018H,OFFH ; TH_DB
18 FF 66.
OBD8 18 18 18 18 18 18 670 DB 018H,018H,018H,018H,018H,018H ; BT_DB
OBOE 16 18 18 18 18 18 671 DB 018H,018H,018H,018H,018H,018H,018H,OF8H ; TH_09
18 f8 672
OBE6
OBEC
00 00
00 00
00 00 00 00
00 00 00 00
673
674
DB
DB
OOOH,OOOH~OOOH,OOOH~OOOH,OOOH
OOOH,OOOH~OOOH,OOOH.OOOH,OOOH,OOOH,OlFH·;
; 8T_09
TH_DA
00 1F 675
OBF4
OBFA
18 18
FF fF
FFFF
18 18 18 18
FF FF FF FF
676
677
678
08
DB
018H,018H,018H,018H.018H,018H
OFFH,OFfH,OFFH,OFFH~OFFH,OFFH,OFFH,OFFH ;; TH_DB
BT_OA

OC02 FF FF FF FF FF FF 67' DB OFFH,OFFH,OFFH,OFFH,OFFH,OFFH ; BT_DB

OC08 00 00 00 00 00 00 680 DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OFFH ; TH_DC
00 FF 681
OC10 FF FF FF FF FF FF 682 DB OfFH,OFFH,OFFH,OFFH,OFFH,OffH ; BT_DC
OC16 FO FO FO FO FO FO 68' DB OfOH,OfOH,OFOH,OfOH,OFOH,OfOH,OFOH,OfOH ; TH_DD
FO FO 68'
OC1E FO FO FO FO fO FO 6B5 DB OFOH.OFOH.OFOH.OfOH,OFOH,OFOH , BT_DD
OC24 OF OF OF OF OF OF 686 DB OOFH,OOFH,OOFH,OOFH,OOFH,OOFH,OOFH,OOFH ; TH_OE
OF OF 687
OC2C
OC32
OF OF
FF FF
FF 00
OF OF OF OF
FF FF FF FF
688
6B9
6'0
DB
DB gn~:g~~~:g~~~:g~~~:g~~~:g~~~,oFFH,OOOH ; ~~=g~
OC3A 00 00 00 00 00 00 6" DB DOOH, OOOH, OOOH~ OOOH, OOOH~ OOOH
OC40 00 00 00 00 00 16
DC D8
6.,
6,2
6 ••
DB OOOH~ OOOH, OOOH, OOOH, OOOH, 076H, OOCH, ODeH ; TH_EO
OC48 DB DC 16 00 00 00 695 DB OD8H. ODCH, 076H, OOOH, OOOH, OOOH

158 IBM Enhanced Grapbics Adapter August 2, 1984

OC4E 00 00 00 00 7C C6 696 DB 000H,OOOH,OOOH,OOOH,07CH,OC6H,OFCH,OC6H ; TH_E1
FC c6 697
OC56 C6 FC CO CO 40 00 696 DB OC6H,OFCH,OCOH,OCOH,040H,OOOH ; BT_El
OC5C 00 00 FE C6 C6 CO 699 DB 000H,OOOH,OFEH,OC6H,OC6H,OCOH,OCOH,OCOH ; TH_E2
CO CO 700
OC64 CO CO CO 00 00 00 701 DB OCOH, OCOH, OCOH, OOOH, OOOH, OOOH BT E2
OC6A 00 00 00 00 FE 6C 702 DB OOOH, OOOH, OOOH, OOOH, OFEH, 06CH, 06CH, 06CH TH=E3
6C 6C 703
OC72 6C 6C 6C 00 00 00 704 DB 06CH, 06CH, 06CH, OOOH, OOOH, OOOH 8T_E3
OC78 00 00 FE C6 60 30 705 DB OOOH, OOOH, OFEH, OC6H, 060H, 030H, 018H, 030H TH_E4
18 30 706
OC80 60 C6 FE 00 00 00 707 DB 060H,OC6H,OFEH,000H,000H,000H , BT E4
OC86 00 00 00 00 00 7E 706 06 OOOH, OOOH, OOOH, OOOH, OOOH, 07EH, OD8H, 008H ; TH=E5
08 08 709
OC8E 08 06 70 00 00 00 710 DB OD8H, 008H, 070H, OOOH, OOOH, OOOH ; BT E5
OC94 00 00 00 00 66 66 711 DB 000H,000H,000H,000H,066H,066H,066H,066H ; TH=E6
66 66 712
OC9C 7C 60 60 CO 00 00 713 DB 07CH, 060H, 060H, OCOH, OOOH, OOOH BT_E6
OCA2 00 00 00 00 76 DC 714 DB OOOH, OOOH, OOOH, OOOH, 076H,ODCH, 018H, 01 8H TH_E7
18 18 715
OCM 18 16 18 00 00 00 716 DB 018H, 018H, 018H, OOOH, OOOH,OOOH BT_E7
aceD 00 00 7E 18 3C 66 717 DB OOOH, OOOH, 07EH, 018H, 03CH, 066H, 066H, 066H TH_EB
66 66 716
OCB8 3C 18 7E 00 00 00 719 DB 03CH,018H,07£H,000H,000H,000H , BT_E8
OCBE 00 00 38 6C C6 C6 720 DB 000H,000H,038H,06CH,OC6H,OC6H,OFEH,OC6H ; TH_E9
FE C6 721
OCC6 C6 6C 38 00 00 00 722 DB OC6H, 06CH, 038H, OOOH, OOOH, OOOH BT E9
OCCC 00 00 38 6C C6 C6 723 DB OOOH, OOOH, 038H, 06CH, OC6H, OC6H, OC6H, 06CH TH=EA
c6 6c 724
OC04 6C 6C EE 00 00 00 725 DB 06CH, 06CH, OEEH, OOOH, OOOH, OOOH BT_EA
OCOA 00 00 1E 30 18 DC 726 DB OOOH, OOOH, 01 EH, 030H, 018H, OOCH, 03EH, 066H TH_EB
3£ 66 727
OCE2 66 66 3C 00 00 00 726 DB 066H,066H,03CH,000H,000H,000H , BT £B
OCE8 00 00 00 00 00 7E 729 DB 000H,000H,OOOH,000H,000H,07EH,00BH,00BH ; nCEC
DB 03 730
OCFO 7E 00 00 00 00 00 731 06 07EH, OOOH, OOOH, OOOH, OOOH, OOOH BT EC
OCF6 00 00 03 06 7£ DB 732 DB OOOH, OOOH, 003H. 006H, 07EH, OOBH, OOBH, OF3H TH=EO
DB F3 733
DC FE 7E 60 CO 00 00 00 734 DB 07EH,060H,OCOH,OOOH,000H,000H ; BT ED
0004 00 00 1C 30 60 60 735 DB OOOH, OOOH, 01 CH, 030H, 060H, 060H, 07CH, 060H ; TH=EE
7C 60 736
OOOC 60 30 lC 00 00 00 737 DB 060H,030H,01CH,000H,OOOH,OOOH , BT_EE
0012 00 00 00 7C C6 C6 736 DB OOOH, OOOH, OOOH, 07CH, OC6H,OC6H, OC6H, OC6H ; TH_EF
C6 C6 739
OOlA C6 C6 C6 00 00 00 740 DB OC6H, OC6H, OC6H, OOOH, OOOH, OOOH
741
0020 00 00 00 FE 00 00 742 DB OOOH,OOOH,OOOH,OFEH,OOOH,OOOH,OFEH,OOOH ; TH_FO
FE 00 743
0028 00 FE 00 00 00 00 744 DB OOOH, OFEH, OOOH, OOOH, OOOH, OOOH BT_FO
002E 00 00 00 16 16 7E 745 DB OOOH, OOOH, OOOH, 018H, 01 8H, 07EH, 018H, 01 8H TH_Fl
18 18 746
0036 00 00 fF 00 00 00 747 DB OOOH, OOOH, OFFH, OOOH, OOOH, OOOH BT_Fl
003C 00 00 30 18 DC 06 746 DB OOOH, OOOH, 030H, 018H, 00CH,006H, OOCH, 018H TH_F2
DC 18 749
0044 30 00 7E 00 00 00 750 DB 030H, OOOH, 07EH, OOOH, OOOH, OOOH BT_F2
OD4A 00 00 DC 18 30 60 751 DB OOOH, OOOH, OOCH, 018H, 030H, 060H, 030H, 01 8H TH_F3
30 18 752
0052 DC 00 7E 00 00 00 753 DB OOCH, OOOH, 07£H, OOOH, OOOH, OOOH BT_F3
0058 00 00 DE 1B 1B 18 754 DB OOOH, OOOH, OOEH, 01 BH, 01 BH, 018H, 018H, 01 8H TH_F4
18 18 755
0060 18 18 18 16 18 18 756 DB 018H,018H,018H,018H,018H,018H BT F4
0066 18 18 18 18 18 18 757 DB 018H, 018H, 018H, 018H, 018H, 018H, 018H, 018H TH=F5
18 18 756
006E 08 08 70 00 00 00 759 06 008H, 008H, 070H, OOOH, OOOH, OOOH BT_f5
0074 00 00 00 18 18 00 760 DB OOOH, OOOH, OOOH, 018H, 018H, OOOH, 07EH, OOOH TH_F6
7£ 00 761
007C 18 18 00 00 00 00 762 DB 018H,018H,000H,000H,000H,000H BT F6
0082 00 00 00 00 76 DC 763 DB OOOH, OOOH, OOOH, OOOH, 076H, OOCH, OOOH, 076H TH=F7
00 76 764
008A DC 00 00 00 00 00 765 DB ODCH,OOOH,OOOH,OOOH,OOOH,OOOH , BT f7
0090 00 38 6C 6C 38 00 766 06 OOOH, 038H, 06CH, 06CH. 038H, OOOH, OOOH, OOOH ; TH=f8
00 00 767
0098 00 00 00 00 00 00 766 06 OOOH, OOOH, OOOH, OOOH, OOOH, OOOH BT_F8
009E 00 00 00 00 00 00 769 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, 018H, 018H TH_F9
18 18 770
00A6 00 00 00 00 00 00 771 06 OOOH, OOOH, OOOH, OOOH, OOOH, OOOH BT_F9
OOAC 00 00 00 00 00 00 772 DB OOOH, OOOH, OOOH, OOOH,OOOH, OOOH, OOOH, 01 8H TH_FA
00 18 773
0084 00 00 00 00 00 00 774 DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH , BT_FA
OOBA 00 OF OC DC DC DC 775 DB OOOH, OOFH, OOCH, OOCH, OOCH, OOCH, OOCH, OECH ; TH_FB
DC EC 776
00C2 6C 3C 1C 00 00 00 777 DB 06CH,03CH,OlCH,000H,000H,000H , BT_FB
OOC8 00 08 6C 6C 6C 6C 776 DB OOOH, OD8H, 06CH, 06CH, 05CH, 06CH, 06CH, OOOH ; TH_FC
6C 00 779
0000 00 00 00 00 00 00 760 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH BT FC
0006 00 70 08 30 60 C8 761 DB OOOH, 070H, 008H, 030H,060H, OC8H, OF8H, OOOH TH=FO
F8 00 762
ODOE 00 00 00 00 00 00 763 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH , BT_FO
00E4 00 00 00 00 7C 7C 764 DB 000H,000H,000H,000H,07CH,07CH,07CH,07CH ; TH_FE
7C 7C 765
OOEC 7C 7C 00 00 00 00 766 DB 07CH, 07CH, OOOH, OOOH, OOOH, OOOH , BT_FE
00F2 00 00 00 00 00 00 767 DB OOOH, OOOH, OOOH, OOOH,OOOH, OOOH, OOOH, OOOH ; TH_FF
00 00 766
OOFA 00 00 00 00 00 00 769 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH BT_FF
OEOO 790 CODE ENDS
791 END

1 PAGE,120
2 SUBTTL MONOCHROME CHARACTER GENERATOR - ALPHA SUPPLEMENT
0000 3 CODE SEGMENT PUBL I C
4 PUBL I C CGMN_FOG
0000 5 CGMNJOG LABEL BYTE
6
7 STRUCTURE OF TH 1S FILE
6 DB XXH WHERE xx IS THE HEX CODE FOR THE FOLLOWING CHAR
9 DB [BYTES 0 - 13 OF THAT CHARACTER J
10
11 DB OOH INDICATES NO MORE REPLACEMENTS TO BE DONE
12
13
0000 10 14 DB 010H
0001 00 00 00 00 24 66 15 DB OOOH, OOOH, OOOH, 000H,024H, 066H, OFFH, 066H TH_' 0
FF 66 16
0009 24 00 00 00 00 00 17 DB 024H, OOOH, OOOH, OOOH,OOOH, OOOH , BT_l0
OOOF 22 16 DB 022H ;
0010 00 63 63 63 22 00 19 DB 000H,063H,063H,063H,022H,000H,000H,000H; TH_22 "
00 00 20
0018 00 00 00 00 00 00 21 DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH BT_22 "
~OlE 2B 22 DB 02BH ,
001F 000000 18 18 18 23 DB 000H,OOOH,OOOH,018H,018H,018H,OFFH,018H ; TH_2B +
FF 18 24
0027 18 18 00 00 00 00 25 DB 018H, 018H, OOOH, OOOH,OOOH, OOOH BT~2B +
0020 20 26 DB 020H
002E 00 00 00 00 00 00 27 DB OOOH,OOOH,OOOH,OOOH,OOOH,OODH,OFFH,OOOH TH_20-
FF 00 26

August 2, 1984 IBM Enhanced Graphics Adapter 159

0036 00 00 00 00 00 00 29 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH BT_20 -
003C 40 30 DB 040H
0030 00 00 C3 E7 FF DB 31 DB OOOH, OOOH, OC3H, OE7H, OFFH, OOBH, OC3H, OC3H ; TH_40 M
C3 C3 32
0045 C3 C3 C3 00 00 00 33 DB OC3H, OC3H, OC3H, OOOH, OOOH, OOOH BT_40 M
004B 54 34 DB 054H
004C 00 00 FF DB 99 18 35 DB 000H,000H,OFFH,00BH,099H,018H,018H,018H ; TH_54 T
18 18 36
0054 18 18 3C 00 00 00 37 DB 018H, 018H, 03CH, OOOH, OOOH, OOOH ; BT_54 T
005A 56 3B DB 056H
005B 00 00 C3 C3 C3 C3 39 DB OOOH, OOOH, OC3H, OC3H, OC3H, OC3H, OC3H, OC3H ; TH_56 V
C3 C3 40
0063 66 3C 18 00 00 00 41 DB 066H, 03CH, 018H, OOOH, OOOH, OOOH BT_56 V
0069 57 42 DB 057H
006A 00 00 C3 C3 C3 C3 43 DB OOOH,OOOH, OC3H, OC3H, OC3H, OC3H, ODBH, OOBH ; TH_57 W
DB DB 44
0072 FF 66 66 00 00 00 45 DB OFFH, 066H, 066H, OOOH, OOOH, OOOH BT_57 W
0078 58' 46 DB Os8H
0079 00 00 C3 C3 66 3C 47 DB OOOH, OOOH, OC3H, OC3H, 066H, 03CH, 018H, 03CH ; TH_58 X
18 3C 4B
0081 66 C3 C3 00 00 00 49 DB 066H,OC3H, OC3H, OOOH, OOOH, OOOH BT_58 X
0087 59 50 DB Os9H
0088 00 00 C3 C3 C3 66 51 DB OOOH, OOOH, OC3H, OC3H, OC3H, 066H, 03CH,018H ; TH_59 Y
3C 18 52
0090 18 18 3C 00 00 00 53 DB a 18H, 01 8H, 03CH, OOOH, OOOH, OOOH BT_59 Y
0096 5A 54 DB OsAH
0097 00 00 fF C3 86 DC 55 DB OOOH, OOOH, OFFH, OC3H,086H, OOCH, 018H, 030H ; TH_5A Z
18 30 56
009F 61 C3 FF 00 00 00 57 DB 061 H, OC3H, OFFH, OOOH, OOOH, OOOH BT_5A Z
OOAs 60 58 DB 060H
00A6 00 00 00 00 00 E6 59 DB OOOH, OOOH, OOOH, OOOH, OOOH, OE6H, OFFH,OOBH ; TH_6D L.C. M
FF DB 60
OOAE DB DB 08 00 00 00 61 DB ODBH, ODBH, OOBH, OOOH, OOOH, OOOH BT_60 L.C. M
0084 76 62 DB 076H
0085 00 00 00 00 00 C3 63 DB OOOH, OOOH, OOOH, OOOH, OOOH, OC3H, OC3H, OC3H ; TH_76 l.C. V
C3 C3 64
OOBO 66 3C 18 00 00 00 65 DB 066H, 03CH, 018H, OOOH,OOOH, OOOH 8T_76 L.C. V
00C3 77 66 DB 077H
00C4 00 00 00 00 00 C3 67 DB OOOH, OOOH, OOOH, OOOH, OOOH, OC3H, OC3H,ODBH ; TH_77 L.C. W
C3 DB 6B
OOCC DB FF 66 00 00 00 69 DB OOBH, a FFH, 066H, OOOH, OOOH, OOOH BT_77 l.C. W
0002 91 70 DB 091H
0003 00 00 00 00 6E 3B 71 DB OOOH, OOOH, OOOH, OOOH, 06EH, 03BH, 01 BH, 07EH ; TH_91
1B 7E 72
00 DB 08 DC 77 00 00 00 73 DB 008H, OOCH, 077H, OOOH, OOOH, OOOH 8T_91
OOEl 9B 74 DB 09BH
00£2 00 18 18 7E C3 CO 75 DB OOOH, 018H, 018H, 07EH, OC3H, OCOH, OCOH, OC3H ; TH_9B
CO C3 76
OOEA 7E 18 18 00 00 00 77 DB 07£H, 018H, 018H, OOOH, OOOH, OOOH BT_9B
OOFO 90 7B DB 090H
OOFl 00 00 C3 66 3C 18 79 DB OOOH, OOOH, OC3H, 066H, 03CH, 018H, OFFH, 018H ; TH_90
fF 18 80
00F9 FF 18 18 00 00 00 Bl DB OFFH, 01 8H, 018H, OOOH, OOOH, OOOH BT_90
DOFF 9' B2 DB 09£H
0100 00 FC 66 66 7C 62 B3 DB OOOH, OFCH, 066H, 066H, 07CH, 062H, 066H, 06FH ; TH_9E
66 6F 84
0108 66 66 F3 00 00 00 85 08 066H, 066H, Of3H, OOOH, OOOH, OOOH BT_9E
010E f1 86 08 OF1H
OlaF 00 00 18 18 18 FF 87 08 OOOH,OOOH, 01 8H, 018H, 018H, OffH, 018H, 018H ; THJl
18 18 88
0117 18 00 fF 00 00 00 89 DB 018H, OOOH, OFFH, OOOH, OOOH, OOOH BTJ1
0110 '6 90 08 O~H ;
011E 00 00 18 18 00 00 91 DB OOOH, OOOH, 018H, 018H, OOOH, OOOH, OFFH, OOOH ; THJ6
fF 00 92
0126 00 18 18 00 00 00 93 DB OOOH, 018H, 018H, OOOH, OOOH, OOOH ; BT_F6
012C 00 94 08 OOOH ; NO MORE
0120 95 CODE ENDS
96 END

1 PAGE,120
2 SUBTTl D,OUBlE DOT CHARACTER GENERATOR
0000 3 CODE SEGMENT PUBLIC
4 PUBLI C CGoOOT,INT_1F_l
0000 5 CGODOT LABEL BYTE
6 DOUBLE DOT
0000 00 00 00 00 00 00 7 DB OOOH, OOOH, OOOH,OOOH, OOOH, OOOH, OOOH, OOOH ; 0_00
00 00 8
0008 7E 81 A5 81 BD 99 9 DB 07EH, 081H, DASH, 081 H, OBDH, 099H, 081 H, 07EH ; 0_01
81 7E 10
0010 7E FF DB FF C3 £7 11 08 07EH, OFFH, OOBH, OFFH, OC3H, OE7H, OFFH, 07EH ; 0_02
FF 7E 12
0018 6C FE FE FE 7C 38 13 08 06CH, OFEH, OFEH, OFEH, 07CH, 038H, 010H, OOOH ; 0_o3
10 00 14
0020 10 38 7C FE 7C 38 15 010H, 038H, 07CH, OFEH, 07CH, 036H, 010H, OOOH ; 0_o4
10 00 16
0028 38 7C 38 FE FE 7C 17 08 038H, 07CH, 038H, OFEH, OFEH, 07CH, 038H, 07CH ; o_05
38 7C 18
0030 10 10 38 7C FE 7C 19 08 010H, 01 OH, 038H, 07CH, OFEH, 07CH, 038H, 07CH ; 0_06
38 7C 20
0038 00 00 18 3C 3C 18 21 08 OOOH, OOOH, 018H, 03CH, 03CH, 018H, OOOH, OOOH ; 0_07
00 00 22
0040 FF FF E7 C3 C3 E7 23 08 OFFH, OFFH, 0£7H, OC3H, OC3H, OE7H, OFFH, OFFH ; 0_08
FF FF 24
0048 00 3C 66 42 42 66 25 DB OOOH, 03CH, 066H, 042H,042H,066H, 03CH, OOOH ; o_09
3c 00 26
0050 fF C3 99 Bo BD 99 27 DB OFFH, OC3H, 099H, OBOH,OBOH, 099H, OC3H, OFFH ; O_OA
C3 FF 2B
0058 OF 07 Of 70 CC CC 29 08 OOFH, 007H, OOFH, 07oH, OCCH, DCCH, DCCH, 078H ; O_DB
CC 78 30
0060 3C 66 66 66 3C 18 31 08 03CH, 066H, 066H, 066H, 03CH, 018H, 07EH, 018H ; O_OC
7E 18 32
0068 3F 33 3F 30 30 70 33 DB 03 FH, 033H, 03FH,030H, 030H, 070H, OFOH, OEOH ; 0_00
FO EO 34
0070 7F 63 7F 63 63 67 35 08 07FH, 063H, 07FH, 063H, 063H, 067H, OE6H, OCOH ; O_OE
E6 CO 36
0078 99 5A 3C E7 E7 3C 37 08 099H, OsAH, 03CH, OE7H, OE7H, 03CH, OsAH, 099H ; O_OF
SA 99 38
39
0080 80 EO F8 FE F8 EO 40 DB 080H, OEOH, OF8H,OFEH, OF8H, OEOH, 080H, OOOH ; 0_10
80 00 41
0088 02 DE 3E FE 3E OE 42 DB 002H,OOEH, 03EH,OFEH, 03EH, OO£H, 002H, OOOH ; 0_11
02 00 43
0090 18 3C 7E 18 18 7£ 44 DB 018H, 03CH, 07£H,018H, 018H, 07EH, 03CH, 018H ; 0_12
3C 18 45
0098 66 66 66 66 66 00 46 08 066H, 066H, 066H. 066H, 066H. OOOH, 066H, OOOH ; 0_13
66 00 47
OOAO 7F DB DB 7B 1B lB 48 08 07FH, OOBH, ODBH, 07BH, 01 BH, 01 BH, 01 BH, OOOH ; o_14
lB 00 49
00A8 3E 63 38 6C 6C 38 50 08 03£H,063H, 038H,06CH,06CH,038H, OCCH. 078H ; 0_15
CC 78 51
OOBO 00 00 00 00 7E 7E 52 DB 000H,OOOH,OOOH,OOOH,07EH,07EH,07EH,000H ; 0_16
7E 00 53
00B8 18 3C 7E 18 7E 3C 54 DB 018H,03CH,07EH,018H,07£H,03CH,018H,OFFH ; 0_17
18 FF 55
OOCO 18 3C 7E 18 18 18 56 08 018H,03CH,07EH,018H,018H,018H,018H,OOOH ; 0_18

160 IBM Enhanced Graphics Adapter August 2, 1984

 18 00 57
00C8 18 18 18 18 7E 3C 58 DB 018H, 01SH, 018H, 01SH, 07EH, 03CH, 018H, OOOH ; 0_19
18 00 5'
0000 00 18 DC FE DC 18 60 DB OOOH, 018H, OOCH, OFEH, OOCH, 018H, OOOH, OOOH ; 0_1A
00 00 61
0008 00 30 60 FE 60 30 62 DB OOOH, 030H, 060H, OFEH, 060H, 030H, OOOH, OOOH ; 0_18
00 00 63
ODED 00 00 CO CO CO FE 64 DB OOOH, OOOH, OCOH, OCOH, OCOH, OFEH, OOOH, OOOH ; D_1C
00 00 65
00E8 00 24 66 FF 66 24 66 DB OOOH, 024H, 066H, OFFH, 066H, 024H, OOOH,OOOH : 0_10
00 00 67
OOFO 00 18 3C 7E FF FF 68 DB OOOH, 018H, 03CH, 07EH, OFFH, OFFH, OOOH, OOOH ; O_lE
00 00 6.
00F8 00 FF FF 7E 3C 18 70 DB OOOH, OFFH, OFFH, 07EH, 03CH, 018H, OOOH, OOOH ; O_1F
00 00 71
72
0100 00 00 00 00 00 00 73 DB OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ; SP 0_20
00 00 74
0108 30 78 78 30 30 00 75 DB 030H, 078H, 078H, 030H, 030H, OOOH, 030H, OOOH ; I 0_21
30 00 76
0110 6C 6C 6C 00 00 00 77 DB 06CH, 06CH, 06CH, OOOH, OOOH, OOOH, OOOH, OOOH ; 0_22
00 00 78
0118 6C 6C FE 6C FE 6C 7. DB 06CH, 06CH, OFEH, 06CH,OfEH, 06CH, 06CH, OOOH ; # 0_23
6C 00 80
0120 30 7C CO 78 DC F8 81 OB 030H,07CH, OCOH, 078H, OOCH, OF8H, 030H, OOOH ; S 0_24
30 00 82
0128 00 C6 CC 18 30 66 83 DB OOOH, OC6H, OCCH, 018H, 030H, 066H, OC6H, OOOH ; PER CENT 0_25
C6 00 84
0130 38 6C 38 76 DC CC 85 DB 038H, 06CH, 038H, 076H, ODCH, OCCH, 076H, OOOH ; & 0_26
76 00 86
0138 60 60 CO 00 00 00 87 DB 060H, 060H, OCOH, OOOH, OOOH, OOOH, OOOH, OOOH ; 0_27
00 00 88
0140 18 30 60 60 60 30 8. DB 018H, 030H, 060H, 060H, 060H,030H, 018H, OOOH : ( 0_28
18 00 '0
0148 60 30 18 18 18 30 060H, 030H, 018H, 018H, 018H, 030H, 060H, OOOH ; 1 0_29

0150
60
00
00
66 3C FF 3C 66
"
'2
.3
DB

OB 000H,066H, 03CH, OFFH, 03CH, 066H, OOOH, OOOH ; * 0_2A

00 00 .4
0158 00 30 30 FC 30 30 .5 OB OOOH, 030H, 030H, OFCH, 030H, 030H, OOOH, OOOH : + 0_2B
00 00 96
0160 00 00 00 00 00 30 .7 DB OOOH, OOOH, OOOH,OOOH, OOOH, 030H, 030H, 060H : 0_2C
30 60 .8
0168
0170
00
00
00
00
00
00
00 FC 00 00
00 00 00 30
••
TOO
101
DB

DB
OOOH, OOOH, OOOH, OFCH, OOOH,OOOH,OOOH, OOOH ;
OOOH, OOOH, OOOH, OOOH, OOOH, 030H, 030H, OOOH ;
- 0_20
0_2E
30 00 102
0178 06 DC 1830 60 CO 103 DB 006H, OOCH, 018H, 030H, 060H, OCOH, 080H, OOOH ; I 0_2F
80 00 104
105
0180 7C C6 CE DE F6 E6 106 DB 07CH,OC6H, OCEH, OOEH, OF6H, OE6H, 07CH, OOOH ; o 0_30
7C 00 107
0188 30 70 30 30 30 30 108 DB 030H, 070H, 030H, 030H, 030H, 030H, 0 FCH, OOOH ; 1 0_31
FC 00 10'
0190 78 CC DC 38 60 CC 110 DB 078H, OCCH, OOCH, 038H, 060H, OCCH, OFCH, OOOH : 2 0_32
FC 00 111
0198 78 CC DC 38 DC CC 112 DB 078H, OCCH, OOCH, 038H, OOCH, OCCH, 078H, OOOH : 3 0_33
78 00 113
01AO lC 3C 6C CC FE DC 114 DB 01CH, 03CH, 06CH, OCCH, OFEH, OOCH, 01 EH, OOOH ; 4 0_34
lE 00 115
01A8 FC CO F8 DC DC CC 116 DB OFCH, OCOH, OF8H, OOCH, OOCH, OCCH, 078H, OOOH ; 5 0_35
78 00 117
01BO 38 60 CO F8 CC CC 118 DB 038H, 060H, OCOH, OF8H, OCCH, OCCH, 078H, OOOH ; 6 0_36

01B8
78
FC
30
00
CC
00
DC 18 30 30 "'
120
121
DB OFCH,OCCH, OOCH, 018H, 030H,030H,030H, OOOH ; 7 0_37
01CO 78 CC CC 78 CC CC 122 DB 078H, OCCH, OCCH, 078H, OCCH, OCCH,078H, OOOH ; 8 0_38
78 00 123
01C8 78 CC CC 7C DC 18 124 DB 078H, OCCH, OCCH, 07CH, OOCH, 018H, 070H, OOOH ; 9 0_39
0100
70
00
00
30 30 00 00 30
125
126 DB OOOH, 030H, 030H, OOOH, OOOH, 030H, 030H, OOOH ; , O_3A
30 00 127
0108 00 30 30 00 00 30 128 DB 000H,030H, 030H, OOOH, OOOH, 030H,030H, 060H ; ; 0_38
30 60 12,
OlEO 18 30 60 CO 60 30 130 DB 018H,030H, 060H, OCOH, 060H, 030H, 018H, OOOH ; < 0_3C
18 00 131
01E8 00 00 FC 00 00 FC 132 DB OOOH, OOOH, 0 FCH, OOOH, OOOH, OFCH, OOOH, OOOH ; '" 0_30
00 00 133
OlFO 60 30 180C1830 134 DB 060H,030H, 018H, OOCH, 018H, 030H, 060H, OOOH ; > 0_3E
60 00 135
01 F8 78 CC DC 18 30 00 136 DB 078H,OCCH, OOCH, 018H, 030H, 000H,030H, OOOH ; ? 0_3F
30 00 137
138
0200 7C C6 DE DE DE CO 13' DB 07CH, OC6H, ODEH, OOEH, ODEH, OCOH, 078H, OOOH ; @ 0_40
78 00 140
0208 30 78 CC CC FC CC 141 030H, 078H, OCCH, OCCH, OFCH, OCCH, OCCH, OOOH ; A 0_41
0210
CC
FC
FC
00
66
00
66 7C 66 66
142
143
144
DB ° °
FCH, 066H, 066H, 07CH, 066H, 066H, FCH, OOOH ; 8 0_42
0218 3C 66 CO CO CO 66 145 DB 03CH, 066H, OCOH,OCOH, OCOH, 066H, 03CH, OOOH : C 0_43
3C 00 146
0220 F8 6C 66 66 66 6C 147 DB OF8H, 06CH,066H,066H, 066H, 06CH, OF8H, OOOH ; o 0_44
F8 00 148
0228 FE 62 68 78 68 62 14. DB OFEH,062H,068H, 078H, 068H, 062H, OFEH, OOOH : E 0_45
FE DO 150
0230 FE 62 68 78 68 60 151 DB OFEH, 062H,068H, 078H, 068H, 060H, OFOH, OOOH : F 0_46
FO 00 152
0238 3C 66 CO CO CE 66 153 DB 03CH, 066H,OCOH, OCOH, OCEH, 066H, 03EH, OOOH : G 0_47
3E 00 154
0240 CC CC CC FC CC CC 155 OCCH, OCCH,OCCH, OFCH, OCCH, aCCH, OCCH, OOOH ; H 0_48
CC 00 156
0248 78 30 30 30 30 30 157 DB 078H, 030H,030H,030H, 030H, 030H, 078H, OOOH ; I 0_49
78 00 158
0250 lE DC OC DC CC CC 15. DB 01 EH, OOCH, OOCH, OOCH, OCCH, OCCH, 078H, OOOH ; J 0_4A
78 00 160
0258 E6 66 6C 78 6c 66 161 DB OE6H, 066H, 06CH, 078H, 06CH,066H, OE6H, OOOH ; K 0_4B
E6 00 162
0260 FO 60 60 60 62 66 163 DB OFOH, 060H, 060H, 060H, 062H, 066H, OFEH, OOOH ; L 0_4C
FE 00 164
0268 C6 EE FE FE D6 c6 165 DB OC6H, OEEH, OFEH, OFEH, 006H, OC6H, OC6H, OOOH ; H 0_40
C6 00 166
0270 C6 E6 F6 DE CE C6 167 08 OC6H, OE6H, 0 F6H, OOEH, OCEH, OC6H, OC6H, OOOH ; N 0_4E
C6 00 168
0278 38 6c c6 C6 C6 6C 169 08 038H, 06CH, OC6H, OC6H, OC6H, 06CH, 038H, OOOH ; a 0_4F
38 00 170
171
0280 FC 66 66 7C 60 60 172 DB OFCH, 066H, 066H, 07CH, 060H, 060H, OFOH, OOOH ; PO_50
FO 00 173
0288 78 CC CC CC DC 78 174 DB 078H,OCCH,OCCH,OCCH, OOCH, 078H, 01 CH, OOOH ; Q 0_51
lC 00 175
0290 FC 66 66 7e 6C 66 176 DB OFCH, 066H,066H,07CH, 06CH, 066H,OE6H, OOOH ; R 0_52
E6 00 177
0298 78 CC EO 70 1C CC 178 DB 078H,OCCH,OEOH,070H, 01CH, OCCH, 078H, OOOH ; SO_53
78 00 17'
02AO FC 84 30 30 30 30 180 DB OFCH, OB4H,030H,030H, 030H, 030H,078H, OOOH ; TO_54
78 00 181
02A8 CC CC CC CC CC CC 182 DB OCCH,OCCH,OCCH,OCCH. OCCH, OCCH,OFCH, OOOH ; U 0_55

August 2, 1984 IBM Enhanced Graphics Adapter 161

 FC 00 183
02BO CC CC CC CC CC 78 18. 08 OCCH, OCCH, OCCH, OCCH, OCCH, 078H, 030H,OOOH ; V 0_56
30 00 185
02B8 C6 C6 c6 06 FE EE 186 DB OC6H, OC6H,OC6H, 006H, OFEH, OEEH, OC6H,000H ; W 0_57
C6 00 187
02CO C6 C6 6C 38 38 6C 188 DB OC6H, OC6H, 06CH, 038H, 038H, 06CH, OC6H, OOOH ; X 0_58
C6 00 189
02C8 CC CC CC 78 30 30 190 DB OCCH,OCCH,OCCH,078H,030H,030H,078H,000H ; YO_59
78 00 191
0200 FE C6 8C 18 32 66 192 DB OFEH,oc6H,08CH,018H,032H,066H,OFEH,000H ; Z 0_5A
FE 00 193
0208 78 60 60 60 60 60 19. DB 078H, 060H, 060H, 060H, 060H, 060H,078H, OOOH ; ( 0_5B
78 00 195
02EO CO 60 30 18 OC 06 196 DB OCOH, 060H, 030H, 01 8H,00CH, 006H, 002H, OOOH ; BACKSLASH 0_5C
02 00 197
02E8 78 18 18 18 18 18 198 OB 078H,018H,018H,018H,018H,018H,078H,000H ; J D._50
78 00 199
02fO 10 38 6c c6 00 00 200 DB 010H,038H,06CH,OC6H,000H,000H,000H,000H ; CIRCUMfLEX o_5£
00 00 201
02f8 00 00 00 00 00 00 202 DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OFFH ; _ 0_5F
00 Ff 203
20.
0300 30 30 18 00 00 00 205 OB 030H, 030H, 018H, OOOH, OOOH, OOOH, OOOH, OOOH ; • 0_60
00 00 206
0308 00 00 78 DC 7C CC 207 DB OOOH, OOOH, 078H, OOCH, 07CH, OCCH, 076H, OOOH ; LOWER CASE A 0_61
76 00 208
0310 EO 60 60 7C 66 66 209 OB OEOH, 060H, 060H, 07CH, 066H, 066H, OOCH, OOOH ; L. C. B 0_62
DC 00 210
0318 00 00 78 CC CO CC 211 DB OOOH,000H,078H,OCCH,OCOH,OCCH,078H,000H ; L.C. C 0_63
0320
78
lC
76
00
DC
00
OC 7C CC CC
212
213
21'
DB 01CH,OOCH,00CH,07CH,OCCH,OCCH,076H,000H ; L.C. ° 0_64
0328 00 00 78 CC FC CO 215 DB 000H,000H,078H,OCCH,OfCH,OCOH,078H,000H ; L.C. E o_65
78 00 216
0330 38 6C 60 FO 60 60 217 DB 038H, 06CH, 060H, OFOH, 060H, 060H,OFOH, OOOH ; L. C. F 0_66
FO 00 218
0338 00 00 76 CC CC 7C 219 DB 000H,000H,076H,oecH,ocCH,07CH,00CH,OF8H ; L.C. G 0_67
DC f8 220
0340 EO 60 6C 76 66 66 221 DB OEOH, 060H, 06CH, 076H, 066H, 066H, OE6H, OOOH ; L. C. H o_68
E6 00 222
0348 30 00 70 30 30 30 223 DB 030H, 000H,070H, 030H, 030H, 030H, 078H, OOOH ; L. C. I 0_69
78 00 22'
0350 DC 00 OC OC DC CC 225 DB 00CH,000H,00CH,00CH,00CH,OCCH,OCCH,078H ; L.C. J D_6A
CC 78 226
0358 EO 60 66 6C 78 6C 227 DB OEOH, 060H, 066H, 06CH, 078H, 06CH,OE6H, OOOH ; L. C. K 0_68
E6 00 228
0360 70 30 30 30 30 30 229 DB 070H, 030H, 030H, 030H, 030H, 030H, 078H, OOOH ; L. C. L 0_6C
78 00 230
0368 00 00 CC FE FE 06 231 000H,000H,OCCH,OFEH,OFEH,006H,OC6H,000H ; L.C. M 0_60
c6 00 232
0370 00 00 f8 CC CC CC 233 OB 000H,000H,OF8H,OCCH,OCCH,OCCH,OCCH,000H ; l.C. N 0_6E
CC 00 234
0378 00 00 78 CC CC CC 235 OB 000H,OOOH,078H,OCCH,OCCH,OCCH,078H,000H ; L.C. 0 0_6F
78 00 236
237
0380 00 00 DC 66 66 7C 238 DB 000H,000H,00CH,066H,066H,07CH,060H,OFOH ; L.C. P 0_70
60 FO 239
0388 00 00 76 CC CC 7C 2'0 DB 000H,000H,076H,OCCH,OCCH,07CH,OOCH,01EH ; l.C. Q 0_71
OC 1E 241
0390 00 00 DC 76 66 60 2'2 OB 000H,000H,OOCH,076H,066H,060H,OfOH,000H ; L.C. R 0_72
FO 00 243
0398 00
F8
00
00
7C CO 78 DC
2"2'5 OB 000H,000H,07CH,OCOH,078H,00CH,OF8H,000H ; L.C. S o_73
03AO 10 30 7C 30 30 34 2.6 DB 010H, 030H, 07CH, 030H, 030H, 034H, 01 8H, OOOH ; L. C. T o_74
18 00 247
03A8 00 00 CC CC CC CC 2'8 DB 000H,000H,OCCH,OCCH,OCCH,OCCH,076H,000H; L.C. U 0_75
76 00 2'9
03BO 00 00 CC CC CC 78 250 DB 000H,000H,OCCH,OCCH,OCCH,078H,030H,000H ; L.C. V o_76
30 00 251
03B8 00 00 c6 06 FE FE 252 DB 000H,000H,OC6H,006H,OFEH,OFEH,06CH,OOOH ; L.C. W o_77
6C 00 253
03CO 00 00 C6 6C 38 6C 25' DB OOOH, OOOH, OC6H, 06CH, 038H, 06CH, oe6H, OOOH ; L. C. X o_78
C6 00 255
03C8 00 00 CC CC CC 7C 256 DB 000H,000H,OCCH,OCCH,OCCH,07CH,00CH,OF8H ; L.C. Y 0_79
DC F8 257
0300 00 00 Fe 98 30 64 258 DB 000H,000H,OFCH,098H,030H,064H,OFCH,000H ; L.C. Z 0_7A
FC 00 259
0308 lC 30 30 EO 30 30 260 DB 01CH, 030H, 030H, OEOH, 030H, 030H, 01CH, OOOH ; L BRAK 0_78
lC 00 261
03EO 18 18 18 00 18 18 262 DB 018H,018H,018H,000H,018H,018H,018H,000H ; I 0_7C
18 00 263
03E8 EO 30 30 lC 30 30 26. DB OEOH,030H, 030H, 01CH, 030H, 030H, OEOH, OOOH ; R BRAK 0_70
EO 00 265
03FO 76 DC 00 00 00 00 266 DB 076H, OOCH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ; TILDE D_7E
00 00 267
03F8 00 10 38 6C C6 C6 268 OB OOOH, 010H, 038H, 06CH, OC6H, OC6H, OFEH, OOOH ; DELTA D_7F
FE 00 269
270
0400 271 LABEL BYTE
272
0400 78 CC CO CC 78 18 273 OB 078H,OCCH, OCOH, OCCH, 078H, 018H, OOCH, 078H; 0_80
DC 78 274
0408 00 CC 00 CC CC CC 275 DB OOOH,OCCH, OOOH, OCCH, OCCH, OCCH, 07EH, OOOH; o_81
7£ 00 276
0410 lC 00 78 CC FC CO 277 DB 01CH,000H,078H,OCCH,OFCH,OCOH,078H,000H; 0_82
78 00 278
0418 7E C3 3C 06 3E 66 279 DB 07EH, OC3H, 03CH, 006H, 03EH, 066H, 03 FH, OOOH; 0_83
3F 00 280
0420 CC 00 78 OC 7C CC 281 DB OCCH, OOOH, 078H, OOCH, 07CH, OCCH, 07EH, OOOH; 0_84
7E 00 282
0428 EO 00 78 OC 7e CC 283 DB OEOH,OOOH,078H,00CH,07CH,OCCH,07EH,OOOH; 0_85
7E 00 28.
0430 30 30 78 DC 7C CC 285 OB 030H, 030H,078H,00CH, 07CH, OCCH, 07EH, OOOH; o_86
7£ 00 286
0438 00 00 78 CO CO 78 287 DB OOOH, OOOH, 078H, OCOH, OCOH, 078H, OOCH, 038H; 0_87
OC 38 288
0440 7E C3 3C 66 7£ 60 289 DB 07EH, OC3H, 03CH, 066H,07EH,060H, 03CH, OOOH; 0_88
3C 00 290
0448 CC 00 78 CC FC CO 291 DB OCCH, OOOH, 078H, OCCH, orCH,OCOH, 078H, OOOH; o_89
78 00 292
0450 EO 00 78 CC FC CO 293 DB OEOH,000H,078H,OCCH,OFCH,OCOH,078H,000H; 0_8A
78 00 29'
0458 CC 00 70 30 30 30 295 DB OCCH,000H,070H,030H,030H,030H,078H,OOOH; 0_8B
78 00 296
0460 7C C6 38 18 18 18 297 OB 07CH,OC6H,038H,018H,018H,018H,03CH,OOOH; 0~8C
3C 00 298
0468 EO 00 70 30 30 30 299 DB OEOH, OOOH, 070H, 030H, 030H, 030H, 078H, OOOH; 0_80
78 00 300
0470 C6 38 6C C6 FE C6 301 DB OC6H, 038H, 06CH, OC6H, OFEH, OC6H, OC6H,000H; 0_8E
C6 00 302
0478 30 30 00 78 CC FC 303 DB 030H,030H,000H,078H,OCCH,OFCH,OCCH,OOOH; O_Sf
CC 00 30.
305
0480 1C 00 FC 60 78 60 306 DB 01CH, OOOH, OFCH, 060H, 078H, 060H, OfCH, OOOH; o_90
FC 00 307
0488 00 00 7F OC 7F CC 308 DB OOOH,OOOH,07FH,00CH,07FH,OCCH,07FH,OOOH; 0_91

162 IBM Enhanced Graphics Adapter August 2, 1984

 7F 00 30.
0490 3E 6C CC FE CC CC 310 DB 03EH, 06CH,OCCH,OFEH, oeCH,OCeH,OeEH,OOOH ; 0_92
CE 00 311
0498 78 CC 00 78 CC ce 312 DB 078H,OceH, 000H,078H, OCCH,OCCH,078H, OOOH ; 0_93
78 00 313
D4AO 00 ce 00 78 CC CC 314 DB OOOH, OceH, OOOH, 078H, OCCH, OCCH, 078H, OOOH ; 0_94
78 00 315
D4AS 00 EO 00 78 CC CC 316 DB OOOH,OEOH, 000H,078H, OCCH,OCCH,078H, OOOH ; .0_95
78 00 317
D4BO 78 CC 00 CC CC CC 31B DB 078H,OCCH, OOOH,OCCH, oeCH,OCCH,07EH, OOOH ; 0_96
7E 00 31,
04B8 00 EO 00 CC CC CC 320 DB OOOH,OEOH, 000H,OCCH,OCCH,OCCH,07EH, OOOH ; 0_97
7E 00 321
D4CO 00 cc 00 CC CC 7C 322 DB OOOH,OCCH, 000H,OCCH,OCCH,07CH,OOCH, OF8H ; 0_98
DC F8 323
04C8 C3 18 3C 66 66 3C 324 DB OC3H,018H, 03CH,066H,066H, 03CH,018H, OOOH ; 0_99
18 00 325
0400 CC 00 CC CC CC CC 32. DB OCCH,OOOH, OCCH,OCCH,OCCH, OCCH,078H, OOOH ; 0_9A
78 00 327
0408 18 18 7E CO CO 7E 32B DB 018H,018H, 07EH,OCOH,OCOH, 07EH, 018H, 018H ; 0_9B
18 18 32,
04EO 38 6C 64 FO 60 E6 330 DB 038H,06CH, 064H,OFOH,060H,OE6H,OFCH, OOOH ; 0_9C
FC 00 331
04E8 CC CC 78 FC 30 FC 332 DB OCCH, OCCH, 078H,OFCH,030H, OFCH,030H, 030H ; 0_90
30 30 333
04FO F8 CC CC FA C6 CF 334 DB OF8H,OCCH, OCCH,OFAH,OC6H, OCFH, OC6H, OC7H ; 0_9E
C6 C7 335
04F8 DE lB 18 3C 18 18 336 DB 00EH,01 BH, 018H, 03CH,018H, 018H, 008H, 070H ; 0_9f
08 70 337
33.
0500 1C 00 78 DC 7C CC 33, DB 01CH,000H, 078H,00CH,07CH, OCCH, 07EH,000H ; O_AO
7E 00 340
0508 38 00 70 30 30 30 341 DB 038H, OOOH, 070H,030H,030H, 030H, 078H,OOOH ; O_Al
78 00 342
0510 00 lC 00 78 CC CC 343 DB OOOH,OlCH, OOOH, 078H,OCCH, OCCH, 078H,000H ; D_A2
78 00 344
0518 00 lC 00 CC CC CC 345 DB OOOH, 01CH, OOOH,OCCH,OCCH, OCCH, 07EH,OOOH ; 0_A3
7E 00 346
0520 00 F8 00 f8 CC CC 347 DB OOOH, Of8H,000H, OF8H,OCCH, OCCH, OCCH,OOOH ; 0_A4
CC 00 34.
0528 FC 00 CC EC FC DC 34. DB OfCH, OOOH, OCCH, OECH, OFCH, OOCH, OCCH,OOOH ; 0_A5
CC 00 350
0530 3C 6C 6C 3E 00 7E 351 DB 03CH, 06CH, 06CH, 03EH, OOOH, 07EH, OOOH,OOOH ; 0_A6
00 00 352
0538 38 6C 6C 38 00 7C 353 DB 038H, 06CH,06CH,038H .. 000H, 07CH, OOOH,OOOH ; 0_A7
00 00 354
0540 30 00 30 60 CO CC 355 DB 030H, OOOH, 030H, 060H .. OCOH, OCCH, 078H,000H ; D_AS
78 00 356
0548 00 00 00 FC CO CO 357 DB OOOH, OOOH, OOOH .. OFCH,OCOH, OCOH, OOOH,OOOH ; 0_A9
00 00 35'
0550 00 00 00 FC DC DC 35. DB OOOH, OOOH, OOOH, OFCH, OOCH, OOCH, OOOH,OOOH ; D_AA
00 00 360
0558 C3 C6 CC DE 33 66 361 DB OC3H, OC6H, OCCH, 00EH .. 033H, 066H, OCCH,OOFH ; D_AB
CC OF 362
0560 C3 c6 CC DB 37 6F 363 DB OC3H, OC6H,OCCH, OOBH, 037H, 06FH, OCFH,003H ; O_AC
CF 03 364
0568 18 18 00 18 18 18 365 DB 018H, 018H, 000H .. 018H, 018H, 018H, 018H,OOOH ; D_AD
18 00 3••
0570 00 33 66 cc 66 33 367 DB OOOH, 033H, 066H,OCCH,066H, 033H, OOOH,OOOH ; O_AE
00 00 36B
0578 00 CC 66 33 66 CC 36. DB OOOH, OCCH, 066H .. 033H,066H, OCCH, OOOH, OOOH ; O_Af
00 00 370
371
0580 22 88 22 88 22 88 372 DB 022H, 088H, 022H,088H,022H .. 088H,022H, 088H ; O_BO
22 88 373
0588 55 AA 55 AA 55 AA 374 DB 055H .. OAAH, 055H,OAAH,055H,OAAH,055H, OAAH ; O_Bl
55 AA 375
0590 DB 77 DB EE DB 77 376 DB ODBH, 077H, OOBH,OEEH,OOBH, 077H,00BH, OEEH ; 0_B2
DB EE 317
0598 18 18 18 18 18 18 378 DB 018H, 018H, 018H,018H, 018H,018H,018H, 018H ; 0_B3
18 18 37.
05AO 18 18 18 18 F8 18 380 DB 018H, 018H, 018H,018H,OF8H,018H,018H, 018H ; 0_B4
18 18 381
05AS 18 18 F8 18 F8 18 382 DB 018H, 018H, OF8H,018H,OF8H,018H,018H, 018H ; 0_B5
18 18 383
05BO 36 36 36 36 F6 36 384 DB 036H, 036H, 036H,036H, OF6H,036H,036H, 036H ; 0_B6
36 36 385
05B8 00 00 00 00 FE 36 386 D8 OOOH, OOOH, OOOH,OOOH,OFEH, 036H,036H, 036H ; 0_87
36 36 387
05CO 00 00 F8 18 F8 18 388 DB 000H,OOOH,OF8H,018H,OF8H,018H,018H,018H ; 0_88
18 18 38,
05C8 36 36 F6 06 F6 36 3,0 D8 036H,036H, OF6H,006H, OF6H,036H, 036H,036H ; 0_B9
36 36 3"
0500 36 36 36 36 36 36 3,2 DB 036H,036H, 036H,036H, 036H, 036H, 036H,036H ; D_BA
36 36 3'3
0508 00 00 FE 06 F6 36 3,4 DB OOOH,OOOH, OFEH,006H, OF6H, 036H, 036H,036H ; 0_B8
36 36 3.5
05EO 36 36 F6 06 FE 00 3,6 DB 036H,036H, OF6H,006H, OFEH, OOOH, OOOH,OOOH ; O_BC
00 00 3,7
05E8 36 36 36 36 FE 00 3,8 DB 036H,036H, 036H,036H, OFEH, OOOH, OOOH,OOOH ; 0_80
00 00 3"
05FO 18 18 F8 18 F8 00 400 DB 018H,01 8H, OF8H,018H,OF8H, OOOH, OOOH,OOOH ; O_BE
00 00 401
05F8 00 00 00 00 F8 18 402 DB OOOH,OOOH, OOOH,OOOH, OF8H, 018H, 018H,Ol8H ; O_BF
18 18 403
404
0600 18 18 18 18 1F 00 405 DB 018H, 018H,018H, 018H,01 FH, OOOH,OOOH, OOOH ; O_CO
00 00 406
0608 18 18 18 18 FF 00 407 DB 018H, 018H,018H, 018H,OFfH,OOOH,OOOH, OOOH ; O_Cl
00 00 408
0610 00 00 00 00 FF 18 40. DB OOOH, OOOH,OOOH,OOOH, OHH,018H,Ol8H, 018H ; 0_C2
18 18 410
0618 18 18 18 18 1F 18 411 DB 018H, 018H, 018H, 018H, 01 FH,018H, 018H,018H ; 0_C3
18 18 412
0620 00 00 00 00 FF 00 413 DB OOOH, OOOH, OOOH,OOOH, OFF"H,OOOH, OOOH,OOOH ; O_CIi-
00 00 414
0628 18 18 18 18 FF 18 415 DB 018H,018H, 018H,018H, OFFH,018H, 018H,018H ; 0_C5
18 18 416
0630 18 18 lF 18 1F 18 417 DB 018H .. 018H, 01 FH,018H. 01 FH,018H, 018H,018H ; 0_C6
18 18 418
0638 36 36 36 36 37 36 41, DB 036H,036H, 036H,036H, 037H, 036H,036H,036H ; 0_C7
36 36 420
0640 36 36 37 30 3F 00 421 DB 036H,036H, 037H,030H,03FH, OOOH,OOOH,OOOH ; 0_C8
00 00 422
0648 00 00 3F 30 37 36 423 D8 OOOH,OOOH, 03FH,030H,037H, 036H,036H,036H ; 0_C9
36 36 424
0650 36 36 F7 00 FF 00 425 DB 036H,036H .. 0F1H, OOOH,OFfH,OOOH,OOOH, OOOH ; D_C"
00 00 426
0658 00 00 FF 00 F1 36 427 DB OOOH,OOOH,OFFH, 000H,OF7H,036H,036H, 036H ; O_CB
36 36 428
0660 36 36 37 30 37 36 42' DB 036H, 036H,037H, 030H,037H,036H,036H .. 036H ; O_CC
36 36 430
0668 00 00 FF 00 FF 00 431 DB OOOH, OOOH, OFFH, OOOH, OFFH, OOOH, OOOH, OOOH ; D_CO
00 00 432
0670 36 36 F1 00 F7 36 433 DB 036H,036H,0F1H,OOOH, OF7H, 036H,036H,036H ; D_CE
36 36 434

August 2, 1984 mM Enhanced Graphics Adapter 163

0678 18 18 FF 00 FF 00 435 DB 018H,018H,OFFH,OOOH,OFFH,000H,000H,OOOH; O_CF
00 00 436
437
0680 36 36 36 36 FF 00 438 DB 036H,036H,036H,036H,OfFH,000H,OOOH,OOOH; 0_00
00 00 439
0688 00 00 FF 00 FF 18 440 08 000H,000H,OFFH,OOOH,OFFH,018H,018H,018H; 0_01
18 18 441
0690 00 00 00 00 FF 36 442 DB OOOH,000H,000H,000H,OFFH,036H,036H,036H; 0_02
36 36 443
0698 36 36 36 36 3f 00 444 DB 036H, 036H, 036H, 036H,03FH, OOOH, OOOH, OOOH; 0_03
00 00 445
06AO 18 18 IF 18 1F 00 446 DB 018H, 018H, 01 FH, 018H, 01 FH, OOOH,OOOH, OOOH; 0_04
00 00 447
06A8 00 00 1F 18 1f 18 448 DB 000H,OOOH,OlfH,018H,OlfH,018H,018H,018H; 0_05
18 18 449
06BO 00 00 00 00 3f 36 450 DB OOOH, OOOH, OOOH,OOOH, 03 FH, 036H, 036H,036H; 0_06
36 36 451
0688 36 36 36 36 FF 36 452 DB 036H,036H,036H,036H,OFFH,036H,036H,036H; 0_07
36 36 453
06CO 18 18 FF 18 FF 18 454 DB 018H,018H,OFFH,018H,OFFH,018H,018H,018H; 0_08
18 18 455
06C8 18 18 18 18 F8 00 456 DB 018H,018H,018H,018H,OF8H,000H,000H,OOOH; 0_09
00 00 457
0600 00 00 00 00 1f 18 458 DB OOOH,OOOH,000H,000H,OlfH,018H,018H,018H; o_oA
18 18 459
0608 FF ff FF fF fF Ff 460 DB OFFH,OFFH,OFFH,OFFH,OFFH,OFfH,OFfH,OFFH; D_DB
FF FF 461
06EO 00 00 00 00 FF ff 462 DB OOOH,OOOH,OOOH,OOOH,OFFH,OFFH,OFFH,OFFH; D_DC
Ff FF 463
06E8 FO FO FO FO FO FO 464 OFOH,OFOH,OFOH,OFOH,OFOH,OFOH,OFOH,OFOH; 0_00
FO FO 465
06FO OF OF OF OF OF OF 466 DB OOFH,OOFH,OOFH,OOFH,OOFH,OOfH,OOFH,OOFH; D_DE
OF OF 467
06F8 FF FF FF FF 00 00 468 DB OFFH,OffH,OfFH,OFFH,OOOH,OOOH,OOOH,OOOH; O_OF
00 00 469
470
0700 00 00 76 DC C8 DC 471 DB OOOH, OOOH, 076H, OOCH, OC8H, OOCH, 076H, OOOH; O_EO
76 00 472
0708 00 78 CC F8 CC F8 473 DB 000H,078H,OCCH,OF8H,OCCH,OF8H,OCOH,OCOH; O_El
CO CO 474
0710 00 FC CC CO CO CO 475 DB OOOH,OFCH,OCCH,OCOH,OCOH,OCOH,OCOH,OOOH; 0_E2
CO 00 476
0718 00 FE 6C 6C 6C 6C 477 DB 000H,OFEH,06CH,06CH,06CH,06CH,06CH,000H: 0_E3
6C 00 478
0720 FC CC 60 30 60 CC 479 DB OFCH,OCCH,060H,030H,060H,OCCH,OFCH,OOOH; 0_[4
FC 00 480
0728 00 00 7E 08 08 08 481 DB OOOH, OOOH, 07EH, 008H, 008H, 008H, 070H, OOOH; D_E5
70 00 482
0730 00 66 66 66 66 7C 483 DB OOOH, 066H, 066H,066H, 066H, 07CH, 060H,OCOH; D_E6
60 CO 484
0738 00 76 DC 18 18 18 485 DB 000H,076H,ODCH,018H,018H,018H,018H,OOOH; 0_£1
18 00 486
0740 FC 30 78 CC CC 78 487 DB OFCH, 030H, 078H, OCCH, OCCH, 018H, 030H, OFCH: 0_E8
30 FC 488
0748 38 6C C6 FE C6 6C 489 DB 038H, 06CH, OC6H, OFEH, OC6H, 06CH, 038H, OOOH: 0_E9
38 00 490
0750 38 6C C6 C6 6C 6C 491 DB 038H, 06CH, OC6H, OC6H, 06CH, 06CH, OEEH, OOOH; O_EA
EE 00 492
0758 1C 30 18 1C CC CC 493 DB 01CH,030H,018H,07CH,OCCH,OCCH,078H,000H; O_EB
78 00 494
0760 00 00 1E DB DB 1E 495 DB OOOH, OOOH, 07EH, ODBH, OOBH, 07EH, OOOH, OOOH; o_EC
00 00 496
0768 06 DC 1E DB DB 1E 497 DB 006H, OOCH, 01EH, OOBH, OOBH, 07EH, 060H, OCOH: O_EO
60 CO 498
0770 38 60 CO F8 CO 60 499 DB 038H, 060H, OCOH, OF8H, OCOH, 060H, 038H, OOOH; O_EE
38 00 500
0778 78 CC CC CC CC CC 501 DB 078H, OCCH, OCCH,OCCH, OCCH, OCCH, OCCH, OOOH; D_EF
CC 00 502
503
0780 00 FC 00 FC 00 FC 504 DB OOOH,OFCH,OOOH,OFCH,OOOH,OFCH,OOOH,OOOH; D_FO
00 00 505
0788 30 30 FC 30 30 00 506 DB 030H,030H,OFCH,030H,030H,OOOH,OFCH,000H; O_Fl
FC 00 507
0790 60 30 18 30 60 00 508 DB 060H, 030H, 018H,030H, 060H, OOOH, OFCH,OOOH; 0_F2
FC 00 509
0798 18 30 60 30 18 00 510 DB 018H,030H,060H,030H,018H,000H,OFCH,000H; 0_F3
FC 00 511
07AD OE 18 lB 18 18 18 512 DB 00EH,OlBH,OlBH,018H,018H,018H,018H,018H; 0_F4
18 18 513
07A8 18 18 18 18 18 08 514 DB 018H,018H,018H,018H,018H,OD8H,OD8H,070H; D_F5
08 10 515
0780 30 30 DO FC 00 30 516 DB 030H, 030H, OOOH, OFCH, OOOH, 030H, 030H, OOOH: D_F6
30 00 517
0788 00 76 DC 00 76 DC 518 DB OOOH, 076H, OOCH, OOOH, 076H, OOCH, OOOH, OOOH; O_f7
00 00 519
07CO 38 6C 6C 38 00 00 520 DB 038H, 06CH, 06CH, 038H, OOOH, OOOH, OOOH, OOOH; D_F8
00 00 521
07C8 00 00 00 18 18 00 522 DB 000H,OOOH,OOOH,018H,018H,OOOH,000H,000H; OJ9
00 00 523
0700 00 00 00 00 18 00 524 DB 000H,OOOH,OOOH,000H,018H,OOOH,000H,000H; O_FA
00 00 525
0708 OF DC OC DC EC 6C 526 DB 00FH,00CH,00CH,OOCH,OECH,06CH,03CH,01CH; O_FB
3C 1C 527
07EO 78 6C 6C 6c 6C 00 528 DB 078H, 06CH, 06CH, 06CH,06CH, OOOH, OOOH, OOOH; D_FC
00 00 529
07E8 70 18 30 60 78 00 530 DB 070H, 018H, 030H, 060H, 078H, OOOH, OOOH, OOOH; D_FD
00 00 531
07FO 00 00 3C 3C 3C 3C 532 DB OOOH, OOOH, 03CH, 03CH, 03CH, 03CH, OOOH, OOOH; O_FE
00 00 533
07F8 00 00 00 00 00 00 534 DB OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH; O_FF
00 00 535
0800 536 CODE ENDS
537 END

PAGE,120
SUBTTL END ADDRESS
0000 CODE SEGMENT PUBL I C
PUBU C END_ADDRESS
0000 6~gloOR~~~S LABEL BYTE
0000
END

164 IBM Enhanced Graphics Adapter August 2, 1984

Index

A compatibility issues 74
configuration switches 80
CRT Controller
Attribute Address Register 56 description 3
Attribute Controller registers 24
description 3 CRT Controller Address
registers 56 Register 24
CRT Controller Overflow
Register 30
Cursor End Register 33
Cursor Location High
B Register 35
Cursor Location Low
Register 35
BIOS Cursor Start Register 32
description 4
vectors with special
meanings 103
BIOS listing 103
Bit Mask Register 54 D
Data Rotate Register 49

c direct drive connector 83

display buffer 4

character generator
ROM 1
Character Map Select E
Register 21
Clocking Mode Register 19
Color Compare Register 48 Enable Set/Reset Register 47
Color Don't Care Register 53 End Horizontal Blanking
color mapping 10 Register 27
Color Plane Enable End Horizontal Retrace
Register 60 Register 29

Index-l
End Vertical Blanking I
Register 40

Input Status Register One 15

Input Status Register Zero 14
F Interface 76
feature connector 76

feature connector 76
Feature Control Register 14
L

G Light Pen High Register 36

light pen interface 84
Light Pen Low Register 37
Graphics Controller Line Compare Register 43
description 3
registers 45
Graphics 1 and 2 Address
Register 46
Graphics 1 Position
M
Register 45
Graphics 2 Position Map Mask Register 20
Register 46 Maximum Scan Line
Register 32
Memory Mode Register 23
Miscellaneous Output
H Register 12
Miscellaneous Register 52
Mode Control Register 41,58
Horizontal Display Enable End Mode Register 50
Register 26 modes
Horizontal Pel Panning alphanumeric 8
Register 60 graphics 8
Horizontal Total Register 25 IBM Color Display 5
IBM Enhanced Color
Display 6
IBM Monochrome
Display 6

Index-2
o Graphics Controller 45
Sequencer 18
Reset Register 18
Offset Register 38
Overscan Color Register 59

s
p
Sequencer
description 3
Palette Registers 57 registers 18
Preset Row Scan Register 31 Sequencer Address Register 18
programming Set/Reset Register 47
considerations 62 specifications 79
compatibility issues 74 configuration switch
creating a split screen 73 settings 81
creating a 512 character configuration switches 80
set 70 direct drive connector 83
creating an 80 by 43 light pen interface 84
alphanumeric mode 71 system board switches 79
programming registers 62 Start Address High Register 34
RAM loadable character Start Address Low Register 34
generator 69 Start Horizontal Blanking
vertical interrupt feature 72 Register 26
Start Horizontal Retrace Pulse
Register 28
Start Vertical Blanking
Register 39
R support logic 4

RAM loadable character

generator 69
Read Map Select Register 50 u
registers
Attribute Controller 56
CRT Controller 24 Underline Location
external 12 Register 39

Index-3
v Vertical Retrace End
Register 36
Vertical Retrace Start
Vertical Display Enable End Register 36
Register 38 Vertical Total Register 30
vertical interrupt feature 72

Index-4
 Personal Computer
Hardware Reference
Library

mM Printer Adapter

6361507
ii
Contents

Description .................................... 1
Programming Considerations ...................... 3
Specifications .................................. 7
Logic Diagrams ................................. 9

iii
iv
Description

The IBM Printer Adapter is specifically designed to attach

printers with a parallel port-interface, but it can be used as a
general input/output port for any device or application that
matches its input/output capabilities. It has 12 TTL-buffer
output points, which are latched and can be written and read
under program control using the microprocessor In or Out
instruction. The adapter also has five steady-state input points
that may be read using the microprocessor's In instructions.

In addition, one input can also be used to create a microprocessor

interrupt. This interrupt can be enabled and disabled under
program control. A reset from the power-on circuit is also ORed
with a program output point, allowing a device to receive a
'power-on reset' when the system unit's microprocessor is reset.

The input/ output signals are made available at the back of the
adapter through a right-angle, printed-circuit-board-mounted,
25-pin, D-shell connector. This connector protrudes through the
rear panel of the system unit or expansion unit, where a cable may
be attached.

When this adapter is used to attach a printer, data or printer

commands are loaded into an 8-bit, latched, output port, and the
strobe line is activated, writing data to the printer. The program
then may read the input ports for printer status indicating when
the next character can be written, or it may use the interrupt line
to indicate "not busy" to the software.

The output ports may also be read at the card's interface for
diagnostic loop functions. This allows faults to be isolated to the
adapter or the attaching device.

This same function is also part of the IBM Monochrome Display

and Printer Adapter.

Printer Adapter 1
The following is a block diagram of the Printer Adapter.

8 25-Pin D-Shell
Connector
~U'BUff"8 .Data Latch 8
po

.... Enable ... Clock

~ Trans- .....
...
8
...
ceiver

r DIR

~ O.C.
Read Drivers SLCTIN

~
A Data
STROBE
Write Data po

Command AUTO
Decoder Write Control
- -
FDXT
Read Status
-INIT
Read
Control
-
A

Bus Control
Buffers Latch

~ Enable
~ ..... Clock r-
5 ERROR
po

4 Enable SLCT

R eset
r r.. ~ Clear PE

ACK

BUSY

Printer Adapter Block Diagram

2 Printer Adapter
Programming Considerations

The Printer Adapter responds to five I/O instructions; two output

and three input. The output instructions transfer data into two
latches whose outputs are presented on pins of a 25-pin D-shell
connector.

Two of the three input instructions allow the system unit's

microprocessor to read back the contents of the two latches. The
third allows the system unit's microprocessor to read the real-time
status from a group of pins on the connector.

A description of each instruction follows.

Printer Adapter

Output to address hex 378

Bit 3 I Bit 2 I Bit 1 I BitO
Pin 5 Pin 4 Pin 3 Pin 2

The instruction captures data from the data bus and is present on
the respective pins. Each of these pins is capable of sourcing 2.6
rnA and sinking 24 rnA.

It is essential that the external device does not try to pull these
lines to ground.

Printer Adapter

Output to address hex 37 A

Bit3 Bit 2 Bit 1 BitO
Pin 17 Pin 16 Pin 14 Pin 1

This instruction causes the latch to capture the five least

significant bits of the data bus. The four least significant bits
present their outputs, or inverted versions of their outputs, to the

Printer Adapter 3
respective pins as shown in the previous figure. If bit 4 is written
as aI, the card will interrupt the system unit's microprocessor on
the condition that pin 10 changes from high to low.

These pins are driven by open-collector drivers pulled to +5 Vdc

through 4.7 kQ resistors. They can each sink approximately 7 rnA
and maintain 0.8 volts down-level.

Printer Adapter
Input from address hex 378

This instruction presents the system unit's microprocessor with

data present on the pins associated with the output to hex 3BC.
This should normally reflect the exact value that was last written
to hex 3BC. If an external device should be driving data on these
pins at the time of an input (in violation of usage ground rules),
this data will be ORed with the latch contents.

Printer Adapter
Input from address hex 379

This instruction presents the real-time status to the system unit's

microprocessor from the pins, as follows.

BitO

Printer Adapter
Input from address hex 37 A

4 Printer Adapter
This instruction causes the data present on pins 1, 14, 16, 17, and
the IRQ bit to be read by the system unit's microprocessor. In
the absence of external drive applied to these pins, data read by
the system unit's microprocessor will match data last written to
hex 3BE in the same bit positions. Notice that data bits 0-2 are
not included. If external drivers are dotted to these pins, that
data will be ORed with data applied to the pins by the hex 3BE
latch.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO

IRQ Pin 17 Pin 16 Pin 14 Pin 1
Enable
Por=O Por= 1 Por=O Por = 1 Por= 1

These pins assume the states shown after a reset from the system
unit's microprocessor.

Printer Adapter 5
6 Printer Adapter
Specifica tions
25-Pin D-Shell
Connector

o
• • 14
• •
• •
• •
• •
• •
• •
•• •
•
•• ••
• • 25
13 •
o
At Standard TTL Levels
Signal Adapter
Name Pin Number
- Strobe 1
+ Data Bit 0 2
+ Data Bit 1 3
+ Data Bit 2 4
+ Data Bit 3 5
+ Data Bit 4 6
+ Data Bit 5 7
+ Data Bit 6 8
Printer + Data Bit 7 9 Printer
- Acknowledge 10 Adapter
+ Busy 11
+ P.End (out of paper) 12
+ Select 13
- Auto Feed 14
- Error 15
- Initialize Printer 16
- Select Input 17
Ground 18-25

Connector Specifications

Printer Adapter 7
8 Printer Adapter
Logic Diagrams

The following page contains the logic diagram for the IBM Printer
Adapter.

Printer Adapter 9
~""
,~ -"--NO ..

---..- oM

~ , !:, '"

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~LFrE5~J'"
... ~

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.: "' COXl.""""
.:~~~
.. .-. " ..~

fTTT~ ~

tf
m .. .~

,
ri' ~ .~
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~
r--- --'" --~-L'.-n-"";·'''' '~
t.
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....
~!.D ,r<::."
-~.

....... I.tk,
~:§~
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-.~ v ...,..
,,~,~
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..., -""~ ~ ,,~

v
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v
::: ... i~' fa~" ~'" ¥. ~" *'" *,u ~" '-- '~'" i.,,;,,I~, '~
17 Lm L", L",
I....-- ~ '--.---I '---' L..J ~ ~ "[ I I .•~. r :l~-
'10- IIF .O""IIF 10 ..F .OIOU 10"", .0"1",F (lx).OOZZ .. F
"!- ..=l~'O,~ '- ~
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... , v ...,,, I

Printer Adapter (Sheet 1 of 1)

----
-
--
--
---
- --
-
-_ -
---
-
-
---
- ---
-. -
Personal Computer
Hardware Reference
Library

mM 5-114" Diskette
Drive Adapter

6361505
ii
Contents

Description .................................... 1
Programming Considerations ...................... 3
Digital-Output Register ...................... 3
Floppy Disk Controller ....................... 4
Command Summary ......................... 8
Programming Summary ...................... 17
Interface ..................................... 19
System 110 Channel Interface ................ 19
Drive A and B Interface ..................... 20
Specifications ................................. 23
Logic Diagrams ................................ 25

iii
iv
Description

The IBM 5-1/4" Diskette Drive Adapter fits into one of the
expansion slots in the system unit. It is connected to one or two
diskette drives through an internal, daisy-chained flat cable. The
adapter has a connector at the other end that extends through the
rear panel of the system unit. This connector has signals for two
additional external diskette drives; thus, the 5-1/4 inch diskette
drive adapter can attach four 5-1/4 inch drives - two internal
and two external.

The adapter is designed for double-density, MFM-coded, diskette

drives and uses write precompensation with an analog phase-lock
loop for clock and data recovery. The adapter is a
general-purpose device using the NEC fLPD765 or equivalent
controller. Therefore, the diskette drive parameters are
programmable. In addition, the attachment supports the diskette
drive's write-protect feature. The adapter is buffered on the I/O
bus and uses the system board's direct memory access (DMA) for
record data transfers. An interrupt level also is used to indicate
when an operation is complete and that a status condition requires
microprocessor attention.

In general, the 5-1/4 inch diskette drive adapter presents a

high-level command interface to software I/O drivers.

Diskette Adapter 1
 Clock
and
Timing
Circuit
1
• Write
. • Write
Precompensate
Circuit ~
Write Data

t'-- .../
I Data Read Data
Data
VCO SYNC· Separator
<}- I--
I-
STD. DATA

~ Buffer
I'r- r-v'
NEC
Floppy
Disk
""
Data Window

V
Step
Direction
Write Enable
f " , ,
~-

Controller
V Head Select
Index
I"" "'-.J Write Protect
./1 '-J Track 0

iRes~t f-- B
Drive A Motor On

Digital
~
f--C
Control Decoder f--D Drive A Select

'1
Port
I-- B
INTR. f-- C
I I-- D

5-1/4 Inch Diskette Drive Adapter Block Diagram

Programming Considerations

This attachment consists of an 8-bit digital output register in

parallel with a NEe p.PD765 or equivalent floppy disk controller
(FDe).

In the following description, drive numbers 0, 1,2, and 3 are

equivalent to drives A, B, e, and D.

Digital-Output Register
The Digital-Output register (DOR) is an output-only register used
to control drive motors, drive selection, and feature enable. All
bits are cleared by the I/O interface 'reset' line. The bits have the
following functions:

Bits 0 and 1 These bits are decoded by the hardware to

select one drive if its motor is on:

Bit 1 0 Drive
00 0 (A)
o1 1 (B)
10 2 (e)
11 3 (D)

Bit 2 The FDe is held reset when this bit is clear.

It must be set by the program to enable the
FDe.

Bit 3 This bit allows the FDe interrupt and DMA

requests to be gated onto the 110 interface.
If this bit is cleared, the interrupt and DMA
request 110 interface drivers are disabled.

Bits 4,5,6, These bits control, respectively, the motors of

and 7 drives 0, 1,2 (A, B, e), and 3 (D). If a bit is
clear, the associated motor is off, and the
drive cannot be selected.

Diskette Adapter 3
Floppy Disk Controller
The floppy disk controller (FDC) contains two registers that may
be accessed by the system unit's microprocessor: a status register
and a data register. The 8-bit main status register contains the
status information of the FDC and may be accessed at any time.
The 8-bit data register (actually consisting of several registers in a
stack with only one register presented to the data bus at a time)
stores data, commands, parameters, and provides floppy disk
drive (FDD) status information. Data bytes are read from or
written to the data register in order to program or obtain results
after a particular command. The main status register can only be
read and is used to facilitate the transfer of data between the
system unit's microprocessor and FDC.

The bits in the main status register (hex 34F) are defined as
follows:

Bit
Number Name Symbol Description
DBO FDD A Busy DAB FDD number 0 is in the Seek mode.
DB1 FDD B Busy DBB FDD number 1 is in the Seek mode.
DB2 FDD C Busy DCB FDD number 2 is in the Seek mode.
DB3 FDD 0 Busy DDB FDD number 3 is in the Seek mode.
DB4 FOC Busy CB A read or write command is in process.
DB5 Non-DMA NDM The FDC is in the non-DMA mode.
Mode
DB6 Data Inputl 010 Indicates direction of data transfer
Output between FDC and processor. If DIO =" 1;'
then transfer is from FDC data register to
the processor. If 010 = "0;' then transfer
is from the processor to FDC data register.
DB7 Request for ROM Indicates data register is ready to send or
Master receive data to or from the processor. Both
bits 010 and ROM should be used to
perform the handshaking functions of
"ready" and "direction" to the processor.

The FDC is capable of performing 15 different commands. Each

command is initiated by a multi-byte transfer from the system
unit's microprocessor, and the result after execution of the
command may also be a multi-byte transfer back to the system

4 Diskette Adapter
unit's microprocessor. Because of this multi-byte interchange of
information between the FDC and the system unit's
microprocessor, it is convenient to consider each command as
consisting of three phases:

Command Phase
The FDC receives all information required to perform a particular
operation from the system unit's microprocessor.

Execution Phase
The FDC performs the operation it was instructed to do.

Result Phase
After completion of the operation, status and other housekeeping
information are made available to the system unit's
microprocessor.

The following tables define the symbols used in the command

summary. The command summary immediately follows these
tables.

Diskette Adapter 5
 Symbol Name Description

AO Address Line 0 AO controls selection of main status

register (AO = 0) or data register (AO = 1).
C Cylinder Number C stands for the current/selected cylinder
(track) number of the medium.
D Data D stands for the data pattern that is going
to be written into a sector.
07-00 Data Bus 8-bit data bus, where 07 stands for a
most significant bit, and DO stands for a
least significant bit.
OTL Data Length When N is defined as 00, OTL stands for
the data length that users are going to
read from or write to the sector.
.
EOT End of Track EOT stands for the final sector number on
a cylinder.
GPL Gap Length GPL stands for the length of gap 3
(spacing between sectors excluding VCO
sync field).
H Head Address H stands for head number 0 or 1, as
specified in ID field.
HD Head HO stands for a selected head number 0
or 1. (H = HD in all command words).
HLT Head Load Time HLT stands for the head load time in the
FDD (4 to 512 ms in 4-ms increments).
HUT Head Unload Time HUT stands for the head unload time after
a read or write operation has occurred (0
to 480 ms in 32-ms increments).
MF FM or MFM Mode If MF is low, FM mode is selected; if it is
high, MFM mode is selected only if MFM
is implemented.
MT Multi-Track If MT is high, a multi-track operation is to
be performed. (A cylinder under both HOO
and HD 1 will be read or written.)
N Number N stands for the number of data bytes
written in a sector.

Symbol Descriptions (Part 1 of 2)

6 Diskette Adapter
Symbol Name Description

NCN New Cylinder NCN stands for a new cylinder number,

Number which is going to be reached as a result
of the seek operation. (Desired position of
the head.)
ND Non-DMA Mode ND stands for operation in the non-DMA
mode.

PCN Present Cylinder PCN stands for cylinder number at the

Number completion of sense-interrupt-status
command indicating the position of the
head at present time.
R Record R stands for the sector number, which
will be read or written.

R/W Read/Write R/W stands for either read (R) or write

(W) signal.
SC Sector SC indicates the number of sectors per
cylinder.
SK Skip SK stands for skip deleted-data address
mark.
SRT Step Rate Time SRT stands for the stepping rate for the
FDD (2 to 32 ms in 2-ms increments).
STO Status 0 STO-3 stand for one of four registers that
ST 1 Status 1 store the status information after a
ST 2 Status 2 command has been executed. This
ST 3 Status 3 information is available during the result
phase after command execution. These
registers should not be confused with the
main status register (selected by AO = 0).
ST 0-3 may be read only after a command
has been executed and contain
information relevant to that particular
command.
STP Scan Test During a scan operation, if STP = 1, the
data in contiguous sectors is compared
byte-by-byte with data sent from the
processor (or DMA), and if STP = 2, then
alternate sectors are read and compared.
USO, Unit Select US stands for a selected drive number
US1 encoded the same as bits 0 and 1 of the
digital output register (DOR).

Symbol Descriptions (Part 2 of 2)

Diskette Adapter 7
Command Summary
In the following table, 0 indicates "logical 0" for that bit, 1 means
"logical 1," and X means "don't care."

Data Bus
Phase R/W D7 D6 D5 D4 D3 D2 D1 DO Remarks
Read Data
Command W MT MF SK 0 0 1 1 0 Command Codes
W X X X X X HD US1 usa
w C Sector ID information
W H prior to command
W R execution.
W N
W EOT
W GPL
W DTL
Execution Data transfer
between the FDD
and main system.
Result R STO Status information
R ST 1 after command
R ST 2 execution.
R C Sector ID information
R H after command
R R execution.
R N
Read Deleted Data
Command W MT MF SK 0 1 1 0 0 Command Codes
W X X X X X HDUS1USO
W C Sector ID information
W H prior to command
W R execution.
W N
W EOT
W GPL
W DTL
Execution Data transfer
between the FDD
and main system.
Result R STO Status information
R ST 1 after command
R ST 2 execution.
R C Sector ID information
R H after command
R R execution.
R N

8 Diskette Adapter
 Data Bus
Phase R/W 07 06 05 04 03 02 01 DO Remarks
Write Data
Command W MT MF 0 a a 1 a 1 Command Codes
W X X X X X HO US1 usa
W C Sector 10 information
W H prior to command
W R execution.
W N
W EOT
W GPL
W OTL
Execution Data transfer
between the main
system and FOO.
Result R ST a Status information
R ST 1 after command
R ST 2 execution.
R C Sector 10 information
R H after command
R R execution.
R N
Write Deleted Data
Command W MT MF a a 1 1a a Command Codes
W X X X X X HO US1 usa
w C Sector 10 information
W H prior to command
W R execution.
W N
W EOT
W GPL
W OTL
Execution Data transfer
between the FOD and
main system.
Result R STa Status 10 information
R ST 1 after command
R ST 2 execution.
R C Sector 10 information
R H after command
R R execution.
R N

Diskette Adapter 9
 Oata Bus
Phase R/W 07 06 05 04 03 02 01 00 Remarks
Read a Track
Command W 0 MF SK 0 0 0 1 0 Command Codes
W X X X X X HO US1 usa
w C Sector ID information
W H prior to command
W R execution.
W N
W EOT
W GPL
W DTL
Execution Data transfer
between the FDD
and main system.
FDC reads all of
cylinder's contents
from index hole to
EOT.
Result R STO Status information
R ST 1 after command
R ST 2 execution.
R C Sector ID information
R H after command
R R execution.
R N
Read 10
Command W 0 MF 0 0 1 0 1 0 Command Codes
W X X X X X HD US1 usa
Execution The first correct ID
information on the
cylinder is stored in
data register.
Result R STO Status information
R ST 1 after command
R ST 2 execution.
R C Sector ID information
R H during execution
R R phase.
R N

10 Diskette Adapter
 Oata Bus
Phase R/W 07 06 05 04 03 02 01 00 Remarks
Format a Track
Command W 0 MF 0 0 1 1 0 0 Command Codes
W X X X X X HD US1 usa
W N Bytes/Sector
W SC Sector/Track
W GPL Gap 3
W D filler byte.
Execution FDC formats an
entire cylinder.
Result R STO Status information
R ST 1 after command
R ST 2 execution.
R C In this case, the ID
R H information has no
R R meaning.
R N
Scan Equal
Command W MT MF SK 1 0 0 0 1 Command Codes
W X X X X X HD US1 usa
w C Sector ID information
W H prior to command
W R execution.
W N
W EOT
W GPL
W STP
Execution Data compared
between the FDD
and the main system.
Result R STO Status information
R ST 1 after Command
R ST 2 execution.
R C Sector ID information
R H after command
R R execution.
R N

Diskette Adapter 11
 Oata Bus
Phase R/W 07 06 05 04 03 02 01 00 Remarks
Scan Low or Equal
Command W MT MF SK 1 1 0 0 1 Command Codes
W X X X X X HD US1 usa
w C Sector 10 information
W H prior to command
W R execution.
W N
W EOT
W GPL
W STP
Execution Data compared
between the FDD
and main system.
Result R STO Status information
R ST 1 after command
R ST 2 execution.
R C Sector 10 information
R H after command
R R execution.
R N
Scan High or Equal
Command W MT MF SK 1 1 1 0 1 Command Codes
W X X X X X HD US1 usa
w C Sector 10 information
W H prior to command
W R execution.
W N
W EOT
W GPL
W STP
Execution Data compared
between the FDD
and main system.
Result R STO Status information
R ST 1 after command
R ST 2 execution.
R C Sector 10 information
R H after command
R R execution.
R N

12 Diskette Adapter
 Data Bus
Phase R/W 07 06 05 04 03 02 01 DO Remarks
Recalibrate
Command W 0 0 0 0 0 1 1 1 Command Codes
W X X X X X 0 US1USO
Execution Head retracted to
No Result track 0
Phase
Sense Interrupt Status
Command W 0 0 0 0 1 0 0 0 Command Codes
Result R STO Status information at
R PCN the end of seek
operation about the
FOC
Specify
Command W 0 0 0 0 0 0 1 1 Command Codes
W t--SRT HUT-
W HLT ND
No Result
Phase
Sense Drive Status
Command W 0 0 0 0 0 1 0 0 Command Codes
W X X X X X HO US1 usa
Result R ST 3 Status information
about FDD.
Seek
Command W 0 0 0 0 1 1 1 1 Command Codes
W X X X X X HO US1 usa
w NCN
Execution Head is positioned
over proper cylinder
on diskette.
No Result
Phase
Invalid
Command W Invalid Codes Invalid command
codes (NoOp - FOC
goes into standby
state).
Result R STO ST 0: 80.

Diskette Adapter 13
 Bit
No. Name Symbol Description
D7 D7 = 0 and D6 = 0
Interrupt IC Normal termination of command (NT).
Code Command was completed and properly
executed.
D6 D7 = 0 and D6 = 1
Abnormal termination of command (AT).
Execution of command was started, but
was not successfully completed.
D7 = 1 and D6 = 0
Invalid command issue (IC). Command
that was issued was never started.
D7 = 1 and D6 = 1
Abnormal termination because, during
command execution, the ready signal
from FDD changed state.
D5 Seek End SE When the FDC completes the seek
command, this flag is set to 1 (high).
D4 Equipment EC If a fault signal is received from the
Check FDD, or if the track 0 signal fails to occur
after 77 step pulses (recalibrate
command), then this flag is set.
D3 Not Ready NR When the FDD is in the not-ready state
and a read or write command is issued,
this flag is set. If a read or write command
is issued to side 1 of a single-sided drive,
then this flag is set.
D2 Head Address HD This flag is used to indicate the state of
the head at interrupt.
D1 Unit Select 1 US 1 These flags are used to indicate a drive
DO Unit Select 0 usa unit number at interrupt.

Command Status Register 0

14 Diskette Adapter
 Bit
No. Name Symbol Description
D7 End of EN When the FDC tries to access a sector
Cylinder beyond the final sector of a cylinder, this
flag is set.
D6 - - Not used. This bit is always 0 (low).
D5 Data Error DE When the FDC detects a CRC error in
either the ID field or the data field, this
flag is set.
D4 Over Run OR If the FDC is not serviced by the main
system during data transfers within a
certain time interval, this flag is set.
D3 - - Not used. This bit is always 0 (low).
D2 No Data ND During execution of a read data, write
deleted data, or scan command, if the
FDC cannot find the sector specified in
the ID register, this flag is set. During
execution of the read ID command, if the
FDC cannot read the ID field without an
error, then this flag is set. During the
execution of the read a cylinder
command, if the starting sector cannot be
found, then this flag is set.
D1 Not Writable NW During execution of a write data, write
deleted data, or format-a-cylinder
command, if the FDC detects a
write-protect signal from the FDD, then
this flag is set.
DO Missing MA If the FDC cannot detect the ID address
Address mark, this flag is set. Also, at the same
Mark time, the MD (missing address mark in
the data field) of status register 2 is set.

Command Status Register 1

Diskette Adapter 15
 Bit
No. Name Symbol Description
D7 - - Not used. This bit is always 0 (low).
D6 Control Mark CM During execution of the read data or scan
command, if the FDC encounters a sector
that contains a deleted data address
mark, this flag is set.
D5 Data Error in DD If the FDC detects a CRC error in the data,
Data Field then this flag is set.

D4 Wrong WC This bit is related to the ND bit, and when

Cylinder the contents of C on the medium are
different from that stored in the ID
register, this flag is set.
D3 Scan Equal SH During execution of the scan command, if
Hit the condition of "equal" is satisfied, this
flag is set.
D2 Scan Not SN During execution of the scan command,
Satisfied if the FDC cannot find a sector on the
cylinder that meets the condition, then
this flag is set.
D1 Bad Cylinder BC This bit is related to the N D bit, and when
the contents of C on the medium are
different from that stored in the ID
register, and the contents of C is FF, then
this flag is set.
DO Missing MD When data is read from the medium, if
Address Mark the FDC cannot find a data address mark
in Data Field or deleted data address mark, then this
flag is set.

Command Status Register 2

16 Diskette Adapter
 Bit
No. Name Symbol Description
07 Fault FT This bit is the status of the fault signal
from the FDD.
06 Write WP This bit is the status of the
Protected write-protected signal from the FDD.
05 Ready RY This bit is the status of the ready signal
from the FDD.
04 Track 0 TO This bit is the status of the track 0 signal
from the FDD.
03 Two Side TS This bit is the status of the two-side
signal from the FDD.
02 Head Address HD This bit is the status of the side-select
signal from the FDD.
01 Unit Select 1 US 1 This bit is the status of the unit-select-1
signal from the FDD.
DO Unit Select 0 USO This bit is the status of the unit-select-O
signal from the FDD.

Command Status Register 3

Programming Summary
FDC Data Register I/O Address Hex 3F5
FDC Main Status Register I/O Address Hex 3F4
Digital Output Register I/O Address Hex 3F2
BitO Drive 00: DR #A 10: DR #C
1 Select 01:DR#B 11 : DR #0
2 Not FDC Reset
3 Enable INT & DMA Requests
4 Drive A Motor Enable
5 Drive B Motor Enable
6 Drive C Motor Enable
7 Drive 0 Motor Enable
All bits cleared with channel reset.

OPC Registers

Diskette Adapter 17
FDC Constants (in hex)

N: 02 GPL Format: 05
SC: 08 GPLR/W: 2A
HUT: F HLT: 01
SRT: C (6 ms track-to-track)

Drive Constants
Head Load 35 ms
Head Settle 15 ms
Motor Start 250 ms

Comments

• Head loads with drive select, wait HD load time before R/W.

• Following access, wait HD settle time before R/W.

• Drive motors should be off when not in use. Only A or Band

Cor D may run simultaneously. Wait motor start time before
R/W.

• Motor must be on for drive to be selected.

• Data errors can occur while using a home television as the

system display. Placing the TV too close to the diskette area
can cause this to occur. To correct the problem, move the TV
away from, or to the opposite side of the system unit.

18 Diskette Adapter
Interface

System 1/0 Channel Interface

All signals are TTL-compatible:

Most Positive Up Level +5.5 Vdc

Least Positive Up Level +2.7Vdc
Most Positive Down Level +0.5 Vdc
Least Positive Down Level -0.5 Vdc

The following lines are used by this adapter.

+00-7 (Bidirectional, Load: 1 74LS, Driver: 74LS 3-state):

These eight lines form a bus through which all
commands, status, and data are transferred. Bit 0 is
the low-order bit.

+AO-9 (Adapter input, Load: 1 74LS): These 10 lines form an

address bus by which a register is selected to receive or
supply the byte transferred through lines DO-7. Bit 0
is the low-order bit.

+AEN (Adapter input, load: 1 74LS): The content of lines

AO-9 is ignored if this line is active.

-lOW (Adapter input, Load: 1 74LS): The content of lines

DO-7 is stored in the register addressed by lines AO-9
or DACK2 at the trailing edge of this signal.

-lOR (Adapter input, Load: 1 7 4LS): The content of the

register addressed by lines AO-9 or DACK2 is gated
onto lines DO-7 when this line is active.

-DACK2 (Adapter input, load: 2 74LS): This line being active

degates output DRQ2, selects the FDC data register as
the source or destination of bus DO-7, and indirectly
gates T / C to IRQ6.

Diskette Adapter 19
+T/C (Adapter input, load: 4 74LS): This line along with
DACK2 being active indicates that the byte of data for
which the DMA count was initialized is now being
transferred.

+RESET (Adapter input, load: I 74LS): An up level ends any

operation in process and clears the digital output
register (DOR).

+DRQ2 (Adapter output, driver: 74LS 3-state): This line is

made active when the attachment is ready to transfer a
byte of data to or from main storage. The line is made
inactive by DACK2 becoming active or an I/O read of
the FDC data register.

+IRQ6 (Adapter output, driver: 74LS 3-state): This line is

made active when the FDC has completed an
operation. It results in an interrupt to a routine that
should examine the FDC result bytes to reset the line
and determine the ending condition.

Drive A and B Interface

All signals are TTL-compatible:

Most Positive Up Level + 5.5 Vdc

Least Positive Up Level + 2.4 Vdc
Most Positive Down Level + 0.4 Vdc
Least Positive Down Level - 0.5 Vdc

All adapter outputs are driven by open-collector gates. The

drives must provide termination networks to Vcc (except 'motor
enable', which has a 2,000-ohm resistor to Vcc).

Each adapter input is terminated with a I 50-ohm resistor to Vcc.

20 Diskette Adapter
Adapter Outputs

-Drive Select A and B (Driver: 7438): These two lines are

used by drives A and B to degate all
drivers to the adapter and receivers
from the attachment (except 'motor
enable') when the line associated
with a drive is inactive.

- Motor Enable A and B (Driver: 7438): The drive associated

with each of these lines must control
its spindle motor such that it starts
when the line becomes active and
stops when the line becomes
inactive.

-Step (Driver: 7438): The selected drive

moves the read/write head one
cylinder in or out per the direction
line for each pulse present on this
line.

-Direction (Driver: 7438): For each recognized

pulse of the 'step' line, the
read/write head moves one cylinder
toward the spindle if this line is
active, and away from the spindle if
inactive.

- Head Select (Driver: 7438): Head 1 (upper

head) will be selected when this line
is active (low).

-Write Data (Driver: 7438): For each

inactive-to-active transition of this
line while 'write enable' is active, the
selected drive causes a flux change
to be stored on the diskette.

-Write Enable (Driver: 7348): The drive disables

write current in the head unless this
line is active.

Diskette Adapter 21
Adapter Inputs

-Index The selected drive must supply one pulse per

diskette revolution on this line.

- Write Protect The selected drive must make this line active
if a write-protected diskette is in the drive.

-Track 0 The selected drive must make this line active

if the read/write head is over track O.

-Read Data The selected drive supplies a pulse on this

line for each flux change encountered on the
diskette.

22 Diskette Adapter
Specifications
34- Pin Keyed
Edge Connector

Component
Side

Note: Lands 1-33 (odd numbers) are on the back of the

board. Lands 2-34 (even numbers) are on the front. or
component side.

At Standard TTL Levels Land Number

Ground-Odd Numbers 1-33
Unused 2.4.6
Index 8
Motor Enable A 10
Drive Select B 12
Drive Select A 14
Motor Enable B 16
Diskette Direction (Stepper Motorl 18 Drive
Drives Step Pulse 20 Adapter
Write Data 22
Write Enable 24
Track 0 26
Write Protect 28
Read Data 30
Select Head 1 32
Unused 34

Connector Specifications (Part 1 of 2)

Diskette Adapter 23
 37-Pin D-Shell
Connector
o
1 • • 20

19 • 37
o

At Standard TTL levels Pin Number

Unused 1-5
Index 6
Motor Enable C 7
Drive Select D 8
Drive Select C 9
Motor Enable D 10
Direction (Stepper Motor) 11

External Step Pulse 12 Drive

Drives Write Data 13 Adapter
Write Enable 14
Track 0 15
Write Protect 16
Read Data 17
Select Head 1 18
Ground 20-37

Connector Specifications (Part 2 of 2)

24 Diskette Adapter
 (2) + El'A8LE DRtVE 314
!2) - ENABl.E DAM 314
+",11> 2118

~~~~~~~~~~~~~~~~~~~~~"~-g"~"~-'~~i: ~:I~~~~o~,~~~~~~~ ~~'i'§~~~+INDEX

(2) _ DRIVE SELECT 1
(21 - DftM SELECT 2 II> + IoORITEPI'IOTECT (3)
t31
(2) _ MOTOR ENA8LE 1
:; + 1R,"CII 0 :::
(2) _ MOTOR ENABlE 2

'"
'"
'"
(S) + WRITE DATA

~~~~g~, ~,~il"~
lSI + WRITE ENABlE
(2) _ DRIVE SELECT 3
!2) _ DflIV£SELECT4
(2) _ MOTOftENABl.E3 10 DR[VES3&4 n
(2) _ MOTOR ENABLE 4
NOTES I &2

+'" 11>2K 3 '"

"e +AO
+A1
(2)
(2)
8'16-1 1/4'" ~
PROCESSOR Al'l +A2 (2)
RP-2
" .. A3
+A4
(2)
(2)
+A5 (2)
+A6 (2)
+A7 t2}
," .. A6 (2)

'"'"
+A9 (2)
I SIGNALS ON DRIVE PINS 10 THRU II> ARE SWAPPED BV THE DRIVE (ABLE

:~ :~ ".
,e,
+AEN
-lOR
(ll
12)

:~
TIO
:~ 8.21lFD
'" :~~ET l!:
14
I')
12
II
'"
,e'
,e,
_ +TC
_ _ +00
+01
(3)
(2)
(2)
II> TO 10
'"
'CO
,"
+02
_ _ _ +03
(2)
(2)
2 ALL DRiVES ARE JUMPERED FOR MULTIPLO OPERAT[ON. HEAD LOAD
WITH DRIVE SELECT AND DRIVE SELECT ViA INPUT PIN 12. TERMINATlNG
,,. .. 04
_ _ _ +05
(2)
(2)

:g~
_ _ +06 (2)
_ _ _ +07 (2)
rn .0'11 ",FO SHOULD BE ADJACENT TO MODU~ES MC ,'161. 1'+.8. 7451'1.lbMHZOSC.
RI'-I.I1C'I0'fI.11{'I02'I,74L5Ibl&74LSI'I1 B.2"Fl)CAPSSHOULD8ENEARAS'i)(lATED~ PltlS '"
_ _ _ OACK2 (3)

[LD ALL SlGtlAL UNES H["HER THAN OR EQUAL TO IMHZ SHOULD BE IIEPT TO THE
SHORTEST 'POSSIBLE LENGTH. THIS IS A PRIMARV DESIGN GOAL

') MAKE NO CONNEClIOt< TO UNUSED PINS ON 1HE VCO. CHARGE PUMP & DATA SEI'!!IRATOR MODULES

b ALL VOLTAGE AND (,ROUtlD eONtiECTIONS TO THE veo. CHARGE PUMP AND ASSOCIATED DISCRETE
COMPONENTS SHOULD 6E SEPARATE FROM OTHER CIRCUITS AND THEN JOINED TO THE OTHER
CiRCUITS AT ONE POINT

5-1/4 Inch Diskette Drive Adapter (Sheet 1 of 4)

 ~~...L--
''"" --~~ GATE- +ENABLE DRIVE 3/4
7"LG~
,,
& ENABLE DRIVE 314
''""
'"
(1) +A<;
,
u,"
,I, 1

K:~'
11, +Ab
(1)
(1)
+A7
+AB
7'+:18,
I,
'"
, 74~~ L
(1) +A9
u"
~'SO»'~'----l1~~:~~,'~"r,'~~~====jt=L~~~-----------
,I
~ ~ rV UZ9
L __ -.JuIS
DRIVE SELECT 3
'"

~ ,"'mJ
----r---;======4::j"tl--' Ag~ ~I;~~~lll
~ ~ g~ :~ ~
(11 +AZ
II 6 U 14

U 13 ~ ===it g~ :; 1: tH2 ~ 17~3a-"1

q g; ~llq ~Ir'''-'--++---~=--=--=":i:'t-=!L.fT''------------
'~13
10 7'+LS12 8

I~Kt !~I :7'*'18-":

'"
~7 ~ 2~ 3
'"
lr I
LJ-______-l-____________-W+t:j,,:tl:[)~~"'------------MOTORENA8LEl
7LtlS01t J2 7'+38-4
(1) +RESET ----1-1---------''-1 2 (t)

J
Ll--______+-__________--+-lJ:::~,,~l:[).__t-'·'------------MOTOA
UI2 9 1"38-'1

ENABLE 2 (1)

__ ..J U ..

91
L-l-____________________-W===::l,,4=:[)~.lL-----------MOTOR
7'1'18-'118
ENABLE 3 (1)
p, -DA"
(3) Dl.CK&lt 12 ~ 14i8--I j'

'"'" 'D'
.00 L---t====================~==jt~==~~"=-----------
13

L_---1ulS
MQTORENABLE4 (1)

.02
'" 'D'
'"'"'" 'D'
.",

.""
'"'" .D7 '"
."
'''"""
HO

(1) -IOR

5-1/4 Inch Diskette Drive Adapter (Sheet 2 of 4)

 ,
, +lbMHZ 14}

+"i00 KHZ WRiTE CLOCK 14}

r
IK~~~
MR2 GlI'l
, t2 MHZ (21

~roo--oo2 ,

C::
+WRITE DATA III

D I~(~
+2TRQbNC TR 10 .----- ,
" ~~ R~:
.2 8 <A 7 + DIRECTION III
4 CLK!
~Ol
OSC.
~ ---L: ~-~CLKI
n .. we
CPI Qi :>--N( ~2A
7 .". I CLF 7 14 PO Q~ II = IS CLR ~~A
~D2 Q2~ IrEA
= NOTE 5J 74lS10'l ~ 14LS10"
~OB r-'!---
U2
"' U2 ~D~ ~~NC II IB
YB

" c8J ',,,,

,-!-< CLR Q1
~- r----R- 28
2 I ~
e'lB-1
., -
2K
RP-2
----3! We< wDA '>0 U \I
2"iOnSEC
Et1B
" E8
WRITE PRE(QMP06A110N
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5-1/4 Inch Diskette Drive Adapter (Sheet 3 of 4)

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-- -
--
--- --
-- ---
- ---
---
Personal Computer
--- -
,- Hardware Reference
Library

mM Fixed Disk
Adapter

6361503
ii
Contents

Description .................................... 1
Fixed Disk Controller ........................ 1
Programming Considerations ...................... 3
Status Register ............................. 3
Sense Bytes ................................ 4
Data Register .............................. 7
Control Byte ............................... 8
Command Summary ........................ 10
Programming Summary ...................... 14
Interface ..................................... 15
Specifications ................................. 17
Logic Diagrams ................................ 19
BIOS Listing .................................. 25

iii
it>
Description

The Fixed Disk Adapter attaches to one or two fixed disk drive
units through an internal, daisy-chained, flat cable (datal control
cable). Each system supports a maximum of one Fixed Disk
Adapter and two fixed disk drives.

The adapter is buffered on the I/O bus and uses the system
board's direct memory access (DMA) for record data transfers.
An interrupt level also is used to indicate operation completion
and status conditions that require microprocessor attention.

The Fixed Disk Adapter provides automatic II-bit burst error

detection and correction in the form of 32-bit error checking and
correction (ECC).

The device level control for the Fixed Disk Adapter is contained
on a ROM module on the adapter. A listing of this device level
control can be found in "BIOS Listing" of this section.

Warning: The last cylinder on the fixed disk drive is reserved

for diagnostic use. The diagnostic write test will destroy any
data on this cylinder.

Fixed Disk Controller

The disk controller has two registers that may be accessed by the
system unit's microprocessor: a status register and a data register.
The 8-bit status register contains the status information of the
disk controller, and can be accessed at any time. The 8-bit data
register (actually consisting of several registers in a stack with
only one register presented to the data bus) stores data,
commands, and parameters, and provides the disk controller's
status information. Data bytes are read from, or written to the
data register in order to program or obtain the results after a
particular command. The status register is a read-only register
that is used to help the transfer of data between the system unit's
microprocessor and the disk controller. The controller-select
pulse is generated by writing to port address hex 322.

Fixed Disk Adapter 1

 Serializer /
Deserializer
J2
To
SERDES Data } Drives
ECC Separator

Edge
Connector

Data Bus
OB7-DBO
Control Sector
Buffer

a-Bit
Processor

.Fixed Disk Adapter Block Diagram

Programming Considerations

Status Register
At the end of all commands from the system board, the disk
controller sends a completion status byte to the system board.
This byte informs the system unit's microprocessor if an error
occurred during the execution of the command. The following
shows the format of this byte.

~I
6 5 4 3 2
o d o o o e

Bits 0, 1, 2, 3, 4, 6, 7 These bits are set to zero.

Bit 1 When set, this bit shows an error has

occurred during command execution.

Bit 5 This bit shows the logical unit number

of the drive.

If the interrupts are enabled, the controller sends an interrupt

when it is ready to transfer the status byte. Busy from the disk
controller is unasserted when the byte is transferred to complete
the command.

Fixed Disk Adapter 3

Sense Bytes
If the status register receives an error (bit 1 set), the disk
controller requests four bytes of sense data. The format for the
four bytes is as follows:

Bits 7 6 5 4 3 2 1 0
Byte 0 Address Error Type Error Code
Valid I o I I
Byte 1 0 0 d
I Head Number
Byte 2 Cylinder High I Sector Number
Byte 3 Cylinder Low

Remarks
d = drive

Byte 0 Bits 0, 1, 2, 3 Error code.

Byte 0 Bits 4,5 Error type.

Byte 0 Bit 6 Set to 0 (spare)

Byte 0 Bit 7 The address-valid bit. Set only when

the previous command required a
disk address, in which case it is
returned as a 1; otherwise, it is O.

4 Fixed Disk Adapter

Disk Controller Error Tables
The following disk controller error tables list the error types and
error codes found in byte 0:

Error Type Error Code

Bits 5 4 3 2 1 0 Description
0 0 0 0 0 0 The controller did not detect any error
during the execution of the previous
operation.
0 0 0 0 0 1 The controller did not detect an index signal
from the drive.
0 0 0 0 1 0 The controller did not get a seek-complete
signal from the drive after a seek operation
(for all non-buffered step seeks).
0 0 0 0 1 1 The controller detected a write fault from
the drive during the last operation.
0 0 0 1 0 0 After the controller selected the drive, the
drive did not respond with a ready signal.
0 0 0 1 0 1 Not used.
0 0 0 1 1 0 After stepping the maximum number of
cylinders, the controller did not receive the
track 00 signal from the drive.

0 0 0 1 1 1 Not used.
0 0 1 0 0 0 The drive is still seeking. This status is
reported by the Test Drive Ready command
for an overlap seek condition when the
drive has not completed the seek. No
time-out is measured by the controller for
the seek to complete.

Fixed Disk Adapter 5

 Error Type Error Code
Bits 5 4 3 2 1 0 Description
0 1 0 0 0 0 ID Read Error: The controller detected an
ECC error in the target ID field on the disk.
0 1 0 0 0 1 Data Error: The controller detected an
uncorrectable ECC error in the target sector
during a read operation.
0 1 0 0 1 0 Address Mark: The controller did not detect
the target address mark (AM) on the disk.
0 1 0 0 1 1 Not used.
0 1 0 1 0 0 Sector Not Found: The controller found the
correct cylinder and head, but not the
target sector.
0 1 0 1 0 1 Seek Error: The cylinder or head address
(either or both) did not compare with the
expected target address as a result of a
seek.
0 1 0 1 1 0 Not used.

0 1 0 1 1 1 Not used.
0 1 1 0 0 0 Correctable Data Error: The controller
detected a correctable ECC error in the
target field.
0 1 1 0 0 1 Bad Track: The controller detected a bad
track flag during the last operation. No
retries are attempted on this error.

Error Type Error Code

Bits 5 4 3 2 1 0 Description
1 0 0 0 0 0 Invalid Command: The controller has
received an invalid command from the
system unit.
1 0 0 0 0 1 Illegal Disk Address. The controller
detected an address that is beyond the
maximum range.

6 Fixed Disk Adapter

 Error Type Error Code
Bits 5 4 3 2 1 0 Description
1 1 0 0 0 0 RAM Error: The controller detected a data
error during the RAM sector-buffer
diagnostic test.
1 1 0 0 0 1 Program Memory Checksum Error: During
this internal diagnostic test, the controller
detected a program-memory cheCksum
error.
1 1 0 0 1 0 ECC Polynominal Error: During the
controller's internal diagnostic tests, the
hardware ECC generator failed its test.

Data Register
The system unit's microprocessor specifies the operation by
sending the 6-byte device control block (DCB) to the controller.
The figure below shows the coniposition of the DCB, and defines
the bytes that make up the DCB.

Bit 7 6 5 4 3 2 1 0
Byte 0 Command Opcode
Class
Byte 1 0 0 d Head Number
Byte 2 Cylinder High
I Sector Number
Byte 3 Cylinder Low
Byte 4 Interleave or Block Count
Byte 5 Control Field

Byte 0 Bits 7, 6, and 5 identify the class of the command.

Bits 4 through 0 contain the Opcode command.

Byte 1 Bit 5 identifies the drive number. Bits 4 through 0

contain the disk head number to be selected. Bits
6 and 7 are not used.

Fixed Disk Adapter 7

Byte 2 Bits 6 and 7 contain the two most significant bits
of the cylinder number. Bits 0 through 5 contain
the sector number.

Byte 3 Bits 0 through 7 are the eight least-significant bits

of the cylinder number.

Byte 4 Bits 0 through 7 specify the interleave or block

count.

Byte 5 Bits 0 through 7 contain the control field.

Control Byte
Byte 5 is the control field of the DeB and allows the user to
select options for several types of disk drives. The format of this
byte is as follows:

I I
Bits
7
r
6
a
5
0
4
0
3
0
2
s s ~I
Remarks
r = retries
s = step option
a = retry option on data ECC
error

Bit 7 Disables the four retries by the controller on all

disk-access commands. Set this bit only during the
evaluation of the performance of a disk drive.

Bit 6 If set to 0 during read commands, a reread is

attempted when an Eee error occurs. If no error
occurs during reread, the command will finish
without an error status. If this bit is set to 1, no
reread is attempted.

Bits 5, 4, 3 Set to O.

8 Fixed Disk Adapter

Bits 2, 1, 0 These bits define the type of drive and select the
step option. See the following figure.

Bits 2. 1. 0
0 0 0 This drive is [lot specified and defaults to 3 milliseconqs per
steP
0 0 1 N/A
0 1 0 N/A
0 1 1 N/A
1 0 0 200 microseconds per step.
1 0 1 70 microseconds per step (specified by BIOS).
1 1 0 3 milliseconds per step.
1 1 1 3 milliseconds per step.

Fixed Dislt Adapter 9

Command Summary

Command Data Control Block Remarks

Test Drive Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1)

Ready Byte 0 0 0 010 0 0 0 0 x = don't care
(Class 0, Byte 1 0 0 d Ix x x x x Bytes 2, 3, 4, 5 = don't
Opcode 00) care

Recalibrate Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

(Class 0, Byte 0 0 0 01 0 0 0 0 1 x = don't care
Opcode 01) Byte 1 0 0 d Ix x x x x r = retries
Byte 5 r 0 0 0 0 s s s s = Step Option
Bytes 2, 3, 4 = don't
care
ch = cylinder high

Reserved This Opcode is not

(Class 0, used.
Opcode 02)
Request Sense Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )
Status Byte 0 0 0 01 0 0 0 1 1 x = don't care
(Class 0, Byte 1 0 0 d Ix x x x x Bytes 2, 3, 4, 5 = don't
Opcode 03) care

Format Drive Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

(Class 0, Byte 0 0 0 01 0 0 1 0 0 r = retries
Opcode 04) Byte 1 0 0 d I Head Number s = step option
Byte 2 ch 10 0 0 0 0 0 ch = cylinder high
Byte 3 Cylinder Low
Byte 4 0 0 01 Interleave Interleave 1 to 16
Byte 5 r 0 0 0 0 s s s for 51 2-byte sectors.

Ready Verify Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

(Class 0, Byte 0 0 0 01 0 0 1 0 1 r = retries
Opcode 05) Byte 1 0 0 I
d Head Number s = step option
Byte 2 ch I Sector Number a = retry option on
Byte 3 Cylinder Low data ECC
Byte 4 Block Count ch = cylinder high
Byte 5 r a 0 0 0 s s s

10 Fixed Disk Adapter

Command Data Control Block Remarks

Format Track Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

(Class 0, Byte 0 0 0 010 0 1 1 0 r = retries
Opcode 06) Byte 1 0 0 d I Head Number s = step option
Byte 2 ch 10 0 0 0 0 0 ch = cylinder high
Byte 3 Cylinder Low
Byte 4 0 0 01 Interleave Interleave 1 to 16
Byte 5 r 0 0 0 0 s s s for 512-byte sectors.

Format Bad Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

Track Byte 0 0 0 010 0 1 1 1 r = retries
(Class 0, Byte 1 0 0 d I Head Number s = step option
Opcode 07) Byte 2 ch 10 0 0 0 0 0 ch = cylinder high
Byte 3 Cylinder Low
Byte 4 0 0 01 Interleave Interleave 1 to 16
Byte 5 r 0 0 0 0 s s s for 512-byte sectors.

Read Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

(Class 0, Byte 0 0 0 0[0 1 0 0 0 r = retries
Opcode 08) Byte 1 0 0 d I Head Number a = retry option on
Byte 2 ch I Sector Number data ECC error
Byte 3 Cylinder Low s "" step option
Byte 5 r a 0 0 0 s s s ch = cylinder high

Reserved This Opcode is not

(Class 0, used.
Opcode 09)

Write Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

(Class 0, Byte 0 0 0 010 1 0 1 0 r = retries
Opcode OA) Byte 1 0 0 d I Head Number s = step option
Byte 2 ch I Sector Number ch = cylinder high
Byte 3 Cylinder Low
Byte 4 Block Count
Byte 5 r 0 0 0 0 s s s

Seek Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1)

(Class 0, Byte 0 0 0 010 1 0 1 1 r = retries
Opcode OB) Byte 1 0 0 d I Head Number s '" step option
Byte 2 ch 10 0 0 0 0 0 x = don't care
Byte 3 Cylinder Low ch = cylinder high
Byte 4 x x x x x x x x
Byte 5 r 0 0 0 0 s s s

Fixed Disk Adapter 11

 Command Data Control Block Remarks

Initialize I Bit 17 6 5 4 3 2 1 01 Bytes 1, 2, 3, 4, 5, =

Drive I Byte 0 10 0 010 1 1 0 01 don't care
Characteristics *
(Class 0,
OpcodeOC)

Read ECC Burst I Bit 17 6 5 4 3 2 1 01 Bytes 1, 2, 3, 4, 5, =

Error Length I Byte 0 10 0 01 0 1 1 0 1I don't care
(Class 0,
Opcode OD)

Read Data from LBit 17 6 5 4 3 2 1 01 Bytes 1, 2, 3, 4, 5, =

Sector Buffer IByteO 10 0 OlO 1 1 1 01 don't care
(Class 0,
Opcode OE)

Write Data to I Bit 17 6 5 4 3 2 1 01 Bytes 1, 2, 3, 4,5, =

Sector Buffer IByte 0 10 0 010 1 1 1 1 I don't care
(Class 0,
Opcode OF)

RAM I Bit 17 6 5 4 3 2 1 01 Bytes 1, 2, 3,4,5, =

Diagnostic IByte 0 11 1 1 [0 0 0 0 01 don't care
(Class 7,
Opcode 00)

Reserved This Opcode is not

(Class 7, used.
Opcode 01)

Reserved This Opcode is not

(Class 7, used.
Opcode 02)

*Initialize Drive Characteristics: The DBC must be followed by eight additional bytes.
Maximum number of cylinders (2 bytes)
Maximum number of heads (1 byte)
Start reduced write current cylinder (2 bytes)
Start write precompensation cylinder (2 bytes)
Maximum ECC data burst length (1 byte)

12 Fixed Disk Adapter

 Command Data Control Block Remarks

Drive Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

Diagnostic Byte 0 1 1 1 10 0 0 1 1 s = step option
(Class 7, Byte 1 0 0 dlx x x x x r = retries
Opcode 03) Byte 2 x x x x x x x x x = don't care
Byte 3 x x x x x x x x
Byte 4 x x x x x x x x
Byte 5 r 0 0 0 0 s s s

Controller I Bit 7 6 5 4 3 2 1 0 Bytes 1, 2, 3, 4,5, =

Internal I Byte 0 1 1 1 10 0 1 0 0 don't care
Diagnostics
(Class 7,
Opcode 04)

Read Long* Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

(Class 7, Byte 0 1 1 1 10 0 1 0 1 s = step option
Opcode 05) Byte 1 0 0 d I Head Number r = retries
Byte 2 ch J Sector Number ch = cylinder high
Byte 3 Cylinder Low
Byte 4 Block Count
Byte 5 r 0 0 0 0 s s s

Write Long * * Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

(Class 7, Byte 0 1 1 1 10 0 1 1 0 s = step option
Opcode 06) Byte 1 0 0 d I Head Number r = retries
Byte 2 ch I Sector Number ch = cylinder high
Byte 3 Cylinder Low
Byte 4 Block Count
Byte 5 r 0 0 0 0 s s s

*Returns 512 bytes plus 4 bytes of ECC data per sector.

* *Requires 512 bytes plus 4 bytes of ECC data per sector.

Fixed Disk Adapter 13

Programming Summary
The two least-significant bits of the address bus are sent to the
system board's I/O port decoder, which has two sections. One
section is enabled by the I/O read signal ( -lOR) and the other by
the I/O write signal (-lOW). The result is a total of four
read/write ports assigned to the disk controller board.

The address enable signal (AEN) is asserted by the system board

when DMA is controlling data transfer. When AEN is asserted,
the I/O port decoder is disabled.

The following figure is a table of the read/write ports.

R/W Port Address Function

Read 320 Read data (from controller to system unitl.
Write 320 Write data (from system unit to controllerl.
Read 321 Read controller hardware status.
Write 321 Controller reset.
Read 322 Reserved.
Write 322 Generate controller-select pulse.
Read 323 Not used.
Write 323 Write pattern to DMA and interrupt mask
register.

14 Fixed Disk Adapter

Interface

The following lines are used by the disk controller:

AO-AI9 Positive true 20-bit address. The least-significant 10

bits contain the I/O address within the range of hex
320 to hex 323 when an I/O read or write is
executed by the system unit. The full 20 bits are
decoded to address the read-only memory (ROM)
between the addresses of hex C8000 and C9FFF.

DO-D7 Positive 8-bit data bus over which data and status
information is passed between the system board and
the controller.

-lOR Negative true signal that is asserted when the system

board reads status or data from the controller under
either programmed I/O or DMA control.

-lOW Negative true signal that is asserted when the system

board sends a command or data to the controller
under either programmed I/O or DMA control.

AEN Positive true signal that is asserted when the DMA in

the system board is generating the I/O Read (-lOR)
or I/O Write (-lOW) signals and has control of the
address and data buses.

RESET Positive true signal that forces the disk controller to

its initial power-up condition.

IRQ 5 Positive true interrupt-request signal that is asserted

by the controller when enabled to interrupt the
system board on the return ending status byte from
the controller.

DRQ3 Positive true DMA-request signal that is asserted by

the controller when data is available for transfer to
or from the controller under DMA control. This
signal remains active until the system board's DMA
channel activates the DMA-acknowledge signal
(-DACK 3) in response.

Fixed Disk Adapter 15

-DACK 3 This signal is true when negative, and is generated by
the system board DMA channel in response to a
DMA request (DRQ 3).

16 Fixed Disk Adapter

Specifications

The Fixed Disk Adapter connector and interface specifications

follow.

Fixed Disk Adapter 17

 Pin 34 fil~l~,::,
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Pin 20rru!ZlJ!-...'
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Pin 2~2~ ,-
Position 5 has No Pin
(for Cable Orientation)
Pin 1
Signal Pin Number
Ground-Odd Numbers 1-33
Reserved 4.16.30.32
- Reduced Write Current 2
- Write Gate 6
- Seek Complete 8
Disk - Track 00 10 Disk
Drive - Write Fault 12 Adapter
Connector - Head"Select 2° 14 Connector
J1 - Head Select 2' 18 J1
-Index 20
- Ready 22
-Step 24
- Drive Select 1 26
- Drive Select 2 28
- Direction In 34

Signal Pin Number

Ground 2.4.6.8.12.16.20
Drive Select 1
Reserved 3,7
Spare 9.10.5 (No Pin)

Disk Ground 11 Disk

Drive MFM Wire Data 13 Adapter
Connector - MTM Write Data 14 Connector
J2orJ3 Ground 15 J2 or J3
MFM Read Data 17
- MFM Read Data 18
Ground 19

Fixed Disk Adapter Interface Specifications

18 Fixed Disk Adapter

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Fixed Disk Adapter (Sheet 1 of 6)

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01 15 lS04 2B 1 n +
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ill
vee", 11 27
~r-- •
14 vee 35
~ 3.'
GNO=29
'-7 VCC=31.5
GND=20
29
30
01
D
3. GND -15 32
3

=t~~:,t::~:r.:r:;r~rAII:i= :1:1::~:4 :b1

36
~
31
lJ'"'V 11

16
I .81: 33~1~1:738 40 Bl 00 D5 0302100

882ZK DIP A Al AZ A3A4A5A6 7 AD DISKU1

,
BH
22KDlP
5 5 7F 6
t>-.:
j AD +AO
•
·· ,, .
~

~
+A1
All 21
R~+ 11 0
~

~• I•"
~ 7f 3 ~-!::-

~
A5
~ "VA ~
LS3 AS A9
LSI 13 9F 0 !!...!!Z.
~LS257 7 ISUC.1 11 0 2148
02 !l....!!fi.. E"OJD2~
~
~
2732
t:::lsYG PROM 01 ~ ~21~1~

' t -~ I--
4 1H 0-

-;:1l t:! • 17
AD DI ~ ¥,=t oo~
~
• 6 AQ DO
5 ~ CSOE
AD , ~ csiE '·'-P~iiiE I TE N l T BUS 3.1

~12
I' 8ll-
S-
~' 3 LS3Z IOLS
11
9
11
1H
'Y"
rr T EHOUT
1,3
1

- a;P." 00
~LS74'3 12:l_.
11 8 11 10~l 9
lS04 ~3
.51

Fixed Disk Adapter (Sheet 2 of 6)

 +POWERCLOCK

6 -READ GATE -DELAY CLOCK

R10
41n 4MHZCLK
+ROGATE

+SElDR2

SEL~~~3S=t::===iE
-ORASEL
-ORB
-INDEX
11
13
+SELDRT

~14lh~~ATOR
+tNDEX

,>O,!'.6_ _ _ _ _ _ _ _~2B~~----'-~A.'!!..!!!"':!!SEc!.T----> 5.6

W DIP 06
;-".,!!..,..--------r-:mrl -REDUCE WRITE CURRENT
~_ _-..-.J<::..J!!!L.l!I ;-".,!!......-----<ID4l -DIRECTION
'A, 3 B 3 12
"><"""~-------<-:m!4l -STEP
15 tCIB
142G
f
0 ~---~~ ;-"'~-----<=n -HD2

~:~:.~IS~@~[:====::i±~~ :f- ~
LSI55 1 6
f')c;:¥'--""---------r-:miB"l -HDl
I~---~~ -HDO
-RESET

,,
+WRITEGATE
2B
-READY GiJj:j'·!D~---.......,*-'-~<m-:::T.1.l!-~[;d
03
, 4.6

28 ::~~: ~8 D2 ).!!-:------<mo -DRIVE SELECT T

-SEEKCOMPCj~~====~::t=~
-WRITE FAULT ( -12
28 3 lB YB: 4
Dl
DO P-'---------<mn -DRIVESELECTO
28 5 lB 2A Y8
-TRACK 0 Q[j,.,[[)~-----",*,'--<:C!.~;:J
TERM lS2411 ~------<mn -WRITE GATE

Fixed Disk Adapter (Sheet 3 of 6)

 +DELDATA
~
~ -ClAMPVCO

~
~ WINDOW CLOCK
+NRZ DO DATA
2.6

Q.

a:>0 +ENABLE NRl DATA

-NRIClOCK
2.6

t
.
'a 10 MHZ CRVSTAL
5.6
~

+MFMWRO
-MFMWRO

+MFMWRI
-MIIMWRI

""1.",C.",EA",S,",,,,,,,,,,,C,,,OM,,"P~I~X 2B·13 J2.J3,GNOPINS

2,4.6.8.10,
06 TERM .48 11,12,15.16.19.20

.
-INCREASE PRECOMP
-TESTENA L
All +5V

"
Fixed Disk Adapter (Sheet 4 of 6)
 WINODWClK
+ DEL DATA

J-'
+5VA

-1
J3-1 TPB

'38
33"

-CLAMP VCO
\'1"" AG5l0pF
9'"

-AM DETECT
'_6
+ RD GATE
-AM RESET

Fixed Disk Adapter (Sheet 5 of 6)

 4) -HAl WR DATA J4
3)-AMRESET ~
tt5

I·~·i
.;,." .Bom '5'
3 >-Wi AM [L:>
5)=:~ D:~~ DD
J4
~1,3.7"1
IK
.48
04.
:;~-~'.~C'~'A~S~'..P',,'C"B._P________________~~
>--RO GATE crr::> ':' TEST CONNECTOR .SO
: :> 10 MHZ CRYSTAL UI:> .51

4:> -TEST EHABlE ~m::>

J4
+t2V

r-------------.u-----------,
l 3300 TO 202 PACKAGE I
I I
: L.320MP5.0 I
I IQ·OII--t-----~::-:-----.,_--~~ -5VA
I CI G
I
I ~ I
4MHZClDCK
I I
I
I
IL___ ____________________________ J I

~
D +5V6LTS
83.829

rpg TP10
GROUItD
Bl,BID,B31

B9
o +12VOLTS

NOTES:
UNLESS OTHERWISE SPECIFIED:
1. All RESISTOIIS 1/4 W,5'\'1, CARBON FILTER.
2. ALL CAPS +10V DR BREATER+ID%.
3. NO MORE THAN 15 lOADS PER PULLUP NET.

Fixed Disk Adapter (Sheet 6 of 6)

BIOS Listing

The BIOS Listing for the IBM Fixed Disk Adapter follows.

Fixed Disk Adapter 25

LaC OBJ LINE SOURCE

$TITLE( FIXED DISK BIOS FOR IBM DISK CONTROLLER)

j w_ IHT 13 -------------------- _________________________________ _

; FIXED DISK lID INTERFACE

THIS INTERFACE PROVIDES ACCESS TO 5 1/4" FIXED 0151(5

THROUGH THE IBM FIXED DISK CONTROLLER.

10 j -- - - -- ---------------------- - --- - - - - - - --- - - - - -- - -------- - -------

11
12 ; - - - - - - - - - - - - ------ -- - --- - ----- -- - - - - ----- - --------- ----- --------
13 THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH
14 SOFTWARE INTERRUPTS ONLY. ANY ADDRESSES PRESENT IN
15 THE LISTINGS ARE INCLUDED ONLY FOR COMPLETENESS.
16 NOT FOR REFERENCE. APPLICATIONS WHICH REFERENCE
17 ABSOLUTE ADDRESSES WITHIN THE CODE SEGMENT
18 VIOLATE THE STRUCTURE AND DESI~N OF BIOS.
19 ; ------------------------~--------.------------------------------
2.
21 i INPUT (AH = HEX VALUE)
22
23 IAH)=OO RESET DISK ~Dl. = 80H,61H) I PISKETTE
2. (AH 1=01 READ THE STAnJS OF THE LAST DISK OPERATION INTO tAli
25 NOTE: Dl < SOH - DISKETTE
26 Dl > 80H - DISK
27 IAHI=02 READ THE DESIREQ SECTORS INTO MEMORY
28 IAHI=03 WRITE THE DESIRED SECTORS FROM MEMORY
29 IAHI=04 VERIFY THE DESIRED SECTORS
3D IAHI=05 FPRMAT THE DESIRED TRACK
31 IAH)=06 FORMAT THE DESIRED TRACK AND SET BAD SECTOR FLAGS
32 (AH )=07 FORMAT THE DRIVE STARTING AT THE DESIRED TRACK
33 IAH )=OS RETURN THE CURRENT DRIVE PARAMETERS
34
35 I AH )=09 INITIAlIZE DRIVE PAIR CHARACTERISTICS
36 INTERRUPT 41 POINTS TO DATA BLOCK
37 I AH I=OA READ LONG
38 IAHI=OB WRITE LmlG
3. NOTE: READ AND WRITE LONG ENCOMPASS 512 + it BYTES ECC
4. (AH I=OC SEEK
41 IAHI=OD Al.TERNATE DISK RESET (SEE Dli
4' (AH I=O~ READ SECTOR BUFFER
43 IAHI=OF ~ITE SECTOR BUFFER,
44 IRECDt1f1ENDED PRACTICE BEFORE FORMATTING)
45 IAH)=10 TEST DRIVE READY
46 tAHI=l1 RECALIBRATE
47 (AHI=12 CONTROLLER RAM DIAGNOSTIC
48 (AHI=13 DRIVE I;)IAGNOSTIC
4. IAHI=14 CONTROLl~R INTERNAL DIAGNOSTIC
5.
51 REGISTERS USED FOR FIXED DISK OPERATIONS
52
53 (DLI - DRIVE NUt1BER ISOH-S7H FOR DISK, VALUE CHECKED)
54 IDHI - H~AD HUt1BER [P-7 ALLOWED, NOT VALUE CHECKED)
55 (CH) - CYlINDER HUt1BER (0-1023. NOT VALUE CHECKEDHSEE CU
56 (CLI - SECTOR NUMBER 11-17. NOT VALUE CHECKED)
57
58 NOTE: HIGH 2 BITS OF ~YlINDER HUt1BER ARE PLACED
5' IN THE HIGH 2 BITS OF THE CL REGISTER
6. (10 BITS TOTAL)
61 (All - NUI1BER OF SECTORS (MAXItM'1 POSSIBLE RANGE 1-80H.
62 FOR READIWRITE LONG 1-79H,
63 (INTERLEAVE VALUE FOR FORMAT 1-160)
64 IES:BX) - ADDRESS OF BUFFER FOR READS AND WRITES.
65 (NOT REQUIRED FOR VERIFY)
66
67 ; OUTPUT
6!S AH = STATUS OF CURRENT OPERATION
69 STATUS BITS ARE DEFINED IN THE EQUATES BElCH
70 CY = 0 SUCCESSFUL OPERATION (AH:O ON RETURN)
71 CY : 1 FAIlED OPERATION (AH HAS ERROR REASON)
72
73 NOTE: ERROR I1H INDICATES THAT THE DATA READ HAD A RECOVERABLE
74 ERROR WHICH WAS CORRECTED BY THE ECC ALGORITHM. THE DATA
75 IS PROBABLY GOOD. HOWEVER THE BIOS ROUTINE INDICATES AN
76 ERROR TO ALLOW THE CONTROL LIft(; PROGRAM A CHANCE TO DECIDE
17 Fnp ITSELF. THE ERROR HAY HOT RECUR IF THE OA.TA IS

26 Fixed Disk Adapter

LOC OBJ LINE SOURCE

70 REWRITTEN. (AU CONTAINS THE BURST LENGTH.

7'
00 IF DRIVE PARAMETERS WERE REQUESTED.
01
OZ DL ; NUMBER OF CONSECUTIVE ACKNOWLEDGING DRIVES ATTACHED (0-21
01 (CONTROllER CARD ZERO TALLY ONLY)
84 DH :: MAXIMUM USEABLE VALUE FOR HEAD NUMBER
85 CH = MAXIMUM USEABLE VALUE FOR CYLINDER HUMBER
Bb CL = MAXIMUM USEABLE VALUE FOR SECTOR NUMBER
87 AND CYLINDER NUMBER HIGH BITS
80
0' REGISTERS WILL BE PRESERVED EXCEPT WHEN THEY ARE USED TO RETURH
90 INFORMATION.
91
92 NOTE: IF AN ERROR IS REPORTED BY THE DISK CODE. THE APPROPRIATE
93 AcnON IS TO RESET THE DISK. THEN RETRY THE OPERATION.

'495 ; ----------------- -------------------------------------------------------

'6
OOFF
OOBe ,.
'7 SENSEJAIL
UNDEF _ERR
EDU
EDU
OFFH
OBBH
I SENSE OPERATIOH FAILED
I UNDEfINED ERROR OCCURRED
0080
0040 "
100
TIME_OUT
BAD_SEEK
EDU
EQU
80H
40H
; ATTACHMENT FAILED TO RESPOND
; SEEK OPERATIOH FAILED
0020 101 BAD_CNTLR EDU ZOH I CONTROLLER HAS FAILED
0011 lOZ DATA_CORRECTED EDU 11H ; ECC CORRECTED DATA ERROR
0010 101 BAD_ECC EDU lOH ; BAD ECC ON DISK READ
oooe 104 BAD_TRACK EDU 08H ; BAD TRACK FLAG DETECTED
0009 105 DMA_BOlrnOARY EQU 09H ; ATTEMPT TO DHA ACROSS 64K BOUNDARY
0007 106 INITJAIL EDU 07H ; DRIVE P....RAMETER ACTIVITY FAILED
0005 107 BAD_RESET EDU 05H ; RESET FAILED
0004 108 RECORD_NOTJNO EDU 04H ; REQUESTED SECTOR NOT FOl.n'ro
0002 109 BAD_ADDR_MARK EQU OZH I ADDRESS MARK NOT FOUND
0001 110 BAD_CMD EQU OlH I BAD COMMAND PASSED TO DISK I/O
111
112 ; ----------------------------------------
113 INTERRUPT AND STATUS AREAS
114 ; -------------- --------------------------
115
116 DU!1I1Y SEGMENT AT 0
0034 117 ORG ODH*4 ; FIXED D 15K INTERRUPT VECTOR
0034 118 HOISK_INT LABEL DWOOD
004C 11' DRG 13H*4 I DISK INTERRUPT VECTOR
004C 1ZO DRG_VECTOR LABEL DWORD
0064 1Zl ORG 19H*4 I BOOTSTRAP INTERRUPT VECTOR
0064 lZZ BOOT_VEC LABEL DWORD
0078 lZl ORG lEH*4 I DISKETTE PARAMETERS
0078 lZ4 DISKETTE_PARM LABEL DWORD
0100 lZ5 DRG 040H*4 I NEW DISKETTE INTERRUPT VECTOR
0100 126 DISK_VECTOR LABEL DWORD
0104 lZ7 ORG 041H*4 ; FIXED DISK PARAMETER VECTOR
0104 lZO HF _TBL_VEC LABEL DWORD
7C00 129 ORG 7COOH ; BOOTSTRAP LOADER VECTOR
7eOD 130 BOOT_lOCN LABEL FAR
III DUMI1Y ENDS
m
III DATA SEGMENT AT 40H
0042 !l4 DRG 4ZH
0042 !l5 CMD_BLOCK LABEL BYTE
0042 (7 1?) 136 HO_ERROR 08 7 DUP(?l ; OVERLAYS DISKETTE STATUS
DQbt !l7 ORG ObCH
006t n?? 138 TIMER_lOW OW ; TIMER LOW WORD
0072 139 ORG 7ZH
0072 7111 140 RESETJLAG OW • lZ34H IF KEYBOARD RESET UNDERWAY
0074 141 DRG 74H
0074 11 14Z DISK_STATUS 08 ; FIXED DISK STATUS BYTE
0075 11 141 HF _HUM 08 ; COUNT OF FIXED OISK DRIVES
0076 ?? 144 CONTROL_BYTE DB ; COUTROL BYTE DRIVE OPTIONS
0077 ?? 145 PORT_OFF 08 ; PORT OFFSET
146 DATA ENOS
147
148 COOE SEGMENT
14'
150 1--------------------------------------------------------
lSI ; HARDWARE SPECIFIC VALUES

'"
153 - CONTROLLER I/O PORT
154 > WHEI'i READ FIWM,

Fixed Disk Adapter 27

LaC OSJ LINE SOURCE

155 HF _F'ORT+O - READ DATA (fROM CONTROLLER TO CPU)

156 HF _PORT+l ... READ CONTROLLER HARDWARE STATUS
151 (CONTROLLER TO CPU)
158 HF _PORT+2 ... READ CONFIGImATlON SWITCHES
159 HF_PORT+! - NOT USED
160 > WHEN WRITTEN TO:
161 HF_PORT+O - WRITE DATA (fROM CPU TO CONTROLLER) :
162 HF __ PORHI - CONTROLLER RESET
163 HF _PORT+2 - GENERATE CONTROLLER SELECT PUlsE
164 HF_PORT+3 - WRIl'E PATTERN TO OHA AND INTERRUPT
165 MASK REGISTER
166
167 i ... -- ------- - - --- --------------- -- ------- ... --- -------------
168
0320 16. HF _PORT EQU 0320H I DISK PORT
OQ08 17. Rl_BUSY EQU 000010008 J DISK PORT 1 BUSY BIT
0004 171 Rl_BUS EQU 00000100B 1 COMMAND/DATA BIT
0002 172 Rl_IOMOOE EQU 000000108 MODE BIT
0001 173 Rl_REQ EQU 000000018 REQUEST BIT
170
0047 17. DHA_READ EQU 010001118 J CHANNEL 3 (047H)
004B 176 DM.\.WRlTE EQU 010010118 I CHANNEL 3 (048H)
0000 177 DHA EQU 0 I DHA ADDRESS
0082 178 DHA_HIGH EQU 082H I PORT FOR HIGH ,. BITS OF OMA
17.
DOGD 180 TST_RDY_Cf'I) EQU 000000008 I CNTLR READY (DOH)
0001 181 RECAL_Cf'I) EQU 000000018 RECAL 101HI
0003 18. SENSE_CI'I) EQU 000000118 SENSE 103H)
OOOct 183 FMTDRV_CMD EQU 00000100B DRIVE 104H)
ODDS 18_ CH~TRK_Ct1D EQU 00000101B T CHK (OSH)
0006 18S FMTTRK_CMD EQU 000001108 TRACK (06H)
0007 186 FMTBAD_CMD EQU 000001118 BAD (07H)
0008 187 READ_CMD EQU 000010008 READ (08H)
OOOA. 188 WRITE_CtID EQU 000010108 WRITE (OAH)
DOOB 18. SEEK_CMD EQU 000010118 SEEK (OBH)
Dooe 1'0 INIT_DRV_CtIJ EQU 000011008 INIT (OCH)
DODD 1.1 RD_ECC_CI1D EQU 000011018 BURST (DOH)
DOOE 1" RD_BUFF _CMD EQU 00001110B BUFFR 10EH)
DOOF 1.3 WR_BUFF _CtIJ EQU 00001111B BUFFR (OFH)
oDeD 1'_ RAM_DlAG_CND EOU 111000008 RAM (EOH)
00E3 1.5 CHK_DRV_CtI) EOU 111000118 DRV (ElH)
OOE4 1.6 CNTLR_DIAG_CHD EQU 11100100B CNTLR (E4H)
00E5 1.7 HO_LONG_Cm EQU 111001018 RlONG (E5H)
00E6 1.8 WR_LONG_CMD EQU 11100110B WlONG (E6H)
1••
0020 .OO INT_CTL_PORT EOU 20" I 8259 CONTROL PORT
0020
.0.
.01 Eot EQU
'0" I END OF INTERRUPT CONtlAHD

000& ."
.0_ HAX]IlE EQU
0002
...
'06
S_HAX_FIlE

ASS\Jt1E
EQU

CS:COOE
0000 207 o.G 0"
0000 55
0001 AA .0.
'08 DB
DB
055H
OUH
I GENERIC BIOS HEADER

0002 10 ." DB 16D

."
212 1-----"" -.. -.. ---------------------------------------- ... ----------... -
213 1 FIXED DISK lID SETUP
21_
215 - ESTABLISH TRANSFER VECTORS FOR THE FIXED DISK
216 - PERFORM POWER ON DIAGNOSTICS
217 SHOULD AN ERROR OCCUR" "1701" MESSAGE IS DISPUYED
218
219 1_ -- ------- -- --------------- w _w _______ . ____________ w - - -----------

•• 0
.21 DISK_SETUP PROC FAR

...
0003
0003 EBIE
0005 35303030303539
••• JHP
DB
SHORT L3
'5000059 (C)COPYRIGHT IBM 19B2' I COPYRIGHT NOTICE
20284329434FSO
5952494748542.0
20494240203139

0023
3632

0023 tBCO
..-
••S
"6
l3:
ASSU1E
SUB
DS:Dl.It1MY
AX,AX I ZERO
002:5 8E08 ,.7 MO. DS,AX

28 Fixed Disk Adapter

LaC OBJ LINE SOURCE

0027 FA 22. eLI

0028 A14COO 22. MOV AX,WORD PTR ORG_IIECTOR ; GET DISKETTE IIECTOR
0026 A3COOl 230 MOV WORD PTR DISK_VECTOR,AX I INTO INT 40H
002£ Al4EOO 231 MOV AX,WORD PTR ORG_IIECTOR+2
0031 A30201 232 HOV WORD PTR DISK_IIECTOR+2.AX
0034 C7064C005602 233 HOV WORD PTR ORG_ VECTOR, OFFSET DIsK_IO I HDISK HANDLER
C03A 8COE4EOO ,,. HOV WORO PTR ORG_YECTOR+2:,CS
003E 886007 235 HOV AX. OFFSET HD_INT I HDISK INTERRUPT
0041 A3340Q 23. HOV WORD PTR HDIsK_INT, AX
0044 6COE3600 237 MaY WORD PTR HDISK_lHT+2:.CS
0048 C70664008601 23. MaY WORD PTR BOOT_IIEe.OFFSET BOOT_STRAP I BOOTSTRAP
004E 8CO£6600 23. HOV WORD PTR BOOT_IIEC+2.CS
0052 C7060401£703 240 MaY WORD PTR HF _TBl_IIEC.OFFSET Fa_TBl I PARAMETER TBL
0058 8eOE0601 241 HOV WORD PTR HF _TBl_VEC+2 .CS
Dose FB 242 STI
243
244 ASSUME 05:0ATA
0050 884000 ,.5 MOV AX.OATA I ESTABLISH SEGMENT
0060 8ED8 24. HOV 05,AX
0062 C606740000 247 HOV OISK_STATU5.0 I RESET TliE STATUS INDICATOR
0067 C606750000 246 HOV HF _HUH,O I ZERO COUNT OF DRIVES
D06e C606430000 24. HOV CMD_BlOCK+l,O I DRIVE ZERO. SET VALUE IN BLOCK
0071 C606770000 250 HOV PORT_OFF. a ; ZERO CARD OFFSET
251
0076 892500 252 HOV CX.25H ; RETRY COUNT
0079 253 L4:
0079 EBF200 254 ; RESET CONTROLLER
oo?e 7305 255 JHe L7
007E E2F9 25. LOOP L4 ; TRY RESET AGAIN
0080 E9BFDO 257 JHP ERROR_EX
0083 256 L7:
0083 890100 25. HOV CXol
0086 BA8000 2.0 MOV OX.80H
2.,
0089 B60D12 2.2 HOV AX,1200H I CONTROllER DIAGNOSTICS
DOet CD 13 2.3 INT 13H
006E 7303 2.4 JNe P7
0090 E9AFOQ 265 JHP ERROR_EX
0093 2 •• P7:
0093 880014 2.7 HOY AX,1400H I CONTROllER DIAGNOSTICS
0096 con 266 INT 13H
0098 7303 2 •• JNe P.
009,A. E9.6.500 270 JMP ERROR_EX
0090 271 P9:
0090 C7066COOOOOO 272 HOV TIMER_LOW. a j ZERO TIMER
aDA] .6.17200 273 MOV AX.RESETJLAG
00A6 3D3412 274 eHP AX.l234H I KEYBOARD RESET
OOA9 7506 275 JNE P6
OOA8 C7066C009AOI 27. MOV TIMER_LOW.410D I SKIP WAIT ON RESET
DaB 1 277 P8l
OOBI £421 276 IN AL.021H ; TIMER
0083 24FE 27. AND AL,OFEH j ENABLE TIMER
0065 E621 260 OUT 021H ,AL ; START TIMER
DOB7 261 P4l
00B7 E88400 262 J RESET CONTROLLER
oaBA 7207 263 Je P10
ooee 8BOOI0 264 MOV AX,lOOOH I READY
DOBF COl3 26' INT 13H
OOCI 7308 26. JNe P2
OOC] '67 Pia:
00C3 A16eoo 266 MOY AX, TlMER_ LOW
aOC6 308EOI 289 eMP AX,4460 ; 25 SECONDS
00C9 72£t ,.0 JB P4
00C8 EB7S90 291 JMP ERROR_EX
DaCE ,92 P2:
DaCE MOIDa 2.3 MOV CX.l
ODD 1 BA800Q 294 MOV OX.80H
29.
0004 880011 29. MOV AX.llOOH ; RECALlBRATE
0007 con 297 INT 13H
0009 7267 2.6 Je ERROR_EX
299
0008 880009 300 MOV AX,0900H ; SET DRIVE PARAMETERS
OODe COil 3" INT 13H
OOEO 7260 3" Je ERROR_EX
303
OOH B800C8 304 HOV AX,OC800H I OMA TO BUFFER

Fixed Disk Adapter 29

LOC OBJ LINE SOURCE

ODES SEeD 305 MOV ES,AX ; SET SEGMENT

00E7 2808 300 sue BX.BX
OOE9 a8000F 307 MOV AX,OFOOH J WRITE SECTOR 8UFFER
OOEt con 308 INT J3H
DOEE 7252 30. JC ERROR_EX
310
OOFO FE067500 3JJ IHC HF _tM1 J DRIVE ZERO RESPONDED
31'
00F4 8.4.1302 313 MOV OX,213H J EXPANSION BOX
OOF7 BODO 314 MOV AL,O
00F9 EE 315 OUT OX,AL i TURN BOX OFF
OOFA. BA2103 310 MOV OX,321H ; TEST IF CONTROLLER
OOFO EC 317 IH AL,OX J ••• IS IN THE SYSTEM l~IT

OOFE 240F 318 AND AL.OFH

0100 3eOF 31' CMP AL.OFH
Cla2 7406 320 JE BOX_ON
0104 C7066COOA40 1 321 MOV TIMER_LOW.42:00 ; CONTROLLER IS IN SYSTEM !..tIIT
OIDA. 322
010A. 8.4.1302 323 MOV OX,213H I EXPANSION BOX
0100 BOFF 324 MOV AL,OFFH
010F EE 325 OUT OX,At • TURN BOX ON
320
0110 890100 327 MOV eX,l j ATTEMPT NEXT DRIVES
0113 BA8100 "8 MOV Dx.oalH
0116 32. P3:
0116 ZBce 330 sue AX,AX j RESET
Olle COll 331 ,NT 13H
011A 7240 33' JC POD_DONE
OIlC 880011 333 MOV AX,OllOOH J RECAL
OllF COIl 334 IHT J3H
0121 7308 335 JHC P5
0123 A.16eOO 330 MOV AX, TIMER_LOW
0126 30BEOI 337 CMP AX.446D I 25 SECONDS
0129 nEB 338 JB P3
0128 E82F90 33' JMP POD_DONE
012E 340 P5:
012E 880009 341 MOV AX,0900H J INITIALIZE CHARACTERISTICS
0131 con 34' INT 13H
0133 7227 343 JC POD_DONE
0135 FE067500 344 lHe HF _NUt1 1 TALLY ANOTltER DRIYE
0139 81F.4.8100 345 CMP OX, (SOH + 5_MAX]ILE - 1)

0130 7310 340 JAE POD_DONE

013F 42 347 IHC OX
0140 EBD4 .48 JMP P3
34.
350 ; ----- POD ERROR
351
0142 35' ERROR_EX:
0142 BOOFOO 353 MOV BP,OFH I POD ERROR FLAG
014:5 28CO 354 sua AX,AX
0147 85FO 355 MOV SI.AX
0149 89060090 350 MOV CX.FI7L ; MESSAGE CHARACTER COUNT
0140 8700 357 MOV BH,O I PAGE ZERO
014F 358
014F 2E8A.846Btn 35. HOV AL,CS:F17[SIJ I GET BYTE
0154 840E 300 HOV AH.14D ; VIDEO OUT
0156 COlO 301 INT lOH I DISPLAY CHARACTER
015846 30' INC 51 ; NEXT CHAR
0159 E2F4 303 LOOP OUT_CH I 00 MORE
0158 F9 364 STC
DISC 305 POD_DONE:
DISC FA 300 ClI
0150 E421 307 IH AL,021H I 8E SURE TIMER IS DISABLED
015F OCOI 308 OR AL,OlH
0161 E621 30. OUT 021H,AL
0163 F8 37. STl
0164 EBASOD 371 CALL OSBL
0167 CB 37' RET
373
016& 31373031 374 FJ7 DB '1701',ODH.OAH
Clbt 00
0160 0.4.
0006 375 F17L EQU S-F17
370
016E 377 HD_RESET_l PROC NEAR
016E 51 378 PUSH CX ; SAVE REGISTER
016F 52 31. PUSH DX

30 Fixed Disk Adapter

LOC OBJ LINE SOURCE

0170 F8 380 eLe ; CLEAR CARPY

0171 990001 381 MOV eX,OloaH ; RETRY COUNT
0174 382 l6:
0174 e80706 383 CALL PORT_I
0177 EE 384 OUT DX,AL ; RESET CARD
0178 E80306 385 CAll PORT_l
0178 EC 386 IN AL,Di< ; CHECK STATUS
OI7e 2402 387 AND AL.2 ; ERROR BIT
OI7E 7403 388 Jl .3
0180 E2F2 389 lOOP 16
0182 F9 390 STe
0183 391 R3:
0183 SA 392 POP OX RESTORE REGISTER
0184- 59 393 PDP ex
0185 C3 394 RET
395 HO_RESET_l ENoP
396
397 DISK_SETUP ENDP
398
399 ;----- INT 19 ---------------------------------------------------
400
401 INTERRUPT 19 BOOT STRAP LOADER
402
403 THE FIXED DISK BIOS REPLACES THE INTERRUPT 19
404 BOOT STRAP VECTOR IHTH A POINTER TO THIS BOOT ROUTINE
405 RESET THE DEFAULT DISK AHe DISKETTE PARAMETER VECTORS
406 THE BOOT BLOCK 'to BE READ IN IolIlL BE ATTEMPTED FROM
407 CYLINDER a SECTOR 1 OF THE DEVICE.
408 THE BOOTSTRAP SEQUENCE IS:
409 > ATTEMPT TO LOAD FROM THE DISKETTE !HTO THE BOOT
410 LOCATION (0000:7COO) AND TRANSFER CONTROL THERE
411 > IF THE DISKETTE FAILS THE FIXED DISK IS TRIED FOR A
412 VALID BOOTSTRAP BLOCK. A VALID BOOT BLOCK ON THE
413 FIXED DISK CONSISTS OF THE BYTES 055H OAAH AS Tl-IE
414 LAST TWO BYTES OF THE BLOCK
415 > IF THE ABOVE FAILS CONTROL IS PASSED TO RESIDENT BASIC
41.
417 ; ---- ---- -- --- -------------- ----------------- ---- ----------------
418
0186 419 BOOT_STRAP:
420 ASSUNE OS :OUMHY, ES : DUMMY
0186 2BCO 421 sua AX,AX
0188 8E08 422 MOV OS,AX ESTABLISH SEGMENT
423
424 ;----- RESET PARAMETER VECTORS
425
018A FA 426 eLI
013B C7060401E703 427 MoV WORD PTR HF_TBL_VEC, OFFSET fD_reL
0191 8COE0601 42. MoV WORD PTR HF_TBL_VEC+Z. CS
0195 C70678000102 429 MoV WORD PTR DISKETTE]ARH, OFFSET DISKETTE_TSl
019B 8COE7AOO 430 MoV WORD PTR DISKETTE_PARM+2. CS
019F FB 431 sn
432
433 ;----- ATTEMPT BOOTSTRAP FRON DISKETTE
434
DIAD 690300 435 MOV CX.3 ; SET RETRY COUNT
01A3 43. HI: ; IPL_SYSTEM
01.4.3 51 437 PUSH ex 1 SAVE RETRY COUNT
OIA4 2602 438 sua OX.OX ; DRIV~ ZERO
01A6 2BCO 439 SUB AX,AX ; RESET THE DISKETTE
01A8 CDll 440 INT 13H ; FILE 10 CAll
01AA nOF 441 Je H2 ; IF ERROR, TRY AGAIN
01AC 880102 442 MOV AX,0201H ; READ IN THE SINGLE SECTOR
443
OlAF 2B02 444 sua DX,DX
01BI 8EC2 445 MOV ES,DX I ESTABLISH SEGMENT
0163 BB007C 44. MOV ex .OFFSET BOOT_LOCN
447
01B6 890100 448 MOV CX.l ; SECTOR I, TRACK 0
01B9 CDl3 449 INT 13H ; FILE 10 CAll
OlBB 59 450 H2: POP ex ; RECOVER RETRi COWl
OIBC 730A 451 JNC H4 i CF SE~ BY UNSUCCESSFU!- READ
OlBE aOFC80 452 eMP AH, BOH j IF TIME OUT, NO RETRY
01Cl 740A 453 Jl H5 ; TRY FIXED DISK
01C3 E20E 454 LOOP HI ; DO IT FOR RETRY TIMES
OlCS EB0690 455 JMP H5 ; UNABLE TO IPL FROM THE DISKETTE
0lC8 45. H4: ; IPL WAS SUCCESSFUL

Fixed Disk Adapter 31

LOC OBJ LINE SOURCE

OIC8 £A007COOOO 457 JMP BOOT_LOCN

458
459 ; ----- ATTEMPT BOOTSTRAP FROM FIXEO DISK
460
OICO 461 H5:
Oleo 2BCO 462 SUB AX. AX. ; F1ESET DISKETTE
OleF 2602 463 SUB DX,DX
OlDl COB 464 INT 13H
0103 890300 465 MOV eX,3 I SET RETRY COUNT
0106 466 H6: ; IPl_SYSTEH
0106 51 467 PUSH ex ; SAVE RETRY COUNT
0107 BA800a 468 MOV OX, ooaOH ; FIXED DISK ZERO
OIDA 28CO 469 SUB AX,AX ; RESET THE FIXED DISK
OlOe COl3 470 INT 13H I FILE 10 CALL
alOE 7212. 471 JC H7 I IF ERROR. TRY AGAIN
DIED 880102 472 MOV AX,0201H ; READ IN THE SINGLE SEC'rOR
OlE3 2BDB 473 SUB eX,ex
0lE5 SEC3 474 tlOY ES,BX
0lE7 BB007e 475 MOV BX,OFFSET BOOT_LoeN ; TO THE BOOT LOCATION
OlEA BA8000 476 MOV Dx,eOH ; DRIVE NUMBER
OlEO 690100 477 HOV ex,} ; SECTOR 1, TRACK 0
DIFO C013 478 INT 13H ; FILE 10 CALL
CIF2 59 479 H7: POP ex j RECOVER RETRY COUNT
OlF3 7208 480 JC HB
OIFS AIFE7D 481 MOV AX,WORD rTR BOOT_lOCN+510Q
DIF8 3D55AA 482 CMP AX,QAA55H j TEST FOR GENERIC BOOT BLOCK
OlFB 74CB 483 JZ N4
OIFD 484 H8:
DIFO E207 485 LOOP H6 I DO IT FOR RETRY TIMES
486
487 j------ UNABLE TO IPl FROM THE OISKETTE OR FIXED DISK
488
OIFF COIB 489 INT 18N j RESIOENT BASIC
490
0201 491 DISKETTE_ TBl:
492
0201 CF
0202 02
493
494
DB
08 ,
llaOlUl8 1 5RT=C. HO UNlQAD=OF -
; HO LOAD=l, MODE=OI1A -
1ST SPEC BYTE
2HD SPEC BYTE
0203 25 495 08 25N ; WAIT AFTER OPN TIL MOTOR OFF
0204 02 496 08 2 ; 512 BYTES PER SECTOR
0205 08 497 08 ; EDT (LAST SECTOR ON TRACK)
0206 ZA 498 08 02AH I GAP LENGTH
0207 FF 499 08 OFFH DTl
0208 50 500 08 050H ; GAP LENGTH FOR FORHAT
02.09 F6 501 08 OF6H ; FILL BYTE FOR FORHAT
020A 19 502 08 25 1 HEAD SETTLE TIME (MILLISECONDS}
02.06 04 S03 08 ; MOTOR START TIME (1/8 SECOND)
S04
505 ;----- HAKE SURE THAT ALL HOUSEKEEPING IS DONE BEFORE EXIT
506
ozoc S07 OSB L PROC NEAR
S08 ASSUME DS:DATA
ozoc 1E 509 PUSH OS SAVE SEGMENT
0200 B84000 510 MOV AX,OATA
0210 8E08 5II MOV OS,AX
51'
0212 8A267700 513 HOV
0216 50 514 PUSH AX ; SAVE OFFSET
515
0217 C606770000 516 MOV
021e E86905 517 CALL PORT_3
0211" 2ACO 518 sus AL,AL
0221 EE 519 OUT OX,AL ; RESET !NT/DNA NASK
0222 C606770004 520 MOV PORT_OFF ,4H
0227 E85E05 521 CALL PORT_3
022A 2ACO 52' SUB AL.AL
D22C EE 523 OUT OX.Al ; RESET INT /DNA MASK
0220 C606770008 524 MOV PORT_OFf,8H
0232 E85305 525 CALL PORT_3
0235 2ACO 526 SUB Al,AL
0237 EE 527 OUT OX.AL ; RESET INT /DNA NASK
0238 C60677000C 528 MOV PORT_OFF. OCH
0230 E84805 529 CAll PORT_3
D2tiO 2ACO 530 SUB Al,AL
0242 EE 531 OUT OX ,AL ; RESET INT/ONA MASK
t10V Al,07H
0243 B007
0245 E60A '"
533 OUT DMA+IO.AL I SET DMA MODE TO DISABLE

32 Fixed Disk Adapter

LaC OBJ LINE SOURCE

0,47 FA. 5,4 CLI ; DISABLE INTERRUPTS

02:48 E421 535 IH Al,021H
024A oelD 536 DO AL,OZIiIH
024C E621 537 OUT 02lH,AL ; DISABLE INTERRUPT 5
024E FB 538 STI ; ENABLE INTERRUPTS
024F 58
0250 88267700
539
540
'0'
MOV
AX
PORT_OfF ,AH
t RESTORE OFFSET

0254 IF 541 PO, OS ; RESTORE SEGMENT

02.55 C3 S42 RET
543 DSBl ENIlP
544
545 I -- --- - - ---------- - -- --------------------
546 FIXED DISK BIOS ENTRY POINT
547 ; - -- --------------- ----------------------
548
02:56 549 DISK_IO PROC FAR
550 ASSUME OS: NOTHING, ES: NOTHING
0256 80FAeo 551 CMP Dl,80H ; TEST FOR FIXED DISK DRIVE
0259 7305 552 JAE HARD_DISK ; YES, HAHOLE HERE
0258 C040 553 IHT 40H ; DISKETTE HANDLER
0250 554 RET_2:
0250 CA02:00 555 RET I BACK TO CALLER
0260 556 HARD_DISK:
557 ASSUME OS:O.1.T"
0260 FB 558 STI I ENABLE INTERRUPTS
0261 OAE4 559 OR AH.AH
0263 7509 560 JHZ A3
0265 C040 561 INT 40H I RESET NEt WHEN AH=O
0267 2AE4 562 SUB AH.AH
0269 80fA81 563 CMP Dl.leOH + S_MAXJllE - 1J
026C 77Ef 564 JA RET_2
026E 565 A3:
026E 80FC08 566 CMP AH,08 I GET PARAMETERS IS A SPECIAL CASE
0271 7503 567 JNZ A2
0273 E91A01 568 JMP GET_PARH_N
0276 569 A2;
0276 53 570 PUSH ex ; SAVE REGISTERS DURING OPERATION
0277 51 571 PUSH CX
0278 S2 572 PUSH ox
0279 IE 573 PUSH OS
027A 06 574 PUSH ES
0276 56 575 PUSH SI
027C 57 576 PUSH or
577
0270 E86AOO 578 CAll DISK_Io_com PERFORM THE OPERATum
579
0280 50 sao PUSH AX
0281 E888FF 581 CALL D56L ; BE SURE DISABLES OCCURRED
0284 684000 582 MOV AX.DATA
0287 8ED8 583 MOV DS,AX I ESTABLISH SEGMENT
0289 58 584 PO, AX
02:8A 8A267400 585 MOV AH ,DISK_STATUS ; GET STATUS FROM OPERATION
028E 80FCOl 586 CMP AH.l I SET THE CARIi/)' HAG TO INDICATE
0291 F5 587 CMC , SUCCESS OR FAILURE
0292 SF 588 POP OI ; RESTORE REGISTERS
0293 5E 589 pop SI
0294 07 590 POP ES
0295 IF 591 POP OS
0296 SA 592 PO' ox
0297 59 593 POP CX
0298 56 594 POP 8X
0299 CA0200 595 RET 1 THROW MoIA)' SAvea Fl.A~S

596 DISK_IO EtIDP

597
029C 598 M1 LABEL worm ; FUNCTION TRANSFER TABLE
02:9C 3803 '99
600
ow
OW
DISK_RESET
RETURN_STATUS
; OOQH
; OOIH
D29E 4003
02AO 5603 601 OW DISK_READ I D02H
02A2 6003 6" ow DISK_l>IRITE DOJH
02A4 6A03 6" ow DISK_ VERF I D04H
02A6 7203 604 ow FHT_TFlK ; DOSH
02A8 7903 60S OW FMT_BAO ; 006H
02AA e003 606 ow FHT_DRV I Q07H
02AC 3003 607 ow 6AD_COHMAtro ooaH
OZAE 2704 60s ow INICORV I 009H
0260 CF04 6" ow RO_LONG OOAH
0262 0004 610 ow WR_LONG DosH

Fixed Disk Adapter 33

LaC OBJ LINE SOURCE

0284 F204 611 ow ; OOCH

0286 ;3803 612 ow
DISK_SEEK
DISK_RESET , OOOH
02SS F904 613 D~ RD_BUFF I OOEH
02BA. 0705 61. ow WR_BUFF ; OOFH
a2BC 1505 6,5 ow 1ST_ROY J 0101'1
028E lCOS 61, ow HDISK_RECAL I 011H
02tO 2305 617 .w RAM_DIAG I 012H
02e2 ZAOS 618 ow CHK_DRV I 013H
02t4 3105 61. ow CNTLR_DIAG ; 014H
002A 620 MIL EQU $-NI
621
q2C6 622 SETUP_A PROt NEAR
623
02t6 C606740000 62. MbV DISK_STATUS,O J RESET THE STATUS INtl~CATOR
02tB 51 625 PUSH CX I SAVE ex
6'6
627 1----- CALCULATE THE PORt QFFSET
6~8
02ec 8AEA 629 MOV CH,Ot i SAVE DL
02eE 80CAOJ 630 OR CL,I
0201 FEeA 631 DEC DL
0203 DOE2 632 SHL pL'l I GENERATE OFFSET
0205 88167700 633 MOV PORT_OFF ,OL I STORE OFFSET
0209 8.1.05 634 "OV OL.CH • RESTORE Dl
~2DB 80E201 635 AND OL,l
636
020E BI05 637 MOV Cl,S I $HIFT COUNT
02EO 02E2 638 SHL Ct.eL I DfHVE tM1BER I 0 ,I )
02E2 OA06 63. OR OltOH ; HEAD I'U18ER
02E4 asi64300 64. MOV CMD_BlOCK+l,DL
OZE6 59 641 POP ex
02E9 C3 642 RET
6ft3 SETUP_A EHDP
644
02EA 645 DISK_IO_CONT "DC NEAR
02EA 50 646 PUSH AX
02EB 884000 647 MOV AX ,DATA
02EE 8ED8 64' MOV OS,AX ; ESTABLISH SEGMENT
02FO 58 64. POP AX
02Fl 60FCOl 650 CMP AH.OIH J RET~N STATUS
02F4 7503 651 JHZ A.
02F6 E65590 65' JMP RETURN_STATUS
02F9 653 A4:
OZf980EA60 654 ~~ OL.80H ; CotNERT DRIVE HlII1BER TO 0 BASED RANGE
02FC ~OFA08 655 eMP DL.MAXJILE , LEGAL DRIVE TEST
02FF 732F 656 JAE BAD_COMMAND
657
0301 E6C2FF 658 CALL SETUP_A
65~

660 ; ----- SET UP CQt1t1AND BLOCK

661
0304 FEC9 662 DEC CL J SECTORS 0-16 FOR CotrrROLLER
0306 C606420000 663 MeV CHD_BLOCK+O.O
03~B 880£4400 664 MeV CHD_BLOCK+2,CL ; SECTOR AND HIGH 2 BITS CYLINDER
030F 862£4500 665 MOV CMD_BLOCK+3.CH J CYLINDER
0~13 1.24600 666 MOV CI"IIJ_BLQCK+4.AL J INTERLEAVE / BLOCK COUNT
0316 A07600 667 MOV AL.CONTRQL_BYTE ; CONTROL BYTE (STEP OPTION)
0319 A24700 668 MOV CMD_BLOCK+5.Al
031t 59 ~69 P\JSH AX J SAVE AX
031D 6At4 670 HOY AL.AH I GET INTO LOW BYTE
031F 32E4 611 XOR AH.AH I ZERO HlliH BYTE
0321 DIED 672 SAL AX.l I *2 FOR TABLE LOOKUP
0323 8BFO 673 MOV SI.Ax I PUT INTO SI FOR BRANCH
0325 302AOO 674 CMP AX,HlL ; TEST WITHIN RANGE
032656 675 POP AX ; RESTORE AX
0329 7305 676 JN8 8~D_COHJ'1AND
0328 2EFFA49C02 677 JMP WORD PTR CS:[SI + OFFSET Mll
0330 678 BAD_COMMAND :
0330 C606740001 67. MeV DISK_STATUS. BAD_CtI) ; COMMAND ERROR
0335 BODO 680 MOV AL,O
0337 Cl 681 RET
682 OISK_IO_C;ONT ENDP.
68'
684 I - - - - - - - - - - - - - -- -- ----- --- ---------- -- - - ---------
61t~ RESET THE DISK SYSTEM CAH = OOOH)
686 t ----------------------------,.------- - - - ----------
681

34 Fixed Disk Adapter

LaC OSJ LINE SOURCE

0338 688 DISK_RESET PROt NEAR

0338 E84304 689 CAll PORT_l i RESET PORT
0336 EE 690 OUT OX,AL I ISSUE RESET
OBC E83F04 691 CALL PORT_l I CONTROLLER HARDWARE STATUS
033F EC 692 IN AL.DX ; GET STATUS
0340 2402 69' AND AL.2 ; ERROR BIT
0342 7406 694 JZ ORI
0344 C606740005 695 HOV DISK_STATUS ,BAD_RESET
O~49 C3 696 RET
034A 697 oRl:
034A E90AOO 698 JHP INIT_DRY SET THE DRIVE PARAMETERS
699 OISK_RESET ENDP
700
701 ; - ---- - --- -- -- ----- --- -- ------------- ------------
702 DISK STATUS ROUTINE (AH = OOlH)
70 3 ; -- ------ - -- - - --------- - -- - ---------- ------------
704
0340 705 RETURN_STATUS PROC NEAR
0340 A07400 706 HOV AL,DISK_STATUS I OBTAIN PREVIOUS STATUS
0350 C606740000 707 HOV DISK_STATUS.O i RESET STATUS
0355 C3 708 RET
709
710
711 i ------------------------------------------------
71Z DISK READ ROUTINE (AH = OOZH)
713 i ------------ - -- - --------- - -- ------------ --------
714
0356 715 DISK_READ PROC NEAR
0356 8047 716 HOV AL.OMA_READ MODE BYTE FOR OMA READ
0358 C606420008 717 HOV
0350 E9E501 718 JHP
719 DISK_READ ENDP
720
721 ; -------------- ------ - ------ --- --- ---------------
722 DISK WRITE ROUTINE (AH = 003HI
7Z3 ; -------------------- - --------- --- ---------------
724
0360 725 PROC NEAR
0360 804B 726 HOV AL.OHA_WRITE ; HODE BYTE FOR DHA WRITE
0362 C60642000A 727 HOV
0367 E90801 728
729
730
731 ; --------- -- ---- ------- --------------------------
732 DISK VERIFY (AH = 004H)
733 ; ------------------------------------------------
734
036A 735 OISK_VERF PROC NEAR
036A C606420005 736 HOV
036F E9C401 737 JHP
738 DISK_VERF
739
740 ; ------------------------ --- ---- -----------------
741 FORHATTIHG IAH = OOSH 006H 007H)
742 ; ---------------------- -- ------------------------
743
0372 744 FHT_TRK PROC NEAR ; FORMAT TRACK (AH = OOSH)
0372 C606420006 745 MOV CHO_BLOCK. FMTTRK_CMO
0377 EBOC 746 JMP SHORT FHT_CONT
747 FHT_TRK ENDP
748
0379 749 ; FaRHAT BAD TRACK (AH = 006H)
0379 C606420007 750
037E EB05 751 JHe
752 FMT_BAD ENDP
753
0380 754 ; FORHAT DRIVE (AH = 007H)
0380 C606420004 755 HOV CMD_BLOCK. FHTORV_CI1O
756 FMT_DRV END?
757
0385 758 FMT_CONT:
0385 A04400 759 HOV AL.CMD_BlOCK+2 ; ZERO OUT SECTOR FIELD
0388 24CO 760 AfID AL,llOOOOOOB
038A A24400 761 HOV CMD_BLOCK+2,AL
038D E9A60 1 762 JNP NDHA_OPN
763

Fixed Disk Adapter 35

laC OBJ LINE SOURCE

764 ; ------ .. ------ -----------------.. -------------- ---

765 GET PARAMETERS (AH = 8)
766 ; -- .... ----- --- -- ------------------------------- ---
767
0390 7.8 GET]ARH_N LABEL NEM~
0390 769 GET_PARM PROC FAR i GET DRIVE PARAMETERS
0390 1E 770 PUSH OS o SAVE REGISTERS
0391 06 771 PUSH ES
0392 53 77' PUSH BX
773
774 ASSUME DS:DUt1t1Y
0393 2BCO 775 SUB AX,AX ESTABLISH ADDRESSING
0395 6E08 776 Mav OS,AX
0397 C41E0401 777 LES BX,HF _TaL_VEe
778 ASSUME OS:DATA
03'98 884000 77, MOV AX,DATA
039E 8E06 7., Mav as,AX J eSTABLISH SEGMENT
781
C3Ae aOEABO 782 sull DL,SOH
03A) 80FAoe 783 eMP DL,MAX]IlE I TEST WITHIN RANGE
03A6 73ZF 784 JAE G4
785
03A8 E81BFF 786 CALL SETUP _A
787
03A8 E80FOl 7M CALL SW2_0FFS
03AE 7227 789 JC G4
03BO 0308 790 ADD BX,AX
791
03B, 268B07 792 Mav AX,ES:[BXJ I MAX NUHBEF! OF CYLINDERS
03B5 200200 793 SUB AX,2 I ADJUST FOR O-N
794 I AND RESERve LAST TRACK
03Ba 8AE6 795 MDV CH,Al
03BA 250003 796 AND AX,0300H I HIGH TWO BITS OF, cn
03BO 01E8 797 SHR AX'}
03BF DIES 798 SHR AX.l
03(:1Dell 799 'R AL,OllH ; SECTORS
03C3 8Ace 800 MOV CL,AL
8"
03es 266A7702 8" MOV DH.ES:{BXJ!2J ; HEADS
03C9 FEtE 8" DEC OH ; O-N RANGE
03e8 6AI67500 804 MaV DLjHF _NUl1 ; DRIVE COUNT
03eF 2BCO 8" SUB AX,AX
0301 8" G5 ~
0301 58 .,7 pop BX ; RESTORE REGISTERS
0302 07 .08 POP ES
0303 IF 8" POP oS
0304 CAD20D 8" RET
0307 811 G4:
0307 C606740007 812 Mav DISK_STATUS. INrCFAIL I OPERATION FAILED
ClOC 6407
030E 2Aca
8"
814
Mav
Sull
AH.INIT]AIL
AL,AL
03EO 2802 81S SUB DX,DX
03E2 2BC9 81. SUB CX,CX
03£4 F9 817 STO I SET ERROR FLAG
03ES EBEA 818 JMP GS

8" GET_PARM ENDP

8"
621 ; ----- .. -- ------------------------------------------------
822 I INITIALIZE DRIVE CHARACTERISTICS
8"
824 FIXED DISK PARAMETER TABLE
825
826 THE TABLE IS COMPOSED OF A. BLOCK DEFINED A.S:
821
"8 (1 WORD) - MAXIMUM HUMBER Or CYLINDERS

...
8"
8"
j

(1
1 BYTE) - MAXIMUM tM1BER OF HEADS
WORD' - STARTING REDUCED WRITE CURRENT
(1 WORO I - STARTING WRITE PRECOMPENSATlON CYL
cn

8" (1 BYTE) - MAXIMUM ECC DATA BURST LENGTH

8" Il BYTEJ - CONTROL BYTE IDRIVE STEP OPTION)

83' BIT 7 DISABLE DISK-ACCESS RETRIES:
835 BIT 6 DISABLE ECC RETRIES
8" BITS 5-3 ZERO
837 BITS 2-0 DRIVE OPTION
838 (1 BYTE) - STANDARD TIME OUT VALUE (SEE BELCH)
8" (1 BYTE J - TINE OUT VALUE FOR FORMAT DRIVE
8., (1 eYTE) - TIME OUT VALUE FOR CHECK DRIVE
8., (4 BYTES)

36 Fixed Disk Adapter

LOC OBJ LINE SOURCE

8., - RESERVED fOR FUTURE USE

8.3
8 •• - TO DYNAMICALLY DEFINE A SET OF PARAMETERS
8.5 BUILD A TABLE OF VALUES AND PLACE THE
84. CORRESPONDING VECTOR INTO INTERRUPT 41.
8.7
8.8 NOTE:
8.' THE DEFAULT TABLE IS VECTORED IN FOR
850 AN INTERRUPT 19H (BOOTSTRAP J
851
8S>
853 ; ON THE CARD SWITCH SETTINGS
85.
855 DRIVE 0 DRIVE 1
85.
857 ON
858 : -1- -2- I -3- -4-:
8. . OFF
8.0
8.,
8.'
8.3 TRANSLATION TABLE
8 ••
8.5 1/3 : 2/4 : TABLE ENTRY
8 ••
8.7 ON ON
8.8 ON OFF
8.' OFF ON
870 OFF OFF
871
812 ; ------------------------- -- - ------- - .------ .---- --------
a73
03E7 87.
875
87. ;----- DRIVE TYPE 00
877
03E7 3201 878 DW 03060
03E9 02 87' DO 02D
03EA 3201 8ao DW 03060
03EC 0000 881 DW 00000
03EE DB 88' DO OOH
03EF 00 883 DO OOH
03FO DC SS. DO OCH I STAHOARD
03Fl 84 8" DO OB4H j fORMAT DRIVE
03F2 28 88. DB 028H ; CHECK DRIVE
03F3 00000000 887 DO 0,0,0,0
888
88' j----- DRIVE TYPE 01
890
03F7 7701 891 DW 03750
03F9 08 8" DO 08D
03FA 7701 8'3 DW 03750
03FC 0000 8'. DW 00000
03FE DB 8" DO OOH
03FF 05 8'. DO 05H
0400 ac 897 DO OCH ; STANDARD
0401 64 8'8 DO OB4H j FORMAT DRIVE
0402 28 a" 00 026H ; CHECK DRIVE
0403 00000000 900 DB 0,0,0,0
901
'02 j----- DRIVE TYPE 02
903
0407 3201 90. ow 03060
0409 06 905 DO 06D
040A BODO 90. DW 01280
040C 0001 907 DW 02560
040E DB 908 DO OOH
Q40F as 90' D8 05H
0410 ac 910 DO OCH ; STANDARD
0411 84 '11 DO OB4H j FORHAT DRIVE
0412 28
0413 00000000 '"
913
D8
DO
028H
0,0,0,0
; CHECK DRIVE

91.
915 ;----- DRIVE TYPE 03
91.
0417 3201 917 OW 03060
0419 04 918 DB 040

Fixed Disk Adapter 37

LOC OSJ LINE SOURCE

041A 3201 919 OW 03060

041C 0000 920 OW 00000
041E DB 921 DB OBH
041F 05 922 OB 05H
0420 DC 923 DB OCH I STANDARD
0421 B4 924 DB DB4H ; FORMAT DRIVE
0422 28 925 DB 028H ; CHECK DRIVE
0423 00000000 926 DB 0,0,0.0
927
0427 928 IN IT_DRY PROC HEAR
929
930 ; ----- DO DRIVE ZERO
931
0427 C606420QOC 932 MOV CMD_BLDCKtO .INIT_DRV_tHO
04ZC C606430000 933 MOV CMD_BLOCK+l.D
0431 E81000 934 CAll INIT_DRV_R
0434 7200 935 JC nUT_DRV_OUT
936
937 j----- 00 DRIVE ONE
938
0436 C6D64Z000C 939 MOV CMD_BlOCK+D. INIT _DlN_Ct1D
0436 C606430020 940 MDV tHO_BLOCK+ 1. 001000006
0440 E80100 941 CALL INIT_ORV_R
0443 942 IN!T_DRV_OUT:
0443 C3 943 RET
944 WIT_DRV EHOP
945
0444 946 INIT_DRV_R PROt NEA.R
947 ASSUME ES:CODE
0444 2ACO 948 SUB Al,Al
0446 E8190 I 949 CALL tOMMAHO ISSUE THE COMMAND
0449 7301 950 JNt Bl
0448 C3 951 RET
044C 952 Bl:
044C IE 953 PUSH OS ; SAVE SEGMENT
954 ASSUME DS:Dl.It1HY
0440 2BCO 955 SUB AX,AX
044F 8E08 956 MOV OS,AX ; ESTABLISH SEGMENT
0451 C41E0401 957 LES BX,HF _TBl_VEC
0455 IF 958 POP OS ; RESTORE SEGMENT
959 ASSUHE OS:OATA
0456 E83403 960 CAll SW2:_0FF5
0459 7257 961 JC B3
045B 0308 962 ADD BX,AX
963
964 I~--~- SEND DRIVE PARAMETERS MOST SIGNIFICANT BYTE FIRST
965
0450 BFOI00 966 MOV 01.1
0460 E85FOO 967 CALL INIT_ORV_S
0463 7240 968 JC B3
969
0465 BFOOOO 970 MOV 01.0
0468 E85700 971 CALL lNlT_DRV_S
046B 7245 972 JC B3
973
0460 BF0200 974 MDV 01.2
0470 E84FOO 975 CAll INIT_ORV_S
0473 7230 976 JC B3
977
0475 BF0400 978 MDV 01.4
0478 E84700 979 CAll 1NIT_DRV_S
0478 7235 980 JC B3
981
0470 BF0300 982 MOV 01,3
0480 E83FOO 983 CAll lNIT_ORV_S
0483 7220 984 JC B3
985
0485 BF0600 986 MOV 01.6
0468 E83700 987 CAll INIT_DRY_S
048B 7225 988 JC B3
989
0480 BF0500 990 MDV 01,5
0490 E82FOO 991 CAll nUT_ORV_S
0493 7210 992 JC B3
993
0495 BF0700 994 MOV 01,7
0498 E82700 995 CAll INlT_ORY_S

38 Fixed Disk Adapter

LaC OBJ LINE SOURCE

0498 7215 99. JC B'

997
0490 BF0800 99. MOY DI,8 ; DRIVE STEP OPTION
04AQ 26eAD 1 999 MOY AL,ES:[BX + OIl
04A3 A27600 1000 MOY CONTROL_SHE.AL
1001
04A6 28C9 1002 SUB eX,ex
04A8 1003 85:
04A8 E80302 1004 CALL PORT_l
04AB EC 1005 IN AL,DX
04AC ABOl 1006 TEST AL ,R I_IOMODE ; STATUS INPUT NODE
04AE 7509 1007 JNZ 86
0480 E2:f6 1008 lOOP 85
0482 1009 B1:
0482 C606740007 1010 MaY DISK_STATUS.INITJAIL ,OPERATION FAILED
0487 f9 1011 STC
0468 C3 1012 RET
1013
0489 1014 86:
0489 E88502 1015 CALL PORT_O
04BC EC 1016 IN AL.DX
0480 2402 1017 ANO AL,2 ; HASK ERROR BIT
04BF 75Fl 1018 JNZ B1
04Cl C3 1019 RET
1020 ASSUME ES: NOTHING
1021 ENDP
1022
1023 ;----- SEND THE BHE OUT TO THE CONTROLLER
1024
04C2 1025 INIT_DRV_S PROt NEAR
04C2 E8e501 1026 CAll HD_WAIT_REQ
04C5 7207 1027 JC 01
04C7 EBA70Z 1028 CALL PORT_O
04CA 2MAOI 1029 NOV AL,ES:tBX + OIl
04CO EE 1030 OUT DX,AL
04CE 1031 01:
04CE C3 1032 RET
1033 ENDP
1034
1035 ; ------------ ---------------- - ___ -- _____ _
1036 READ LONG (AH = OAH)
1037 ; ------------ - --------------- ---------- --
1038
04CF 1039 PRoe NEAR
04CF E81900 1040 CALL CHK_LONG
0402 7268 1041 JC G8
0404 C6064200E5 1042 MOV CMD_BLDCK+O,RD_LONG_CI1O
0409 8047 1043 HOV AL.DHA_READ
0406 EB68 1044 JMP SHORT DHA_OPN
1045 ENOP
1046
1047 ; ------------------- - ----------------- __ _
1048 WRITE LONG (AH OBH)
1049 ; ----------------------------- - ----------
1050
0400 1051 PROC NEAR
0400 EBOBOO 1052
04EO 7250 1053 JC 68
04E2 C60642:00E6 1054
04E7 8048 1055 HOV Al,ONA_WRITE
04E9 EBSA 1056 JMP SHORT DNA_OPN
1057 WR_LOHG ENOP
1058
04E8 1059 PROC NEAR
04E6 A04600 1060 MOY AL.CHD_BLOCK+4
04[E 3e80 1061 CMP AL,080H
04FO FS 1062 eMC
04Fl C3 1063 RET
1064 CHK_LONG ENilP
1065
1066 ; ------------------ - -- --- ----- _____ --- __ _
1067 SEEK I AH =
OCH)
1068 ; -----------------------_ ----- ____ - _____ _
1069
04F2 1070 PROC HEAR
04F2 C606420008 1071 MOY CHO_BLoeK ,SEEK_eND
04F7 E630 1072 JMP SHORT NOMA_OPN

Fixed Disk Adapter 39

LOC 06J LINE SOURCE

1073 ENDP
1074
1075 ; --- .. -- - ... ------............... -- --- ...... --_ .. _______ "' __ .. ___ _
1076 REAl) SECTOR BUFFER UH = DEH)
1077 i -------- .. ----------------- .. ---------------------
1(178
04F9 1079
04F9 C606420DOE Hl80
04FE C60b46DOOl 1081 MOV CHD_BlOCK+4.1 , ONLY ONE BLOCK
0503 se47 11182 MOV AL.OHA_READ
050,5 E83E 1083 JMP SHORT DMA_OPH
1084 !lUi/_BUFF ENDP
108S
1086 ; .. -------------------------... -_ .. _________________ _
1187 WJfITE SECTOR BUFfER I AH = IFH)
lIJ88 ; ------------------------------------___________ _
1089
0,87 1690
OSI7 C"'428"" 1691
osee C6U46DOOl 1092 MOV CHll_BlDCK+4.1 I ONLY ONE BLOCK
0511 11948 109] MOV AL.DNA_WRITE
osn Eel8 1094 JH" SHaRT DNA_OPH

1096
1 0 97 ; --------- -- --- .. - --------________________ .... ___ .. _ ..
1098 TEST DISK READY (AH = 01 OH)
1 0 99 ; ----------------- --- _ - ---- --- --- - _____ .. ________ _
1110
0515 1101 TST_ROY PROC NEAR
0$15 C:,,6£t20ote 1102 MaV CHO_BlOCKt-O, TST_ROY_C~
05U EBlA 1103 JMP SHORT NOHA_OPN
1104 TST_RDY ENDP
1105
1106 ; --.. -----.. ----------.. ---... ---------- _____ .. _______ _
1107
Il08
RECALIBRATE (AH =
011H)
; ------------- __ "._ .. __ ... ___ ... _______________ .... _____ _

1109
OSlt 1110 HDISK_"ECAL PROC NEAR
D51C C606420001 1111 MOV tHO_BLOCK ,RECA~CHO
0521 EBU 1112 JMP SHORT NDMA_OPN
1113 HDISK_RECAL ENOP
1114
1115 ; -- .. -- .. ----------- .. ,.-- .. -------_________________ .. _____ .. __ _
1116 CONTROLLER RAM DIAGNOSTICS UH 012H) =
1117 ; - .... ---------------------- ______________ .. ______ .. ________ _
1118
0523 1119 PAce NEAR
0523 C60Mt200ED 1120 MOV
0528 EBOC 1l/!:1 JMP
1122 ,NOP
1123
1124 ; - .. ---------- .. ------------------.. ----- .... --- ____ .. _
1125 DRIVE DIAGNOSTICS (AH = 013H)
1126 ; -----------.. ..,.----- .... --- .. ----------- .... -----------
1127
052A 1128 CHK_DRV PROC NEAR
052A C6D6428eE3 1129
aS2:F EB85 1130 JMP
1131 CHK_DRV Et-I>P
1132
1133 J --... --- .......... ---- ....... ---- .. ------ .. - ......... ---.. ------------ .... -----
1134 CONTROLLER INTERNAL DIAGNOSTICS (AH = 014HI
1135 ) ---------.--- ... ------.--- .... ---- .. -- .. ------ ... ---.......... -- .. ----
1136
0531 1137 PROC NEAR
0$31 C6f16421&E4 1138 MOV CMD_BLOCK+O .CNTLR....DIAG_CHD
1139 ENDP
11ItG
1141 i -------....... ----- .. ------------------.. --.. - .. ----------------
1142 SUPPORT ROUTINES
1143 ; - .. ------.------------------------ .. --------------------- ..
ll44
1536 1145 N&lMA_OP'N:
0536 eOll2 1146 HOV AL,02H
1538 E82:700 1147 CALL COMMAND I IS$UE THE COtflAHD
0538 7221 1148 JC GIl
11-530 lun, 1149 JMP SHORT Gl

40 Fixed Disk Adapter

LOC OBJ LINE SOURCE

053F 1150 66:

053F C606740009 1151 NOV DISK_STATUS, DNA_BOUNDARY
0544 C3 1152 RET
0545 1153
0545 E85701 1154 ; SET UP FOR DNA OPEPATION
0543 72F5 ll55 JC G8
054A B003 US6 HOV AL,03H
054C E81300 1157 CALL COMMAND ; ISSUE THE COMMAND
054F nOD 1158 JC G11
0551 B003 1159 NOV Al,03H
0553 E60A 1160 OUT DMA+! 0, Al ; INITIALIZE THE DISK CHANNEL
0555 ll61 G3:
0555 E421 1162 IN AL,021H
0557 Z40F 1163 AtID Al,ODFH
0559 HZ1 1164 OUT 021H,AL
0558 EBAAOl 1165 CALL WAIT_HIT
OSSE 1166 G11:
OSSE E83800 1167 CALL EPPOR_CHK
0561 C3 1168 RET
1169
1170 ; --------------------------------------------------------
1171 ; COMNAND
1172 THIS ROUTINE OUTPUTS THE COMMAND BLOCK
1173 INPUT
1174 Al = CONTROLLER DNA/INTERRUPT REGISTER MASK
1175
1176 ; --------------------------------------------------------
1177
0562 1178 COMNAHD PRot NEAR
0562 BE4200 1179 MOV SI,OFFSET CHD_BLOCK
0565 E81B02 Ilea CALL PORT_2
0568 EE 1181 OUT DX,Al CONTROLLER SELECT PULSE
0569 E81C02 1182 CALL PORT_3
056C EE 1183 OUT OX,Al
0560 2:8C9 1184 SUB ex.cx ; WAIT COUNT
056F E80C02- 1185
0572 1186
0572 EC 1187 IN AL,OX ; GET STATUS
0573 240F 1188 ANO Al,OFH
0575 3COD 1189 CNP Al.RI_BUSY OR RI_BUS 00 Rl_REQ
0577 7409 1190 JE Cl
0579 ElF7 1191 lOOP
0578 C606740060 lIn NOV
0580 F9 1193 STC
0581 C3 1194 RET 1 ERROR RETURN
0582- 1195 Cl:
0582 Fe 1196 CLD
0583 B90600 ll97 NOV CX,6 ; BYTE COUNT
0586 1198 CM3:
0586 E8E801 1199
0589 At 1200 lOOSB ; GET THE NEXT COHNAN[) BYTE
058A EE 1201 OUT OX.AL ; OUT IT GOES
0588 E2F9 1202 lOOP CM3 ; DO MORE
1203
0580 E8EEOI 1204 CALL PORT_l ; STATUS
0590 EC 1205 IN AL,DX
0591 A80 1 1206 TEST AL,RI_REQ
0593 7406 1207 JZ CN7
0595 e606740020 1208 NOV DISK_STATUS .BAD_CNTLR
059A F9 1209 STC
0598 1210 CM7:
0598 C3 1211 RET
1212 COMMAND ENDP
1213
1214 ; ------ ------- --------- -- -- - - - - ------,. -------- ---
1215 SENSE STATUS BYTES
1216
1217 j BYTE a
1218 BIT ADDRESS VALID, WHEN SET
1219 BIT SPARE, SET TO ZERO
1220 BITS 5-4 ERROR TYPE
1221 BITS 3-0 ERROR CODE
1222
1223 BYTE 1
1224 BITS 7-6 ZERO
1225 BIT 5 DRIVE (0-11
1226 BITS 4-0 HEAD NUMBER

Fixed Disk Adapter 41

LaC OBJ LINE SOURCE

1227
1228 ; BYTE 2:
1229 BITS 7-5 CYlINDER HIGH
1230 BITS 4-0 SECTOR HUMBER
1231
1232 ; BYTE 3
1233 BITS 7-0 CYLINDER LOW
1234
1235 i ------- ------- - -------------- ------ -------------
1236
0590 1237 ERROR_CHK PROt NEAR
1238 ASSUME ES:OATA
059C A07400 1239 MOY AL,OISK_STATUS I CHECK IF THERE WAS AN ERROR
059F OACO 1240 OR Al,Al
05Al 7501 1241 JNZ G'I
05A3 C3 1242 RET
1243
1244 j----- PERFORM SENSE STATUS
1245
05A4 1246 G21:
05A4 884000 1247 MaY AX,DATA
05A 7 8EtO 1248 MaY ES,AX ESTABLISH SEGMENT
05A9 2BCO 1249 SUB AX,AX
05A6 SSFe 1250 MOY DI,AX
05AO C606420003 1251 MOY CMD_BLOCK+O ,SENSE_tHO
0562 2ACO 1252 SUB Al,Al
0564 E8ABFF 1253 CALL COMMAND i ISSUE SENSE STATUS COMMAND
0587 7223 1254 JC SENSE_ABORT ; CAHNOT RECOVER
0589 B90400 1255 MOY CX,4
osse 12:56 G22 :
05BC E8CBOO 1257 CALL HO_WAIT_REQ
05BF 7220 1258 JC G24
05Cl E8AOOI 1259 CALL PORT_O
05C4 EC 1260 IN Al.OX
05C5 26884542 1261 MaY ES :HO_ERRORt OI] .Al ; STORE AWAY SENSE BYTES
05C9 47 1262 INC or
05CA E8BI01 1263 CAll PORT_l
05CO E2ED 1264 LOOP G22
05CF E88800 1265 CALL HO_WAIT_REQ
0502 7200 1266 JC G24
0504 E09AOl 1267 CALL PORT_O
0507 EC 1268 IN AL.oX
0508 A802 1269 TEST AL.2
050A 740F 1270 JZ STAT_ERR
050e 1271 SENSE_ABORT:
05DC C6067400FF 1272 MOY DISK_STATUS .SENSE_FAIl
05El 1273 G24:
05El F9 1274 STC
05E2 C3 1275 RET
1276 ERROR_CHK ENDP
1277
05E3 1A06 1278 T_O OW TYPE_a
05E5 2706 1279 T_I OW TYPE_I
05E7 6A06 1280 T_' ow TYPE_2
05E9 7706 1281 T_' ow TYPE_3
1282
05EB 1283 STAT_ERR:
05EB 268AIE4200 1284 MOV Bl,ES:HD_ERROR ; GET ERROR BYTE
05FO 8AC3 1285 MaV AliBl
05F2 240F 1286 ANO Al.OFH
05F4 80E330 1287 AND Bl. 00 1100008 ; ISOLATE TYPE
05F7 2AFF 1288 SUB BH.BH
05F9 BI03 1289 MOV Cl.3
05FB 03EB 1290 SHR BX,Cl ; ADJUST
05FD 2EFFA7E305 1291 JMP WORD PTR CS:[BX .. OFFSET T_O I
1292 ASSUME ES:NOTHING
1293
0602 1294 TYPE a_TABLE LABEl BYTE
0602 00204020800020 1295 OB O. BAD_CHTLR .BAO_SEEK • BAO_CHTLR • TIHE_OUT, 0, BAD_CN'lLR
0609 0040 1296 OB o ,BAD_SEEK
0009 1297 TYPEO_LEN EOU $- TYPEO_ TABLE

060B 1298 TYPE I_TABLE LABEl BYTE

060B 1010020004 1299 OB BAD_ECC, BAD_ECC. BAD _AOOR_MARK. 0, RECORD_NOTJND
0610 400000110B 1300 OB BAD_SEEK.O. 0 ,DATA_CORRECTED .BAO_TRACK
OOOA 1301 TYPEl LEN EOU $-TYPEl_TABlE
0615 1302 TYPE2_TABLE LABEL BYTE
0615 0102 1303 OB BAO_CND. BAD_AD OR_HARK

42 Fixed Disk Adapter

LOC OBJ LINE SOURCE

0002 1304 TYPE2_LEN EOU $-TYPE2_ TABLE

0617 1305 TYPD_TABLE LABEL BYTE
01)17 202010 1306 DB BAD_CHTlR ,BAD_CHTLR ,BAD_ECC
0003 1307 TYPE3_lEH EOU $-TYPE3_ TABLE
1308
1309 ;----- TYPE 0 ERROR
1310
061A 1311 TYPE_O :
061A 880206 1312 MOV BX.OFFSET TYPED_TABLE
0610 3C09 1313 CMP Al. TYPED_LEN ; CHECK IF ERROR IS DEFINED
OolF 7363 1314 JAE UNDEF _ERR_l
0621 2ED7 1315 XlAT C5:TYPEO_TABLE I TABLE LOOKUP
0623 A27400 1316 MOV DISK_STATUS,AL ; SET ERROR CODE
0626 C3 1317 RET
1318
1319 ; ------ TYPE 1 ERROR
1320
0627 1321 TYPE_I:
0627 8BOB06 1322 MOV BX,OFFSET TYPE I_TABLE
062A 86ca 1323 MOV eX.AX
Obze 3COA 1324 CMP AL,TYPEl_lEN ; CHECK If ERROR IS DEFINED
06ZE 7354 1325 JAE UNDEF _ERR_l
0630 ZED7 1326 XlAT CS:TYPEl_TABLE i TABLE LOOKUP
0632 A27400 1327 MOV DISK_STATUS,Al ; SET ERROR CODE
0635 80EI08 1328 AND Cl , 08H ; CORRECTED Eec
0638 80F908 1329 CMP Cl,08H
0638 7S2A 1330 JNZ G30
1331
1332 ;----- OBTAIH ECC ERROR BURST lENGTH
1333
0630 t606420000 1334 MOV tNO_BlOtKtO IRO_Ett_tHO
0642 2ACO 1335 SUB Al,Al
0644 E8lBFF 1336 CAll COMMAND
0647 72lE 1337 JC G30
0649 E83EOO 1338 tAll HD_WAIT_REQ
064C 7219 1339 JC G30
064E E82001 1340 tALL PORT 0
0651 EC 1341 IN Al,OX
0652: 8At8 1342: MOV Cl,Al
0654 E83300 1343 tAll HD_WAIT_REQ
0657 nOE 1344 JC G30
0659 E81501 1345 CAll PORT_O
06se Et 1346 IN Al,DX
0650 A801 1347 TEST Al,OlH
065F 7406 1348 JZ G30
0661 t60674002:0 1349 MOV OISK_ STATUS, BAO_ CNTLR
0666 F9 1350 STC
0667 1351 G30:
0667 8ACl 1352: MOV Al,Cl
0669 C3 1353 RET
1354
1355 ; ----- TYPE 2 ERROR
1356
066A 1357 T'l'PE_2:
066A BBlS06 1358 MOV BX,OFFSET TYPE2_TABlE
0660 3C02 1359 CMP Al, TYPE2_LEN 1 CHECK IF ERROR IS DEFINED
066F 7313 1360 JAE UHDEF _ERR_L
0671 2E07 1361 XLAT CS:TYPEl_TABlE ; TABLE LOOKUP
0673 A27400 1362 MOV DISK_STATUS,AL ; SET ERROR CODE
0676 C3 1363 RET
1364
1365 1----- TYPE '3 ERROR
1366
0677 1367 TYPE_3:
0677 BB1706 1368 MOV BX,OFFSET TYPE3_ TABLE
067A 3t03 1369 CMP Al, TYPE3_LEN
067t 7306 1370 JAE UHOEF _ERR_l
067E 2E07 1371 XLAT CS:TYPE3_TABlE
0680 A2:7400 1372 MOV DISK_STATUS,AL
0683 t3 1373 RET
1374
0684 1375 UNDEF _ERR_L:
0684 C6067400BB 1376 MOV DISK_STATUS,UHDEF _ERR
0689 C3 1377 RET
1378
068A 1379 HO_WAIT_REQ PROt NEAR
068A 51 1380 PUSH cx

Fixed Disk Adapter 43

LOC OBJ LINE SOURCE

068& 28C9 1381 SU8 eX,ex

068D E8[EOO 1382 CALL PORT_l
0690 1383 U:
0690 EC 1384 IN AL,OX
0691 A801 1385 TEST AL,Rl_REQ
0693 75118 1386 JNZ I'
0695 E2F9 1387 lOOP LI
0691 C606740080 1388 I10V DISK_STATUS. TIME_OUT
069C F9 1389 5TC
069D 1390 L2:
069D 59 1391 pop CX
069E CS 1392 RET
1393 HD_WAIT_REQ EtIlP
1394
1395 J -------------------------------- - .. - ...... ---------- .. --.,. .. -_ ..
1396 ; DMA_SETUP
1397 ntIS ROUTINE SETS UP FOR DHA OPERATIONS.
1198 i INPUT
1399 (AU :: HODE BYTE FOR THE DHA
1400 (ES:8Xl ;:; ADDRESS TO READ/WRITE THE DATA
1401 I OUTPUT
1402 I AX) OESTROYED
1403 J .. -------------- .. ----------------------------------------
069F 1404 DHA_SETUP PROC NEAR
069F 50 1405 PUSN AX
0640 404600
06A3 3(:81
06.5 58
06A6
06A8 F9
n02
1406
1407
1408
1409
1'\10
I10V
CMP
POP
JB
5TC
.
AL.CI1D_BlOCK"4
AL,8tH

JI
I BLOCK COUNT OUT OF RANGE

06A9 C3 1411 RET

06AA 1412 Jl:
06AA 51 1413 PUSH CX I SAVE THE REGISTER
06A8 FA 1414 CLI j NO MORE INTERRUPTS
06AC E60C 1415 OUT DI1A+12,AL I SET THE FIRSTILAST FIF
MAE 50 1416 PUSH AX
06AF 58 1417 POP AX
0680 E~08 1418 OUT DHA+ll.AL J OUTPUT THE MODE BYTE
0682 eceo 1419 "OV AX,ES j GET THE ES VALUE

06B4 BI04 1420 "OV Cl.4 , SHlFT COUNT

06B6 DlGO 1421 ROI AX,CL I ROTATE LEFT
068& SAES 1422 "OV CH,AL i GET HIGHEST NYBBLE OF ES TO CH
06BA 24FO 1423 AND Al.OFOH , ZERO THE LOW NYBBLE FROM SEGHENT
Obec 03C3 1424 ADD AX.BX I TEST FOR CARRY FROM ADDITION
06BE 7302 1425 mc J33
06CO FEC5 1426 lNC eH I CARRY HEANS HIGH 4 BITS MUST BE tNC
06C2 1427 J33:
06C2 50 1428 PUSN AX , SAVE START ADDRESS
06C3 E606 1429 OUT DI1A+6"U 1 OUTPUT LOW ADDRESS
06C5 8AC4 1430 MOV AL.AH
06C7 E606 1431 OUT OMA+6,Al j OUTPUT HIGH ADDRESS

06C9 8ACS 1432 I10V AL,CH I GET HIGH 4 BITS

06CB 240F 1435 ANO AL.OFH
06CD E682 1434 OUT DHA_HIGH.AL i OUTPUT THE HIGH 4 BITS TO PAGE REG
1435
1436 1-----.. OETERHINE COUNT
1437
06CF A04600 U.38 I10V Al,CtID_BLOCK+4 I RECOVER BLOCK COUNT
0602 ODED 1439 SNI AL.l I HULTIPLY BY 512 BYTES PER SECTOR
0604 FEC8 1440 DEC Al ANO DECREMENT VALUE BY ONE
0606 8AEO 1441 I10V AH,Al
0608 BOFF 1442 I10V AL,OFFH
1443

060A 50
0608 Mft200
06DE 3Ce5
1444
1445
1446
1447
1448
PUSH
,",V
C"P
.
1----- HAtilLE READ AND WRITE LONG 15160 BYTE BLOCKS)

AL,ct1D_aLOCK+O
ALoRD_LONG_CHO
I SAVE REGISTER
I GET COMMAND

06EO 7407 1449 JE ADD_

06E2 3CE6
06E4 7403
06E6 58
06E7 EBll
1450
1451
1452
1453
C"P
JE
POP
J"P
.
AL.WR_lONG_CMD
A004

SHORT J20
1 RESTORE REGISTER

06E9 1454 ADD4;

06E9 58 1't55 POP AX I RESTORE REGIST~R
06EA aa0402 1456 ,",V AX,516D I ONE BLOCK (512) PLUS 4 BYTES ECC
06ED 53 1457 PUSN BX

44 Fixed Disk Adapter

LOC OBJ LINE SOURCE

06Ef 2AFF 1458 SUB SH,SH

06FO 8AIE4600 1459 MOV BL,CMD_BLOCK+4
06F4 52 1460 PUSH OX
06F5 F7E3 1461 MUL BX ; BLOCK COUHT TIMES Sib
06F7 SA 1462 PDP OX
06F8 58 1463 PDP BX
06F9 48 1464 DEC AX I ADJUST
06FA 1465 J20:
1466
06FA 50 1467 PUSH AX SAVE COUHT VALUE
06FB E607 1468 OUT DMA+7.AL lOW BYTE OF COUNT
06FO 8AC4 1469 MOV AL,AH
D6FF f607 1470 OUT OHA+7,AL 1 HIGH BYTE OF COUHT
0701 FB 1471 sn ; INTERRUPTS BACK ON
0702 S9 1472 POP CX ; J;!ECOVER COUtU VALUE
0703 58 1473 POP AX ; RECOVER ADDRESS VALUE
0704 03el 1474 ADD AX,ex ; ADD. TEST FOR 64K OVERflOW
0706 59 1475 POP CX ; RECOVER REGISTER
0707 C3 1476 .ET ; RE11..IRN TO cALLER. CFL SET BY ABOVE IF ERROR
1477 DHA_SETUP ENOP
1478
1479 ,------------------------------------------------
1480 ; WAIT_lNT
1481 THIS ROUTINE WAITS FOR THE FIXED DISK
1482 CotHROLLER TO SIGNAL THAT AN ItHERRUPT
1483 HAS OCCURRED.
1484 ; ------------------ -- ----- --------------- --------
0708 1485 WAIT_INT PIWC NEAR
0708 FB 1486 sn TURN ON INTERRUPTS
0709 53 1487 PUSH BX PRESERVE REGISTERS
070A 51 1488 PUSH CX
070B 06 1489 PUSH ES
070C 56 1490 PUSH 51
0700 IE 1491 PUSH OS
1492 ASSUME OS:DUHMY
070E 2BCO 1493 SUB AX,AX
0710 8E08 1494 MOV DS,AX I ESTABLISH SEGMENT
0712 C4360401 1495 LES SI,HF_TBl_VEC
1496 ASSUME OS:DATA
0716 IF 1497 POP OS
1498
1499 ;----- SET TIMEOUT VAlUES
1500
0717 2AFF 1501 SUB BH,BH
0719 268A5C09 1502 HOV BL,BYTE PTR ES:tSIlt91 ; STANDARD TIME OUT
071D 8A264200 1503 MOV AH,CMD_BLOCK
ani 80FC04 1504 CMP AH.FMTDRV_CMD
0724 7506 1505 JHZ W5
0726 268A5COA 1506 MOV Bl.IHTE PTR ES:[SIHOAH] FORMAT DRIVE
072A EB09 1507 JMP SHORT W4
onc 80Fcn 1508 1015: CMP AH. CHK_DRV _CND
onF 7504 1509 JHZ W4
0731 268A5COB 1510 MOV Bl.BHE PTR ES:[SIl!OBHl ; CHECK DRIVE
0735 1511 1014:
0735 28C9 1512 SUB CX.CX
1513
1514 1----- WAIT FOR INTERRUPT
1515
0737 1516 loll:
0737 £84400 1517 CALL PORT_l
073A EC 1518 IN AL,DX
0738 2420 1519 AND ,A,L.020H
0730 3C20 1520 CMP Al.020H ; DID INTERRUPT OCCUR
073F 740A 1521 JZ W'
0741 E2F4 1522 LOOP WI ; INNER LOOP
0743 4B 1523 DEC BX
0744 75Ft 1524 JHZ WI • OUTER LOOP
0746 C606740080 1525 MOV DISK_STATUS. TIME_OUT
0748 1526 1012:
074B E82300 1527 CALL PORT_O
074E EC 1528 IN AL.DX
074F 2402 1529 MID AL.2 ; ERROR BIT
0751 08067400 1530 OR DISK_STATUS.AL ; SAVE
0755 E83000 1531 CALL PORT_3 ; INTERRUPT MASK REGISTER
0758 32CO 1532 XOR AL,AL ; ZERO
075A EE 1533 OUT OX.AL ; RESET MASK
0758 5E 1534 POP 51 ; RESTORE REGISTERS

Fixed Disk Adapter 45

LOC OBJ LINE SOURCE

07se 07 1535 pop ES

0750 59 1536 pop CX
07SE 58 1537 POP BX
075F C3 1538 RET
1539 WAIT_INT ENOP
1540
0760 1541 HD_INT PROC NEAR
0760 50 1542 PUSH AX
0761 B020 1543 MOV AL,EOI J END OF INTERRUPT
0763 E620 1544 OUT INT_CTL_PORT,Al
0765 B007 1545 MOV AL,07H ; SET DHA HOOE TO DISABLE
0767 E60A 1546 OUT DMA+IO,AL
0769 E421 1547 IN AL,OZlH
0766 DClD 1548 OR AL.020H
0760 E621 1549 OUT 021H,AL
076f 58 1550 POP AX
0770 CF 1551 IRET
1552 HD_INT ENOP
1553
1554 ;----------------------------------------
1555 , PORTS
1556 GENERATE PROPER PORT VALUE
1557 8ASED ON THE PORT OfFSET
1558 1----------------------------------------
1559
0771 1560 PORT_O PROC NEAR
0771 BA2003 1561 MOV DX.HF _PORT j BASE VALUE
0774 50 1562 PUSH AX
0775 2AE4 1563 SUB AH,AH
0777 A07700 1564 MOV .U,PORT_OFF I ADO IN THE OFFSET
077A 0300 1565 ADO OX.AX
077C 58 1566 POP AX
0770 C3 1567 RET
1568 PDRT_O ENOP
1569
077E 1570 PORT_l PROC NEAR
077E E8FOFF 1571 CALL PORT_O
0781 42 1572 INC OX ; INCREMENT TO PORT ONE
0782 C3 1573 RET
1574 PORT_l ENOP
1575
0783 1576 PORT_2 PROC NEAR
0783 E8F8FF 1577 CALL PORT_1
0786 42 1578 INC OX I INCREMENT TO PORT TWO
0787 C3 1579 RET
1580 PORT_2 ENOP
1581
0788 1582 PORT_3 PROC NEAR
0788 E8F8FF 1583 CALL PORT_2
0768 4Z 1564 INC OX • INCREMENT TO PORT THREE
076C C3 1585 RET
1566 PORT_3 ENOP
1587
1566 ; -------~----------------------------------------
1589 I SW2_0FFS
1590 DETERHINE PARAMETER TABLE OFFSET
1591 USING CONTROllER PORT T1oIO AND
1592 DRIVE NUNBER SPECIFIER (0-1)
1593 1------------------------------------------------
1594
0780 1595 SW2.0FFS PROC NEAR
0780 E8F3FF 1596 CALL PORT_2
0790 EC 1597 IN AL.OX I READ PORT 2
0791 50 1598 PUSH AX
07901: E8E9FF 1599 CALL PORT_I
0795 EC 1600 IN AL,DX
0796 2402 1601 ANO AL.Z I CHECK FOR ERROR
0798 58 1602 POP AX
0799 7516 1603 JNZ SW2_0FFS_ERR
0798 8A264300 1604 MOY AH .CMD_BLOCK+l
079F 80E420 1605 ANO AH.00I00000B I DRIVE 0 OR 1
07A2 7504 1606 JNZ SW2_AND
07A4 00E8 1607 SHR Al.I ; ADJUST
07A6 DOE8 1608 SHR AL.I
07A8 1609 SW2_AND:
07A8 2403 1610 ANO AL.OllB I ISOLATE
07AA 8104 1611 MeV Cl.ft

46 Fixed Disk Adapter

LOC OBJ LINE SOURCE

07Ae 02EO 1612 SHL AL,CL I ADJUST

07AE 2AE4 1613 SUB AH,AH
07BO C3 1614 RET
07Bl 1615 SW2_0FFS_ERR:
07Bl F9 1616 STC
0782 C3 1617 RET
1618 SW2_0FfS EHOP
1619
07B3 30382F31362F38 1620 DB '08/16/82' ; RELEASE MARKER
32
1621
07B6 1622 END_ADDRESS LABEl BYTE
1623 CODE ENOS
1624 ENO

Fixed Disk Adapter 47

Notes:

48 Fixed Disk Adapter

--
- -- -- -
-
--- -
---- Personal Computer
--
-- --
-_
-
- ---
---
-.- Hardware Reference
Library

Fixed Disk and Diskette

Drive Adapter
Contents

Description .................................... 1
Fixed Disk Function ............................. 1
Task File .................................. 2
Task File Registers .......................... 2
Miscellaneous Information ................... 11
Diskette Function .............................. 11
Diskette Controller ......................... 14
Diskette Controller Commands ............... 16
Controller Commands ...................... 20
Command Status Registers ................... 32
Interfaces .................................... 36
Interface Lines ............................ 37
Logic Diagrams ................................ 41

iii
Notes:

iv
Description

The IBM Personal Computer AT Fixed Disk and Diskette Drive

Adapter connects to the system board using one of the system
expansion slots. The adapter controls the 5-1/4 inch diskette
drives and fixed disk drives. Connectors on the adapter supply all
the signals necessary to operate up to two fixed drives and one
diskette drive or one fixed drive and two diskette drives. The
adapter will allow concurrent data operations on one diskette and
one fixed disk drive.

The adapter operates when connected to a system board

expansion slot. This channel is described in the" System Board"
section of the IBM Personal Computer AT Technical Reference
Manual.

Fixed Disk Function

The fixed disk function features 512-byte sectors; high-speed,

programmed input/output (PIO) data transfers; error correction
code (ECC) correction of up to five bits on data fields; multiple
sector operations across track and cylinder boundaries; and
on-board diagnostic tests. The adapter will support two fixed
disks with up to 16 read/write heads and 1024 cylinders.

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 1
Task File
A task file, which contains eight registers, controls fixed-disk
operations. The following figure shows the addresses and
functions of these registers.

I/O Address
Primary Secondary Read Write
1 FO 170 Data Register Data Register
1 F1 171 Error Register Write Precomp
1 F2 172 Sector Count Sector Count
1 F3 173 Sector Number Sector Number
1 F4 174 Cylinder Low Cylinder Low
1F5 175 Cylinder High Cylinder High
1 F6 176 Drive/Head Drive/Head
1 F7 177 Status Register Command Register
Task File

Task File Registers

Data Register

The data register provides access to the sector buffer for read and
write operations in the PIG mode. This register must not be
accessed unless a Read or Write command is being executed. The
register provides a 16-bit path into the sector buffer for normal
Read and Write commands. When a R/W Long is issued, the 4
ECC bytes are transferred by byte with at least 2 microseconds
between transfers. Data Request (DRQ) must be active before
I I

the transferring of the ECC bytes.

Error Register

The error register is a read-only register that contains specific

information related to the previous command. The data is valid
only when the error bit in the status register is set, unless the
adapter is in diagnostic mode. Diagnostic mode is the state
immediately after power is switched on or after a Diagnose
command. In these cases, the register must be checked regardless
of the status register indicator. The following are bit values for
the diagnostic mode.

August 31, 1984

2 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Diagnostic Mode

01 No errors

02 Controller error

03 Sector buffer error

04 ECC device error

05 Control processor error

The following are bit definitions for the operational mode.

Operational Mode

Bit 0 Data Address Mark (DAM) Not Found-This bit

indicates that DAM could not be found within 16 bytes
of the ID field.

Bit 1 TR 000 Error-This bit will be set if, during a Restore

command, the track 000 line from the fixed disk is not
true within 1023 step pulses to the drive.

Bit 2 Aborted Command-A command is aborted based on

the drive status (Write Fault, Not Seek Complete, Drive
Not Ready, or an invalid command). The status and
error registers may be decoded to determine the cause.

Bit 3 Not used.

Bit 4 ID Not Found-The ID field with the specified cylinder,

head, and sector number could not be found. If retries
are enabled, the controller attempts to read the ID 16
times before indicating the error. If retries are disabled,
the track is scanned a maximum of two times before
setting this error bit.

Bit 5 Not used

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 3
Bit 6 Data Eee Error-This bit indicates that an
uncorrectable Eee error occurred in the target's data
field during a read command.

Bit 7 Bad Block Detect-This bit indicates that the bad block
mark was detected in the target's ID field. No Read or
Write commands will be executed in any data fields
marked bad.

Write Precompensation Register

The value in this register is the starting cylinder number divided

by 4. The I reduced write current I signal to the drive is activated
and the adapter's write precompensation logic is turned on when
this number is entered into the register.

Sector Count Register

The sector count register defines the number of sectors to be

transferred during a Verify, Read, Write, or Format command.
During a multi-sector operation, the sector count is decremented
and the sector number is incremented. When the disk is being
formatted, the number of sectors per track must be loaded into
the register prior to each Format command. The adapter supports
multi-sector transfers across track and cylinder boundaries. The
drive characteristics must be set up by the Set Parameters
command before initiating a multi-sector transfer. The sector
count register must be loaded with the number of sectors to be
transferred for any data-related command.

Note: A 0 in the sector count register specifies a 256-sector

transfer.

Sector Number Register

The target's logical sector number for Read, Write, and Verify
commands is loaded into this register. The starting sector number
is loaded into this register for multi-sector operations.

August 31, 1984

4 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Cylinder Number Registers

The target number for Read, Write, Seek, and Verify commands
is loaded into these registers as shown in the following figure. The
cylinder-number registers address up to 1024 cylinders.

Cylinder High Cylinder Low

Register Bits 76543210 76543210
Cvlinder Bits --98 76543210
Cylinder Number Registers

Drive/Head Register

Bit 7 Set to 1

Bit 6 Set to 0

Bit 5 Set to 1

Bit 4 Drive Select-This bit selects the drive. A 0

indicates the first fixed disk drive, and a 1
indicates the second.

Bit 3-Bit 0 Head Select Bits-Bits 3 through 0 specify the

desired read/write head. Bit 0 is the
least-significant (0101 selects head 5). The
adapter supports up to 16 read/write heads. For
access to heads 8 through 15, bit 3 of the fixed
disk register (address hex 3F6) must be set to 1.

Note: This register must be loaded with the maximum

number of heads for each drive before a Set Parameters
command is issued.

Status Register

The controller sets up the status register with the command status
after execution. The program must look at this register to
determine the result of any operation. If the busy bit is set, no
other bits are valid. A read of the status register clears interrupt

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 5
request 14. If -write fault or error is active, or if -seek
I I I I I

complete or -ready is inactive, a multi-sector operation is

I I I

aborted.

The following defines the bits of the status register:

Bit 7 Busy-This bit indicates the controller's status.

A 1 indicates the controller is executing a
command. If this bit is set, no other status
register bit is valid, and the other registers reflect
the status register's contents; therefore, the busy
bit must be examined before any fixed disk
register is read.

Bit 6 Drive Ready-A 1 on this bit together with a 1

on seek complete bit (bit 4) indicates that the
fixed disk drive is ready to read, write, or seek. A
o indicates that read, write, and seek are
inhibited.

Bit 5 Write Fault-A 1 on this bit indicates improper

operation of the drive; read, write, or seek is
inhibited.

Bit 4 Seek Complete-A 1 on this bit indicates that the

read/write heads have completed a seek
operation.

Bit 3 Data Request-This bit indicates that the sector

buffer requires servicing during a Read or Write
command. If either bit 7 (busy) or this bit is
active, a command is being executed. Upon
receipt of any command, this bit is reset.

Bit 2 Corrected Data-A 1 on this bit indicates that

the data read from the disk was successfully
corrected by the ECC algorithm. Soft errors will
not end multi-sector operations.

Bit 1 Index-This bit is set to 1 each revolution of the

disk.

August 31, 1984

6 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Bit 0 Error-A 1 on this bit indicates that the previous
command ended in an error, and that one or more
bits are set in the error register. The next
command from the controller resets the error bit.
This bit, when set, halts multi-sector operations.

Command Register

The command register accepts eight commands to perform fixed

disk operations. Commands are executed by loading the task file
and writing in the command register while the controller status is
not busy. If -write fault is active or if -drive ready or -seek
I I I I I

complete are inactive, the controller will not execute any

I

command. Any code not defined in the following figure causes an

Aborted Command error. Interrupt request 14 is reset when any
command is written. The following are acceptable commands to
the command register.

Command Bits
7 6 5 4 3 2 1 0
Restore 0 0 0 1 R3 R2 Rl RO
Seek 0 1 1 1 R3 R2 Rl RO
Read Sector 0 0 1 0 0 0 L T
Write Sector 0 0 1 1 0 0 L T
Format Track 0 1 0 1 0 0 0 0
Read Verify 0 1 0 0 0 0 0 T
Diagnose 1 0 0 1 0 0 0 0
Set Parameters 1 0 0 1 0 0 0 1
Valid Command-Register Commands

Note: Stepping rate values and bit definitions for Land T

are shown in the following figures.

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 7
The following figure shows the stepping rate as defined by R3
through RO.

R3 R2 R1 RD Stepping Rate
a a a a 35 us
a a a 1 0.5 ms
a a 1 a 1.0 ms
a a 1 1 1.5 ms
a 1 a a 2.0ms
a 1 a 1 2.5 ms
a 1 1 a 3.0ms
a 1 1 1 3.5 ms
1 a a a 4.0ms
1 a a 1 4.5 ms
1 a 1 a 5.0 ms
1 a 1 1 5.5 ms
1 1 a a 6.0 ms
1 1 a 1 6.5 ms
1 1 1 a 7.0 ms
1 1 1 1 7.5 ms
Stepping Rate

Note: After a Diagnose or Reset Command, the stepping

rate is set to 7.5 milliseconds.

The following figure shows the bit definitions for bits Land T.

Bit Definition D 1
L Data Mode Data Only Data Plus 4 Byte ECC
T Retry Mode Retries Enabled Retries Disabled
Land T Bit Definitions

Note: When retries are disabled, ECC and ID field retries

are limited to less than two complete revolutions.

Following are descriptions of the valid command-register

commands.

Restore: The controller issues step pulses to the drive until the
Track 000 indicator from the drive is active. If Track 000 is not
active within 1023 steps the error bit in the status register is set
and a Track 000 error is posted in the error register. The implied
seek step rate can be set up using the stepping rate figure on the

August 31, 1984

8 Personal Computer AT Fixed Disk and Diskette Drive Adapter
previous page. The restore step rate is established by the seek
complete signal from the drive (each step pulse is issued after
seek complete is asserted by the drive from the previous step).

Seek: The Seek command moves the R/W heads to the cylinder
specified in the task files. The adapter supports overlapped
seeking on two drives or setup of the buffered seek stepping rate
for the implied seek during a Read/Write command. An interrupt
is generated at the completion of the command.

Read Sector: A number of sectors (1-256) may be read from

the fixed disk with or without the ECC field appended in the
Programmed I/O (PIO) mode. If the heads are not over the
target track, the controller issues step pulses to the drive and
checks for the proper ID field before reading any data. The
stepping rate used during the implied seek is the value specified
during the previous Seek or Restore command. Data errors, up to
5 bits in length, are automatically corrected on Read Short
commands. If an uncorrectable error occurs, the data transfer
still takes place; however, a multi-sector read ends after the
system reads the sector in error. Interrupts occur as each sector is
ready to be read by the system. No interrupt is generated at the
end of the command, after the last sector is read by the system.

Write Sector: A number of sectors (1-256) may be written to

the fixed disk with or without the ECC field appended in the PIO
mode. The Write Sector command also supports implied seeks.
Interrupts for the Write command occur before each sector is
transferred to the buffer (except the first) and at the end of the
command. The first sector may be written to the buffer
immediately after the command has been sent, and I -data
request is active.
I

Format Track: The track specified by the task file is formatted

with ID and data fields according to the interleave table
transferred to the buffer. The interleave table is composed of two
bytes per sector as follows: 00, Physical Sector 1, 00, Physical
Sector 2, ... 00, Physical Sector 17. The table for 2-to-l
interleave is: 00,01,00, OA, 00, 02, 00, OB, 00, 03, 00, OC, 00,
04,00,OD,00,05,00,OE,00,06,00,OF,00,07,00,10,00,08,
00, 11, 00, 09. The data transfer must be 512 bytes even though
the table may be only 34 bytes. The sector count register must be
loaded with the number of sectors per track before each Format

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 9
Track command. An interrupt is generated at the completion of
the command; the Format Track command supports no error
reporting. A bad block may be specified by replacing a 00 table
entry with an 80.

When switching between drives, a restore command must be

executed prior to attempting a format.

Preform the following when formatting a drive with more than 8

read/write heads:

1. Restore

2. Format all cylinders, heads 0 - 7 only

3. Restore

4. Format all cylinders, heads 8 and above.

Read Verify: This command is similar to to a Read command

except that no data is sent to the host. This allows the system to
verify the integrity of the fixed disk drive. A single interrupt is
generated upon completion of the command or in the event of an
error.

Diagnose: This command causes the adapter to execute its

self-test code and return the results to the error register. An
interrupt is generated at the completion of this command.

Set Parameters: This command sets up the drive parameters

(maximum number of heads and sectors per track). The
drive/head register specifies the drive affected. The sector count
and drive/head registers must be set up before this command is
issued. The adapter uses the values specified for track and
cylinder crossing during multi-sector operations. An interrupt is
generated at the completion of this command. This command
must be issued before any multi-sector operations are attempted.
The adapter supports two fixed disk drives with different
characteristics, as defined by this command.

August 31, 1984

10 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Miscellaneous InCormation
The following is miscellaneous information about the fixed disk
drive function.

• The adapter performs normal read/write operations on a

data field only after a successful match of that sector's ID
with the targeted ID.

• ID fields are checked for errors when read from the disk.

• The adapter supports only Eee on data fields and only eRe
on ID fields. The eRe polynomial is X16 + X12 + X5 + 1;
the Eee polynomial is X32 + X28 + X26 + X19 + X17 +
X10 + X6 + X2 + 1. All shift registers are preset to hex F
before calculating the checksums, which begin with the
respective address marks.

Diskette Function

The 5-1/4 inch diskette drive function is an integral part of the

Fixed Disk and Diskette Drive Adapter. One or two diskette
drives are attached to the adapter through an internal,
daisy-chained, flat cable. The attachment will support 160K.-,
320K.-, and 1.2M.-byte diskette drives.

The address assignments for diskette functions are shown in the

following figure.

I/O Address
Primary Secondary Read Write
3F2 372 - Digital Output Register
3F4 374 Main Status Register Main Status Register
3F5 375 Diskette Data Register Diskette Data Register
3F6 376 - Fixed Disk Register
3F7 377 Digital Input Register Diskette Control Register
Diskette Function

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 11
The adapter is designed for a double-density, MFM-coded,
diskette drive and uses write precompensation with an analog
circuit for clock and data recovery. The diskette-drive parameters
are programmable, and the diskette drive's write-protect feature is
supported. The adapter is buffered on the I/O bus and uses the
system board's direct memory access (DMA) for record data
transfers. An interrupt level also is used to indicate when an
operation is complete and that a status condition requires
microprocessor attention.

Digital Output Register (hex 3F2)

The digital output register (DOR) is an output-only register used

to control drive motors, drive selection, and feature enable. The
bit definitions follow:

Bit 7 Reserved

Bit 6 Reserved

Bit 5 Drive B Motor Enable

Bit 4 Drive A Motor Enable

Bit 3 Enable Diskette Interrupts and DMA

Bit 2 Diskette Function Reset

Bit 1 Set to a logical 0

Bit 0 Drive Select-A 0 on this bit indicates that drive

A is selected.

Note: A channel reset clears all bits.

Digital Input Register (hex 3F7)

The digital input register is an 8-bit, read-only register used for

diagnostic purposes. The following are bit definitions for this
register:

August 31, 1984

12 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Bit 7 Diskette Change

Bit 6 Write Gate

Bit 5 Head Select 3/Reduced Write Current

Bit 4 Head Select 2

Bit 3 Head Select 1

Bit 2 Head Select 0

Bit 1 Drive Select 1

Bit 0 Drive Select 0

Note: Bits 0 through 6 apply to the currently

selected fixed disk drive. These bits are valid
for 50 microseconds after a write to the
Drive Head Register.

Data Rates
The diskette function will support three data rates: 250,000,
300,000 and 500,000 bits per second.

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 13
Diskette Controller
The diskette controller has two registers to which the system
unit's microprocessor has access: a status register and a data
register. The status register may only be read and is used to
facilitate the transfer of data between the processor and diskette
controller. The 8-bit status register has the status information
about the diskette and may be accessed at any time. The 8-bit
data register (hex 3F5), which actually consists of several
registers in a stack with only one register presented to the data
bus at a time, stores data, commands, and parameters, and
provides diskette-drive status information. Data bytes are read
from or written to the data register in order to program or obtain
results after a particular command.

The bits in the status register (hex 34F) are defined as follows:

Bit 7 Request for Master (RQM)- The data register

is ready to send or receive data to or from the
processor.

Bit 6 Data Input/Output (DIO)-The direction of

data transfer between the diskette controller and
the processor. If this bit is a 1, transfer is from
the diskette controller's data register to the
processor; if it is a 0, the opposite is true.

Bit 5 Non-DMA Mode (NDM)-The diskette

controller is in the non-DMA mode.

Bit 4 Diskette Controller Busy (CB)- A Read or

Write command is being executed.

Bit 3 Reserved

Bit 2 Reserved

Bit 1 Diskette Drive B Busy (DBB)- Diskette drive

B is in the seek mode.

Bit 0 Diskette Drive A Busy (DAB)- Diskette drive

A is in the seek mode.

August 31, 1984

14 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Diskette Control Register (hex 3F7)

This register is assigned two addresses, hex 3F7 (primary) and

hex 377 (secondary). This is a four bit write only register. The
bits are defined as follows:

Bits 7 - 2 Reserved

Bits 2 - 0 Diskette Data Rate- These bits select the

diskette data rate as shown in the following
figure:

Bit 0 Bit 1 Diskette

Data Rate
0 0 500,000 bps
0 1 300,000 bps
1 0 250.000 bps
1 1 Unused
Diskette Data Rate

Fixed Disk Register (hex 3F6)

This register is assigned two addresses, 3F6 (primary) and 376

(secondary). This is a four bit write only register. The bits are
defined as follows:

Bits 7 - 4 Reserved

Bit 3 A logical 0 enables reduced write current. A

logical 1 enables head select 3.

Bit 2 A logical 1 enables reset fixed disk function.

Bit 1 A logical 0 enables fixed disk interrupts.

Bit 0 Reserved

Note: Bit 3 defines the function of the fixed disk control

interface connector (pin 2).

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 15
Diskette Controller Commands
The diskette controller can perform 16 different commands.
Each command is initiated by a multibyte transfer from the
processor, and the result after execution of the command may
also be a multibyte transfer back to the processor. Because of
this multibyte interchange of information between the diskette
controller and the processor, each command can be considered to
consist of three phases:

Command Phase: The processor issues a sequence of Write

commands to the diskette controller that direct the controller to
perform a specific operation.

Execution Phase: The diskette controller performs the specified

operation.

Result Phase: After completion of the operation, status and

other housekeeping information is made available to the processor
through a sequence of Read commands to the processor.

The following is a list of commands that may be issued to the

diskette controller:

• Read Data

• Read Deleted Data

• Write Data

• Write Deleted Data

• Read a Track

• Read ID

• Format a Track

• Scan Equal

• Scan Low or Equal

• Scan High or Equal

August 31, 1984

16 Personal Computer AT Fixed Disk and Diskette Drive Adapter
• Recalibrate

• Sense Interrupt Status

• Specify

• Sense Drive Status

• Seek

• Invalid.

Symbol Descriptions

The following are descriptions of the symbols used in the

"Command Definitions" later in this section.

AO Address Line O-A logical 0 selects the main status

register, and a 1 selects the data register.

C Cylinder Number-Contains the current or selected

cylinder number in binary notation.

D Data-Contains the data pattern to be written to a

sector.

D7 -DO Data Bus-An 8-bit data bus in which D7 is the

most-significant bit and DO is the least- significant.

DTL Data Length-When N is 00, DTL is the data length to

be read from or written to a sector.

EOT End of Track-The final sector number on a cylinder.

GPL Gap Length-The length of gap 3 (spacing between

sectors excluding the VCO synchronous field).

H Head Address-The head number, either 0 or 1, as

specified in the ID field.

HD Head-The selected head number, 0 or 1. (H = HD in

all command words.)

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 17
HLT Head Load Time-The head load time in the selected
drive (2 to 256 milliseconds in 2- millisecond increments
for the 1.2M-byte drive and 4 to 512 milliseconds in 4
millisecond increments for the 320K-byte drive ).

HUT Head Unload Time-The head unload time after a read

or write operation (0 to 240 milliseconds in
16-millisecond increments for the 1.2M-byte drive and 0
to 480 milliseconds in 32- millisecond increments for the
320K-byte drive.

MF FM or MFM Mode-A 0 selects FM mode and a 1

selects MFM (MFM is selected only if it is
implemented. )

MT Multitrack-A 1 selects multitrack operation. (Both

HDO and HDI will be read or written.)

N Number-The number of data bytes written in a sector.

NCN New Cylinder-The new cylinder number for a seek

operation

ND Non-Data Mode- This indicates an operation in the

non-data mode.

PCN Present Cylinder Number-The cylinder number at the

completion of a Sense interrupt status command
(present position of the head).

R Record-The sector number to be read or written.

R/W Read/Write-This stands for either a I read or write

I I I

signal.

SC Sector-The number of sectors per cylinder.

SK Skip-This stands for skip deleted-data address mark.

August 31, 1984

18 Personal Computer AT Fixed Disk and Diskette Drive Adapter
SRT This 4 bit byte indicates the stepping rate for the
diskette drive as follows:

1.2M-Byte Diskette Drive

1111 1 millisecond
111 a 2 milliseconds
11 a 1 3 milliseconds

320K-Byte Diskette Drive

1111 2 milliseconds
111 a 4 milliseconds
11 a 1 6 milliseconds

ST O-ST 3 Status a-Status 3-0ne of the four registers that

stores status information after a command is executed.

STP Scan Test-If STP is 1, the data in contiguous sectors is

compared with the data sent by the processor during a
scan operation. If STP is 2, then alternate sections are
read and compared.

USO-US1 Unit Select-The selected driver number encoded the

same as bits a and 1 of the digital output register
(DOR).

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 19
Controller Commands
The following are commands that may be issued to the controller.

Note: An X is used to indicate a don't-care condition.

Commands not shown in binary format are shown as bytes.

Read Data

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
MT MF SK 0 0 1 1 0
X X X X X HO US1 usa
c
H
R
N
EOT
GPL
OTL

Result Phase: The following bytes are issued by the controller in

the result phase:

STO
STl
ST2
C
H
R
N

August 31, 1984

20 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Read Deleted Data

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
MT MF SK 0 1 1 0 0
X X X X X HO US1 usa
c
H
R
N
EOT
GPL
OTL

Result Phase: The following bytes are issued by the controller in

the result phase:

STO
STl
C
H
R
N

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 21
Write Data

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
MT MF a a a 1 a 1
x X x x X HO US1 usa
c
H
R
N
EaT
GPL
OTL

Result Phase: The following bytes are issued by the controller in

the result phase:

STO
STl
ST2
C
H
R
N

August 31, 1984

22 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Write Deleted Data

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 00
MT MF 0 0 1 0 0 1
X X X X X HO US1 USO
C
H
R
N
EOT
GPL
OTL

Result Phase: The following bytes are issued by the controller in

the result phase:

STO
STl
ST2
C
H
R
N

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 23
Read a Track

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
a MF SK a a a 1 a
x x x x X HO US1 usa
c
H
R
N
EaT
GPL
OTL

Result Phase: The following bytes are issued by the controller in

the result phase:

STO
STl
ST2
C
H
R
N

August 31, 1984

24 Personal Computer AT Fixed Disk and Diskette Drive Adapter
ReadID

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
a MF a a 1 a 1 a
x x x x X HO US1 usa
Result Phase: The following bytes are issued by the processor in
the command phase:

STO
STl
ST2
C
H
R
N

Format a Track

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
a MF a a 1 1 a a
x x x x X HO US1 usa
N
SC
GPL
0

August 31, 1984 .

Personal Computer AT Fixed Disk and Diskette Drive Adapter 2S
Result Phase: The following bytes are issued by the controller in
the result phase:

STO
STl
ST2
C
H
R
N

Scan Equal

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
MT MF SK 1 0 0 0 1
X X X X X HO US1 usa
c
H
R
N
EOT
GPL
STP

Result Phase: The following bytes are issued by the controller in

the result phase:

STO
STl
ST2
C
H
R
N

August 31, 1984

26 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Scan Low or Equal

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
MT MF SK 1 1 0 0 1
X X X X X HO US1 usa
c
H
R
N
EOT
GPL
STP

Result Phase: The following bytes are issued by the controller in

the result phase:

STO
STl
ST2
C
H
R
N

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 27
Scan High or Equal

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 00
MT MF SK 1 1 1 a 1
x X x x X HO US1 usa
c
H
R
N
EDT
GPL
STP

Result Phase: The following bytes are issued by the controller in

the result phase:

STO
STl
ST2
C
H
R
N

Recalibrate

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 00
a a a a 0111
X X X X X a US1 usa

Result Phase: This command has no result phase.

August 31, 1984

28 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Sense Interrupt Status

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 00
o 000 100 0

Result Phase: The following bytes are issued by the controller in

the result phase:

STO
peN

Specify

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 00
o 0 0 0 0 0 1 1
( SRT ) ( HUT
( HLT ) ( NO

Result Phase: This command has no result phase.

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 29
Sense Driver Status

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
a a a a a a 1 a
x x x x X HO US1 usa
Result Phase: The following bytes are issued by the controller in
the result phase:

sn

Seek

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 DO
a a a a 1 1 1 1
x x x X X HO US1 usa
NCN

Result Phase: This command has no result phase.

August 31, 1984

30 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Invalid

Command Phase: The following bytes are issued by the

processor in the command phase:

07 06 05 04 03 02 01 00
Invalid Codes
X X X X X HO US1 USO

Result Phase: The following byte is issued by the controller in

the result phase:

STO

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 31
Command Status Registers
The following is information about the command status registers
STO through ST3.

Command Status Register 0 (STO)

The following are bit definitions for command status register o.

Bit 7-Bit 6 Interrupt Code (IC)

00 Normal Termination of Command

(NT)-The command was completed and
properly executed.

01 Abrupt Termination of Command

(AT)-The execution of the command was
started but not successfully completed.

10 Invalid Command Issue (IC)-The issued

command was never started.

11 Abnormal termination because, during the

execution of a command, the ready signal
I I

from the diskette drive changed state.

Bit 5 Seek End (SE)-Set to 1 when the controller

completes the Seek command.

Bit 4 Equipment Check (EC)-Set if a fault signal

I I

is received from the diskette drive, or if the

Itrack-O signal fails to occur after 77 step pulses
I

(Recalibrate Command).

Bit 3 Not Ready (NR)-This flag is set when the

diskette drive is in the not-ready state and a Read
or Write command is issued. It is also set if a
Read or Write command is issued to side 1 of a
single-sided diskette drive.

Bit 2 Head Address (HD)-Indicates the state of the

head at interrupt.

August 31, 1984

32 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Bit I-Bit 0 Unit select 0 and 1 (US 0 and 1 )-Indicate a
drive's unit number at interrupt. The following
figure shows the binary values to select each
drive:

Bit 1 Bit 0 Drive

Selected
0 0 A
0 1 B
1 0 Unused
1 1 Unused
Unit Selection

Command Status Register 1 (STl)

The following are bit definitions for command status register 1.

Bit 7 End of Cylinder (EC)-Set when the controller

tries to gain access to a sector beyond the final
sector of a cylinder.

Bit 6 Not Used-Always O.

Bit 5 Data Error (DE)-Set when the controller

detects a CRC error in either the ID field or the
data field.

Bit 4 Overrun (OR)-Set if the controller is not

serviced by the main system within a certain time
limit during data transfers.

Bit 3 Not Used-This bit is always set to O.

Bit 2 No Data (ND)-Set if the controller cannot find

the sector specified in the ID register during the
execution of a Read Data, Write Deleted Data, or
Scan Command. This flag is also set if the
controller cannot read the ID field without an
error during the execution of a Read ID

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 33
 command or if the starting sector cannot be
found during the execution of a Read Cylinder
command.

Bit 1 Not Writable (NW)-Set if the controller detects

a I write-protect I signal from the diskette drive
during execution of a Write Data, Write Deleted
Data, or Format Cylinder command.

Bit 0 Missing Address Mark (MA)-Set if the

controller cannot detect the ID address mark. At
the same time, the MD of status register 2 is set.

Command Status Register 2 (ST2)

Bit 7 Not Used-Always o.

Bit 6 Control Mark (CM)-This flag is set if the
controller encounters a sector that has a deleted
data-address mark during execution of a Read
Data or Scan command.

Bit 5 Data Error in Data Field (DD)-Set if the

controller detects an error in the data.

Bit 4 Wrong Cylinder (WC)-This flag is related to

ND (no data) and when the contents of C on the
medium are different from that stored in the ID
register, this flag is set.

Bit 3 Scan Equal Hit (SH)-Set if the contiguous

sector data equals the processor data during the
execution of a Scan command.

Bit 2 Scan Not Satisfied (SN)-Set if the controller

cannot find a sector on the cylinder that meets
the condition during a Scan command.

Bit 1 Bad Cylinder (BC)-Related to ND; when the

contents of C on the medium are different from
that stored in the ID register, and the contents of
C is FF, this flag is set.

August 31, 1984

34 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Bit 0 Missing Address Mark in Data Field (MD)- Set
if the controller cannot find a data address mark
or a deleted data address mark when data is read
from the medium.

Command Status Register 3 (ST3)

The following are bit definitions for command status register 3.

Bit 7 Fault (FT)-Status of the fault signal from the

I I

diskette drive.

Bit 6 Write Protect (WP)-Status of the

Iwrite-protect signal from the diskette drive.
I

Bit 5 Ready (RY)-Status of the I ready signal from

I

the diskette drive.

Bit 4 Track 0 (TO)-Status of the I track 0 signal I

from the diskette drive.

Bit 3 Two Side (TS)-Status of the I two side signal I

from the diskette drive.

Bit 2 Head Address (HD)-Status of the side-select I I

signal from the diskette drive.

Bit 1 Unit Select 1 (US 1)-Status of the

Iunit-select-l signal from the diskette drive.
I

Bit 0 U nit Select 0 (US 0 )-Status of the I unit select

o signal from the diskette drive.
I

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 35
Interfaces

The system interface is through the I/O channel. The address,

DMA, and interrupt assignments are shown in the following
figures.

I/O Address
Primary Secondary Read Write
3F2 372 Digital Output Register
3F4 374 Main Status Register Main Status Register
3F5 375 Diskette Data Register Diskette Data Register
3F6 376 Fixed Disk Register
3F7 377 DiQital Input ReQister Diskette Control ReQister
Diskette Function

Note: DMA request is level 2 and interrupt request is level 6.

I/O Address
Primary Secondary Read Write
1FO 170 Data Register Data Register
1 F1 171 Error Register Write Precomp
1F2 172 Sector Count Sector Count
1F3 173 Sector Number Sector Number
1F4 174 Cylinder Low Cylinder Low
1F5 175 Cylinder High Cylinder High
1F6 176 Drive/Head Register Drive / Head Register
1F7 177 Status Register Command Register
Fixed Disk Function

Note: Interrupt request is level 14.

The following operations are supported by this adapter:

• 16 bit programmed I/O (PIO), data transfers to the fixed

disk. All other transfers are 8 bits wide.

• The I/O addresses, recognized by the adapter for either the

fixed disk.or the diskette function, are independently selected
by jumpers.

August 31, 1984

36 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Interface Lines
The interface to the fixed disk drive consists of the Control cable
and the Data cable. The following figures show signals and pin
assignments for these cables.

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 37
 1 2

··..
··..
··.
·.
34

- r---

Ground - Odd Numbers 1-33

_ - Reduced Write Current/- Head Select 3 2
-
--
_ - Head Select 2
_ - Write Gate
4
6
- Seek Complete
- Track 000
8..
10 .. -
-
- Write Fault
_ - Head Select 0 14
12.
-
Reserved 16
Fix ed Disk
Fixed Dis k
_ - Head Select 1 18 And Diskette
Drive
- -Index 20_
Ada pter

- Ready 22_
-
- - Step
- Drive Select 1
24

26
-= - Drive Select 2 28
- Reserved 30
Reserved 32
_ - Direction In 34
-
- '---

Note: Connection is through a 2-by-17 Berg connector. Pin

15 is reserved to polarize the connector.
August 31, 1984
38 Personal Computer AT Fixed Disk and Diskette Drive Adapter
 1 2

..

- -
+ MFM Write Data 13

- MFM Write Data 14

+ MFM Read Data 17
Fixe d Disk
Fixed Disk
- MFM Read Data 18 And Diskette
Drive
Ada pIer
Ground-Pins 2,4,6,11,12,15,16,19,20

All Other Pins Unused

- '----

Note: Connection is through a 2-by-1O Berg connector. Pin 8

is reserved to polarize the connector.

August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 39
The interface to the diskette drives is a single cable that carries
both data and control signals. The signals and pin assignments are
as follows.
1 2

···....
c:::::Jc:::::::::::J c=J C=:l

···...
c::.::J c:::::J;~c:::::::::::Jc::JCJ

C J== =
c:=::::J c:=::::J ==
c::::::J ~ c::::::J c::==:J c::=::J [=::J c::::J c::J
··..
c.::::::J c=J

CJ~c_~=Jc=J~c:::J
c:::::::::::J c::l [===:J c::::::::J C=::J c:::::J c::J c:::::J c::::J

c:::::J c:::::Jc::Jc:=::J D~ ·
33 34
.
- r---

Ground - Odd Numbers 1-33

--
Reduced Write 2
Reserved 4

Drive Select 3 6
- Index 8_
...

--- Drive Select 0

Drive Select 1
10
12
-
--
Drive Select 2 14

Diskette --- Motor On

Direction Select
16
18
Fixe d Disk
And Diskette
Drive
- Ada pter
---
Step 20

--.. Write Data 22

- Write Gate
Track 00
24
26 _
..
Write Protect 28_
..
Read Data 30
..
-- Side 1 Select

Diskette Change
32
34 _

- L..-

Note: Connection is through a 2-by-17 Berg connector. Pin 5

is reserved to polarize the connector.
August 31, 1984
40 Personal Computer AT Fixed Disk and Diskette Drive Adapter
 PUP IS {SNT 2,11 1)

PUP 51 {SHT 1.2.1.11

PUP11\SHT4.5,l}

"
2N'NO&

."
,.
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17.8Kn
L - t - - - t - - - ' = + - - - - - . - - - - V A R welK (SHT11

NOTES (UNLESS OTHERwt<;£ NOTED) :

~PINS '.1.'>.1.9.1I.ll.I'5.17,IQ,ZI.2l,2';.27,2CJ.1IIt4D11AREGROUNDONJI&J'>

&
.& ,J1 & Jlt GND PlNS:Z.'I.&.II,IZ,I'>.I&,IQANOZO

Fixed Disk and Diskette Drive Adapter (Sheet 1 of 9)

 (SHY 61

utS SDHOf'''''--------+------~'f-l:-»'-+'-,-___1-------,----,-----,----"'O'::++f--f--f--____i
(SHT2IB(R-
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(SHT7)WRC:P
(SHT5) AD
~~ ~2~~"--------+------~lrt~~I~-+-------~------~-+-+-+--~
(SHT5IAI 1"5 AI I
SIlIflf-'''''----------'
(SNT51A2
(SHTI) HRST-
(SHTil WR-
; M,~E'-_ ~,,~,,~------~-~-'~.~~"--~,lr~~'~I~,---------l---,-----,--~------+-+__-____i
1
cu 1'J 112
(SHT51 RO-
(IH12) B(S-
18 ~_l::H~~~"'~,,~.='='.~,--------~~LH:_~~~---------,----------+--____i
(IHT3IRAb
(SHYij(SO-
=:-=-
17
9JZ8 DRQH~""'- - - - - - , -
~ 21 :~t~~:;3:SHT21
L0,GND
(SHT2) (St-

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(SNTI)P\P)I!I "INT 011'J
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P2"5 !~ (SNT8) RllIITA 'J7 RDATA

."
CORRO(IHTB) (SHT1)WReP Zo;WCLK
Wo/oto; ~~ 'J8
ERROIt(SHTI)

WAUPL
(SHT1)IOI'IlZ (SNT5)

-M1?"

Fixed Disk and Diskette Drive Adapter (Sheet 2 of 9)

 (SHT 3) R DB-
~T3)WRB-l
==[:1 I 21
+~V

20 21t
RAO I):OE DE 1/07 17 SOBle; (SHT 5)
RAI 6 AI 1/06 16
SDB" (SHT 5)
RA2 7 A2 U~~ I/o~ I~

(SHTS)
lr
RD- ~
IblSA
UI9
~RDA-(SHTJ)
~RDB-(SHT3)
RA1
RA4
8 M 20161 IAl't III
I A4 1101 IJ
SDBI1 (SHT 5)
SDBI2 (SHTS)
SOB II (SHTS)
RA~ A~ 9
~
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(SHTS) WR- F-- WRA - (SHT 3) RAb 1 Ab 1101 10
f!'1--- WRB - SDBQ (SHTS)
=:!
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~
(SHT 3)
(~~~C2~ -----:S
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CI >!-
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pq
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=~:~rr
(SHT2) CHR- (SHTJ) WRA- (SHT 2)(SHT 5)
(SH T3 ) RDA -

Fixed Disk and Diskette Drive Adapter (Sheet 3 of 9)

 JI

(SHT 1) PUPI '5

(SHT 7) FORO SYNC
1~~ ,,'"-----; 2 WCCNTRl-

+.v (SHT 6) FDSEl-1----'-'-<j).!L--ifI »'-'----;14 051-

3S
I RDY
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ISNT 61 FRST- I RST ,.------,12 D52-

(SHT 5) FOA(K -
U20
(5HT 5) FTDtC
16 ~~CK
LSIIf 10 MOT EN 1-
JI U'O
veo 24 veo EN (SKT 1)
DRG Ilf DRQ (SHT 7) 16 MQTEN2-
(5HT 1) FFODATA RDATA INT 18 FINT (SHT 5)
GNO 8,
22 RCLK
WE"~---1----------~)o~-------+--------;24
HO 27
WRTEN-
1487 12 HSI
(SHI Ii) Foes -
b DBD
ISHT 5) FDACK-
SOBI 7 OBI
SIP n 20 STEP-
SDB2 : 082 SEEK ~Q
1.,-;-"-1 10 DBl

1""
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SDBIf II OBit SEEK (5HT 4)
I I ~====~~------------~--~--------------------t-~~~-----j18 DIR-
L soss IZ DBr; OIR 18

150n 150n
_
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lSI4
5086
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wO!\
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PSI
10
12
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1 WR
INDEX.-
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If cs
&. GNO
U22
LSIIf (SHT 5)·SAOS ' ClK
AO
1 , 2 (SHT 7) FREP IQ
WRf PROl- 2. 21 WCLK
(SHT 7) FWCLK
U22 n lOX
TRK 0- 2'
, , lS11f
lit WP/TS

'---"q>''-_____--'''-'-1'3 FLT/TKO
U59 20
LSIIf

f----4---------9'-<1,,~·--DC HG ISHT 6)
U22
LSIIt

WDA (SHT 7)
FWE (SHT 7)
L.'::::======= PS
PSOI (SHT
(5HT 7)7)

Fixed Disk and Diskette Drive Adapter (Sheet 4 of 9)

 "'0=
>
., =
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ill
0
ill
~

=w
!.:-'
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0
....
IC
ALE - (SHT 5)
pup 68 (SHT I)
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FAST I/O 16-

a
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(SHT 3)
(SHT 3)
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el8

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5DI~

.,= S===~'~~'=~I2~~~~====~
WC (SHT 3) A4 6 CIS 5DI2
..... A£N ~~~
LDDOR- (SHI6) (SHT 3) SDBII ,,' "4
~: s~o
SOli
~ All .. U60 LOFCR - (SHT 6.7) (SHT 1) SDBID ,,4 SOlO
HDCS- (SHT 5)
'"
A2b~===:=;i;~3~
LDFDR- (SHT 6) (SHT 1)

>
2 IG Wc (SHT 3) 5DO.

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5008
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14 2G ,/C (SHT 5) I0R8-
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~====="t1~~~
SALt A27 ENDIR- (SHT 6)
SA9 A22 £NHDSTAT - (SHT 6) 'WD;(FER- (<;-(7)
~ SA7 A24
IoIAUPL (SHT 2,6)

Irr=;========~Jj
~' FDCS- (SHT 4)
(SHT 2) WAUP
~ (SHT2jSBRG
Q.

~ II LS24'; 9
:~ :~&;~S:~ ~
5OB7
(SHT 1) H07
!il' E (SHT 1) H06 12 8~U4S ~ 8 5086
5007
5006
5A2 A29
~ I~ 8"3
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.&;. Fixed Disk and Diskette Drive Adapter (Sheet 5 of 9)

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Fixed Disk and Diskette Drive Adapter (Sheet 6 of 9)

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August 31, 1984

Personal Computer AT Fixed Disk and Diskette Drive Adapter 47
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Fixed Disk and Diskette Drive Adapter (Sheet 8 of 9)

 +12V (SHT8]

(SHT 8) VREG 2 --+---+-+-'-1

ROb
--------l
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"
L<
4.7MH
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--FDCLK (SHT4)
I~ U48 veo (SHT 1)

CD DECOUPLE veo USING .luF CAP FROM PIN 16 TO PIN 9. CONNECT

PIN 9 TO CLOSEST DIGITAL GROLNO. CONNECT PIN 8 TO ANALOG GND "C"

Fixed Disk and Diskette Drive Adapter (Sheet 9 of 9)

Notes:

August 31, 1984

50 Personal Computer AT Fixed Disk and Diskette Drive Adapter
--
-
---
-
-
-----
--
- --
--- ---
---
---
Personal Computer
,- Hardware Reference
Library

IBM Personal Computer

20MB Fixed Disk
Drive Adapter

6139790 March 17, 1986

Notes:
Contents

Description ..................................... 1
Fixed Disk Controller .......................... 1
Programming Considerations ....................... 3
Types of Drives ............................... 3
Status Register ............................... 4
Sense Bytes .................................. 4
Data Register ................................ 7
Programming Summary ........................ 14
Interface ...................................... 15
Connectors ............... ;.................... 17
Logic Diagrams ................................. 19
BIOS Listing ................................... 23

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Index-l

March 17, 1986 v

Notes:

vi March 17, 1986

Description

The 20MB Fixed Disk Drive Adapter attaches to one or two fixed
disk drive units through an internal, daisy-chained, flat cable
(datal control cable).

The adapter is buffered on the 110 bus and uses the system
board's direct memory access (DMA) for fixed-disk-drive data
transfers. When the adapter is enabled, an interrupt request
occurs on the IRQ-5 line to the 8259A Interrupt Controller. The
8259A then causes an interrupt hex OD.

The Fixed Disk Drive Adapter provides automatic 11-bit burst

error detection and correction in the form of 32-bit error
checking and correction (ECC).

The device level control for the Fixed Disk Adapter is contained
on a ROM module on the adapter. A listing of this device level
control can be found in "BIOS Listing" of this section.

Warning: The last cylinder on the fixed disk drive is reserved for
diagnostic use. The diagnostic write test will destroy any data on
this cylinder.

Fixed Disk Controller

The disk controller has three registers that may be accessed by the
system unit's microprocessor: a status register, a data register, and
a read-option-jumpers register. The 8-bit status register contains
the status information of the disk controller, and can be accessed
at any time. This register is read-only and is used to help the
transfer of data between the system unit's microprocessor and the
disk controller. The 8-bit data register (actually consisting of
several registers in a stack with only one register presented to the
data bus) stores data, commands, and parameters, and provides
the disk controller's status information. Data bytes are read from,
or written to the data register in order to program or obtain the
results after a particular command. The controller-select pulse is
generated by writing to port address hex 322.

March 17, 1986 20MB Fixed Disk Drive Adapter 1

The following is a block diagram of the IBM 20MB Fixed Disk
Drive Adapter.

Control Serial izerl

Deserializer

J2
liD
)
SERDES
ECC Interface
Edge liD
Interface J3
Connector

Data Bus

8-Bit
DB7-DBO

-- Sector Buffer

Processor

220MB Fixed Disk Drive Adapter March 17,1986

Programming Considerations

Types of Drives
The fixed disk drive adapter will accommodate any two of four
different types of drives. The figure below shows the
configuration of the different type drives.

Start of Landing
Type Cylinders Heads Write Pre-Camp Zone
1 306 4 a 306
2 615 4 300 615
13 306 8 128 336
16 612 4 a 663

Fixed Disk Types

The figure below shows the switch settings for the above
mentioned drive types. Switches 1 and 2 set the parameters of
Drive 0, and switches 3 and 4 set Drive 1.

Drive a Drive 1
Switch Switch
1 2 3 4
Type 1 On On On On
Type 2 Off On Off On
Type 13 Off Off on Off
Type 16 On Off On Off

March 17, 1986 20MB Fixed Disk Drive Adapter 3

Status Register
At the end of all commands from the system board, the disk
controller sends a completion status byte to the system board.
This byte informs the system unit's microprocessor if an error
occurred during the execution of the command. The following
shows the format of this byte.

I Bit I : I : I : I : I : I : I : I : I

Bit 5 This bit shows the logical unit number

of the drive.

Bit 1 When set, this bit shows an error has

occurred during command execution.

Bits 7, 6, 4, 3, 2, 0 These bits are set to zero.

If the interrupts are enabled, the controller sends an interrupt

when it is ready to transfer the status byte. Busy from the disk
controller is unasserted when the byte is transferred to complete
the command.

Sense Bytes
If the status register receives an error (bit 1 set), the disk
controller requests four bytes of sense data. The format for the
four bytes is as follows:
Bits 7 6 5 4 3 2 1 0
Byte 0 Address I I
0 Error Type Error Code

Byte 1
Va 1 i d
0 0 d
I
Head Number
Byte 2 Cy 1 i nder High Sector Number
Byte 3 Cylinder Low
Remarks: d = drive

420MB Fixed Disk Drive Adapter March 17, 1986

Disk Controller Error Tables
The following disk controller error tables list the error types and
error codes found in byte O.

The address-valid bit (bit 7) is only set when the previous

command required a disk address. Bit 6 is set to 0 (spare).

Error Error Code

Type
Bits 5 4 3 2 I 0 Description
0 0 0 0 0 0 The controller did not detect any error
during the execution of the previous
operation.
0 0 0 0 0 I The controller did not detect an index signal
from the drive.
0 0 0 0 I 0 The controller did not get a seek-complete
signal from the drive after a seek operation
(for all non-buffered step seeks).
0 0 0 0 I I The controller detected a write fault from
the drive during the last operation.
0 0 0 I 0 0 After the contro 11 er selected the drive, the
drive did not respond with a ready signal.
0 0 0 I 0 I Not Used.

0 0 0 1 I 0 After stepping the maximum number of cylinders,

the contro 11 er did not receive the track 00
signal from the drive.
0 0 0 I I I Not Used.

0 0 I 0 0 0 The drive is st ill seeking. This status is

reported by the test Drive Ready command for
an overlap seek condition when the drive had
not completed the seek. No time-out is measured
by the contro 11 er for the seek to complete.

March 17, 1986 20MB Fixed Disk Drive Adapter 5

 Error Error Code
Type
Bits 5 4 3 2 1 0 Description
0 1 0 0 0 0 ID Read Error: The controller detected an
ECC error in the target ID field on the disk.
0 1 0 0 0 1 Data Error: The controller detected an
uncorrectable ECC error in the target sector
during a read operation.
0 1 0 0 1 0 Address Mark: The controller did not detect
the target address mark (AM) on the disk.
0 1 0 0 1 1 Not Used.

0 1 0 1 0 0 Sector Not Found: The contro ller found the

correct cyl inder and head, but not the
target sector.
0 1 0 1 0 1 Seek Error: The cyl inder or head address
(either or both) did not compare with the
expected target address as a result
of a seek.
0 1 0 1 1 0 Not Used.

0 1 0 1 1 I Not Used.

0 1 1 0 0 0 Correctable Data Error: The controller

detected a correctable ECC error in the
target fie ld.
0 1 I 0 0 1 Bad Track: The controller detected a bad
track flag during the last operation. No
retries are attempted on this error.

Error Error Code

Type
Bits 5 4 3 2 I 0 Description
1 o0 0 0 0 1nva lid Command: The controller had
received an i nva lid command from the
system unit.
I o 0 0 0 1 Illega I Disk Address: The controller detected
an address that is beyond the
maximum range.

6 20MB Fixed Disk Drive Adapter March 17,1986

 Error Error Code
Type
Bits 5 4 3 2 1 0 Description
1 1 0 0 0 0 RAM Error: the controller detected a data
error during the RAM sector-buffer
diagnostic test.
1 1 0 0 0 1 Program Memory Checksum Error: During
this internal diagnostic test, the contro ller
detected a program-memory checksum error.
1 1 0 0 1 0 ECC Polynomial Error: During the
contro ller' s i nterna 1 diagnostic tests, the
hardware ECC generator fa i led its test.

Data Register
The system unit's microprocessor specifies the operation by
sending the 6-byte device control block (DCB) to the controller.
The figure below shows the format of the DCB, and defines the
bytes that make up the DeB.

Bits 7 6 5 4 3 2 1 0

Byte 5 Control Field

Byte 4 Interleave or Block Count
Byte 3 Cy 1 i nder Low
Byte 2 Cy 1 i nder High I Sector Number
Byte 1 0 0 d Head Number
Byte 0 Command Opcode
Class

Byte 5 Bits 7 through 0 contain the control field.

Byte 4 Bits 7 through 0 specify the interleave or block

count.

Byte 3 Bits 7 through 0 are the eight least-significant bits

of the cylinder number.

March 17, 1986 20MB Fixed Disk Drive Adapter 7

Byte 2 Bits 7 and 6 are the two most significant bits of the
cylinder number. Bits 0 through 5 define the sector
number.

Byte 1 Bit 5 identifies the drive number. Bits 4 through 0

contain the disk head number to be selected. Bits 6
and 7 are not used.

Byte 0 Bits 7, 6, and 5 identify the class of the command.

Bits 4 through 0 contain the Opcode (see command
byte on page 10

Control Byte
Byte 5 is the control field of the DeB and allows the user to
select options for several types of disk drives. The format of this
byte is as follows:

I s;t I : I : I : I : I : I : I : I: I

Bit 7 Disables the four retries by the controller on all

disk-access commands. Set this bit only during the
evaluation of the performance of a disk drive.

Bit 6 If set to 0 during read commands, a reread is

attempted when an Eee error occurs. If no error
occurs during reread, the command will finish
without an error status. If this bit is set to 1, no
reread is attempted.

Bits 5,4,3 Set to O.

820MB Fixed Disk Drive Adapter March 17, 1986

Bits 2, 1,0 These bits define the type of drive and select the
step option. See the following figure.

Bits 2, 1, 0
0 0 0 This drive is not specified and defaults
to 3 mill i seconds per step.
0 0 1 N/A
0 1 0 N/A
0 1 1 N/A
1 0 0 200 microseconds per step.
1 0 1 70 microseconds per step (specified by BIOS).
1 1 0 3 mi 11 iseconds per step.
1 1 1 3 mi 11 iseconds per step.

March 17,1986 20MB Fixed Disk Drive Adapter 9

Command Byte

Command Data Control Block Remarks

Test Drive Bit 76543210 d = drive (0 or 1)

Ready Byte 0 000 0 0 0 0 0 x = don't care
(Class 0, Byte 1 o0 d x x x x x Bytes 2, 3, 4,
Opcode 00) 5, = don't care.

Recalibrate Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1)

(Class 0, Byte 0 o0 0 0 0 0 0 1 x = don't care
Opcode 00)
Byte 1 o0 d x x x x x r = retries
Byte 5 rOO 0 0 s s s s = Step Option
Bytes 2, 3, 4, = don't care
ch = cyl inder high
Reserved
(Class 0, This Opcode is not used.
Opcode 02)
Request Sense Bit 7 6 5 4 3 2 1 0 d=drive(Oorl)
Status Byte 0 o0 0 0 0 0 1 1 x = don't care
(Class 0, ~----~------+---------~
Opcode 03) Byte 1 o0 d x x x x x Bytes 2, 3, 4,
5, = don't care.
Format Drive Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1)
(Class 0, Byte 0 o0 000 1 0 0 r = retries
Opcode 04) ~-----+----~--------~
Byte 1 o0 d Head No. s = Step Option
Byte 2 ch 10 0 0 0 0 0 ch = cylinder high
Byte 3 Cylinder Low
Byte 4 o0 0 Interleave Interleave 1 to 16
Byte 5 rOO 0 0 s S 5 for 512-byte sectors.

Ready Verify Bit 76543210 d = drive (0 or 1)

(Class 0, Byte 0 o0 0 0 0 101 r = retries
Opcode 05)
Byte 1 o0 d Head No. s = Step Option
Byte 2 ch ISector No. a = retry option on
data ECC
Byte 3 Cy I i nder Low
Byte 4 Block Count ch = cylinder high
Byte 5 r a 000 s s s for 512-byte sectors.

1020MB Fixed Disk Drive Adapter March 17, 1986

 Command Data Control Block Remarks

Format Track Bit 7 6 5 4 3 2 1 0 d ~

dr i ve (0 or II
(Class 0, Byte 0 0 o0 o0 1 10 r ~
retries
Opcode 06)
Byte 1 0 o d Head No. s ~
step option
Byte 2 ch 10 o 0 0 0 0 ch ~ cylinder high
Byte 3 Cylinder Low
Byte 4 o 0 01 Interleave Interleave 1 to 16
Byte 5 r 0 0 0 os s s for 512-byte sectors.

Format Bad Bit 7 654 3 2 1 0 d ~

dr ive (0 or 1 )
Track
(Class 0, Byte 0 0 0 0 o0 1 1 1 x ~
don't care
Opcode 07)
Byte 1 0 0 d Head No. s ~
Step Option
Byte 2 ch 10 o 000 0 ch ~ cylinder high
Byte 3 Cylinder Low
Byte 4 o 0 01 Interleave Interleave 1 to 16
Byte 5 r 0 0 0 o s s s for 512-byte sectors.
Read
(Class 0, Bit 7 6 5 4 3 2 1 0 d ~
dr i ve (0 or II
Opcode 08)
Byte 0 0 0 0 0 1 0 0 0 r ~
retries
Byte 1 0 0 d Head No. a ~
retry option on
data ECC error
Byte 2 ch Isector No.
Byte 3 Cyl inder Low s ~ step option
Byte 5 r a 000 s s s ch ~ cyl inder high
Reserved
(Class 0, This Opcode is not used.
Opcode 09)
Write Bit 7 6 5' 4 3 2 1 0 d ~
dr ive (0 or II
(Class 0,
Opcode OA) Byte 0 0 0 0 0 1 0 1 0 r ~
retries
Byte 1 0 0 d Head No. s ~
step option
Byte 2 chlsector No. ch ~ cylinder high
Byte 3 Cy 1 i nder Low
Byte 4 Block Count
Byte 5 rOO 0 0 s s s

March 17, 1986 20MB Fixed Disk Drive Adapter 11

 Command Data Control Block Remarks

Seek Bit 7 654 3 2 1 0 d = drive (0 or 1)

(Class 0, Byte 0 0 0 o 0 1 0 1 1 r = retries
Opcode OB)
Byte 1 0 0 d Head No. s = Step Option
Byte 2 ch 10 000 0 0 x = don't care
Byte 3 Cy I i nder Low
Byte 4 x x x x x x x x
Byte 5 rOO 0 0 s s s

In i t i a Ii ze Bit 7 6 5 4 3 2 1 0 Bytes 1, 2, 3, 4, 5, =
Drive
Character- Byte 0 0 000 1 1 0 0 don't care.
istics*
(Class 0,
Opcode OC)
Read ECC Bit 76543 2 1 0 Bytes 1, 2, 3, 4, 5, =
Burst Length
(Class 0, Byte 0 o 0 0 0 1 1 0 1 don't care.
Opcode 00)
Read Data Bit 7 6 5 4 3 2 1 0 Bytes 1, 2, 3, 4, 5, =
from Sector
Buffer Byte 0 o0 0 0 1 1 1 0 don't care.
(Class 0,
Opcode OE)
Write Data to Bit 7 6 5 4 3 2 1 0 Bytes 1, 2, 3, 4, 5, =
Sector Buffer
(Class 0, Byte 0 o 000 1 1 1 1 don't care.
Opcode OF)

RAM Bit 7 654 3 2 1 0 Bytes 1, 2, 3, 4, 5, =

Diagnostic
(Class 7, Byte 0 1 1 1 o 0 a a a don't care.
Opcode 00)

Reserved This Opcode is not used.

(Class 7,
Opcode 01)
Reserved This Opcode is not used.
(Class 7,
Opcode 02)
*Initial ize Drive Characteristics: The DBC must be fol lowed by eight
additional bytes.
Maximum number of cylinders (2 bytes)
Maximum number of heads (1 byte)
Start reduced write current cyl inder (2 bytes)
Start write precompensation cylinder (2 bytes)
Maximum ECC data burst length (1 byte)

1220MB Fixed Disk Drive Adapter March 17, 1986

 Command Data Control Block Remarks

Dr i ve Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1)
Diagnostic
(Class 7. Byte 0 1 1 1 0 0 0 1 1 r = retries
Opcode 03)
Byte 1 0 0 d x x x x x s = step option
Byte 2 x x x x x x x x x = don't care
Byte 3 x x x x x x x x
Byte 4 x x x x x x x x
Byte 5 r 0 0 o0 s s s

Controller Bit 7 6 5 4 3 2 1 0 Bytes 1. 2. 3. 4. 5. =

Internal
Diagnostics Byte 0 1 1 1 o0 1 0 0 don't care.
(Class 7.
Opcode 04)

Read Long * Bit 7 6 5 4 3 2 1 0 d = dr i ve (0 or 1)

Track
(Class 7. Byte 0 1 1 1 o0 1 0 1 r = retries
Opcode 05)
Byte 1 o0 d Head No. s = step option
Byte 2 ch I Sector No. ch = cyl inder high
Byte 3 Cy 1 i nder Low
Byte 4 Block Count
Byte 5 rOO 0 0 s s s

Write Long **
(Class 7. Bit 7 6 543 2 1 0 d = drive (0 or 1)
Opcode 06)
Byte 0 1 1 1 o0 1 1 0 s = step option
Byte 1 0 0 d Head No. s = step option
Byte 2 ch Isector No. ch = cy 1 i nder high
Byte 3 Cyl inder Low s = step option
Byte 4 Block Count
Byte 5 rOO 0 0 s s s

* Returns 512 bytes plus 4 bytes of ECC data per sector.

** Requires 512 bytes plus 4 bytes of ECC data per sector.

March 17, 1986 20MB Fixed Disk Drive Adapter 13

Programming Summary
The two least-significant bits of the address bus are sent to the
system board's I/O port decoder, which has two sections. One
section is enabled by the I/O read signal (-lOR) and the other by
the I/O write signal (-lOW). The result is a total of four
read/ write ports assigned to the disk controller board.

The address enable signal (AEN) is asserted by the system board

when DMA is controlling data transfer. When AEN is active, the
I/ 0 port decoder is disabled.

The following figure is a table of the read/write ports.

R!W Port Address Function

Read 320 Read data (from controller to system unit)
Wr i te 320 Write data (from system unit to controller)
Read 321 Read controller hardware status.
Wr i te 321 Controller reset.
Read 322 Read option jumpers
Write 322 Generate controller-select-pulse
Read 323 Not used.
Write 323 Write pattern to DMA and interrupt
mask register.

1420MB Fixed Disk Drive Adapter March 17,1986

Interface
The following lines are used by the disk controller:

AO-AI9 Positive true 20-bit address. The least-significant 10

bits contain the I/O address within the range of hex
320 to hex 323 when an I/O read or write is executed
by the system unit. The full 20 bits are decoded to
address the read-only memory (ROM) between the
addresses of hex C8000 and hex C9FFF.

DO-D7 Positive 8-bit data bus over which data and status
information is passed between the system board and
the controller.

-lOR This signal is active when the system board reads

status or data from the controller under either
programmed I/O or DMA control.

-lOW This signal is active when the system board sends a

command or data to the controller under either
programmed I/O or DMA control.

AEN This signal is active when the DMA in the system

board is generating the I/O Read (-lOR) or I/O
Write (-lOW) signals and has control of the address
and data buses.

RESET This signal forces the disk controller to its initial

power-up condition.

IRQ 5 This signal is active by the controller when enabled to

interrupt the system board on the return ending status
byte from the controller.

DRQ 3 This signal is activated by the controller when data is

available for transfer to or from the controller under
DMA control. This signal remains active until the
system board's DMA channel activates the
DMA-acknowledge signal (-DACK 3) in response.

March 17,1986 20MB Fixed Disk Drive Adapter 15

-DACK 3 This signal is active when negative, and is generated
by the system board DMA channel in response to a
DMA request (DRQ 3).

1620MB Fixed Disk Drive Adapter March 17, 1986

Connectors

The 20MB Fixed Disk Drive Adapter connector and interface

specifications follow.

Land
At Standard TTL Levels Number
Ground-Odd Numbers 1-33
-Reserved 2, 16, 30, 32
-Head Select 2 4
-Write Gate 6
-Seek Complete 8
-Track 000 10
-Wr i te Fau It 12
-Head Select 0 14
Disk -Head Select 1 18 Disk
Drive Adapter
J1 -Index 20 J1

-Ready 22
-Step 24
-D rive Select 1 26
-Drive Select 2 28
-Drive Select 3 30
-Drive Select 4 32
-D i rect ion In 34

March 17,1986 20MB Fixed Disk Drive Adapter 17

 -Drive Selected I

Reserved 3,5,7,9
Key 5
+MFM Wr i te Data 13
-MFM Wr i te Data 14
Fixe d +MFM Read Data 17 Fixed
Disk Disk
Driv e -MFM Read Data 18 Adapt er
J2 0 r J3 J2 or J3
Ground Pins 2,4,6,8,10,11,12,15,
16,19,20
All Other Pins Unused

1820MB Fixed Disk Drive Adapter March 17,1986

ISH.3A)
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A.
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ISH.S)
ISH.S)
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06--
ISH.S) 07

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20MB Fixed Disk Drive Adapter (Sheet 1 of 4)

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20M B Fixed Disk Drive Adapter (Sheet 2 of 4)

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20M B Fixed Disk Drive Adapter (Sheet 4 of 4)

BIOS Listing

The BIOS Listing for the IBM 20MB Fixed Disk Drive Adapter
follows.

March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 23

 [BM Personal Computer MACRO Assembler VerSion 2.00 I-I
0lSK2 ---- 10/28/85 FIXED DISK BIOS ! 0-28-85

I PAGE 118,121
2 TITLE DISK2 ---- 10/28/85 FIXED DISK BIOS
3
4 ;-- INT 13H -----------------------------
5
6 FIXED DISK I/O INTERFACE
7
8 TH I S I NTERF ACE PROV I DES ACCESS TO F I XED 0 I SKS
9 THROUGH THE IBM F I XED 0 I SK CONTROllER.
10
II ; -- ------- ------------- - - ------------- ------------- ------ - -----
12
13 ; -- ------- - - ------------ - - -------- - ---- -- -- -------- ------- - - -- ---
14 ; THE 81DS ROUT I NES ARE MEANT TO 8E ACCESSED THROUGH
15 ; SOFTWARE INTERRUPTS ONLY. ANY ADDRESSES PRESENT IN
16 THE LISTINGS ARE INCLUDED ONLY FOR COMPLETENESS,
17 NOT FOR REFERENCE. APPL I CAT IONS WH I CH REFERENCE
18 ABSOLUTE ADDRESSES WITH I N THE CODE SEGMENT
19 ; V lOLA TE THE STRUCTURE AND DES I GN OF B [OS.
20 ; -- --
-------- ---- -- - - ---------- ---- - - --------- -------
21
22 INPUT (AH " HEX VALUE)
23
24 (AH)= OOH RESET DISK (DL = 80H,8!HI / DISKETTE
25 (AHi" OIH READ THE STATUS OF THE LAST DISK OPERATION INTO (AU
26 NOTE: DL < 80H - DISKETTE
27 DL > SOH - 0 I SK
28 (AH)= 02H REAO THE DESIRED SECTORS INTO MEMORY
29 (AHI" 03H WRITE THE DESIRED SECTORS FROM MEMORY
30 (AH)" 04H VER I FY THE DES I RED SECTORS
31 (AH)" 05H FORMAT THE OES I RED TRACK
32 (AHI = 06H FORMAT THE DESIRED TRACK AND SET BAD SECTOR FLAGS
33 (AH)= 07H FORMAT THE DRIVE STARTING AT THE DESIRED TRACK
34 (AH)" 08H RETURN THE CURRENT DR [VE PARAMETERS
35
(AHI= 09H [N[TlALIZE DRIVE PAIR CHARACTERISTICS
"
37
38 (AHi" OAH
INTERRUPT 41H POINTS TO DATA BLOCK
READ LONG
39 (AHJ" OBH WR I TE LONG
40 NOTE: READ AND WRITE lONG ENCOMPASS
41 512 BYTES + 4 BYTES OF ECC
42 (AH) " OCH SEEK
43 (AH) " ODH AL TERN ATE DISK RESET (SEE DL I
44 (AH) " OEH READ SECTOR BUFFER
45 (AH) " OFH WR I TE SECTOR BUFFER,
46 (RECOMMENDED PRACT I CE BEFORE FORMATT [NG)
47 (AH) IOH TEST OR I VE READY
48 (AH) IIH RECAL I BRA TE
49 (AH) I2H CONTROLLER RAM 0 [AGNOST I C
50 (AH) I3H DRIVE DIAGNOSTIC
51 (AH) 14H CONTROLLER INTERNAL 0 I AGNOST [C
52
53 REGISTERS USED FOR FIXED DISK OPERATIONS
54
55 (DLI DR[VE NUMBER (80H-87H FOR DISK, VALUE CHECKED)
56 (DHI HEAD NUMBER (0-70 ALLOWED, NOT VALUE CHECKED I
57 (CHI CYLINDER NUMBER (0-10230, NOT VALUE CHECKED) (SEE CU
58 (CLI SECTOR NUMBER ( 1-170, NOT VALUE CHECKED)
59
60 NOTE: HIGH 2 BI TS OF CYL [NDER NUMBER ARE PLACED
61 IN THE HIGH 2 BITS OF THE CL REGISTER
62 (10 BITS TOTAl)
63 (AU NUMBER OF SECTORS (MAXIMUM POSSIBLE RANGE 1-80H,
64 FOR READ/WRITE LONG 1-79H)
65 ( I NTERLEA VE VALI,IE FOR FORMAT I - I 60 I
66 (ES:BXI ADDRESS OF BUFFER FOR READS AND WR [TES,
67 (NOT REQU I RED FOR VER I FY I
68
69 OUTPUT
70 AH " STATUS OF CURRENT OPERATION
71 STATUS BITS ARE DEFINEO IN THE EGlUATES BELOW
72 CY = 0 SUCCESSFUL OPERATION (AH" OOH ON RETURN)
73 CY " I FA[LED OPERATION (AH HAS ERROR REASON)
74
75 NOTE: ERROR IIH [NDICATES THAT THE DATA READ HAD A RECOVERABLE
76 ERROR WHICH WAS CORRECTED BY THE ECC ALGORITHM. THE DATA
77 IS PROBABLY GOOD, HOWEVER THE BIOS ROUT I NE I NO [CA TES AN
78 ERROR TO ALLOW THE CON TROLL [NG PROGRAM A CHANCE TO DEC I DE
79 FOR ITSELF, THE ERROR MAY NOT RECUR IF THE DATA IS
80 REWRITTEN. (ALI CONTAINS THE BURST LENGTH.
81
82 I F DR I VE PARAMETERS WERE REQUESTED,
83
84 DL " NUMBER OF CONSECUTIVE ACKNOWLEDGING DRIVES
85 ATTACHED (0-21 ICONTROlLER CARD ZERO TALLY ONLYI
86 DH " MAX I MUM USEABLE VALUE FOR HEAD NUMBER
87 CH " MAXIMUM USEABLE VALUE FOR CYLINDER NUMBER
88 CL " MAX I MUM USEABLE VALUE FOR SECTOR NUMBER
89 AND CYL I NDER NUMBER H [GH BITS
90
91 IF AN ERROR OCCURS ON READ DRIVE PARAMETERS,
92
93 AH " ERROR CODE (INIT FAILI
94 AL :: CX '" OX " 0 -
95
96 REGISTERS WILL BE PRESERVED EXCEPT WHEN THEY ARE USED TO RETURN
97 INFORMATION.
98
99 NOTE: IF AN ERROR [S REPORTED BY THE D[SK CODE, THE APPROPRIATE
100 ACT I ON I S TO RESET THE 0 [SK, THEN RETRY THE OPERAT I ON.
101
102

24 20MB Fixed Disk Drive Adapter BIOS March 17, 1986

 [BM Person .. 1 Computer MACRO Assemb I er Vers I on 2.00 1-2
DISK2 ---- 10/28/85 F[XED DISK BIOS 10-28-B5

103 PAGE
104 ; ----- - - -- ------- - ------- ------- - - ---- - -- - -------- - ------
105 ; ERROR RETURN STATUS (AH):: PH WHEN CY= I
106
107
108 DOFF SENSE FAIL EQU OFFH SENSE OPERAT I ON FA [LED
109 :: OOCC WR I TE-F AUL T EQU OCCH WRITE FAULT ON SELECTED DRIVE
110 OOBB UNDEF-ERR EQU OBSH UNDEF I NED ERROR OCCURRED
I I 1 0080 TIME OUT EQU 080H A TT ACHMENT FA I LED TO RESPOND
112 :: 0040 BAD SEEK EQU 040H SEEK OPERATION FAILED
1 13 0020 BAD-CNTLR EQU 020H CONTROLLER HAS FA [LEO
114 0011 DA TA CORRECTED EQU o 11H ECC CORRECTED DATA ERROR
115 00 I 0 BAD ECC EQU O\OH BAD ECC ON 0 [SK READ
I 16 OOOB BAD-TRACK EQU OOBH BAD TRACK FLAG DETECTED
I 17 0009 DMA -BOUNDARY EQU 009H ATTEMPT TO OMA ACROSS 64K BOUNDARY
I 18 0007 [NIT FAIL EQU 007H DRIVE PARAMETER ACTIVITY FAILED
I 19 0005 BAD RESET EQU 005H RESET FAILED
120 0004 RECaRD NOT FNo EQU 004H REQUESTED SECTOR NOT FOUND
121 0002 BAD ADDR MARK EQU 002H ADDRESS MARK NOT FOUND
122 0001 BAo::::CMo - EQU 00 I H BAD COMMAND PASSED TO 0 I SK I {a
123
124
125 I NTERRUPT AND STATUS AREAS
126
127
;- - - --------- - - - --
- - - --
128 0000 ABSO SEGMENT AT OH
129 0034 ORG 000H·4 F [XED 0 I SK I NTERRUPT VECTOR
130 0034 Ho [SK I NT LABEL DWORO
131 004C ORG o 13H·4 DISK I NTERRUPT VECTOR
132 004C ORG_ VECTOR LABEL DWORD
133 0064 ORG o 19H·4 BOOTSTRAP INTERRUPT VECTOR
134 0064 BOOT _ VEC LABEL oWORD
135 0078 ORG 01 EH·4 DISKETTE PARAMETERS
136 0078 DISKETTE_PARM LABEL DWORD
137 0 I 00 ORG 040H-4 NEW 0 I SKETTE [NTERRUPT VECTOR
138 0100 01 SK_VECTOR LABEL oWORD
139 0104 ORG 041H·4 F I XED 0 [SK PARAMETER VECTOR
140 0 I 04 HF _ TBL_ VEC LABEL DWORD
141 7COO ORG 7COOH BOOTSTRAP LOADER VECTOR
142 7COO BOOT LOCN LABEL FAR
143 7COO ABSO- ENOS
144
145 0000 DATA SEGMENT AT 40H
146
147
006C
006C 1777
ORG
OW , T I MER LOW WORD
148
149
0072
0072 RESET_FLAG
ORG
OW ,
072H
1234H [F KEYBOARD RESET UNDERWAY
150 0074 ORG 074H
151 0074 DISK STATUS DB FIXED DISK STATUS BYTE
152 0075 HF NOM DB COUNT OF FIXED DISK DRIVES
153 0076 CONTROL BYTE DB CONTROL BYTE DR I VE OPT IONS
154 0077 PORT OFF DB PORT OFFSET
155 0078 oATA- ENOS
156
157 0000 CODE SEGMENT
158
159 ; - --- ---- --- - - - - - -------- - - - - -----
160 HARDWARE SPECIFIC VALUES
161 1
162 CONTROLLER I {O PORT
163 > WHEN READ FROM:
164 HF PORT+O READ DATA (FROM CONTROLLER TO CPUI
165 HF-PORT + 1 READ CONTROLLER HARDWARE STATUS
166 - (CONTROLLER TO CPU I
167 HF _PORT+2 READ CONFIGURATION SWITCHES
168 HF PORT + 3 - NOT USED
169 > WHEN WR I TTEN TO:
170 HF PORT+ 0 WR I TE OAT A I FROM CPU TO CONTROLLER I
171 HF-PORT+ I CONTROLLER RESET
172 HF-PORT+2 GENERATE CONTROLLER SELECT PULSE
173 HF-PORT+3 WR I TE PATTERN TO DMA AND INTERRUPT
174 MASK REG! STER
175
176
177
178 CMD BLOCK EQU 8YTE PTR [BP1-B CMO BLOCK HEAD
179 0320 HF PORT EQU 0320H 01 SK PORT
180 0020 INTAOO EQU 020H 8259 PORT
181 0021 INTAO I EQU 021 H 8259 PORT
182 0020 EOI EQU 020H END OF I NTERRUPT COMMAND
183 0008 R I 8USY EQU 00001000B DISK PORT 1 BUSY BIT
184 0004 R I-BUS EQU OOOOOIOOB COMMAND/DATA BIT
185 0002 Rl-IOMOoE EQU 000000 1 DB MODE BIT
1860001 R1::::REQ EQU 0000000 I B REQUEST B[T
187
188 0047 DMA READ EOU 01000111B 1047HI
189 004B DMA-WR [TE EQU 01001011B CHANNEL 3 (04BH)
190 0000 OMA EQU OOOH OMA ADDRESS
191 0082 DMA_H I GH EOU OB2H PORT FOR HIGH 4 BITS OF OMA
192
193 0000 TST ROY CMD EQU 000000008 CNTLR READY { OOHI
194 0001 RECAL CMD EQU 0000000IB RECAL (OIHI
195 0003 SENSE-CMD EQU 00000011 B SENSE 103H)
196 0004 FMToRV CMD EOU 00000 I OOB DRIVE (04Hl
197 0005 CHK TRK CMD EOU 000001018 T CHK ( 05H)
198 0006 FMTTRK CMD EQU 000001108 TRACK 106H)
199 0007 FMTBAO-CMD EQU OOOOOIIIB BAD 107H)
200 0008 READ CMD EQU 0000 I 0008 READ 108H)
20 I OOOA WRITE CMo EQU 000010108 WRITE (OAHI
202 OOOB SEEK CMD EQU OOOOIOIIB SEEK (08H)
203 OOOC I N I T-ORV CMD EOU OOOOIIOOB INIT (OCHI
204 0000 RD ECC CMO EOU 000011018 8URST (DOH)
205 OOOE RD-BUFF CMD EQU 00001110B BUFFR (OEHI
206 OOOF WR-BUFF-CMO EQU 000011118 BUFFR (OFH)
207 OOEO RAM O[AG CMD EOU 1 I 100000B RAM IEOHI
208 00E3 CHK-DRV CMD EQU 11100011 B ORV IE3HI
209 00E4 CNTLR DIAG CMO EQU I I 1001 OOB CNTLR {E4HI
210 00E5 RD LONG CMD EOU I I 100101 B RLONG {E5HI
211 00E6 WR:::LONG:::CMD EQU I I 10011 OB WLONG (E6HI
212
213 OOOB MAX FILE EQU
214 0002 S_MAX FILE EQU

March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 25

 IBM Personal Computer MACRO Assembler Version 2.00 1-3
0lSK2 ---- 10/Z8/85 FIXED O[SK 8[OS 10-28-85

215 PAGE
216 ASSUME CS:CODE,OS:ABSO
217 0000 ORG OH
218 0000 55 DB 055H I GENER [C B I as HEADER
219 0001 AA DB OAAH
220 OOOZ 08 DB 080 ; 4K MODULE
221
222 ; --- - -------- - - - ----- - - - - --- - - - ----- ---- ----- -- - ---
223 ; FIXED DISK I/O SETUP
224 ;
225 ; ESTABl [SH TRANSFER VECTORS FOR THE F I XED 0 I SK
225 PERFORM POWER ON 0 I AGNOSTI CS
227 ; SHOULD AN ERROR OCCUR A "170 I" MESSAGE IS D I SPLA YEO
228 ;
229 ;
230
231 0003 01 SK SETUP FROC FAR
232 0003 E8 35 - JMP SHORT L3
233 0005 35 39 58 37 32 39 DB '59X7291 IC) COPYRIGHT IBM CORP.' COPYR I GHT NOT I CE
234 31 20 Z8 43 29 20
235 43 4F 50 59 52 49
236 47 48 54 20 49 42
237 40 20 20 43 4F 52
238 50 2E
239 0025 2C 31 39 38 32 ZO DB ',1982,1985,'
240 2C 31 39 38 35 2E
241 0031 20 31 30 ZF 32 38 DB , 10/28/85' RELEASE MARKER
242 2F 38 35
243 D03A L3 :
244 003A 28 CO SUB AX ,AX ADDRESS LOW RAM
245 003C 8E 08 MOV OS,AX
240 003E FA CLI
247 003F A I 004C R MOV AX, WORD PTR ORG VECTOR LOAD 0 I SKETTE [P
248 0042 A3 0100 R MOV WORD PTR 01 SK VECTOR,AX STORE AT I NT 40H
249 0045 A I 004E R MOV AX,WORD PTR ORG VECTOR+2 LOAD D [SKETTE CS
250 0048 A3 0102 R MOV WORD PTR DISK VECTOR+2,AX STORE AT INT 40H
251 0048 C7 06 004C R 0251 R MOV WORD PTR ORG VECTOR, OFFSET 0 I SK 10 F I XED 0 [SK HANDLER
252 0051 8C DE 004E R MDV WORD PTR ORG-VECTOR+2,CS AT [NT 13H
253 0055 B8 0755 R MDV AX, OFFSET Hi) I NT F I XED 0 I SK INTERRUPT
254 0058 A3 0034 R MOV WORD PTR HOI SI< INT ,AX HANDLER AT I NT ODH
255 0058 8C OE 0036 R MOV WORD FTR HDISK-INT+2,CS
256 005F C7 06 0064 R 0192 R MOV WORD FTR SOOT VEC,OFFSET BOOT STRAP BOOTSTRAP ROUT[NE AT
257 0065 8C DE 0066 R MOV WORD PTR BOOT-VEC+2,CS - [NT 19H
258 0069 C7 06 0104 R 03FF R MOV WORD PTR HF TeL VEC, OFFSET FO TBL PARAMETER TABLE AT
259 006F 8C DE 0106 R MDV WORD PTR HF=:TBL=:VEC+2,CS - [NT 41H
260 0073 F8 STI
261
252 ASSUME
263 0074 88 ---- R MOV AX,oATA ESTA8L I SH SEGMENT
254 0077 8E 08 MOV OS,AX
265 0079 C6 06 0074 R 00 MOV DISK STATUS,O RESET THE STATUS INDICATOR
266 007E C6 06 0075 R 00 MOV HF NUM,O ZERO COUNT OF DR I YES
267 0083 C6 06 0077 R 00 MOV PORT OFF, 0 ZERO CARD OFFSET
268 0088 B9 0025 MOV CX,25H RETRY COUNT
269 008B L4:
270 0088 E8 0177 R CALL HO RESET 1 RESET CONTROLLER
271 008E 73 05 JNC L 7- -
272 0090 E2 F9 LOOP L4 TRY RESET AGA I N
273 0092 E9 0154 R JMP ERROR_EX
274 0095 L 7:
275 0095 89 000 I MOV CX,l
216 0098 8A 0080 MOV DX,80H
277 0098 B8 1200 MOV AX,I200H CONTROLLER D I AGNOST I CS
278 009E CO 13 INT I3H CHECK THE I NTERNAL RAM
279 OOAO 73 03 JNC P7 BUFFERS
280 00A2 E9 0154 R JMP ERROR_EX
281 00A5 P7 :
282 00A5 88 1400 MOV AX,I400H CONTROLLER D I AGNOST I CS
283 00A8 CO 13 INT I3H I NTERNAL CHECKSUM AND
284 OOAA 73 03 JNC P9 ECC CIRCUITRY TEST.
285 OOAC E9 0154 R JMP ERROR_EX
285 OOAF P9:
287 OOAF C7 06 006C R 0000 MOV TIMER LOW,O ZERO TIMER
288 00B5 81 3E 0072 R 1234 CMP RESET-FLAG, 1234H KEYBOARD RESET
289 00B8 75 06 JNE P8 -
290 OOBO C7 06 006C R 019A MDV TIMER_LOW,410D SKIP WAIT ON RESET
291 00C3 P8:
292 00C3 FA CLI D I SABLE INTERRUPTS
293 00C4 E4 21 IN AL,INTAOI TIMER
294 ODC6 24 FE ANO AL,OFEH ENABLE T [MER
295 00C8 E6 21 OUT INTA01,AL START TIMER
296 OOCA FB ST I I NTERRUPTS ON
297 00C8 P4:
298 00C8 E8 0177 R· CALL HD RESET 1 RESET CONTROLLER
299 OOCE 72 07 JC p(5 -
300 0000 88 1000 MOV AX,IOOOH TEST TO SEE IF THE DRIVE
301 00D3 CD 13 INT I3H [S READY
302 0005 73 OA JNC P2
303 0007 PIO:
304 0007 AI 006C R MDV AX, Tl MER LOW
305 OODA 30 OIBE CMP AX,446D - 25 SECONDS
306 0000 72 EC JB P4
307 OOOF E8 73 JMP SHORT ERROR_EX
308 OOEI P2:
309 OOEI 88 1100 MDV AX,IIOOH RECAL 18RATE THE OR I YE 0
310 00E4 CO 13 INT I3H
311 OOE6 72 6C JC ERROR_EX
312
313 00E8 88 0900 MOV AX,0900H SET DR I VE PARAMETERS
314 O{)EB CD 13 INT I3H FOR DRIVE 0
315 ODED 72 65 JC ERROR_EX
316
317 OOEF 88 C800 MOV AX ,OC800H DNA TO BUFFER
318 00F2 8E CO MDV ES,AX SET SEGMENT
319 00F4 2B 08 SUB BX,ex
320 00F6 88 OFOO MDV AX,OFOOH WR [TE SECTOR BUFFER
321 00F9 CD 13 INT I3H
322 00,F8 72 57 JC ERROR_EX
323
324 OOFO FE 06 0075 R INC HF NUM DR I VE ZERO RESPONDED
325 0101 BA 0213 MDV OX-;213H EXPANS [ON BOX
326 0104 80 00 MOV Al,O
327 0106 EE OUT OX,AL TURN BOX OFF
328 Ol078A0321 MDV DX,321H TEST IF CONTROLLER

26 20MB Fixed Disk Drive Adapter BIOS March 17,1986

 IBM Persona I Computer MACRO Assemb I er ion 2.00 1-'
DISK2 ---- 10/28/85 FIXED DISK BIOS 10-28-85

329 OIOA EC IN AL,DX IS IN THE SYSTEM UNIT

330 OIOB 24 OF AND AL, OFH
331 0100 3C OF CMP AL, OFH
332 OIOF 74 06 JE BOX ON
333 0111 C7 06 006C R 0lA4 MOV TlMER_LOW,420D CONTROLLER I SIN SYSTEM UN I T
334 0I I7
335 0117 BA 0213 MOV DX,213H EXPANS [ON BOX
336011ABOFF MOV AL, QFFH
337 Olle EE OUT aX,AL TURN BOX ON
338 OlIO 69 0001 MOV CX, I ATTEMPT NEXT DR I VES
339 0120 BA 0081 MOV DX,08IH
340 0123 P3:
341 0123 2B CO SUB AX,AX RESET THE CONTROLLER
342 0125 CD 13 INT 13H
343 0127 72 42 JC POD DONE
344 0129 B8 I 100 MOV AX,OIIOOH RECALlBRATE THE DRIVE I
345 012C CD 13 tNT 13H
346 012E 73 OA JNC P5
347 0130 AI 006C R MOV AX,TIMER LOW
348 013330 OIBE CMP AX,446D - 25 SECONDS
349 0136 72 EB JB P3
350 0138 EB 31 JMP SHORT POD_DONE
351 013A P5:
352 013A B8 0900 MOV AX,0900H INITIALIZE DRIVE CHARACTERISTICS
353 0130 CO 13 INT 13H FOR DRIVE I
354 013F 72 2A JC POD DONE
355 0141 FE 06 0075 R INC HF NUM I: TALLY ANOTHER DRIVE
356 0145 81 FA 0081 CMP DX-;-180H + S_MAX_FtLE
357 0149 73 20 JAE POD DONE
358 014B 42 INC OX -
359 014C EB 05 JMP P3
360
361 014E 31 37 30 31 ODOA FI1 DB '1701' ,ODH,OAH POST MESSAGE
362 0006 FI7L EOU I-FI7
363
36' POD ERROR
365
366 0154 ERROR EX:
367 0154 BO OOOF - MOV BP,OFH POD ERROR FLAG
368 0157 2B F6 SUB S I, S I
369 0159 B9 0006 MDV CX,FI7L MESSAGE CHARACTER COUNT
370 015C B7 00 MDV BH,O PAGE ZERO
371 015E OUT_CH:
372 015E 2E: 8A 84 014E R MDV AL,CS:FI7(SI] GET BYTE
373 0163 B4 OE MDV AH,I40 VIDEO OUT
374 0165 CD 10 INT IOH D I SPLA Y CHARACTER
375 0167 46 INC SI NEXT CHAR
376 0168 E2 F4 LOOP OUT_CH DO MORE
377 016A F9 STC
378 016B POD DONE:
379 016B FA - CLl NO INTERRUPTS
380 016C E4 21 IN AL,INTAOI READ THE I NTERRUPT MASK
381 0 I 6E OC 0I OR AL,O IH o I SABLE THE T I MER
382 0170 E6 21 OUT INTAOI,AL
383 0172 FB STI ENABLE INTERRUPTS
384 0173 E8 0232 R CALL OSBL o I SABLE THE CARD MASKS
385 0176 CB RET
386
387
388
389
0177
0 I 77 51
0178 52
HD RESET I
- PUSH
PUSH
C,
PROC

OX
NEAR
SAVE REG I STER

390 0179 B9 0100 MDV CX, 0 I OOH RETRY COUNT

391 017C L6:
392 017C E8 0760 R CALL PORT 0
393 017F 42 INC OX- ADDRESS PORT I
394 0180 EE OUT DX,AL RESET CARD
395 0181 EB 00 JMP 1+2 I/O DELAY AT LEAST +5us
396 0183 EB 00 JMP 1+2 ALLOW T I ME TO CLEAR THE
397 0185 EB 00 JMP $+2 HARDWARE STATUS REGISTER
398 0187 EC IN AL,DX READ THE HARDWARE STATUS
399 018824 3F AND AL,OOIIIIIIB MASK OFF UPPER 2 BITS AND CLEAR CY
400 OIBA 74 03 JZ R3 EXIT IF REGISTER IS CLEARED WITH CY=O
401 DI8C E2 EE LOOP L6 TRY AGAIN
402 018E F9 STC SET ERROR CONDITION CY=I
403 018F R3:
404 018F 5A POP OX RESTORE REG 1 STER
405 0190 59 POP CX
406 0191 C3 RET
407 0192 HD RESET I ENDP
408 0 I 92 DISK_SETUP ENDP

March 17,1986 20MB Fixed Disk Drive Adapter BIOS 27

 IBM PersonOiI Computer MACRO Assembler Version 2.00 I-S
DISK2 ---- 10/28/85 FIXED DISK 810S 10-28-85

409 PAGE
410 ; --- I NT 19 H --- ------- --- ------- ------ -- ----------- ---------
411
412 INTERRUPT 19 800T STRAP LOADER
413
414 THE F I XED 0 I SK B I OS REPLACES THE INTERRUPT 19H BOOT
415 STRAP VECTOR WITH A PO I NTER TO TH I S BOOT ROUT I NE AND
416 RESETS THE DEFAULT DISK AND DISKETTE PARAMETER VECTORS
411
418 THE BOOT BLOCK TO BE READ IN WILL 8E ATTEMPTED FROM
419 CYL I NDER 0 SECTOR 1 OF THE DEV I CE.
420
421 THE BOOTSTRAP SEQUENCE IS:
422 ATTEMPT TO LOAD FROM THE DISKETTE INTO THE BOOT
423 LoCAT I ON (0000: 7COOH) WHERE CONTROL I S TRANSFERRED.
424 IF THE DISKETTE FAILS THE FIXED DISK IS TRIED FOR A
42S VALID BOOTSTRAP 8LOCK. A VALID 800T 8LoCK ON THE
426 F I XED 0 I SK CONS I STS OF THE 8YTES 055H OAAH AS THE
427 LAST TWO 8YTES OF THE 8LOCK.
428 IF THE A80VE FAILS CONTROL IS PASSED TO RESIDENT BASIC
429
430
431
432 0192 BOOT STRAP:
433 - ASSUME OS: ABSO, ES: ABSO
434 0192 2B CO SUB AX,AX
43S 0194 8E 08 NOV DS,AX EST A8L I SH SEGMENT
436 0196 B4 CO NOV AH,OCOH
437 0198 CD 15 IN7 ISH READ CONF I GURAT I ON PARAMETERS
438 IF XT OR PC, I NTERRUPTS ARE 0 I SABLEO
439 RESET PARAMETER VECTORS AT THIS POINT.
440
441 o 19A FA CLI
442 0198 CT 06 0104 R 03FF R MoV WORD PTR HF TBL VEC, OFFSET FD TBL
443 01AI 8C OE 0106 R MOV WORD PTR HF-TBL -VEC+2, CS -
444 0lA5 73 OA JNC HO - - ; JMP I F I NT 15 FUNCT I ON IMPLEMENTED
44S
446 0lA7 C7 06 0078 R 0227 R MOV WORD PTR 0 I SKETTE PARM, OFFSET 0 I SKETTE TBL
447 OIAD 8C OE 001A R MOV WORD PTR DISKETTE:::PARM+2,CS -
448 OIBI HO:
449 0181 FB STI
4S0
4S1 ATTEMPT BOOTSTRAP FROM 01 SKETTE
4S2
4S3 01 B2 2B 02 SUB OX,DX OR I VE ZERO
4S4
4SS ESTABLISH ES:BX POINTER
4S6
4S7 0lB4 8E C2 NOV ES ,OX ESTABLISH SEGMENT
4S8 0186 BB 7COO R NOV BX,OFFSET BooT_LOCN SET BX TO 1COOH
4S9
460 CLEAR BOOT_LOCN
461
462 0189 FC CLO DIRECT I ON FORWARD
463 o IBA 33 CO XOR AX, AX
464 018C 89 0100 NOV CX,256 CLEAR 256 WORDS
46S 018F 88 FB NOV DI,8X POINT TO BOOT LOCATION 8UFFER
466 OICI F3/ A8 REP STOSW ZERO THE BOOT LOCAT I ON BUFFER
467
468 0lC3 89 0004 NOV CX,4 SET RETRY COUNT
469 o IC6 HI: IPL SYSTEM
470 o IC6 51 PUSH CX SAVE RETRY COUNT
471 0lC7 2B CO SUB AX,AX RESET THE 0 I SKETTE
472 0lC9 CD 13 INT 13H FILE 10 CALL
473 OICB 72 08 JC H2 IF ERROR, TRY AGAIN
474
47S OICD B8 0201 NOV AX,020!H READ I N THE SINGLE SECTOR
476 0100 B9 000 I NOV CX,I SECTOR I, TRACK 0
477 0103 CO 13 INT 13H FILE 10 CALL •
478 0105 59 H2: POP CX RECOVER RETRY COUNT
479 0106 73 09 JNC H3 CARRY FLAG SET 8'1' UNSUCCESSFUL READ
480
481 0108 80 FC 80 CNP AH,80H IF TIME OUT, NO RETRY
482 OIOB 74 22 JZ H6 TRY FIXED DISK
483
484 0100 E2 E7 LOOP HI DO I T FOR RETRY TIMES
48S OIOF EB IE JNP SHORT H6 UNABLE TO I PL FROM THE 0 I SKETTE
486
487 OIEI 80 3E 7COO R 06 H3: CMP BYTE PTR BOOT_LOCN,06H CHECK FOR FIRST INSTRUCTION INVALID
488 0lE6 72 30 JB HIO IF 800T NOT VAllO, GO TO BASIC
489
490 INSURE DATA PATTERN FIRST 8 WORDS NOT ALL EQUAL
491
492 0lE8 8F 7COO R NOV 01 ,OFFSET BOOT LoCN ; CHECK DATA PATTERN
493 0lE8 89 0008 NOV CX,8 - ; CHECK THE NEXT 8 WORDS
494 OIEE AI 7COO R NOV AX,WORD PTR BOOT_LOCN ; LOAD THE FIRST WORD
49S
496 OIFI 83 C7 02 H4: AOO 01,2 ; PO I NT TO NEXT WORD
497 0lF4 38 05 CNP AX, (01 J ; CHECK DATA PATTERN FOR A FILL PATTERN
498 01F6 EI F9 LoOPZ H4
499 0lF8 74 28 JZ HIO ; BOOT NOT VALID, GO TO BASIC
SOO o IFA H5:
SOl OIFA EA 7COO ---- R JMP 800T _LOCN
S02
S03 ATTEMPT BOOTSTRAP FROM FIXED DISK
S04
SOS 01 FF H6:
S06 01 FF 28 CO SUB AX, AX RESET D (SKETTE
S07 0201 CD 13 INT 13H
S08 0203 89 0003 MOV CX,3 SET RETRY COUNT
S09 0206 8A 0080 NOV DX,ooaOH FIXED DISK ZERO
SIO 0209 H7 : IPL SYSTEM
SII 0209 51 PUSH SAVE RETRY COUNT
SI2 020A 2B CO SUB AX, AX RESET THE F I XED 0 I SK
SI3 020C CD 13 INT 13H FILE 10 CALL
SI4 020E 72 08 JC H8 IF ERROR, TRY AGAIN
SIS
SI6 ES AND BX ALREADY ESTABLISHED
SI1
SI8 0210 B8 0201 NOV AX, 020 1H READ I N THE SINGLE SECTOR
5>9 0213 89 0001 NOV ex, I SECTOR I, TRACK 0
S20 0216 CD 13 INT 13H FILE 10 CALL
S21 0218 59 H8: POP CX RECOVER RETRY COUNT
S22 0219 12 08 JC H9

28 20MB Fixed Disk Drive Adapter BIOS March 17,1986

 IBM Personal Comput.l!lr MACRO Assl!lmbll!lr Vl!lrslon 2.00 1-6
OlSK2 ---- 10/28/85 FIXED DISK BIOS 10-28-85

523 0218 AI 70FE R MOV AX, WORD PTR BOOT LOCN+510D

524 021 E 30 AA55 CMP AX, OAA5SH - ; TEST FOR GENER I C BOOT BLOCK
525 0221 74 01 .JZ H5 J GO TO 800T LOCATION
526 0223 H9:

.2.
521
.28
53.
0223 E2 E4

;-----
LOOP H1 ;

UNABLE TO IPL FROM THE DISKETTE OR FIXED DISK

DO IT FOR RETRY TIMES

531 0225
532 0225 CO 18 INT 18H RESIDENT BASIC
533
534 0227 01 SKETTE_ TBL I
.35
536 0227 CF DB 110011 I IB SRT=O, HD UNLOAD=OF - 1 ST SPEC BYTE
537 0228 02 DB 2 HD LOAD= I, MODE=DMA - 2ND SPEC BYTE
538 0229 25 DB 25H MOTOR TIMEOUT AFTER OPERATION
539 022A 02 DB 2 51 2 8YTES PER SECTOR
540 0228 08 DB 8 EOT (LAST SECTOR ON TRACK)
541 022C 2A DB 02AH GAP LENGTH
542 0220 FF DB OFFH DTL
543 022E 50 DB 050H GAP LENGTH FOR FORMAT
544 022F F6 DB OF6H FILL BYTE FOR FORMAT
545
546
0230
0231
19
04
DB 2. HEAD SETTLE T I ME (M I LL I SECONDS)
MOTOR START TIME (118 SECOND)
DB 4
.41
548 ;----- MAKE SURE THAT ALL HOUSEKEEPING IS DONE BEFORE EXIT
'4'
550 0232 D58L PROC NEAR
551 0232 2A CO SUB AL,AL ; RESET I NT IDMA MASK
552 0234 BA 0323 MDV DX,HF _PORT+3 LOAD FOR PORT ADDRESS :3
553 0231 FA eLi 01 SA8LE INTERRUPTS
554 0238 EE DUT DX,AL RESET I NT/DMA MASK CARD a
555 0239 83 C2 04 ADD DX,4
556 023C EE DUT DX,AL RESET INT/DMA MASK CARD 1
557 0230 83 C2 04 ADD DX,4
558 0240 EE DUT aX,AL RESET (NT/DMA MASK CARD 2
559 0241 83 C2 04 ADD OX,4
560 0244 EE DUT DX,AL J RESET INT /DMA MASK CARD :3
'61
562 0245 80 07 MDV AL,07H
563 0247 E6 OA DUT DMA+IO,AL SET DMA MODE TO 0 I SA8LE
564 0249 E4 21 IN AL,INTAOI
565 0248 OC 20 DR AL,020H
566 0240 E6 21 OUT INTAOI,AL oI SABLE I REQ 5
567 024F FB 511 ENABLE INTERRUPTS
568 0250 C3 RET
569 0251 OSBL ENDP
51 •
• 11
512
.13 FIXED DISK BIOS ENTRY POINT
.14
51. ; - --- -- - - -- - ---- - - - - - ------- -- - --------------------------
516
577 0251 DISK 10 PROC FAR
518 - ASSUME OS :DATA,ES:NOTHING
579 0251 80 FA 80 eMP DL,080H TEST FOR FIXED DISK DRIVE
580 0254 73 05 "AE HARD 01 SK YES, HANDLE HERE
581 0256 CO 40 INT 40H - DISKETTE HANDLER
582 0258
583 0258 CA 0002 RET J BACK TO CALLER
.84
585 0258 HARD DISK:
586 0258 FB - STI J ENABLE INTERRUPTS
587 025C OA E4 OR AH,AH
588 025E 75 09 "NZ A3
589 0260 CO 40 INT 40H RESET NEC WHEN AH=O
590 0262 2A E4 SUB AH,AH
591 0264 80 FA 81 e"p DL, (80H+S MAX FILE-I) DL IN LIMITS?
592 0267 77 EF "A RET_2 - -
593 0269 A3:
594 0269 80 FC 08 e"p AH,8 GET PARAMETERS I S A SPEC I AL CASE
595 026C 75 03 "NZ A2
596
597
026E
0271
E9 0380 R
A21 ""P GET_PARM_N

598 0271 55 PUSH BP SAVE THE BASE POINTER

599 0272 8B EC NOV 8P,SP LOAD THE CMD BLOCK PO INTER

6.,
600 0274 83 EC 08 SUB SP,8 ALLOCATE SPACE FOR THE COMMAND BLOCK
ON THE STACK.
602 0277 53 PUSH BX SAVE REGISTERS DURING OPERATION
603 0278 51 PUSH ex
604 0279 52 PUSH ox
605 027A IE PUSH DS
606 0278 06 PUSH ES
607 02IC 56 PUSH 51
608 0270 57 PUSH DI
609 027E 8E ---- R NOV 51 ,DATA
610 0281 8E DE NOV DS,SI J ESTABLISH DATA SEGMENT
6"
612 0283 E8 0200 R CALL DISK_IO_CONT PERFORM THE OPERATION
613
614 0286 SO PUSH AX
615 0287 E8 0232 R CALL DSBL BE SURE 0 I SABLES OCCURRED
616 028A 88 ---- R MOV AX,DATA
617 0280 8E 08 MOV DS,AX ESTA8L I SH SEGMENT
618 028F 58 POP AX RESTORE THE REGI STERS
619 0290 8A 26 0074 R MOV AH,DISK STATUS GET STATUS FROM OPERATION
620 0294 SF POP DI -
621 0295 5E POP 51
622 0296 07 POP ES
623 0297 IF POP OS
624 029B SA POP OX
625 0299 59 POP ex
626 029A 5B POP BX
621
628 0298 83 C4 08 ADD SP,8 ADJUST FOR THE COMMAND BLOCK.
629 029E 50 POP BP RESTORE 8ASE POINTER
630 029F BO FC 01 eMP AH, I SET THE CARRY FLAG TO INDICATE
631 02A2 FS eMe SUCCESS OR FAILURE
632 02A3 CA 0002 RET THROW AWAY SAVED FLAGS
633 02A6 DISK_IO ENDP

March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 29

 IBM Personal Computer MACRO Assembler Version 2.00 1-7
O[SK2 ---- 10/28/85 FIXED DISK 8[OS 10-28-85

.34 PAGE
635 02A6 MI LA8EL WORD FUNCT [ON TRANSFER TA8LE
636 02A6 032E R OW DISK RESET OOOH
637 02A8 0347 R OW RETURN STATUS 001 H
638 02AA 0350 R OW DISK READ 002H
639 02AC 0359 R OW DISK-WR[TE 003H
640 02AE 0362 R OW 01 SK-VERF 004H
641 0280 0369 R OW FMT TRK DOSH
642 0282 036F R OW FMT-BAD D06H
643 0284 0375 R OW FMT-DRV D07H
644 0286 0326 R OW 8AD-COMMAND OOSH
645 0288 043F R OW [NIT DRV 009H
646 028A 04F4 R OW RD LONG OOAH
647 028C 0501 R OW WR-LONG 008H
648 028E 0515 R OW D 15K SEEK DOCH
649 02CO 032E R OW DISK-RESET OODH
650 02C2 0518 R OW RD 8UFF OOEH
651 02C4 0527 R OW WR-8UFF OOFH
652 02C6 0533 R OW TST ROY OIOH
653 02C8 0539 R OW HOISK RECAL OIIH
654 02CA 053F R OW RAM OTAG QI2H
655 02CC 0545 R OW CHK-DRV o 13H
656 02CE 0548 R OW CNTLR DIAG 014H
657 '" 002A MIL EQU $-M1 -
.58
659 0200 01 SK 10 CONT PROC NEAR
660 0200 80 FC 01 - -CMP AH,OIH RETURN STATUS
661 0203 74 72 JE RETURN_STATUS
•• 2
CONVERT DR I VE NUM8ER TO 0 8ASED RANGE

...
663 0205 80 EA 80 5UB DL ,080H
664 0208 80 FA 08 e"p DL,MAX FILE LEGAL DR I VE TEST
665 0208 73 49 JAE 8AO_COMMAND

667 0200 C6 06 0074 R 00 "OV

•• 8
•• 9 SET UP COMMAND 8LOCK
.70
671 02E2 FE C9 DEC CL SECTORS 0-16 FOR CONTROLLER
672 02E4 C6 46 F8 00 "OV CMD 8LOCK+0, 0 SET TO ZERO THE OP CODE
673 02E8 88 4E FA "OV CMD-BLOCK+2,CL SECTOR AND HIGH 2 6 [TS CYL I NOER
674 02E8 88 6E F8 "OV CMD-8LOCK+3,CH CYL I NDER LOW
675 02EE 88 46 FC "OV CMD-BLOCK+4, AL [NTERLEAVE / 8LOCK COUNT
676 02FI AO 0076 R "OV AL, CONTROL BYTE CONTROL 8YTE (STEP OPT [ON)
677 02F4 88 46 FD "OV CMD_8LOCK+5,AL SET THE CONTROL F [ELD
.78
.79 CALCULATE THE PORT OFFSET
.80
681 02F7 8A EA "OV CH,DL SAVE DL
682 02F9 80 CA 0I OR DL,1
683 02FC FE CA DEC OL
684 02FE DO E2 5HL OL,I GENERATE OFFSET
685 0300 88 16 0077 R "OV PORT OFF ,Dl STORE OFFSET
686 0304 8A 05 "OV OL,eH RESTORE Dl
687 0306 80 E2 01 AND DL,I MAKE DR I VE 0 OR I
688 0309 81 05 "OV CL,5 SHI FT COUNT
689 0308 02 E2 5HL OL,Cl DRIVE NUMBER (0,1)
690 0300 OA 06 OR DL,DH HEAD NUMBER
691 030F 88 56 F9 "OV CMD_BLOCK+ I ,DL SET THE DR [VE AND HEAD
.92
693 0312 66 C8 "OV CX,AX CALCULATE JUMP ADDRESS
694 0314 8A CO "OV CL,CH GET I NTO LOW BYTE
695 031632 ED XOR CH,CH ZERO HIGH BYTE
696 031801 EI 5AL CX, I -2 FOR TA8lE LOOKUP
697 031A 88 FI "OV S I, CX PUT INTO S I FOR BRANCH
b98 031C 83 F9 2A e"p CX,MIL TEST WITHIN RANGE
699 031F 73 05 JNB 8AD COMMAND
700 0321 2E: FF A4 02A6 R J"P WORD PTR CS:[SI+OFFSET MIl ; GO DO THE COMMAND
70 I 0326 8AD COMMAND:
702 0326 C6 06 0074 R 01 - MOV DISK STATUS,8AD CMD SET 8AD COMMAND ERROR
703 0328 80 00 "OV AL,O- -
704 0320 C3 RET ; EXIT
705 032E D[SK_IO_CONT ENDP
70.
707 ; ---------- - ----------- - -- ----- ------ - -------
708 ; RESET THE DISK SYSTEM (AH '" OOOH) :
709
710
711 032E D[SK RESET PROC NEAR
712 032E E8 0760 R - CALL PORT 0 RESET PORT
713 0331 42 INC ox - PORT I ADDRESS
714 0332 EE OUT DX,AL RESET CARD
715
716
0333
0335
E8
E8
00
00
J"P
J"P
"2
'.2
I/O DELAY AT LEAST +5us
ALLOW T I ME TO CLEAR THE
717
718
0337
0339
E8
EC
00 J"P
IN
'.2
AL,DX
HARDWARE STATUS REG (STER
READ THE HARDWARE STATUS
719 033A 24 3F AND AL,OOIIIIIIB MASK OFF UPPER 2 BITS AND CLEAR CY
720 033C 74 06 JZ ORI EXIT IF REGISTER IS CLEARED WITH CY",O
721 033E C6 06 0074 R 05 "OV 01 SK_ST ATUS, 8AD _RESET SET THE ERROR COND I T I ON
722 0343 C3 RET EX[T
723 0344 DRI:
724 0344 E9 043F R J"P SET THE DRIVE PARAMETERS
725
72b 0347 DISK_RESET ENDP
727
728
729 DISK STATUS ROUTINE (AH '" OOIH)
730 ; -------- -------------- ----------------- -- - ------- - ------
731
732 0347 RETURN STATUS PROC NEAR
733 0347 AO 0074 R - MOV AL,DISK STATUS OBTA[N PREVIOUS STATUS
734 034A C6 06 0074 R 00 "OV 01 SK_STATUS, 0 RESET STATUS
735 034F C3 RET
736 0350 RETURN_STATUS ENDP
737
738 ; -- ---- ------------ - ---------
739 ; OISK READ ROUTINE (AH = 002H) :
740
741
742 0350 DISK READ PROC NEAR
743 0350 80 47 - MDV I MODE 8YTE FOR DMA READ
744 0352 C6 46 F8 OS "OV ~~D D~~5~;~~. READ CMD
745 0356 E9 055E R J"P DMA-OPN -
746 0359 DISK_READ ENDP
747

30 20MB Fixed Disk Drive Adapter BIOS March 17, 1986

 IBM Personal Computer MACRO Assembler VersIon 2.00 1-6
0lSK2 ---- 10/28/85 FIXED DISK BIOS 10-28-85

746 ; --- - - --- - - -- --- - - - - - - - - ---

749 ; DISK WRITE ROUT[NE IAH = 003H) :
750
751
752 0359 DISK WR[TE PROC NEAR
753 0359 80 48 - MOV AL,DMA WR I TE ; MODE BYTE FOR DMA WR I TE
754 035B C6 46 F8 OA MOV CMD 8LOCK+O,WRITE CMD
755 035F E9 055E R JMP DMA-OPN -
756 0362 DISK_WRITE ENOP
757
756 . - - ----- ---- - --- - - --------- - - --------- --
759 ; DISK VER[FY IAH = 004H)
760
761
762 0362 DISK VERF PROC NEAR
763 0362 C6 46 F6 as - MOV CMD 8LOCK+O,CHK TRK CMO
764 0366 E9 054F R JMP NOMA OPN --
765 0369 DISK_VERF ENDP-
766
767 ; --- - - --- - - - - -- - - -- -- ----- - --- - - - - --- - - - -- -- - - - - - -- - - - --
766 ; FORMATTING IAH = 005H 006H OOTHI :
769
770
771 0369 FMT TRK PROC NEAR ; FORMAT TRACK (AH = 005H I
772 0369 C6 46 F6 06 - MOV CMO 8LOCK+O,FMTTRK CMO
773 0360 EB OA JMP SHORT FMT _CONT -
774 D36F FMT _ TRK ENOP
775
776 D36F FMT 8AD PROC NEAR FORMAT BAD TRACK (AH = 006Hl
777 036F C6 46 F6 07 - MOV CMO 8LOCK+O,FMTBAD CMD
776 0373 E8 04 JMP SHORT FMT_CONT -
779 0375 FMT _8AD ENDP
760
761 0375 FMT ORV PROC NEAR FORMAT DR[VE IAH = 007H)
782 0375 C6 46 F6 04 - MOV CMD_BLOCK +0, FMTDRV _ CMD
763 0379 FMT _DR V ENDP
764
765 0379 FMT CONTI
766 0379 60 66 FA CO - AND CMD 8LOCK+2,IIOOOOOOB i ZERO OUT SECTOR FJELD
767 0370 E9 054F R JMP NDMA_OPN
786
769
790 GET PARAMETERS AH = 8) :
791
792
793 0380 GET PARM N LABEL NEAR
794 0380 GET-PARM- PROC FAR GET DR I VE PARAMETERS
795 0380 IE - PUSH DS SAVE REGI STERS
796 0381 06 PUSH ES
797 0382 53 PUSH 8X
796
799 ASSUME OS:ABSO
600 0383 2B CO 5U8 AX,AX ESTABLISH ADDRESSING
60 I 0385 8E 08 MOV OS, AX
602 0387 C4 IE 0104 R LES 8X,HF _TBL_VEC
603
604 ASSUME OSIDATA
605 0388 88 ---- R MOV AX,DATA
606 038E 8E 08 MOV OS,AX EST ABL I SH SEGMENT
607 0390 60 EA 60 SU8 DL,80H
606 0393 80 FA 06 CMP DL,MAX FILE TEST WITH I N RANGE
609 0396 73 57 JAE G4 -
610 0398 C6 06 0074 R 00 MOV DISK STATUS,O RESET THE STATUS [NDICATOR
61! 0390 8A EA MOV CH,Oe SAVE THE DRIVE
612 039F 60 CA 01 OR OL, I
613 03A2 FE CA DEC OL
614 03A4 DO E2 SHL DL,I GENERATE OFFSET
615 03A6 66 16 0077 R MOV PORT OFF tOl STORE OFFSET
616 03AA 6A D5 MOV DL,cR RESTORE OL
617 03AC 60 E2 01 AND OL, 0000000 I B DRIVE 0 OR DRIVE I
616 03AF 6A E2 MOV AH,Dl
619 03B I E6 0760 R CALL PORT 0
620 03B4 42 INC OX - PORT_2 ADDRESS
621 03B5 42 INC OX
622 03B6 EC IN AL,DX READ SW I TCH SEll [NGS
623 0387 6D FC 00 CMP AH,D DRIVE 0 OR 1
624 03BA 75 04 JNZ GO
625 03BC DO E6 SHR AL, I R [GHT JUST I FY THE SW ITCH BITS
626 038E DO E6 SHR AL,I
627 03CO GO:
626 03CO 24 03 AND AL,OOOOOOl18 ISOLATE THE TABLE BITS
629 03C2 81 04 MOV CL,4 T ABLE LENGTH IS 16 BYTES
630 03C4 02 EO SHL Al,Cl ADJUST
631 03C6 2A E4 SU8 AH,AH
632 03C8 03 08 ADO 8X,AX
633 03CA 26: 68 07 MOV AX,ES: (BX] MAX NUMBER OF CYLINDERS
634 03CO 2D 0002 SU8 AX ,2 ADJUST FOR O-N
635 AND RESERVE lAST TRACK
636 0300 8A E8 MOV CH,Al
637 0302 25 0300 AND AX,0300H HIGH TWO 8[TS OF CYLINDER
636 0305 DI E6 SHR AX,I
639 0301 DI E6 SHR AX,I
640 0309 DC I! OR AL,OIIH SECTORS
641 030B 8A C6 MOV Cl-,AL
642 0300 26: 6A 77 02 MOV DH,ES: [8X] [2] HEADS
643 03EI FE CE DEC DH O-N RANGE
644 03E3 6A 16 0015 R MOV DL,HF NUM DR I VE COUNT
645 03E7 28 CO SU8 AX, AX-
646 03E9
647 03E9 58 POP 8X RESTORE REGISTERS
646 03EA 07 POP ES
649 03E8 IF POP OS
65D 03EC CA 0002 RET 2 EXIT
651 03EF G4:
652 03EF C6 06 0014 R 07 MOV DISK STATUS, (N[T FA(L OPERATION FAILED
653 03F4 84 07 MOV AH,INIT FAIL -
654 03F6 2A CO SU8 AL,Al -
655 03F8 28 02 SUB OX,OX
656 03FA 28 C9 SU8 CX,CX
657 03FC F9 STC SET ERROR FLAG
656 03FO E8 EA JMP G5 EXIT
659 03FF ENOP

March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 31

 IBM P.rsonal Computer MACRO Assembler
DISK2 ---- 10/28/85 FIXED DISK BIOS
Version 2.00
10-28-85
1-'

..•••,
•• 0

•• 2
PAGE

I NIT I AL I ZE DR I VE CHARACTER I ST I CS

•••
•••
FIXED DISK PARAMETER TABLE

...•••
•••
•• 7

.70
THE TABLE IS COMPOSED OF A BLOCK DEFINED AS:

(I
(I
(I
WORD)
BYTE)
WORD)
-
-
-
MAXIMUM NUMBER OF CYLINDERS
MAXIMUM NUMBER OF HEADS
STARTING REDUCED WRITE CURRENT CYL
.71 (I WORD) - STARTING WRITE PRECOMPENSATION CYL

."
.72
.,.
.7.
II
II
BYTE}
BYTE)
-
-
MAXIMUM ECC DATA BURST LENGTH
CONTROL BYTE IDRIVE STEP OPTION)

.7..77 BIT
BIT
1 DISABLE DISK-ACCESS RETRIES
6 DISABLE ECC RETRIES

.7. BITS 5-3 ZERO

BITS 2-0 DRIVE OPTION

..,
.7'
•• 0

•• 2
•••
II
(1
(I
(I
(I
(I
BYTE)
BYTE)
BYTE)
WORD)
BYTEl
BYTE)
-
-
-
-
-
-
STANDARD TIME OUT VALUE (SEE BELOW)
TIME OUT VALUE FOR FORMAT DRIVE
T I ME OUT VALUE FOR CHECK OR I VE
LAND I NG ZONE
SECTORS/TRACK
RESERVED FOR FUTURE USE
•••
••• - TO DYNAMICALLY DEFINE A SET OF PARAMETERS
•••
•• 7
BUILD A TABLE OF VALUES AND PLACE THE
CORRESPONDING VECTOR INTO INTERRUPT 41 •

..•••••••••,
•• 0
NOTE: THE DEFAULT TABLE IS VECTORED
AN INTERRUPT 19H (BOOTSTRAP)
IN FOR

...••••••
•• 2 ON THE CARD SW ITCH SETT I NGS

ON:
DRP/E 0

I
DRIVE I

I
.'7 I -1- -2- I -3- -4-:
•••
•••
OFF I :
• 00

.0..0.
'01
'02
TRANSLATION TABLE

DRIVE 0
1/2
: DRIVE I
3/4
: TABLE ENTRY

'0'
'0. ON ON : ON ON

.0..,0
'07
'0.
ON OFF
OFF ON
OFF OFF
:
:
:
ON OFF
OFF ON
OFF OFF
:
:
:

..
.11
912
.,,.
913 03FF FD_TBL:

,----- DRIVE TABLE 0

91.
917 03FF 0132 OW 03060 MAX CYLINDERS
918 0401 04 DB 0.0 MAX HEADS
919 0402 0132 OW 03060 START REDUCED WRITE CURRENT CYL
920 0404 0000 OW 0 START WRITE PRECOMPENSATION CYL
921 0406 OB DB OBH MAX ECC BURST DATA LENGTH
922 0401 05 DB OOOOOlOIB CONTROL BYTE
923 0408 10 DB OIOH STANDARD TIME OUT
924 0409 CO DB OCOH T I ME OUT FOR FORMAT DR I VE
925 0401. 28 DB 028H TIME FOR CHECK DRIVE
926 040B 0132 OW 03060 LANDING ZONE

.2.'.0
921 0400 II DB 0170 SECTORS/TRACK
928 040E 00 DB 0 RESERVED
;----- OR I VE TABLE I
.31
932 040F 0264 OW 06120 MAX CYL I NDERS
933 0411 04 DB 0.0 MAX HEADS
934 0412 0264 OW 06120 START REDUCED WRITE CURRENT CYL
935 0414 0000 OW 0 START WRITE PRECOMPENSATION CYL
936 0416 OB DB OBH MAX ECC BURST DATA LENGTH
931 0411 05 DB 0000010lB CONTROL BYTE
938 0418 28 DB 028H STANDARD TIME OUT
939 0419 EO DB OEOH T I ME OUT FOR FORMAT DR I VE
940 041A 42 DB 042H T I ME FOR CHECK DR I VE
941 041B 0297 OW 06630 LAND I NG ZONE
942 0410 11 DB 0110 SECTORS/TRACK
943 041E 00 DB 0 RESERVED
•••
••• ;----- DRIVE TABLE 2
•••
947 041F 0267 OW 06150 MAX CYLI NOERS
948 0421 04 DB 0.0 MAX HEADS
949 0422 0267 OW 06150 START REDUCED WRITE CURRENT CYL
950 0424 01 2C OW 03000 START WRITE PRECOMPENSATION CYL
951 0426 OB DB OBH MAX ECC BURST DATA LENGTH
952 0427 05 DB OOOOOIOIB CONTROL BYTE
953 0428 28 DB 028H STANDARD TIME OUT
954 0429 EO DB OEOH TIME OUT FOR FORMAT DRIVE
955 042A 42 DB 042H TIME FOR CHECK DRIVE
956 042B 0267 OW 06150 LAND I NG ZONE
957 0420 It DB 0170 SECTORS/TRACK

..•••,
958 042E 00 DB 0 RESERVED

•• 0 ;----- DRIVE TABLE 3

962 042F 0132 OW 03060 MAX CYLINDERS

963 0431 08 DB 080 MAX HEADS
964 0432 0132 OW 03060 START REDUCED WR I TE CURRENT CYL
965 0434 0080 OW 01280 START WRITE PRECOMPENSATION CYL
966 0436 OB DB OBH MAX ECC BURST DATA LENGTH
961 0431 05 DB OOOOOIOIB CONTROL BYTE
968 0438 28 DB 028H STANDARD TIME OUT
969 0439 EO DB OEOH T I ME OUT FOR FORMAT DR I VE
910 0431. 42 DB 042H T I ME FOR CHECK DR I VE
911 04380150 OW 03360 LAND I NG ZONE
912 0430 II DB 0110 SECTORS I TRACK
913 043E 00 DB 0 RESERVED

32 20MB Fixed Disk Drive Adapter BIOS March 17, 1986

 IBM Persona! Computer MACRO Assembler Version 2.00 (-10
0lSK2 ---- 10/28/85 FIXED DISK 810S 10-28-85

97.
975 ; ----- - -- ------ ---- - - --------- -------- ----------- -----
976 ; INITIALIZE DRIVE (AH = 09H) :
977
978
979 043F PROC NEAR
980
981 DO OR I VE ZERO
982
983 043F C6 46 F8 OC "OV CMD BLOCK+O, INIT ORV CMD
984 0443 C6 46 F9 00 "OV CMD-BLDCK+I,O - - SET FOR DR I VE 0
985 0447 E8 0458 R CALL INIT DRV R SEND THE PARAMETERS
986 044A 72 08 JC INIT::::DRV::::OUT ERROR?
987
988 DO DRIVE ONE
989
990 044C C6 46 F8 OC "OV CMD 8LOCK+O,INIT DRV CMD
99 I 0450 C6 46 F9 20 "OV CMD-BLOCK+l,OOtOOOOOB SET TO DRIVE I
992 0454 E8 0458 R CALL INIT_DRV_R SEND THE PARAMETERS
993 0457 INIT DRV OUT;
994 0457 C3 - RET EXIT
995 0458 lNIT_ORV
996
997 0458 INIT DRV R PROC NEAR
998 0458 2A CO - SUB AL,AL
999 045A E8 057C R CALL COMMAND I SSUE THE COMMAND
10000450 73 01 JNC BI OX = PORT 0 AFTER CALL
1001 045F C3 RET
\ 002 0460 61 :
1003 0460 8C 09 "OV CX,DS SAVE SEGMENT
1004
1005 ASSUME DS:ABSO
1006 0462 28 CO SUB AX ,AX
1007 0464 8E 08 "OV DS,AX ESTA8L I SH SEGMENT
10080466 C4 IE 0104 R LES 8X ,HF TBL VEC LOAD THE TABLE VECTOR
1009 046A 8E 09 "OV DS,CX- - RESTORE SEGMENT
1010
101 I ASSUME DS:DATA
1012 . - - - - ------ - -- - - ---- - - - - ---- -----
1013 ; DETERMINE PARAMETER TABLE OFFSET
1014 US I NG CONTROLLER PORT TWO AND
1015 DRIVE NUMBER SPECIFIER (0-1)
1016
1017 046C 42 INC OX
1018 0460 42 INC ox ADDRESS PORT 2
1019 046E EC IN AL,DX READ THE SW ITCH SETT I NGS
1020 046F 8A 66 F9 "OV AH ,CMD_BLOCK+ I
1021 047280 E4 20 ANO AH,OOIOOOOOB DRIVE 0 OR I
1022 0475 75 04 JNZ B2
1023 0477 DO E8 SHR AL, I ADJUST
1024 0479 00 E8 SHR AL, I
1025 0478 B2:
1026 0478 24 03 ANO AL,Ol18 ISOLATE
1027 0470 81 04 "OV CL,4
1028 047F 02 EO SHL AL,CL ADJUST
10290481 2A E4 SUB AH,AH
1030 0483 03 08 AOO 8X ,AX
1031 04858409 "OV AH,OOOOl0018 SET MASK FOR DATA MODE CPU TO CARD
1032
1033 SEND DRIVE PARAMETERS MOST SIGNIFICANT BYTE FIRST
1034
10350487 SF 0001 "OV DI, I SEND MS8 OF MAX CYLINDER
1036 048A E8 04E9 R CALL INIT DRV S
1037 0480 72 4C JC 83 - -
1038
1039 048F 8F 0000 "DV PI,O SEND LS8 OF MAX CYL I NDER
1040 0492 E8 04E9 R CALL INIT DRV S
1041 0495 72 44 JC 83 - -
1042
1043 0497 8F 0002 "DV 01,2 SEND THE MAX I MUM HEADS
1044 049A E8 04E9 R CALL INIT DRV S
1045 0490 72 3C JC 83 - -
1046
1047 049F 8F 0004 "OV DI,4 SEND MS8 OF REDUCE WR I TE CURRENT
1048 04A2 E8 04E9 R CALL INIT DRV S CYL I NDER
1049 04A5 72 34 JC 83 - -
t 050
1051 04A7 8F 0003 "OV o [,3 SEND LSB OF REDUCE WRITE CURRENT
1052 04AA E8 04E9 R CALL INIT DRV S CYLINDER
1053 04AD 72 2C JC 83 - -
1054
1055 04AF BF 0006 "OV o [,6 SEND MSB OF WR I TE PRECOMP CYL I NDER
1056 04B2 E8 04E9 R CALL INIT DRV S
1057 0485 72 24 JC 83 - -
\ 058
1059 04B7 SF 0005 "OV DI,5
1060 048A E8 04E9 R CALL INIT DRV S
1061 048072 IC JC B3 - -
1062
1063 04BF 6F 0007 "OV 01,7 SEND ECC BURST LENGTH
1064 04C2 E8 04E9 R CALL [NIT DRV S
1065 04C5 72 14 JC 83 - -
1066
1067 04C7 BF 0008 "OV 01,8 LOAD THE CONTROL BYTE AND PLACE IN
1068 04CA 26: 8A 01 "OV AL, ES: [8X+D I] MEMORY AT 40:76H
1069 04CD A2 0076 R "OV CONTROL_ 8YTE, AL
1070
1071 040026 C9 SUB CX,CX
1072 0402 B4 OF "DV AH,OOOOl1118
10730404 85:
1074 0404 E8 0680 R CALL HD WA IT GO WA I T FOR THE STATE TO HAPPEN
1075 0407 73 09 JNC B6- JMP TO READ THE STATUS 8YTE
1076 0409 E2 F9 LOOP B5 TRY AGAIN
1077 0408 83:
1078 0408 C6 06 0074 R 07 "OV DISK STATUS,INIT_FAIL OPERATION FAILED
1079 04EO F9 STC SET THE ERROR eOND I T I ON
1080 04E I C3 RET
1081 04E2 B6:
1082 04E2 4A OEC DX ADDRESS PORT 0
1083 04E3 EC IN AL,DX READ STATUS BYTE OF THE OPERATION
1084 04E4 24 02 ANO AL,2 MASK ERROR 81T
1085 04E6 75 F3 JNZ 83 ERROR 81T SET?
1086 04E8 C3 RET
1087 04E9 INIT_DRV_R ENDP

March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 33

 IBM Personal Computer MACRO Assembler Vers,on 2.00 \-11
DISK2 ---- 10/28/85 FIXED DISK BIOS 10-28-85

1088
1089 SEND THE BYTE OUT TO THE CONTROLLER
\ 090
\09\ 04E9 INIT DRV S PROC NEAR
1092 04E9 E8 0680 R - CALL HD WA I T GO WA I T FOR REQUEST
1093 04EC 12 05 JC D'- AFTER CALL OX = PORT 1
1094 04EE 411. DEC DX ADDRESS PORT 0
1095 04EF 26: MOV AL,ES: [BX+Ol ]
10<;16 04F2 EE OUT aX,AL WRITE THE OATil. TO THE CARD
1097 04F3 01 :
1098 04F3 C3 RET
1099 04F4 lNIT_DRV_S ENDP
1100
1101
I 102 READ LONG (AH = OAHI :
1 103
I 104
1I0504F4 RD_LONG PROC NEAR
1106 04F4 E8 050E R CALL CHK LONG ; CHECK LIM I TS
1101 04F7 12 SF JC GS -
1108 04F9 C6 46 F8 E5 MDV CMD BLOCK+O,RD LONG CMD
I 109 04FO BO 47 MDV AL,DMA READ - -
I I \ 0 04FF EB 50 JMP SHORT - DMA OPN
I I I I 050 I ENDP -
II \2
1113
1114 ,----
;
WR ITE LONG (AH = OBHI :
1115
1116
1111 050 I WR_LONG PROC NEAR
1118 0501 E8 050E R CALL CHK LONG ; CHECK LIM I TS
1 I 19 0504 12 52 JC GS -
1120 0506 C6 46 F8 E6 MOV CMD BLOCK + 0, WR LONG CMD
1 121 05011. 80 4B MDV AL,DMA WRITE - -
I 122 050C E8 50 JMP SHORT - OMA OPN
1123 050E WR_LONG ENOP -
1124
1125 050E CHK LONG PROC NEAR
1126 050E 811. 46 FC - MOV AL,CMD BLOCK+4 LOAD THE NUMBER OF SECTORS
11210511 3C 80 CMP AL,080H COMPARE WITH LIMITS
1128 0513 F5 CMC SET THE COND I T I ON
1129 0514 C3 RET
11300515 CHK_LONG ENDP

::.~~
1133 SEEK IAH = OCH) :
1134
1135
1136 0515 DISK SEEK PROC NEAR
1131 0515 C6 46 F8 OB - MOV CMD BLOCK+O, SEEK CMD
11380519 E8 34 JMP SHORT NOMA OPN-
11390518 01 SK_SEEK ENDP -
1140
1141
1142 READ SECTOR BUFFER (AH = OEHI :
1143
1144
1145 051B RD BUFF PROC NEAR
1146 0518 C6 46 F8 OE - MOV CMO BLOCK+O,RD BUFF CMD
1141 051F C6 46 FC 01 MDV CMD-BLOCK+4,1 - - ONLY ONE BLOCK
1148 0523 BO 41 MDV AL,OMA READ
1149 0525 EB 31 JMP SHORT - DMA_OPN
I 150 0527 RD_BUFF ENDP
1151
1152
1153
1154
,-----
;
WR I TE SECTOR 8UFFER (AH = OFHI
1155
1156 0521 WR BUFF PROC NEAR
11510521 C6 46 F8 OF - MOV CMO BLOCK + 0 • WR BUFF CMD
1158 052B C6 46 Fe 01 MDV CMD-BLOCK+4, 1 - - ONLY ONE BLOCK
1159 052F BO 4B MOV AL,OMA WRITE
1160 0531 EB 28 JMP SHORT - OMA _ OPN
11610533 WR _BUFF ENDP
1162
1163 ._-------------------------------------------------------
1164 ; TEST DISK READY (AH = OIOHI :
1165
1166
1 167 0533 TST ROY PROC NEAR
1168 0533 C6 46 F8 00 - MOV CMD 8LOCK+O, TST ROY CMD
1169 0537 EB 16 JMP SHORT NDMA_OPN -
1110 0539 TST_ROY ENDP
1111
1112 ; --- ------ - ---------- ------------- ----
1113 ; RECAL I BRATE (AH = 011HI :
1114
1175
11760539 HD I SK RECAL PROC NEAR
1111 0539 C6 46 F8 01 - MOV CMD BLOCK+O,RECAL CMD
11180530 EB 10 JMP SHORT NOMA OPN -
1119053F HDISK_RECAL ENDP -

34 20MB Fixed Disk Drive Adapter BIOS March 17, 1986

 IBM Personal Computer MACRO Assembler VersIon 2.00 [-12
0lSK2 ---- 10/28/85 FIXED DISK 810S 10-28-85

180 PAGE
181 ; - - ---------------- ----------- - ------- - --- - - --- ----------
182 ; CONTROLLER RAM DIAGNOSTICS IAH = 012HI :
183
184
185 053F RAM DIAG PROC NEAR
186 053F C6 46 F8 EO - MOV CMD BLOCK+O,RAM DIAG CMD
181 0543 E8 OA J"P SHORT NOMA OPN -
188 0545 RAM_D I Ar::. ENOP -
189
190
1191 DR I VE 0 I AGNOSTI CS (AH = 013HI :
1192 ; ------ -- ---- ------ - ---------------- --------- ------ - -----
1193
1194 0545 CHK DRV PROC
11950545 C6 46 F8 E3 - MOV
1196 0549 E8 04 J"P
1191 0546 CHK_DRV ENOP
1198
1199 ; --- - -------- ------ --------------------------- ----------
1200 ; CONTROLLER INTERNAL DIAGNOSTICS {AH = 014Hl :
1201
1202
1203 0548 CNTLR DI AG PROC NEAR
1204 0548 C6 46 F8 E4 - MOV CMD BLOCK + 0 ,CNTLR 0 I AG CMO
1205 054F CNTLR_D I AG ENDP --
1206
1201 ; ------- -- ----- ------- ------ - --------- --------- ----- - ----
1208 ; SUPPORT ROUT! NES
1209
1210
1211054F NOMA OPN:
1212 054F BO 02 - MOV AL,02H
1213 0551 E8 057C R CALL COMMAND I S SUE THE COMMAND
1214 0554 72 22 JC Gil
1215 0556 EB 16 J"P SHORT G3
1216 0558 G8:
12110558 C6 06 0074 R 09 "OY
1218 0550 C3 RET
1219 055E OMA OPN:
1220 055E E8 06A5 R - CALL OMA SETUP SET UP FOR OMA OPERAT I ON
1221 0561 72 F5 JC G8 -
1222 0563 BO 03 "OY AL,03H
1223 0565 E8 051C R CALL COMMAND I SSUE THE COMMAND
1224 0568 12 OE JC Gil
1225 056A BO 03 "OY AL,03H
1226 056C E6 OA OUT DMA+l0,AL INITIALIZE THE DISK CHANNEL
1227 056E G3:
1228 056E FA CLI NO INTERRUPTS
1229 056F E4 21 IN AL,INTAOI READ THE MASK
1230 0511 24 OF AND AL,ODFH ENABLE IRQ-5
1231 0513 E6 21 OUT INTA01,AL WR I TE THE MASK OUT
1232 0515 E8 0700 R CALL WAIT_INT PROCEDURE DOES ST I
1233 0518 Gil:
1234 0518 E8 05AD R CALL ERROR_CHK SEE I F THERE I S AN ERROR
1235 051B C3 RET EXIT
1236
1237 ; --------- --------- ----------------- - -------------------
1238 ; COMMAND
1239 ; INPUT TH I S ROUT I NE OUTPUTS THE COMMAND BLOCK
1240
1241 AL = CONTROLLER DMA/INTERRUPT REGISTER MASK
1242
1243
1244
1245 051C COMMAND PROC NEAR
1246 051C E8 0160 R CALL PORT 0 GET THE BASE ADDRESS
1241 051F 42 INC OX -
1248 0580 42 INC OX ADDRESS PORT 2
12490581 EE OUT DX,AL I SSUE CONTROLLER SELECT PULSE
1250 0582 42 INC OX ADDRESS PORT 3
1251 0583 2B C9 SUB CX,CX WA IT COUNT
1252 0585 EE OUT DX,AL WRITE DMA MASK REGISTER
1253 0586 4A DEC OX
1254 0581 4A DEC OX ADDRESS PORT 1
1255 0588 WAIT BUSY:
1256 0588 EC - IN AL,DX READ THE HARDWARE STATUS
1251 0589 24 OF AND AL,OFH
1258 0586 3C 00 C"P AL,Rl BUSY OR RI BUS OR Rl REQ ; CHECK FOR BUSY,COMMAND
1259 0580 14 09 JE CI - - -; AND REQUEST BITS
1260 058F E2 F1 LOOP WA I T BUSY KEEP TRY I NG
1261 0591 C6 06 0014 R 80 "OY 01 SK::::STATUS, T I ME_OUT
1262 0596 F9 STC SET THE ERROR CONo I T I ON
1263 0597 C3 RET ERROR RETURN
1264 0598 CI:
1265 0598 B9 0006 "OY CX,6 SET FOR 6 BYTES OF COMMAND
1266 0598 4A DEC OX ADDRESS PORT 0
1261 059C 88 F5 "OY SI,BP SAVE THE BASE POINTER
1268 059E 83 ED 08 SUB BP,8 SET FIRST BYTE OF COMMAND BLOCK
1269 05AI FA CLI NO I NTERRUPTS I N COMMAND SEQUENCE
1210 05A2 CM3:
1271 05A2 8A 46 00 "OY AL, {BP] GET A COMMAND BYTE
1212 05A5 EE OUT DX,AL ALLOW AT LEAST 2us BETWEEN EACH BYTE
1213 05A6 45 INC BP ON SEND I NG THE COMMAND SEQUENCE.
1274 05A1 E2 F9 LOOP C"3 DO MORE
1215 05A9 88 EE "OY BP,SI RESTORE THE BASE POINTER
1216 05A8 F8 STI I NTERRUPTS BACK ON
1211 05AC C3 RET
1218 05AD COMMAND ENDP

March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 35

 IBM Person"l Computer MACRO Assembler Version 2.00 1-13
DISK2 ---- 10/28/85 FIXED DISK 8105 10-28-85

1219 PAGE
1280
1281
:
;
-- - -- -- -- - -- - -- -- -- ----- - - -- --- --- - -- -- - - -- - --- - ---- ---
1282 ; SENSE STATUS BYTES
1283 ; BYTE 0
1284 ; BIT 1 ADDRESS VALID, WHEN SET
1285 ; B[T 6 SPARE, SET TO ZERO
1286 ; BITS 5-4 ERROR TYPE
1281 ; BITS 3-0 ERROR CODE
1288 ;
1289 ; BYTE 1
1290 BITS 7-6 ZERO
1291 ; 81T 5 DRIVE (0-1)
1292 ; B[TS 4-0 HEAD NUMBER
1293 ;
1294 ; BYTE 2
1295 ; 81TS 1-5 CYL! NDER HIGH
1296 ; BITS 4-0 SECTOR NUMBER
1291 ;
1298 ; BYTE 3
1299 ; B[TS 1-0 CYLI NOER LOW
1300 ;
1301 i - ---- - - ---------- ----- ----------- ----------------------
1302
1303 05AD ERROR CHK PROC NEAR
1304 05AD AO 0074 R - MOV AL,DISK STATUS ; CHECK IF THERE WAS AN ERROR
1305 0580 OA CO OR AL,AL - ; ANYTHING IN AL?
13060582 15 01 JNZ 021
1301 0584 C3 RET
1308
1309 .-------------- ---- --------------
t 31 0 ; PERFORM SENSE STATUS
1311
1312 SENSE STATUS CAN BE ISSUED MULTIPLE
1313 TIMES
13140585 G21 :
13150585 C6 46 F8 03 MDV CMD BLOCK+O, SENSE CMO
13160569 2A CO SUB AL,AL - WRITE ZERO IN INT/OMA MASK
13110568 E8 051C R CALL COMMAND [SSUE SENSE STATUS COMMAND
1318 058E 1226 JC 024 CANNOT RECOVER-EX I T WITH COMMAND
1319 ERROR
1320 05CO 28 FF SUB DI,OI SET [NDEX PO I NTER TO ZERO
1321 05C2 89 0004 MDV CX,4 READ FOUR BYTES
1322 05C5 84 DB MDV AH,OOOOIOIIB SET MASK FOR DATA MODE CARD TO CPU
1323 05C7 G22:
1324 05C1 E8 0680 R CALL HO WA I T GO WAIT FOR DATA INPUT STATE
1325 05CA 72 lA JC G24
1326 05CC 4A DEC OX ADDRESS PORT 0
1327 05CD EC IN AL,DX READ THE DATA BYTE
1328 05CE 88 43 F8 MDV [OI+CMD BLDCK],AL STORE AWAY SENSE BYTES
1329 0501 47 INC 01 - NEXT DATA LOCAT[ON
t 330 0502 E2 F3 LOOP 022 LOOP TILL ALL FOUR READ.
1331 0504 B4 OF MDV AH,OOOO! II IB SET THE MASK FOR STATUS MODE
1332 0506 E8 0680 R CALL HD WAIT GO WAIT FOR STATUS STATE
1333 0509 12 DB JC G24
1334 05DB 4A DEC OX ADDRESS PORT 0
1335 05DC EC IN AL,OX READ THE STATUS BYTE
1336 0500 A8 02 TEST AL,2 SENSE OPERATION FAIL?
1331 05DF 14 OF JZ STAT_ERR GO GET THE ERROR.
1338
1339 05E 1 C6 06 0074 R FF MDV DISK_STATUS. SENSE_FA I L SET SENSE OPERAT[ON FAIL
1340 05E6 G24:
1341 05E6 F9 STC
1342 05E7 C3 RET
1343 05E8 ERROR_CHK ENDP
1344
1345 05E8 061E R T_O OW TYPE 0 ERROR TYPE .JUMP T A8LE
1346 05EA 062B R OW TYPE-I
1341 05EC 0660 R OW TYPE-2
1348 OSEE 061A R ow TYPE::)
1349
1350 05FO STAT ERR:
1351 05FO 8A 5E F8 - MOV BL,CMD BLOCK+O GET ERROR BYTE
1352 05F3 8A C3 MDV AL,BL -
1353 05F5 24 OF AND AL,OFH
1354 05F7 80 E3 30 AND BL,00110000B ISOLATE THE TYPE OF ERROR
1355 05FA 2A FF SUB BH,BH
1356 05FC BI 03 MDV Cl,3
1351 05FE 03 EB SHR BX, CL ; AD.JUST
13580600 2E: FF A1 05E8 R JMP WORD PTR CS:{8X + OFFSET T_O)
1359
1360 0605 TYPEO TABLE LABEL BYTE
1361 0605 00 20 40 CC 80 00 - DB 0, BAD _ CNTLR ,BAD_SEEK, WR I TE_F AUL T , T [ME_OUT. 0 ,BAD_CNTLR
1362 20
1363 060C 00 40 DB o ,BAD SEEK
1364 = 0009 TYPEO_LEN EQU - S-TYPEO_TABLE
1365
1366 060E TYPE 1 TABLE LABEL BYTE
1361 060E 04 10 02 00 04 - DB RECORD NOT FND. BAD ECC, BAD ADDR MARK. 0, RECORD NOT FNO
1368061340 00 00 II DB DB BAD SEEK ,0-;-0 ,DATA C:ORRECTED,BAO-TRACK --
1369 = OOOA TYPE I_LEN EQU- S-TYPEI_TABLE -
1310
1371 0618 TYPE2 TABLE LABEL BYTE
1372 0618 01 02 01 - DB BAD CMO ,BAD ADDR MARK ,BAD CMD
1313 = 0003 TYPE2_LEN EQU- S-TYPE2_TABLE -
1374
1315 061B TYPE3 TABLE LABEL BYTE
- DB
1316 061B 20 20
1371= 0003 TYPE3_LEN ~~~_CNTL~~ ~~~E~~~~~L~AD _ ECC

36 20MB Fixed Disk Drive Adapter BIOS March 17,1986

 IBM Personal Computer MACRO Assernbler Version 2.00 1-14
DISK2 ---- 10/28/85 FIXED DISK BIOS 10-28-85

1318 PAGE
1319 TYPE 0 ERROR
1380
1381 ablE
1382 ablE BB 0605 R MOV eX,OFFSET TYPED TABLE
1383 Ob21 3C 09 eMp AL,TYPEO LEN - CHECK I F ERROR I S OEF I NED
1384 0623 13 62 "AE UNDEF ERR L
1385 0625 2E: 01 XLAT CS:TYPEO TABLE T ABLE LOOKUP
! 386 Ob21 A2 0014 R MOV 01 SK_STATUS,AL SET ERROR CODE
1381 062A C3 RET
1388
1389 :------ TYPE I ERROR
t 390
1391 062B TYPE_l :
1392 Ob2B BB ObOE R MOV BX,OFFSET TYPE I_TABLE
1393 Ob2E 8B CB MOV CX,AX
1394 0630 3C OA eMP AL, TYPE 1 LEN CHECK I F ERROR IS OEF I NED
1395 0632
139b Ob34
13 53
2E: 01
"AE
XLAT
UNOEF ERR L
CS:TYPEI TABLE T ABLE LOOKUP
1391 Ob36 A2 0014 R MOV DISK STATUS,AL SET ERROR CODE
1398 0639 80 E 1 08 AND CL,OSH CORRECTED ECC
1399 063C 80 F9 OB eMP CL ,08H
1400 Ob3F 15 29 "NZ G30
140 I
1402 OBTAIN ECC ERROR BURST LENGTH
1403
1404 0641 C6 46 F8 00 MOV ~~~ A~LOCK + 0 ,RD _ ECC _ CMO
1405 Ob45 2A CO SUB
1406 0641 E8 051C R CALL COMMAND I SSUE THE COMMAND
1401 064A 12 IE X G30
1408 064C B4 OB MOV AH,OOOOI01IB SET MASK FOR DATA INPUT CARD TO CPU
1409 Ob4E E8 06BO R CALL HD WAI T GO WAIT FOR THE INPUT STATE
1410 0651
1411 0653
12
4A
17 "e
DEC
GiO
OX ADDRESS PORT 0
1412 Ob54 EC IN AL,OX READ THE LENGTH OF THE ERROR
1413 0655 8A C8 MOV CL,AL CORRECTED AND SAVE IN CL
1414 0657 B4 OF MOV AH,OOOOIIIIB SET MASK FOR STATUS STATE
14150659 E8 0680 R CALL HD WAI T GO WAIT FOR STATUS STATE
1416 065C
1417 Ob5£
72
4A
OC "e
DEC
G30
OX ADDRESS PORT 0
1418 065F £C IN AL.DX READ THE STATUS BYTE
14190660 A8 02 TEST AL,2 ERROR BIT SEn
1420 0662
1421 0664
14
C6
Ob
06 0074 R 20
"Z
MOV
G30
01 SK_ST ATUS, BAD_CNTLR
1422 Ob69 F9 STG
1423 066A G30 :
1424 066A 8A Cl MOV AL,CL
1425 066C C3 RET
1426
1427 TYPE 2 ERROR
1428
1429 0660
1430 0660 BB 0618 R MOV BX, OFFSET TYPE2 TABLE
1431 Ob70 3C 03 eMp AL. TYPE2 LEN - CHECK I F ERROR I S DEF I NED
1432 0672 13 13 "AE UNDEF ERR L
1433 0674 2£: 07 XLAT CS :TYPE2 TABLE TABLE LOOKUP
1434 0676 A2 0074 R "OV DISK_STATUS,AL SET ERROR CODE
1435 0679 C3 RET
1436
1437 TYPE 3 ERROR
143B
1439 061A
1440 067A BB 061B R MOV BX, OFFSET TYPE3 TABLE
1441 0670 3C 03 eMp AL, TYPE3 LEN - CHECK I F ERROR I S OEF I NED
1442 067F 13 06 "AE UNDEF ERR L
1443 0681 2E: 07 XLAT CS: TYPE3 TABLE T ABLE LOOKUP
1444 0683 A2 0074 R "OV 01 SK_STATUS,AL SET ERROR CODE
1445 0686 C3 RET
1446
1447 0687 UNDEF ERR L:
1448 Ob87 C6 Ob 0074 R BB - MOV DISK_STATUS, UNDEF _ERR
1449 068C C3 RET
1450
1451 .- - - - - -- - - - - - - -- - - - - -- - - - - -- - - - - - - --
- - -
1452 ; ON ENTRY AH CONTA I NS THE CONTROLLER BUS STATUS DECODE :
1453
1454 .; - MASK USED TO CHECK THE HARDWARE STATUS. :
- - - - - - - -- - - - - - - - -- - - - -- - - - -- - - - - -- - - - - - - - - -- -- - - - - - ---
-
1455 Ob80 HD_WAIT PROC NEAR
1456 0680 51 PUSH CX SAVE CX
1451 068E 2B C9 SUB CX, CX SET THE LOOP COUNT
1458 0690
1459 0690 E8 0760 R CALL PORT 0
1460 0693 42 INC OX - PORT 1 ADDRESS
1461 0694 £C IN AL,DX READ-THE HARDWARE STATUS
1462 0695 24 OF AND AL,OOOOIIIIB CLEAR UPPER NIBBLE OF HARDWARE STATUS
1463 0697 3A C4 eMp AL,AH CHECK THE STATE WITH THE MASK
1464 0699
\ 465 069B
74
E2
08
F3
"Z
LOOP
L2
LI
.)MP t F o. K Wt TH CARRY CLEARED
TRY AGAIN
1466 0690 C6 06 0074 R 80 "OV o t SK_ST ATUS. T I ME_OUT
1467 06A2 F9 STe SET ERROR CONO I T I ON
1468 06A3 L2:
1469 06A3 59 ex RESTORE CX
1470 06A4 C3
1471 06A5

March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 37

 IBM Personal Computer MACRO Assembler Version 2.00 1-15
DISK2 ---- 10128185 FIXED DISK BIDS 10-28-85

1472 PAGE
1413 ; -------------- -----------------------------
1474 DMA SETUP
1475 ; - THIS ROUTfNE SETS UP FOR DMA OPERATIONS.
1476 INPUT
1477 (ALl =
MODE BYTE FOR THE DMA
1478 (ES:BX) =
ADDRESS TO READ/WRITE THE DATA
1479 OUTPUT
1480 ; (AX' DESTROYED
148 I ; ----------- - -------------------------------------------
1482
1483 06A5 DMA SETUP PROC NEAR
1484 06A5 80 7E FC 81 - CMP CMO BLOCK +4,81 H BLOCK COUNT OUT OF RANGE
1485 06A9 72 02 JB JI -
1486
1487 06AB F9 STC SET THE ERROR COND I T I ON
1488 06AC C3 RET
1489
1490 D6AD ,)1:
1491 06AD FA CLI NO MORE INTERRUPTS
1492 D6AE E6 DC OUT DMA+12,AL SET THE FIRSTfLAST FIF
1493 06BO BI 04 MOY CL,4 SH 1FT COUNT
1494 0682 E6 08 OUT OMA+ I I,AL OUTPUT THE MODE 8YTE
1495 0684 8C CO MOY AX,ES GET THE ES VALUE
1496 D6B6 D3 CO ROL AX,CL ROTATE LEFT
1497 06B8 8A E8 MOY CH,AL GET HIGHEST NIBBLE OF ES TO CH
1498 068A 24 FO AND AL,OFOH ZERO THE LOW NIBBLE FROM SEGMENT
1499 D6BC 03 C3 ADD AX,BX TEST FOR CARRY FROM ADD I T I ON
1500 D6BE 80 05 00 AOC CH,O CARRY MEANS HIGH 4 B[TS MUST BE [NC
1501
1502 06CI 88 FO MDY S[ ,AX SAVE START ADDRESS
1503 06C3 E6 06 OUT DMA+6,AL OUTPUT LOW ADDRESS
1504 06C5 8A C4 MOY AL,AH
1505 06C7 E6 06 OUT DMA+6,AL OUTPUT HIGH ADDRESS
1506 06C9 8A C5 MOY AL,CH GET HIGH 4 BITS
1507 06CS 24 OF AND AL,OFH
1508 06CO E6 82 OUT DMA_HIGH,AL OUTPUT THE HIGH 4 BITS TO PAGE REG
1509
1510 ;------ DETERMINE COUNT
1511
1512 06CF 8A 66 FC MOY AH,CMD BLOCK+4 RECOVER BLOCK COUNT
t 513 0602 DO E4 SHL AH, I - , MULTIPLY BY 512 BYTES PER SECTOR
1514 0604 32 CO XOR AL,AL ; CLEAR LOW BYTE
1515060648 DEC AX AND DECREMENT VALUE BY ONE
t 516
1517 HANDLE READ AND WRITE LONG (5160 BYTE BLOCKS)
1518
15190607 80 7E F8 E5 CMP CMD BLDCK+O,RD LONG CMD
1520 06DB 74 06 JE ADD4 --
1521
1522 0600 80 7E F8 E6 CMP
1523 06El 75 OF JNE
1524 06E3 ADD4:
1525 06E3 88 0204 MOY AX,516D ONE BLOCK (512) PLUS 4 BYTES ECC
1526 06E6 53 PUSH BX
1527 06E7 2A FF SUB BH,8H
1528 06E9 8A 5E FC MOY BL,CMD BLOCK+4
1529 D6EC 52 PUSH OX -
1530 D6ED F7 E3 MUL BX BLOCK COUNT TIMES 516
1531 06EF 5A POP OX
1532 06FO 58 POP BX
1533 D6FI 48 DEC AX ADJUST
1534 06F2 ,)20:
1535 06F2 86 C8 MOY CX,AX SAVE COUNT VALUE
1536 06F4 E6 07 OUT OMA+7,AL LOW BYTE OF COUNT
1537 OoF6 8A C4 MOY AL,AH
1538 06F8 E6 07 OUT DMA+7,AL HIGH BYTE OF COUNT
1539 06FA F8 ST I INTERRUPT 5 BACK ON
1540 06FB 88 C6 MOY AX,51 RECOVER ADDRESS VALUE
1541 06FD 03 Cl ADO AX,CX ADD, TEST FOR 64K OVERFLOW
1542 06FF C3 RET RETURN TO CALLER,
1543 CY SET BY ABOVE I F ERROR
1544 0700 DMA_SETUP ENDP

38 20MB Fixed Disk Drive Adapter BIOS March 17,1986

 IBM Personal Computer MACRO Assembler Vers'on 2.00 1-16
DISK2 ---- 10{28{85 FIXED DISK BIOS 10-28-85

1545
1546
1541
:
PAGE
-;~ ~ ~-~~~--- - - - -- -- ---- -----------
1548 ; - THIS ROUTINE WAITS FOR THE FIXED DISK
1549 ; CONTROLLER TO SIGNAL THAT AN INTERRUPT
1550 ; HA S OCCURRED.
155 I
1552
1553 0700 WAIT INT PROC NEAR
1554 - ASSUME DS:ABSO
1555 0700 FB STI TURN ON INTERRUPTS
1556 0101 8C DB MO' BX,DS SAVE OS
1551 0103 2B CO SUB AX,AX
1558 0705 8E 08 MO' OS,AX EST ABL I SH SEGMENT
1559 0701 C4 36 0104 R LES SI,HF_TBL_VEC LOAD THE TABLE VECTOR
1560
1561 ASSUME OS: DATA, ES: NOTH I NG
1562 070B 8E DB MO' DS,BX RESTORE OS
1563
1564 ; -- SET TIMEOUT VALUES
1565
1566 0700 2A FF SUB SH,BH
1561 010F 26: 8A 5C 09 MO' BL ,BYTE PTR ES: [S[] (9) LOAD THE STANDARD T I ME OUT
1568 0113 8A 66 F8 MO' AH,CMD BLOCK+O
1569 0716 80 FC 04 eMP AH,FMTDRV_CMD
1510 0719 15 06 JNZ 05
1511
1512 071B 26: 8A 5C OA MO' BL,BYTE PTR ES:[S[)[OAH] LOAD THE FORMAT DR I VE
1513 071F EB 09 JMP SHORT O. T[ME OUT VALUE
15740721 80 FC E3 W5: CMP AH,CHK_DRV_CMD
1575 0724 75 04 JNZ O.
1576
1577 0726 26: 8A 5C OB MO' BL,BYTE PTR ES:[SI)[OBH) ; LOAD THE CHECK DR I VE
1578 07211. W4: CLEAR ~Y Tl ME OUT VALUE
1579 072A F8 eLC
1580 072B B8 9000 MO' AX,9000H DEV I CE WA I T INTERRUPT
1581 072E CO 15 INT 15H
1582 0730 FB ST I ENABLE [NTERRUPTS FOR PC AND
1583 XT MACH I NES.
1584 0131 2B C9 SUB CX,CX SET THE LOOP COUNT
1585
1586 WA [T FOR 1NTERRUPT
1587
1588 0733 WI:
1589 0733 E8 0160 R CALL PORT 0
1590 0736 42 INC ox - PORT I ADDRESS
1591 0131 EC IN AL,OX READ-THE HARDWARE STATUS
1592 0138 11.8 20 TEST AL,020H 0[0 I NTERRUPT OCCUR
1593 07311. 15 Oil. JNZ 02 .JUMP [F YES
1594
1595 013C E2 F5 LOOP 01 INNER LOOP
1596 013E 4B DEC BX
1591 073F 75 F2 JNZ 01 OUTER LOOP
1598
1599 0741 C6 06 0074 R 80 MOV DISK STATUS,TIME_OUT
1600 0746 W2:
1601 0746 411. DEC ox ADDRESS PORT 0
1602 0747 EC IN AL,DX READ THE STATUS BYTE
1603 0748 24 02 AND AL,2 ISOLATE THE ERROR B[T
1604 074A 08 06 0074 R OR DISK STATUS,AL SAVE I N THE STATUS
1605 074E 83 C2 03 ADO DX,3- PORT 3 ADDRESS
1606 0151 32 CO XOR AL,AL ZERO-
1607 0753 EE OUT OX,AL RESET I NTERRUPT MASK
1608 0754 C3 RET
1609
1610 0755 ENDP
1611
1612 ;--- HD INT
1613
1614 FIXED DISK INTERRUPT ODH ROUTINE IRQ-5
1615
1616
1617
1618 0155 PRoe NEAR
16190755 50 PUSH AX SAVE WORK REGISTER
1620 0156 BO 01 MOV AL,07H SET OMA MODE TO 0 I SABLE
1621 0158 E6 OA OUT DMA+IO,AL
1622 01511. FA eLi NO INTERRUPTS
1623 075B E4 21 IN AL,INTAOI LOAD THE I NTERRUPT ENABLE MASK
1624 0150 OC 20 OR AL,020H TURN OFF FIXED DISK IRQ-5
1625 015F E6 21 OUT INTAOI,AL REPLACE THE MA SK
1626 0761 BO 20 MOV AL,EOI LOAD THE END OF INTERRUPT MASK
1627 0763 E6 20 OUT [NTAOO,AL CLEAR THE ACT [VE I NTERRUPT LEVEL
1628 0165 FB STI I NTERRUPTS BACK ON
1629076688 9100 MOV AX,9100H DEV ICE POST
1630 0169 CO 15 INT 15H INTERRUPT
1631 016B 58 POP AX RESTORE AX
1632 016C CF IRET
16330160 ENDP
1634
1635
1636
: -~~~~~---------------- - -------- ---------
1631 GENERATE PROPER PORT VALUE
1638 BASED ON THE PORT OFFSET
1639
1640
1641 0160 PORT_O PROe NEAR
1642 0760 BA 0320 MOV OX,HF PORT BASE VALUE
1643 0170 02 16 0011 R ADO OL,PORT_OFF ADD [N OFFSET VALUE (00,04,08,OC)
1644 0174 C3 RET
1645 0175 PORT_O ENOP
1646
1647 0775 END ADDRESS LABEL BYTE
1648 0175 CODE ENDS
1649 END

March 17, 1986 20MB Fixed Disk Drive Adapter BIOS 39

Notes:

4020MB Fixed Disk Drive Adapter BIOS March 17, 1986

Index

~
addresses, port 14 fixed disk controller 1
fixed disk drive types 3

[!J
BIOS listings 23
block diagram 2 interface 15
interface signals
AEN 15
AO-AI9 15
-DACK 3 16
DO-D7 15
command summary 10 DRQ 3 15
connectors 17 -lOR 15
control byte 8 -lOW 15
controller, fixed disk 1 IRQ 5 15
RESET 15

[EJ
data register 7
description 1 logic diagrams 19

[!]
error tables 5

March 17, 1986 20MB Fixed Disk Drive Adapter Index-l

port addresses 14 sense bytes 4
programming specifications 17
considerations 3 status register 4
programming summary 14 switch settings 3

registers 1 TTL levels 17

Index-220MB Fixed Disk Drive Adapter March 17, 1986

----
-- - ---
--
--- --
- ---
-
Personal Computer
--_.-
---- ---
-- Hardware Reference
Library

mM Asynchronous
Communications
Adapter

6361501
ii
Contents

Description .................................... 1
Programming Considerations ...................... 3
Modes Of Operation ......................... 3
Line-Control Register ........................ 5
Programmable Baud-Rate Generator ............ 7
Line Status Register (LSR) ................... 10
Interrupt Identification Register (IIR) .......... 12
Interrupt Enable Register .................... 14
Modem Control Register .................... 15
Modem Status Register ...................... 16
Receiver Buffer Register ..................... 18
Transmitter Holding Register ................. 19
Selecting the Interface Format and Adapter Address 20
Interrupts ................................ 21
Interface ..................................... 23
Voltage Interchange Information .............. 24
INS8250 Functional Pin Description ........... 25
Specifications ................................. 31
Logic Diagrams ................................ 33

Index ........................................ Index-l

iii
jv
Description

The Asynchronous Communications Adapter's system control

signals and voltage requirements are provided through a 2- by
31-position card-edge connector. Two jumper modules are
provided on the adapter. One jumper module selects either
RS-232C or current-loop operation. The other jumper module
selects one of two addresses for the adapter, so two adapters may
be used in one system. An additional jumper is required on
connector J13 if the adapter is to be installed in expansion slot 8
of an IBM Personal Computer XT or IBM Portable Personal
Computer (see "Selecting the Interface Format and Adapter
Address" in this section).

The adapter is fully programmable and supports asynchronous

communications only. It will add and remove start bits, stop bits,
and parity bits. A programmable baud-rate generator allows
operation from 50 baud to 9600 baud. Five-, six-, seven-, or
eight-bit characters with 1, 1-1/2, or 2 stop bits are supported. A
fully prioritized interrupt system controls transmit, receive, error,
line status, and data set interrupts. Diagnostic capabilities provide
loop back functions of transmit! receive and input/output signals.

The major component of the adapter is an INS8250 LSI chip or

functional equivalent. Features in addition to those listed above
are:

• Full double buffering eliminating the need for precise

synchronization

• Independent receiver clock input

• False-start bit detection

• Line-break generation and detection

Asynchronous Adapter 1
• Modern control functions:

Clear to send (CTS)

Request to send (RTS)
Data set ready (DSR)
Data terminal ready (DTR)
Ring indicator (RI)
Carrier detect (CD)

All communication protocol is a function of the system microcode

and must be loaded before the adapter is operational. All pacing
of the interface and control signal status must be handled by the
system software. The following figure is a block diagram of the
IBM Asynchronous Communications Adapter.

Address Bus Address Chip

Decode r.S::""e-+le-c-:"t~~
Data Bus
----------~ln~te~r~ru~p~t--------~8250
4------------------------1 Asynchronous
Oscillator Communications
1.8432 MHz I------.t Element

EIA
Receivers

Current Loop

25-Pin D-Sheli
Connector

Asynchronous Communications Adapter Block Diagram

2 Asynchronous Adapter
Programming Considerations

Modes Of Operation
The different modes of operation are selected by programming
the 8250 Asynchronous Communications Element. This is done
by selecting the I/O address (hex 3F8 to 3FF primary, and hex
2F8 to 2FF secondary) and writing data out to the adapter.
Address bits AO, Al, and A2, select the different registers that
define the modes of operation. Also, bit 7-the divisor latch
access bit (DLAB)-of the line-control register is used to select
certain registers.

I/O Decode (in Hex)

Primary Alternate
Adapter Adapter Register Selected DLAB State

3F8 2F8 TX Buffer DLAB = 0 (Write)

3F8 2F8 RX Buffer DLAB = 0 (Read)
3F8 2F8 Divisor Latch LSB DLAB =1
3F9 2F9 Divisor Latch MSB DLAB =1
3F9 2F9 Interrupt Enable Register
3FA 2FA Interrupt Identification Registers
3FB 2FB Line Control Register
3FC 2FC Modem Control Register
3FD 2FD Line Status Register
3FE 2FE Modem Status Register

110 Decodes

Asynchronous Adapter 3
 Hex Addresses 3F8 to 3FF AND 2F8 TO iFF
A9 A8 A7 A6 A5 A4 A3 A2 A1 AO DLAB Register
1 1/0 1 1 1 1 1 x x x
0 0 0 0 Receive Buffer (read).
Transmit
Holding Reg. (write)
0 0 1 0 Interrupt Enable
0 1 0 x Interrupt Identification
0 1 1 x Line Control
1 0 0 x Modem Control
1 0 1 x Line Status
1 1 0 x Modem Status
1 1 1 x None
0 0 0 1 Divisor Latch (LSB)
0 0 1 1 Divisor Latch (MSB)
Note: Bit 8 will be logical 1 for the adapter designated as primary or a logical 0
for the adapter designated as alternate (as defined by the address jumper
module on the adapter).

A2, A 1 and AO bits are "don't cares" and are used to select the different
register of the communications chip.

Address Bits

INS8250
The INS8250 has a number of accessible registers. The system
programmer may access or control any of the INS8250 registers
through the system unit's microprocessor. These registers are
used to control INS8250 operations and to transmit and receive
data. The following figure provides a listing and description of
the accessible registers.

4 Asynchronous Adapter
 Register/Signal Reset Control Reset State
Interrupt Enable Register Master Reset All bits Low (0-3 Forced and
4-7 Permanent).
Interrupt Identification Master Reset Bit 0 is High, Bits 1 and 2 Low
Register Bits 3-7 are Permanently Low
Line Control Register Master Reset All Bits Low
Modem Control Register Master Reset All Bits Low
Line Status Register Master Reset Except Bits 5 and 6 are High
Modem Status Register Master Reset Bits 0-3 Low
Bits 4-7 - Input Signal
SOUT Master Reset High
INTRPT (RCVR Errors) Read LSR/MR Low
INTRPT (RCVR Data Ready) Read RBR/MR Low
INTRPT (RCVR Data Ready) Read IIRI Low
Write THR/MR
INTRPT (Modem Status Read MSR/MR Low
Changes)
OUT2 Master Reset High
RTS Master Reset High
DTR Master Reset High
OUT 1 Master Reset High

Asynchronous Communications Reset Functions

Line-Control Register
The system programmer specifies the format of the asynchronous
data communications exchange through the line-control register.
In addition to controlling the format, the programmer may
retrieve the contents of the line-control register for inspection.
This feature simplifies system programming and eliminates the
need for separate storage in system memory of the line
characteristics.

Asynchronous Adapter 5
The contents of the line-control register are as follows:

Hex Address 3FB

Bit 7 6 5 4 3 2 1 a

~
Word Length Select Bit a (WLSO)
Word Length Select Bit 1 (WLS1)
Number of Stop Bits (STB)
Parity Enable (PEN)
Even Parity Select (EPS)
Stick Parity
Set Break
Divisor Latch Access Bit (DLAB)

Bits 0 and 1: These two bits specify the number of bits in each
transmitted or received serial character. The encoding of bits 0
and 1 is as follows:

Bit 1 BitO Word Length

0 0 5 Bits
a 1 6 Bits
1 0 7 Bits
1 1 8 Bits

Bit 2: This bit specifies the number of stop bits in each

transmitted or received serial character. If bit 2 is a logical 0, one
stop bit is generated or checked in the transmitted or received
data, respectively. If bit 2 is logical 1 when a 5-bit word length is
selected through bits 0 and 1, 1-1/2 stop bits are generated or
checked. If bit 2 is logical 1 when either a 6-, 7-, or 8-bit word
length is selected, two stop bits are generated or checked.

Bit 3: This bit is the parity enable bit. When bit 3 is a logical 1, a
parity bit is generated (transmit data) or checked (receive data)
between the last data word bit and stop bit of the serial data.
(The parity bit is used to produce an even or odd number of l's
when the data word bits and the parity bit are summed.)

6 Asynchronous Adapter
Bit 4: This bit is the even parity select bit. When bit 3 is a logical
1 and bit 4 is a logical 0, an odd number of logical 1's is
transmitted or checked in the data word bits and parity bit. When
bit 3 is a logical 1 and bit 4 is a logical 1, an even number of bits
is transmitted or checked.

Bit 5: This bit is the stick parity bit. When bit 3 is a logical 1 and
bit 5 is a logical 1, the parity bit is transmitted and then detected
by the receiver as a logical 0 if bit 4 is a logical 1, or as a logical 1
if bit 4 is a logical O.

Bit 6: This bit is the set break control bit. When bit 6 is a logical
1, the serial output (SOUT) is forced to the spacing (logical 0)
state and remains there regardless of other transmitter activity.
The set break is disabled by setting bit 6 to a logical O. This
feature enables the system unit's microprocessor to alert a
terminal in a computer communications system.

Bit 7: This bit is the divisor latch access bit (DLAB). It must be
set high (logical 1) to access the divisor latches of the baud-rate
generator during a read or write operation. It must be set low
(logical 0) to access the receiver buffer, the transmitter holding
register, or the interrupt enable register.

Programmable Baud-Rate Generator

The INS8250 contains a programmable baud-rate generator that
is capable of taking the clock input (1.8432 MHz) and dividing it
by any divisor from 1 to (2 16 _1). The output frequency of the
baud generator is 16 x the baud rate (divisor # =(frequency
input)/(baud rate x 16)). Two 8-bit latches store the divisor in a
16-bit binary format. These divisor latches must be loaded during
initialization in order to ensure desired operation of the baud-rate
generator. Upon loading either of the divisor latches, a 16-bit
baud counter is immediately loaded. This prevents long counts on
initial load.

Asynchronous Adapter 7
 Hex Address 3F8 DLAB = 1
Bit 7 6 5 4 3 2 o

BitO
Bit 1
Bit 2
Bit 3
Bit4
Bit 5
Bit 6
Bit 7

Divisor Latch Least Significant Bit (DLL)

Hex Address 3F9 DLAB = 1

Bit 7 6 5 4 3 2 o
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15

Divisor Latch Most Significant Bit (DLM)

8 Asynchronous Adapter
The following figure illustrates the use of the baud-rate generator
with a frequency of 1.8432 MHz. For baud rates of 9600 and
below, the error obtained is minimal.

Note: The maximum operating frequency of the baud-rate

generator is 3.1 MHz. In no case should the data speed be
greater than 9600 baud.

Desired Divisor Used Percent Error

Baud to Generate Difference Between
Rate 16x Clock Desired and Actual
(Decimal) (Hex)
50 2304 900 -
75 1536 600 -
110 1047 417 0.026
134.5 857 359 0.058
150 768 300 -
300 384 180 -
600 192 oeo -
1200 96 060 -
1800 64 040 -
2000 58 03A 0.69
2400 48 030 -
3600 32 020 -
4800 24 018 -
7200 16 010 -
9600 12 ooe -

Baud Rate at 1.843 MHz

Asynchronous Adapter 9
Line Status Register (LSR)
This 8-bit register provides status information to the system unit's
microprocessor concerning the data transfer. The contents of the
line status register are indicated and described in the following
figure.

Hex Address 3FD

L:
Bit 7 6 5 4 3 2 o

I I D." R"dy [DR[

Overrun Error (OR)
Parity Error (PE)
L -_ _ _ _ _ _~ Framing Error (FE)
'------------1~ Break Interrupt (BI)
L...-_ _ _ _ _ _ _ _ _ _ Transmitter Holding
Register Empty
(THRE)
L...-_ _ _ _ _ _ _ _ _ _ _~ Tx Shift Register
Empty (TSRE)
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ =0
~
Line Status Register (lSR)

Bit 0: This bit is the receiver data ready (DR) indicator. Bit 0 is
set to logical 1 whenever a complete incoming character has been
received and transferred into the receiver buffer register. Bit 0
may be reset to a logical 0 either by the system unit's
microprocessor reading the data in the receiver buffer register or
by writing logical 0 into it from the system unit's microprocessor.

Bit 1: This bit is the overrun error (OE) indicator. Bit 1 indicates
that data in the receiver buffer register was not read by the
system unit's microprocessor before the next character was
transferred into the receiver buffer register, thereby destroying
the previous character. The DE indicator is reset whenever the
system unit's microprocessor reads the contents of the line status
register.

Bit 2: This bit is the parity error (PE) indicator. Bit 2 indicates
that the received data character does not have the correct even or
odd parity, as selected by the even-parity select bit. The PE bit is

10 Asynchronous Adapter
set to logical 1 upon detection of a parity error and is reset to
logical 0 whenever the system unit's microprocessor reads the
contents of the line status register.

Bit 3: This bit is the framing error (FE) indicator. Bit 3 indicates
that the received character did not have a valid stop bit. Bit 3 is
set to logical 1 whenever the stop bit following the last data bit or
parity is detected as a zero bit (spacing level).

Bit 4: This bit is the break interrupt (BI) indicator. Bit 4 is set to
logical 1 whenever the received data input is held in the spacing
(logical 0) state for longer than a full-word transmission time
(that is, the total time of start bit + data bits + parity + stop
bits).

Note: Bits 1 through 4 are the error conditions that produce a

receiver line status interrupt whenever any of the
corresponding conditions are detected.

Bit 5: This bit is the transmitter-holding-register-empty (THRE)

indicator. Bit 5 indicates that the INS8250 is ready to accept a
new character for transmission. In addition, this bit causes the
INS8250 to issue an interrupt to the system unit's microprocessor
when the transmit-holding-register-empty interrupt enable is set
high. The THRE bit is set to logical 1 when a character is
transferred from the transmitter holding register into the
transmitter shift register. The bit is reset to logical 0 concurrently
with the loading of the transmitter holding register by the system
unit's microprocessor.

Bit 6: This bit is the transmitter-shift-register-empty (TSRE)

indicator. Bit 6 is set to logical 1 whenever the transmitter shift
register is idle. It is reset to logical 0 upon a data transfer from
the transmitter holding register to the transmitter shift register.
Bit 6 is a read-only bit.

Bit 7: This bit is permanently set to logical O.

Asynchronous Adapter 11
Interrupt Identification Register (IIR)
The INS8250 has an on-chip interrupt capability that allows for
complete flexibility in interfacing to all the popular
microprocessors presently available. In order to provide minimum
software overhead during data character transfers, the INS8250
prioritizes interrupts into four levels: receiver line status (priority
1), received data ready (priority 2), transmitter holding register
empty (priority 3), and modem status (priority 4).

Information indicating that a prioritized interrupt is pending, and

the type of prioritized interrupt, is stored in the interrupt
identification register. Refer to the "Interrupt Control
Functions" table. The interrupt identification register (IIR) ,
when addressed during chip-select time, freezes the highest
priority interrupt pending, and no other interrupts are
acknowledged until that particular interrupt is serviced by the
system unit's microprocessor. The contents of the IIR are
indicated and described in the following figure.

Hex Address 3FA

Bit 7 6 543 2 o

II I~~0 If 'O<o,,"p,"oodlO9
Interrupt ID Bit (0)
Interrupt ID Bit (1)
=0
' - - - - - - - -... = 0
' - - - - - - - - -...... = 0
' - - - - - - - - - - -... = 0
' - - - - - - - - - - - -........ = 0

Interrupt Identification Register (UR)

Bit 0: This bit can be used in either a hard-wired prioritized or

polled environment to indicate whether an interrupt is pending,
and the IIR contents may be used as a pointer to the appropriate
interrupt service routine. When bit 0 is logical 1, no interrupt is
pending, and polling (if used) is continued.

12 Asynchronous Adapter
Bits 1 and 2: These two bits of the IIR are used to identify the
highest priority interrupt pending, as indicated in the "Interrupt
Control Functions" table.

Bits 3 through 7: These five bits of the IIR are always logical O.

Interrupt ID
Register Interrupt Set and Reset Functions
Priority Interrupt Interrupt Interrupt
Bit 2 Bit 1 Bit 0 Level Type Source Reset Control
0 0 1 - None None -

1 1 0 Highest Receiver Overrun Error Reading the

Line Status or Line Status
Parity Error Register
or
Framing Error
or
Break Interrupt
1 0 0 Second Received Receiver Reading the
Data Available Data Available Receiver Buffer
Register
0 1 0 Third Transmitter Transmitter Reading the IIR
Holding Holding Register (if
Register Register source of
Empty Empty interrupt)
or
Writing into the
Transmitter
Holding Register
0 0 0 Fourth Modem Clear to Send Reading the
Status or Modem Status
Data Set Ready Register
or
Ring Indicator
or
Received Line
Signal Direct

Interrupt Control Functions

Asynchronous Adapter 13
Interrupt Enable Register
This 8-bit register enables the four types of interrupt of the
INS8250 to separately activate the chip interrupt (INTRPT)
output signal. It is possible to totally disable the interrupt system
by resetting bits 0 through 3 of the interrupt enable register.
Similarly, by setting the appropriate bits of this register to logical
1, selected interrupts can be enabled. Disabling the interrupt
system inhibits the interrupt identification register and the active
(high) INTRPT output from the chip. All other system functions
operate in their normal manner, including the setting of the line
status and modem status registers. The contents of the interrupt
enable register are indicated and described in the following figure.

Hex Address 3F9 PLAB = 0

Bit 7 6 5 4 3 2 1 0

L: 1 = Enable Data
Available Interrupt
1 = Enable Tx Holding Register
Empty Interrupt
1 = Enable Receive Line
Status Interrupt
1 = Enable Modem Status
Interrupt
=0
=0
=0
=0

Interrupt Enable Register (lER)

Bit 0: This bit enables the received-data-available interrupt when

set to logical 1.

Bit 1: This bit enables the transmitter-holding-register-empty

interrupt when set tQ logical 1. .

Bit 2: This bit enables the receiver-line-status interrupt when set

to logical 1.

14 Asynchronous Adapter
Bit 3: This bit enables the modem-status interrupt when set to
logical 1.

Bits 4 through 7: These four bits are always logical O.

Modem Control Register

This 8-bit register controls the interface with the modem or data
set (or a peripheral device emulating a modem). The contents of
the modem control register are indicated and described as follows:

Hex Address 3FC

Bit 7 6 5 4 3 2 0

Data Terminal Ready (DTR)

Request to Send (RTS)
Out 1
Out 2
Loop
= 0
= 0
=0

Modem Control Register (MCR)

Bit 0: This bit controls the data terminal ready (-DTR) output.
When bit 0 is set to a high level, the -DTR output is forced to an
active low. When bit 0 is reset to low level, the -DTR output is
forced high.

Note: The -DTR output of the INS8250 may be applied to an

EIA inverting line driver (such as the DS1488) to obtain the
proper polarity input at the succeeding modem or data set.

Bit 1: This bit controls the request to send (-RTS) output. Bit 1
affects the -RTS output in a manner identical to that described
above for bit O.

Bit 2: This bit controls the output 1 (-OUT 1) signal, which is an

auxiliary user-designated output. Bit 2 affects the -OUT 1 output
in a manner identical to that described above for bit o.

Asynchronous Adapter 15
Bit 3: This bit controls the output 2 (-OUT 2) signal, which is an
auxiliary user-designated output. Bit 3 affects the -OUT 2 output
in a manner identical to that described above for bit O.

Bit 4: This bit provides a loopback feature for diagnostic testing

of the INS8250. When bit 4 is set to logical 1, the following
occurs: the transmitter serial output (SOUT) is set to the marking
(logical 1) state; the receiver serial input (SIN) is disconnected;
the output of the transmitter shift register is "looped back" into
the receiver shift register input; the four modem control inputs
(-CTS, -DSR, -RLSD, and -RI) are disconnected; and the four
modem control outputs (-DTR, -RTS, -OUT 1, and -OUT 2) are
internally connected to the four modem control inputs. In the
diagnostic mode, data that is transmitted is immediately received.
This feature allows the system unit's microprocessor to verify the
transmit-data and receive-data paths of the INS8250.

In the diagnostic mode, the receiver and transmitter interrupts are

fully operational. The modem control interrupts also are
operational, but the interrupts' sources are now the lower four
bits of the modem control register instead of the four modem
control inputs. The interrupts are still controlled by the interrupt
enable register.

The INS8250 interrupt system can be tested by writing into the

lower four bits of the modem status register. Setting any of these
bits to a logical 1 generates the appropriate interrupt (if enabled).
The resetting of these interrupts is the same as in normal INS8250
operation. To return to normal operation, the registers must be
reprogrammed for normal operation, then bit 4 of the modem
control register must be reset to logical O.

Bits 5 through 7: These bits are permanently set to logical O.

Modem Status Register

This 8-bit register provides the current state of the control lines
from the modem (or peripheral device) to the system unit's
microprocessor. In addition to this current-state information,
four bits of the modem status register provide change
information. These bits are set to logical 1 whenever a control

16 Asynchronous Adapter
input from the modem changes state. They are reset to logical 0
whenever the system unit's microprocessor reads the modem
status register.

The content of the modem status register is indicated and

described in the following figure.

Hex Address 3FE

Bit 7 6 543 2 o

Delta Clear to Send IDCTS)

Delta Data Set Ready IDDSR)
Trailing Edge Ring
Indicator ITERI)
Delta Rx Line Signal
Detect IDRLSD)
Clear to Send ICTS)
Data Set Ready IDSR)
Ring Indicator IRI)
Receive Line Signal
Detect IRLSD)

Modem Status Register (MSR)

Bit 0: This bit is the delta clear to send (DCTS) indicator. Bit 0
indicates that the -CTS input to the chip has changed state since
the last time it was read by the system unit's microprocessor.

Bit 1: This bit is the delta data set ready (DDSR) indicator. Bit 1
indicates that the -DSR input to the chip has changed state since
the last time it was read by the system unit's microprocessor.

Bit 2: This bit is the trailing edge of the ring indicator (TERI)
detector. Bit 2 indicates that the -RI input to the chip has changed
from an on (logical 1) to an off (logical 0) condition.

Bit 3: This bit is the delta received line signal detector (DRLSD)
indicator. Bit 3 indicates that the -RLSD input to the chip has
changed state.

Note: Whenever bit 0, 1,2, or 3 is set to logical 1, a modem

status interrupt is generated.

Asynchronous Adapter 17
Bit 4: This bit is the complement of the clear to send (-CTS)
input. If bit 4 (LOOP) of the modem control register (MCR) is
set to logicall, the bit is equivalent to RTS in the MCR.

Bit 5: This bit is the complement of the data set ready (-DSR)
input. If bit 4 of the MCR is set to logicall, the bit is equivalent
to DTR in the MCR.

Bit 6: This bit is the complement of the ring indicator (-RI) input.
If bit 4 of the MCR is set to logical l, the bit is equivalent to
OUT 1 in the MCR.

Bit 7: This bit is the complement of the received line signal detect
(-RLSD) input. If bit 4 of the MCR is set to logicall, the bit is
equivalent to OUT 2 of the MCR.

Receiver Buffer Register

The receiver buffer register contains the received character, which
is defined in the following figure.

Hex Address 3F8 DLAB = 0 Read Only

Bit 7 6 5 4 3 2 0

Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
' - - - - - - - - - _ DataBit5
Data Bit 6
L--_ _ _ _ _ _ _ _ _~ Data Bit 7

Receiver Buffer Register (RBR)

Bit 0 is the least-significant bit and is the first bit serially received.

18 Asynchronous Adapter
Transmitter Holding Register
The transmitter holding register contains the character to be
serially transmitted and is defined as follows:

Hex Address 3F8 DLAB = 0 Write Only

LS
Bit 7 6 5 4 3 2 o
I L Data Bit 0
L----: Data Bit 1
Data Bit 2
Data Bit 3
' - - - - - - - - - . Data Bit 4
L - -_ _ _ _ _ _ _ Data Bit 5

L -_ _ _ _ _ _ _ _- - . Data Bit 6

'--------------i~ Data Bit 7

Transmitter Holding Register (THR)

Bit 0 is the least-significant bit and is the first bit serially

transmitted.

Asynchronous Adapter 19
Selecting the Interface Format and Adapter
Address
The voltage or current-loop interface and adapter address are
selected by plugging in programmed shunt modules with the
locator dots up or down. See the following figure for the
configurations.

Module Position Module Position

for Primary for Alternate
Asynchronous
Adapter

D
D
o
D

Current Loop
Interface Socket
Dot Down

20 Asynchronous Adapter
If the adapter is to be installed in expansion slot 8 of an IBM
Personal Computer XT or IBM Portable Personal Computer, a
jumper is required on connector J 13.

Interrupts
One interrupt line is provided to the system. This interrupt is
IRQ4 for a primary adapter, or IRQ3 for an alternate adapter,
and is positive active. To allow the communications adapter to
send interrupts to the system, bit 3 of the modem control register
must be set to 1 (high). At this point, any interrupts allowed by
the interrupt enable register will cause an interrupt.

The data format will be as follows:

DO 01 02 03 05 06 07

Transmit Start Parity Slop

Data Marking Bit Bil Bils

Data bit 0 is the first bit to be transmitted or received. The

adapter automatically inserts the start bit, the correct parity bit if
programmed to do so, and the stop bit (1, 1-1/2, or 2 depending
on the command in the line-control register).

Asynchronous Adapter 21
22 Asynchronous Adapter
Interface

The communications adapter provides an EIA RS-232C-like

interface. One 25-pin, D-shell, male connector is provided to
attach various peripheral devices. In addition, a current-loop
interface is also located in this same connector. A jumper block is
provided to manually select either the voltage interface or the
current-loop interface.

The current-loop interface is provided to attach certain printers

provided by IBM that use this particular type of interface. IBM
recommends that the current loop not be used beyond a distance
of 15.3 meters (50 feet) as measured by the length of cable
between the two interconnected points.

Pin 18 + receive current loop data

Pin 25 - receive current loop return
Pin 11 - transmit current loop data
Pin 9 + transmit current loop return

+5 Vdc

I
T,,".m;' C;,"";, ~ 49.9 Ohm
~~~ '----------t.:~ Pin 9
Tx Data _ _ _ _~~v~hm _ Pin 11

+5 Vdc

IReceive Circuit
5.6 k-Ohm
OPTO Isolator

Pin 18 X)--- Rx Data

Pin 25

Current Loop Interface

Asynchronous Adapter 23
The voltage interface is a serial interface. It supports certain data
and control signals, as follows:

Pin 2 Transmitted Data

Pin 3 Received Data
Pin 4 Request to Send
Pin 5 Clear to Send
Pin 6 Data Set Ready
Pin 7 Signal Ground
Pin 8 Carrier Detect
Pin 20 Data Terminal Ready
Pin 22 Ring Indicator

The adapter converts these signals to or from TTL levels from or

to EIA voltage levels. These signals are sampled or generated by
the communications control chip. These signals can then be
sensed by the system software to determine the state of the
interface or peripheral device.

Voltage Interchange Information

Interface
Interchange Voltage Binary State Signal Condition Control Function
Positive Voltage = Binary (0) = Spacing = On
Negative Voltage = Binary (1 ) = Marking = Off

Invalid Levels
+ 15 Vdc

On Function
+3Vdc

OVdc Invalid Levels

-3Vdc

Off Function
-15 Vdc

Invalid Levels

The signal will be considered in the marking condition when the

voltage on the interchange circuit, measured at the interface

24 Asynchronous Adapter
point, is more negative than -3 Vdc with respect to signal ground.
The signal will be considered in the spacing condition when the
voltage is more positive than + 3 V dc with respect to signal
ground. The region between +3 Vdc and -3 Vdc is defined as the
transition region, and considered an invalid level. The voltage
that is more negative than -15 V dc or more positive than + 15
V dc will also be considered an invalid level.

During the transmission of data, the marking condition will be

used to denote the binary state 1, and the spacing condition will
be used to denote the binary state O.

For interface control circuits, the function is on when the voltage

is more positive than + 3 V dc with respect to signal ground and is
off when the voltage is more negative than -3 Vdc with respect to
signal ground.

INS8250 Functional Pin Description

The following describes the function of all INS8250 input/ output
pins. Some of these descriptions refer to internal circuits.

Note: In the following descriptions, a low represents a logical

0(0 Vdc nominal) and a high represents a logical 1 (+2.4.
V dc nominal).

Input Signals
Chip Select (CSO, CS1, -CS2), Pins 12-14: When CSO and CSI
are high and -CS2 is low, the chip is selected. Chip selection is
complete when the decoded chip select signal is latched with an
active (low) address strobe (-ADS) input. This enables
communications between the INS8250 and the system unit's
microprocessor.

Asynchronous Adapter 25
Data Input Strobe (DISTR, -DISTR), Pins 22 and 21: When
DISTR is high or -DISTR is low while the chip is selected, it
allows the system unit's microprocessor to read status information
or data from a selected register of the INS8250.

Note: Only an active DISTR or -DISTR input is required to

transfer data from the INS8250 during a read operation.
Therefore, tie either the DISTR input permanently low or the
-DISTR line input permanently high, if not used.

Data Output Strobe (DOSTR, -DOSTR), Pins 19 and 18: When

DOSTR is high or -DOSTR is low while the chip is selected, it
allows the system unit's microprocessor to write data or control
words into a selected register of the INS8250.

Note: Only an active DOSTR or -DOSTR input is required to

transfer data to the INS8250 during a write operation.
Therefore, tie either the DOSTR input permanently low or the
-DOSTR input permanently high, if not used.

Address Strobe (-ADS), Pin 25: When low, provides latching for
the register select (AO, AI, A2) and chip select (CSO, CSI, -CS2)
signals.

Note: An active -ADS input is required when the register

select (AO, AI, A2) signals are not stable for the duration of a
read or write operation. If not required, tie the ADS input
permanently low.

Register Select (AO, AI, A2), Pins 26-28: These three inputs are
used during a read or write operation to select an INS8250
register to read or write to as indicated in the following table.
Note that the state of the divisor latch access bit (DLAB), which
is the most significant bit of the line-control register, affects the
selection of certain INS8250 registers. The DLAB must be set
high by the system software to access the baud-rate generator
divisor latches.

26 Asynchronous Adapter
 DLAB A2 Al AO Register
0 0 0 0 Receiver Buffer (Read), Transmitter
Holding Register (Write)

0 0 0 1 Interrupt Enable
X 0 1 0 Interrupt Identification (Read Only)
X 0 1 1 Line Control
X 1 0 0 Modem Control
X 1 0 1 Line Status
X 1 1 0 Modem Control Status
X 1 1 1 None
1 0 0 0 Divisor Latch (Least Significant Bit)
1 0 0 1 Divisor Latch (Most Significant Bit)

Master Reset (MR), Pin 35: When high, clears all registers
(except the receiver buffer, transmitter holding, and divisor
latches), and the control logic of the INS8250. Also, the state of
various output signals (SOUT, INTRPT, -OUT 1, -OUT 2, -RTS,
-DTR) are affected by an active MR input. Refer to the
"Asynchronous Communications Reset Functions" table.

Receiver Clock (RCLK), Pin 9: This input is the 16 x baud-rate

clock for the receiver section of the chip.

Serial Input (SIN), Pin 10: Serial data input from the
communications link (peripheral device, modem, or data set).

Clear to Send (-CTS), Pin 36: The -CTS signal is a modem

control function input whose condition can be tested by the
system unit's microprocessor by reading bit 4 (CTS) of the
modem status register. Bit 0 (DCTS) of the modem status
register indicates whether the CTS input has changed state since
the previous reading of the modem status register.

Note: Whenever the CTS bit of the modem status register

changes state, an interrupt is generated if the modem status
interrupt is enabled.

Data Set Ready (-DSR), Pin 37: When low, indicates that the
modem or data set is ready to establish the communications link
and transfer data with the INS8250. The -DSR signal is a
modem-control function input whose condition can be tested by

Asynchronous Adapter 27
the system unit's microprocessor by reading bit 5 (DSR) of the
modem status register. Bit 1 (DDSR) of the modem status
register indicates whether the -DSR input has changed since the
previous reading of the modem status register.

Note: Whenever the DSR bit of the modem status register

changes state, an interrupt is generated if the modem status
interrupt is enabled.

Received Line Signal Detect (-RLSD), Pin 38: When low,

indicates that the data carrier had been detected by the modem or
data set. The -RLSD signal is a modem-control function input
whose condition can be tested by the system unit's
microprocessor by reading bit 7 (RLSD) of the modem status
register. Bit 3 (DRLSD) of the modem status register indicates
whether the RLSD input has changed state since the previous
reading of the modem status register.

Note: Whenever the RLSD bit of the modem status register

changes state, an interrupt is generated if the modem status
interrupt is enabled.

Ring Indicator (-RI), Pin 39: When low, indicates that a telephone
ringing signal has been received by the modem or data set. The
-RI signal is a modem-control function input whose condition can
be tested by the system unit's microprocessor by reading bit 6
(RI) of the modem status register. Bit 2 (TERI) of the modem
status register indicates whether the -RI input has changed from a
low to high state since the previous reading of the modem status
register.

Note: Whenever the RI bit of the modem status register

changes from a high to a low state, an interrupt is generated if
the modem status interrupt is enabled.

VCC, Pin 40: +5 Vdc supply.

VSS, Pin 20: Ground (0 Vdc) reference.

28 Asynchronous Adapter
Output Signals
Data Terminal Ready (-DTR), Pin 33: When low, informs the
modem or data set that the INS8250 is ready to communicate.
The -DTR output signal can be set to an active low by
programming bit 0 (DTR) of the modem control register to a high
level. The -DTR signal is set high upon a master reset operation.

Request to Send (-RTS), Pin 32: When low, informs the modem
or data set that the INS8250 is ready to transmit data. The -RTS
output signal can be set to an active low by programming bit 1
(RTS) of the modem control register to a high level. The -RTS
signal is set high upon a master reset operation.

Output 1 (-OUT 1), Pin 34: User-designated output that can be

set to an active low by programming bit 2 (-OUT 1) of the
modem control register to a high level. The -OUT 1 signal is set
high upon a master reset operation.

Output 2 (-OUT 2), Pin 31: User-designated output that can be

set to an active low by programming bit 3 (-OUT 2) of the
modem control register to a high level. The -OUT 2 signal is set
high upon a master reset operation.

Chip Select Out (CSOUT), Pin 24: When high, indicates that the
chip has been selected by active CSO, CS1, and -CS2 inputs. No
data transfer can be initiated until the CSOUT signal is a logical
1.

Driver Disable (DDIS), Pin 23: Goes low whenever the system
unit's microprocessor is reading data from the INS8250. A
high-level DDIS output can be used to disable an external
transceiver (if used between the system unit's microprocessor and
the INS8250 on the D7-DO data bus) at all times, except when
the system unit's microprocessor is reading data.

Baud Out (-BAUDOUT), Pin 15: 16 x clock signal for the

transmitter section of the INS8250. The clock rate is equal to the
main reference oscillator frequency divided by the specified
divisor in the baud-rate generator divisor latches. The
-BAUDOUT may also be used for the receiver section by typing
this output to the RCLK input of the chip.

Asynchronous Adapter 29
Interrupt (INTRPT), Pin 30: Goes high whenever anyone of the
following interrupt types has an active high condition and is
enabled through the interrupt enable register: receiver error flag,
received data available, transmitter holding register empty, or
modem status. The INTRPT signal is reset low upon the
appropriate interrupt service or a master reset operation.

Serial Output (SOUT), Pin 11: Composite serial data output to

the communications link (peripheral device, modem, or data set).
The SOUT signal is set to the marking (logical 1) state upon a
master reset operation.

Input/ Output Signals

Data Bus (07-DO), Pins 1-8: This bus comprises eight tri-state
input/ output lines. The bus provides bidirectional
communications between the INS8250 and the system unit's
microprocessor. Data, control words, and status information are
transferred through the D7-DO data bus.

External Clock Input/Output (XTAL1, XTAL2), Pins 16 and 17:

These two pins connect the main timing reference (crystal or
signal clock) to the INS8250.

30 Asynchronous Adapter
Specifications

The following page shows the connecter pin assignments and

specifications for the Asynchronous Communications Adapter.

Asynchronous Adapter 31
 25-Pin D-Shell connector

o
13 • • 25
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• • 14
•
0
Description Pin
NC 1
Transmitted Data 2
Received Data 3
Request to Send 4
Clear to Send 5
Data Set Ready 6
Signal Ground 7
Received Line Signal Detector 8
+ Transmit Current Loop Data 9
NC 10
- Transmit Current Loop Data 11
NC 12 Asynch ronous
External NC 13 Commu nications
Device NC 14 Adapter
NC 15 (RS-23 2C)

NC 16
NC 17
+ Receive Current Loop Data 18
NC 19
Data Terminal Ready 20
NC 21
Ring Indicator 22
NC 23
NC 24
- Receive Current Loop Return 25

Note: To avoid inducing voltage surges on interchange circuits, signals from

interchange circuits shall not be used to drive inductive devices, such as
relay coils.

Connector Specifications
32 Asynchronous Adapter
~~~~ 1~, 1" 1&3 1C4
BD1~ I:1D.D"F •. D47p F 1·047vF 1·047"F Ull
:~~ +12VDC
Its 1&6 -:- azso
B07 -12VOC
I·~"F l047 J.I~
BOZ RESET 35 MR

,., DO 2
LS245
18

• "" " ,
DO DO DO
ADa
"" 3 17

""
AD7 lHTRPT 3
ADfi
AD5
03
D4
5 D3
fi D4" 03 :4 D3
D4
'04 osos 7 os 04 13
os
'03
'"
D7
8
1~
os
H7
1 DlR Ul
05 12
~~ 11
I os
D7

ill
CS OUT 24

ODlS 23
Ne
Ne
8 U8 9 DlSTR 29 Ne
iOii ,LS DOSTR
ill 33
81' U3 OISTR
iOw
813

'A32
31
, 28 AD
Al 27
'29
Al'
".,N " "" RTS 32

-ENABLE
U2

"3

38

RECEIVE DATA

Asynchronous Communications Adapter (Sheet 1 of 1)

34 Asynchronous Adapter
Index

address strobe (-ADS) 26

baud out (-BAUD OUT) 29

baud-rate generator 7, 9
BI (break interrupt) 11
break interrupt (BI) 11

c
chip select (CSO, CSl, -CS2) 26
chip select (CSO, CSl, CS2) 25
chip select out (CSOUT) 29
clear to send (-CTS) 27
clear to send (CTS) 27
CTS (clear to send) 27
current-loop interface 20, 23

Index-l
D

data bus (D7-DO) 30

data input strobe (-DISTR) 26
data input strobe (DISTR) 26
data output strobe (-DOSTR) 26
data output strobe (DOSTR) 26
data ready (DR) 10
data set ready (-DSR) 27
data set ready (DSR) 27
data speed 9
data terminal ready (-DTR) 15,29
DCTS (delta clear to send) 17,27
DDSR (delta data set ready) 17, 27
delta clear to send (DCTS) 17,27
delta data set ready (DDSR) 17, 27
delta received line signal detect (DRLSD) 17
diagnostic capabilities 1, 16
diagnostic mode 16
divisor latch access bit (DLAB) 3, 7, 26
divisor latches 7
DLAB (divisor latch access bit) 7,26
DR (data ready) 10
driver disable (DDIS) 29
DRLSD (delta received line signal detect) 17

external clock input/output 30

F
FE (framing error) 11
framing error (FE) 11

Index-2
I

IIR (Interrupt Identification Register) 12, 14

input signals 25
-ADS (address strobe) 26
-CS2 (chip select) 25, 26
-CTS (clear to send) 27
-DISTR (data input strobe) 26
-DOSTR (data output strobe) 26
-DSR (data set ready) 27
-RI (ring indicator) 18,28
-RLSD (received line signal detect) 18,28
AO (register select) 3, 26
Al (register select) 3, 26
A2 (register select) 3, 26
CSO (chip select) 25, 26
CS 1 (chip select) 25, 26
DISTR (data input strobe) 26
DOSTR (data output strobe) 26
DSR (data set ready) 27
MR (master reset) 27
RCLK (receiver clock) 27
SIN (serial input) 16,27
VCC 28
VSS 28
XTAL1 (external clock input/output) 30
input/ output signals 30
D7-DO (data bus) 30
XTAL2 (external clock input/output) 30
INS8250 4, 25
INS8250 functional pin description 25
interface 23
interrupt (INTRPT) 14, 30
interrupt enable register 14
interrupt identification register (IIR) 12, 14
interrupts 21
INTRPT (interrupt) 14, 30

Index-3
L

line status register (LSR) 10

line-control register 5
logic diagrams 33
LSR (line status register) 10

master reset (MR) 27

modern control function 2
modern control inputs 16
modern control interrupts 16
modern control outputs 16
modern control register 15
modern status 12
modern status interrupt 15, 17, 27
modern status register 16,27,28
modes of operation 3

o
OE (overrun error) 10
output signals 29
-BAUDOUT (baud out) 29
-DTR (data terminal ready) 15,29
-OUT 1 (output 1) 15,29
-OUT 2 (output 2) 16,29
-RTS (request to send) 15, 29
CSOUT (chip select out) 29
DDIS (driver disable) 29
SOUT (serial output) 7,16,30
output 1 (-OUT 1) 15,29
output 2 (-OUT 2) 16,29
overrun error (OE) 10

Index-4
p

parity error (PE) 10

PE (parity error) 10
programmable baud-rate generator 7
programming considerations 3

R
received line signal detect (-RLSD) 18,28
receiver buffer register 18
receiver clock (RCLK) 27
register select (AO, AI, A2) 3,26
request to send (-RTS) 15,29
ring indicator (-RI) 28

s
selecting the adapter address 20
selecting the interface format and Adapter Address 20
serial input (SIN) 16, 27
serial output (SOUT) 7, 16, 30
specifications 31

Index-5
T

TERI (trailing edge of the ring indicator) 17

THRE (transmitter-holding-register-empty) 11, 12
trailing edge of the ring indicator (TERI) 17
transmitter holding register 12, 19
transmitter-holding-register-empty (THRE) 11, 12
transmitter-shift-register-empty (TSRE) 11
TSRE (transmitter-shift-register-empty) 11

v
voltage interchange information 24
voltage interface 24

Index-6
--- -
-
----- -
---
-
-----
---
-
---
---
,-
Personal Computer
Hardware Reference
Library

SeriaVParallel Adapter
Contents

Description .................................... 1
Serial Portion of the Adapter .................. 1
Parallel Portion of the Adapter ................ 20
Specifications ............................. 25
Logic Diagrams ................................ 27

iii
Notes:

iv
Description

The IBM Personal Computer AT Serial/Parallel Adapter provides

a parallel port and a serial port. It plugs into a system-board
expansion slot. All system-control signals and voltage
requirements are provided through a 2- by 31-position card edge
connector.

Serial Portion of the Adapter

The serial portion of the adapter is fully programmable and
supports asynchronous communications. It will add and remove
start, stop, and parity bits. A programmable baud-rate generator
allows operation from 50 baud to 9600 baud. Five-, six-, seven-
and eight-bit characters with 1, 1.5, or 2 stop bits are supported.
A prioritized interrupt system controls transmit, receive, error,
and line status as well as data-set interrupts.

The rear of the adapter has a 9-pin D-shell connector that is

classified as an RS-232C port. When the optional IBM
Communications Cable (9-Pin), which has a 9-pin D-shell
connector on one end and a 25-pin D-shell connector on the
other end, is connected to the adapter, the 25-pin end of the cable
has all the signals of a standard EIA RS-232C interface.

August 31, 1984

Personal Computer AT Serial/Parallel Adapter 1
The following figure is a block diagram of the serial portion of the
adapter.

Address
Address
Chip Select
.... Controller
Decode
Register - Asynchronous
Communications
Bus Select
Chip
Data Bus ...
Interrupt ...
I Oscillator
1.8432 MHz
I -.. ~

EIA
..
Receivers

- g·Pin
Connector
- EIA
Drivers
-
Serial Portion Block Diagram

The serial portion of the adapter has a controller that provides the
following functions:

• Adds or deletes standard, asynchronous-communications bits

to or from a serial data stream.

• Provides full, double buffering, which eliminates the need for

precise synchronization.

• Provides a programmable baud-rate generator.

• Provides modem controls (CTS, RTS, DSR, DTR, RI, and

CD).

August 31, 1984

2 Personal Computer AT Serial/Parallel Adapter
Communications Application
The serial output port may be addressed as either communications
port 1 or communications port 2 as defined by jumper 11 (see the
following figure). In this section hex addresses begin with an X
which can be either a 3 for communications port 1 (interrupt level
4) or a 2 for communications port 2 (interrupt level 3).

Port 2

The data format will be as follows:

DO 01 02 03 04 05 06 07

~~~~~~~~
Marking Start I Parity Stop
Bit IIIIIIII Bit Bit

Bit 0 is the first data bit to be sent or received. The controller

automatically inserts the start bit, the correct parity bit (if
programmed to do so), and the stop bit (1, 1.5, or 2, depending
on the command in the line-control register).

August 31, 1984

Personal Computer AT Serial/Parallel Adapter 3
Controller Specifications
The following describes the function of controller input/output
signals.

Input Signals

-Clear to Send: (-CTS), Pin 36-The '-CTS' signal is a

modem-control function input, the condition of which can be
tested by the processor by reading bit 4 (-CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register
indicates if the '-CTS' input has changed state since the previous
reading.

Note: Whenever the CTS bit of the modem status register

changes state, an interrupt is generated if the modem-status
interrupt is enabled.

-Data Set Ready: (-DSR), Pin 37-When low, indicates the

modem or data set is ready to establish the communications link
and transfer data with the controller. The '-DSR' signal is a
modem-control function input, the condition of which can be
tested by the processor reading bit 5 (-DSR) of the modem status
register. Bit 1 (DDSR) of the modem status register indicates if
the '-DSR' input has changed since the previous reading.

Note: Whenever the DSR bit of the modem status register

changes state, an interrupt is generated if the modem-status
interrupt is enabled.

-Data Carrier Detect: (-DCD), Pin 38-When low, indicates

the modem or data set detected a data carrier. The '-DCD '
signal is a modem-control function input, the condition of which
can be tested by the processor reading bit 7 (-DCD) of the
modem status register. Bit 3 (DDCD) of the modem status
register indicates if the '-DCD' input has changed state since the
previous reading.

Note: Whenever the DCD bit of the modem status register

changes state, an interrupt is generated if the modem status
interrupt is enabled.

August 31, 1984

4 Personal Computer AT Serial/Parallel Adapter
-Ring Indicator: (-RI), Pin 39-When low, indicates the modem
or data set detected a telephone ringing signal. The '-RI' signal
is a modem-control function input, the condition of which can be
tested by the processor reading bit 6 (-RI) of the modem status
register. Bit 2 (TERI) of the modem status register indicates if
the '-RI' input has changed from an active to an inactive state
since the previous reading.

Note: Whenever the RI bit of the modem status register

changes from an inactive to an active state, an interrupt is
generated if the modem-status interrupt is enabled.

VCC Pin 40-+5 Vdc supply

VSS Pin 20-Ground (0 Vdc) reference

Output Signals

-Data Terminal Ready: (-DTR), Pin 33-When active, informs

the modem or data set that the controller is ready to
communicate. The '-DTR' output signal can be set to an active
level by programming bit 0 (-DTR) of the modem control register
to an active level. The '-DTR' signal is set inactive upon a
master reset operation.

-Request to Send: (-RTS), Pin 32-When active, informs the

modem or data set that the controller is ready to send data. The
'-RTS' output signal can be set to an active level by
programming bit 1 (-RTS) of the modem control register to an
active level. The '-R TS' signal is set inactive upon a master reset
operation.

-Output 1: (-OUT 1), Pin 34-User-designated output that can

be set to an active level by programming bit 2 (-OUT 1) of the
modem control register to an inactive level. The '-OUT 1 ' signal
is set inactive upon a master reset operation. Pin 34 is connected
to an active source.

-Output 2: (-OUT 2), Pin 31-User-designated output that can

be set to an active level by programming bit 3 (-OUT 2) of the
modem control register to an inactive level. The '-OUT 2' signal
is set inactive upon a master reset operation. Pin 31 controls
interrupts to the system.
August 31, 1984
Personal Computer AT Serial/Parallel Adapter 5
Controller-Accessible Registers

The controller has a number of accessible registers. The system

programmer may gain access to or control any of the controller
registers through the microprocessor. These registers are used to
control the controller's operations and to transmit and receive
data. The X in the register address determines the the port
selected; 3 is for port 1 and 2 is for port 2.

Specific registers are selected according to the following figure:

I/O Address Register Selected DLAB State

XF8 TX Buffer o (Write)
XF8 RX Buffer o (Read)
XF8 Divisor Latch LSB 1
XF9 Divisor Latch MSB 1
XF9 Interrupt Enable Register 0
XFA Interrupt Identification Register
XFB Line Control Register
XFC Modem Control Register
XFD Line Status Register
XFE Modem Status Register
XFF Reserved
Controller-Accessible Registers

Transmitter Holding Register (hex XF8): The transmitter

holding register (THR) contains the character to be sent.

Transmitter Holding Register (hex XF8)

lS
Bit 7 6 5 4 3 2 1 0

IL Data BitO
L=--: Data Bit 1
Data Bit 2
Data Bit 3
L--_ _ _ _~ Data Bit 4

~-----_ Data Bit 5

~------_ Data Bit 6
L--_ _ _ _ _ _ _ _ _ Data Bit 7

Transmitter Holding Register

Bit 0 is the least-significant bit and the first bit sent serially.

August 31, 1984

6 Personal Computer AT Serial/Parallel Adapter
Receiver Buffer Register (hex XF8): The receiver buffer
register (RBR) contains the received character.

Receiver Buffer Register (hex XF8)

lS
Bit 7 6 5 4 3 2 1 0

I L Data BitO
~DataBit1
Data Bit 2
Data Bit 3
' - - - - - -. . Data Bit 4
' - - - - - - -. . Data Bit 5
'--------~ Data Bit 6
'---------~ Data Bit 7

Receiver Buffer Register

Bit 0 is the least-significant bit and the first bit received serially.

Programmable Baud-Rate Generator: The controller has a

programmable baud-rate generator that can divide the clock input
0.8432 MHz) by any divisor from 1 to 655,535 or 216_1. The
output frequency of the baud-rate generator is the baud rate
multiplied by 16. Two 8-bit latches store the divisor in a 16-bit
binary format. These divisor latches must be loaded during setup
to ensure desired operation of the baud-rate generator. When
either of the divisor latches is loaded, a 16-bit baud counter is
immediately loaded. This prevents long counts on the first load.

Divisor Latch LSB (hex XF8)

Divisor Latch Least Significant Bit (hex XF8)

lS
Bit 7 6 5 4 3 2 1 0

I LBitO
~Bit1
Bit 2
Bit 3
' - - - - - -. . Bit 4
'-------~ Bit 5
'--------~ Bit 6
'---------~ Bit 7

Divisor Latch Least Significant Bit

August 31, 1984

Personal Computer AT Serial/Parallel Adapter 7
Divisor Latch MSB (hex XF9)

Divisor Latch Most Significant Bit (hex XF9)

Bit 7 6 5 4 3 2 1 0

~
1~BitO
L..==Bit1
Bit 2
Bit 3
' - - - - - - - - Bit 4
' - - - - - - - - Bit 5
L -_ _ _ _ _ _ _ Bit 6
L -_ _ _ _ _ _ _ _ Bit 7

Divisor Latch Most Significant Bit

Interrupt Enable Register (hex XF9): This 8-bit register allows

the four types of controller interrupts to separately activate the
, chip-interrupt' (lNTRPT) output signal. The interrupt system
can be totally disabled by resetting bits 0 through 3 of the
interrupt enable register (IER). Similarly, by setting the
appropriate bits of this register to logical 1, selected interrupts can
be enabled. Disabling the interrupt system inhibits the 'IER' and
the active 'INTRPT' output from the chip. All other system
functions operate normally, including the setting of the line-status
and modem-status registers.

Interrupt Enable Register (hex XF9)

Bit 7 6 5

III
4 3 2 1 0

~ ~ "oc""oo""",,,""'. "',,'""
Transmitler-H oldi ng- Register-Empty
Receiver-Line-Status Interrupt
Modem-Status Interrupt
• =0
=0
=0
=0

Interrupt Enable Register

Bit 0 When set to logical 1, enables the

received-data-available interrupt.

August 31, 1984

8 Personal Computer AT Serial/Parallel Adapter
Bit 1 When set to logical 1, enables the
transmitter-holding-register-empty interrupt.

Bit 2 When set to logical 1, enables the receiver-line-status

interrupt.

Bit 3 When set to logical 1, enables the modem-status

interrupt.

Bits 4-7 These four bits are always logical O.

Interrupt Identification Register (hex XFA): The controller has

an on-chip interrupt capability that makes communications
possible with all of the currently popular microprocessors. In
order to minimize programming overhead during data character
transfers, the controller prioritizes interrupts into four levels:
receiver-line-status (priority 1), received-data-available (priority
2), transmitter-holding-register-empty (priority 3), and modem
status (priority 4).

Information about a pending prioritized interrupt is stored in the

interrupt identification register (IIR). (See the figure "Interrupt
Control Functions," later.) The IIR, when addressed during
chip-select time, stops the pending interrupt with the highest
priority, no other interrupts are acknowledged until the processor
services that interrupt.

Interrupt Identification Register (hex XFA)

Bit 7 6 5 4 3 2 1 0

L ~
III~ 0Interrupt
;"""""" eo",;""
ID Bit 0
Interrupt ID Bit 1
=0
L - - - - -... =o
~----------~=O
L...-_ _ _ _ _ _ _. . =0

' - - - - - - - - -.. =0

Interrupt Identification Register

Bit 0 This bit can be used in either hard-wired, prioritized,

or polled conditions to indicate if an interrupt is
pending. When bit 0 is logical 0, an interrupt is
pending, and the IIR contents may be used as a
August 31, 1984
Personal Computer AT Serial/ParaDel Adapter 9
 pointer to the appropriate interrupt service routine.
When bit 0 is logical 1, no interrupt is pending, and
polling (if used) continues.

Bits 1-2 These two bits identify the pending interrupt that has
the highest priority, as shown in the following figure:

Interrupt
10 Interrupt Set And Reset Functions
Register

Bit Bit Bit Priority Interrupt Interrupt Interrupt

2 1 0 Level Type Source Reset Control

0 0 0 - None None -

1 1 0 Highest Receiver Overrun Error Reading the Line

Line or Status Register
Status Parity Error
or
Framing Error
or
Break Interrupt

1 0 0 Second Received Receiver Data Reading the Receiver

Data Available Buffer Register
Available

0 1 0 Third Transmitter Transmitter Reading the IIR

Holding Holding (if source of interrupt)
Register Register Empty or writing into the
Empty THR

0 0 0 Fourth Modem Clear to Send Reading the Modem

Status or Status Register
Data Set Ready
or
Ring Indicator
or
Received Line
Signal Detect

Interrupt Priority

Bits 3-7 These five bits are always logical O.

Line-Control Register (hex XFB): The system programmer

specifies the format of the asynchronous data communications
exchange through the line control register. In addition to

August 31, 1984

10 Personal Computer AT Serial/Parallel Adapter
controlling the format, the programmer may retrieve the contents
of the line control register for inspection. This feature simplifies
system programming and eliminates the need to store line
characteristics separately in system memory.

Line Control Register (hex XFB)

Bit 7 6 5 4 3 2 1 0

III I~ Wo,dL"""",,,ct B,<o

Word Length Select Bit 1
Number of Stop Bits
Parity Enable
L...-_ _ _ _. - Even Parity Select
L...-_ _ _ _ _. - Stuck Parity
L...-_ _ _ _ _ _. - Set Break

L...-_ _ _ _ _ _----,~ Divisor Latch Access Bit

Line Control Register

Bits 0, 1 These two bits specify the number of bits in each

serial character that is sent or received. The
encoding of bits 0 and 1 is as follows:

BitO Bit 1 Word Length (Bits)

0 0 5
0 1 6
1 0 7
1 1 8
Word Length

Bit 2 This bit specifies the number of stop bits in each

serial character that is sent or received. If bit 2 is a
logical 0, one stop bit is generated or checked in the
data sent or received. If bit 2 is logical 1 when a
5-bit word length is selected through bits 0 and 1,
1-1/2 stop bits are generated or checked. If bit 2 is
logical 1 when either a 6-, 7-, or 8-bit word length
is selected, two stop bits are generated or checked.

Wt 3 This bit is the parity-enable bit. When bit 3 is

logical 1, a parity bit is generated (transmit data) or
checked (receive data) between the last data word

August 31, 1984

Personal Computer AT Serial/Parallel Adapter 11
 and stop bit of the serial data. (The parity bit is
used to produce an even or odd number of 1's when
the data-word bits and parity bit are summed.)

Bit 4 This bit is the even-parity-select bit. When bit 3 is

a logical 1 and bit 4 is a logical 0, an odd number of
logical 1's are sent or checked in the data word bits
and parity bit. When both bit 3 and bit 4 are a
logical 1, an even number of bits are sent or
checked.

Bit 5 This bit is the stuck-parity bit. When bit 3 is a

logical 1 and bit 5 is a logical 1, the parity bit is sent
and then detected by the receiver as a logical 0, if
bit 4 is a logical 1, or as a logical 1 if bit 4 is a
10gica10.

Bit 6 This bit is the set-break control bit. When bit 6 is

set to a logical 1, the serial output (SQUT) is forced
to the spacing (logical 0) state and remains there
regardless of other transmitter activity. The
set-break is disabled by setting bit 6 to logical O.
This feature enables the microprocessor to select a
specific terminal in a computer communications
system.

Bit 7 This bit is the divisor-latch access bit (DLAB). It

must be set high (logical 1) to gain access to the
divisor latches of the baud-rate generator during a
read or write operation. It must be set low (logical
0) to gain access to the receiver buffer, the
transmitter holding register, or the interrupt enable
register.

August 31, 1984

12 Personal Computer AT Serial/Parallel Adapter
Modem Control Register (hex XFC): This 8-bit register
controls the data exchange with the modem or data set (an
external device acting as a modem).

Modem Control Register (hex XFC)

Bit 7 6 5 4 3 2 1 0

IIIL--=:
1- ~ D." T'~;'" RM~
Request to Send
Out 1
Out2
' - - - - - - . - Loop
' - - - - - - - . - =0
' - - - - - - - _ =0
' - - - - - - - - - =0

Modem Control Register

Bit 0 This bit controls the '-data terminal ready' (-DTR)

output. When bit 0 is set to logical 1, the -DTR
output is forced active. When bit 0 is reset to logical
0, the '-DTR' output is forced inactive.
Bit 1 This bit controls the '-request-to-send' (-RTS)
output. Bit 1 affects the '-RTS' output in the same
way bit 0 affects the '-DTR' output.
Bit 2 This bit controls the '-Output I' (-OUT 1) signal,
which is a spare the programmer can use. Bit 2
affects the '-OUT 1 ' output in the same way bit 0
affects the '-DTR' output.
Bit 3 This bit controls the '-Output 2' (-OUT 2) signal,
which is a spare the programmer can use. Bit 3
affects the '-OUT 2' output in the same way bit 0
affects the '-DTR' output.
Bit 4 This bit provides a loop back feature for diagnostic
testing of the controller. When bit 4 is set to logical
1, the following occur: the 'transmitter serial output'
(SOUT) is set to the active state; the 'receiver serial
input' (SIN) is disconnected; the output of the
transmitter shift register is "looped back" to the
receiver shift register input; the four modem-control
inputs (' -CTS', '-DSR', '-RLSD', and '-RI') are

August 31, 1984

Personal Computer AT Seriai/ParaDel Adapter 13
 disconnected; and the four modem-control outputs
( '-DTR " '-RTS', '-OUT I' and '-OUT 2') are
internally connected to the four modem control
inputs. In the diagnostic mode, data sent is
immediately received. This feature allows the
processor to verify the transmit- and receive-data
paths of the controller.

In the diagnostic mode, the receiver and transmitter

interrupts are fully operational, as are the
modem-control interrupts. But the interrupts'
sources are now the lower four bits of the modem
control register (MCR) instead of the four
modem-control inputs. The interrupts are still
controlled by the interrupt enable register.

The controller's interrupt system can be tested by

writing to the lower six bits of the line status register
and the lower four bits of the modem status register.
Setting any of these bits to logical 1 generates the
appropriate interrupt (if enabled). Resetting these
interrupts is the same as for normal controller
operation. To return to normal operation, the
registers must be reprogrammed for normal
operation, and then bit 4 of the MCR must be reset
to logical O.

Bits 5-7 These bits are permanently set to logical O.

August 31, 1984

14 Personal Computer AT Seriai/ParaDel Adapter
Line Status Register (hex XFD): This 8-bit register provides
the processor with status information about the data transfer.

line Status Register (hex XFD)

Bit 7 6 5 4 3 2 1 0

~
I L Data Ready
L-==. Overrun Error
Parity Error
Framing Error
I-.-_ _ _ _~ Break Interrupt
1-.-_ _ _ _ _. . Transmitter Holding Register Empty

'--------~ Tx Shift Register Empty

I-.--------~ =0

Line Status Register

Bit 0 This bit is the receiver data ready (DR) indicator. It

is set to logical 1 whenever a complete incoming
character has been received and transferred into the
receiver buffer register. Bit 0 may be reset to logical
o by reading the data in the receiver buffer register.
Bit 1 This bit is the overrun error (OE) indicator. It
indicates that data in the receiver's buffer register
was not read by the processor before the next
character was transferred into the register, thereby
destroying the previous character. The OE indicator
is reset whenever the processor reads the contents of
the line status register.

Bit 2 This bit is the parity error (PE) indicator and

indicates the received data character does not have
the correct even or odd parity, as selected by the
even-parity-select bit. The PE bit is set to logical 1
upon detection of a parity error, and is reset to
logical 0 whenever the processor reads the contents
of the line status register.

Bit 3 This bit is the framing error (FE) indicator. It

indicates the received character did not have a valid
stop bit. Bit 3 is set to logical 1 whenever the stop
bit following the last data bit or parity bit is detected
as a zero bit (spacing level).

August 31, 1984

Personal Computer AT Serial/Parallel Adapter 15
Bit 4 This bit is the break interrupt (BI) indicator. It is set
to logical 1 whenever the received data input is held
in the spacing state (logical 0) for longer than a full
word transmission time (that is, the total time of
start bit + data bits + parity bits + stop bits).

Note: Bits 1 through 4 are error conditions that

produce a receiver line-status interrupt
whenever any of the corresponding conditions
are detected.

Bit 5 This bit is the transmitter holding register empty

(THRE) indicator. It indicates the controller is
ready to accept a new character for transmission. In
addition, this bit causes the controller to issue an
interrupt to the processor when the THRE interrupt
enable is set active. The THRE bit is set to logical 1
when a character is transferred from the transmitter
holding register into the transmitter shift register. It
is reset to logical 0 when the processor loads the
transmitter holding register.

Bit 6 This bit is the transmitter empty (TEMT) indicator.

It is set to logical 1 whenever the transmitter holding
register (THR) and the transmitter shift register
(TSR) are both empty. It is reset to logical 0 if THR
or TSR contain a data character.

Bit 7 This bit is permanently set to logical O.

August 31, 1984

16 Personal Computer AT Serial/Parallel Adapter
Modem Status Register (hex XFE): The 8-bit MSR provides
the current state of the control lines from the modem (or external
device) to the processor. In addition, four bits of the MSR
provide change information. These four bits are set to logical 1

°
whenever a control input from the modem changes state. They
are reset to logical whenever the processor reads this register.

Modem Status Register (hex XFE)

Bit 7 6 5 4 3 2 1 0

I ~I
L~ 0.'" c,." " Seo'
L==:. Delta Data Set Ready
Trailing Edge Ring Indicator
Delta Data Carrier Detect
' - - - - - - - - Clear to Send
' - - - - - - - _ Data Set Ready
L..-_ _ _ _ _ _... Ring Indicator

' - - - - - - - - - . _ Data Carrier Detect

Modem Status Register

Bit 0 This bit is the delta clear-to-send (DCTS) indicator.

It indicates the '-CTS' input to the chip has changed
state since the last time it was read by the processor.
Bit 1 This bit is the delta data-set-ready (DDSR)
indicator. It indicates the '-DSR' input to the chip
has changed state since the last time it was read by
the processor.
Bit 2 This bit is the trailing-edge ring-indicator (TERI)
detector. It indicates the' -RI' input to the chip has
changed from an active condition to an inactive
condition.
Bit 3 This bit is the delta data-carrier-detect (DDCD)
indicator. It indicates the '-DCD' input to the chip
has changed state.
Note: Whenever bit 0, 1, 2, or 3 is set to a
logical 1, a modem status interrupt is generated.
Bit 4 This bit is the opposite of the '-clear-to-send'
(-CTS) input. If bit 4 of the MCR loop is set to a
logical 1, this bit is equivalent to RTS of the MCR.

August 31, 1984

Personal Computer AT Serial/Parallel Adapter 17
Bit 5 This bit is the opposite of the I -data-set-ready I
(-DSR) input. If bit 4 of the MeR is set to a logical
1, this bit is equivalent to DTR of the MeR.

Bit 6 This bit is the opposite of the -ring-indicator (-RI)

I I

input. If bit 4 of the MeR is set to a logical 1, this

bit is equivalent to OUT 1 of the MeR.

Bit 7 This bit is the opposite of the -data-carrier-detect

I I

(-DeD) input. If bit 4 of the MeR is set to a logical

1, this bit is equivalent to OUT 2 of the MeR.

August 31, 1984

18 Personal Computer AT Serial/Parallel Adapter
Pin Assignment for Serial Port
The following figure shows the pin assignments for the serial port
in a communications environment.

- Carrier Detect 1 -
Receive Data 2
Transmit Data 3
Data Terminal Ready 4
Exter nal Signal Ground 5 Ser ial
Devie e Par allel
Data Set Ready 6 Ada pter
Request To Send 7
Clear To Send 8
Ring Indicator 9

- -

August 31, 1984

Personal Computer AT Serial/Parallel Adapter 19
Parallel Portion of the Adapter
The parallel portion of the adapter makes possible the attachment
of various devices that accept eight bits of parallel data at
standard TTL levels. The rear of the adapter has a 25-pin,
D-shell connector. This port may be addressed as either parallel
port 1 or 2. The port address is determined by the position of
jumper J2, as shown in the following figure.

August 31, 1984

20 Personal Computer AT Serial/Parallel Adapter
The following figure is a block diagram of the parallel portion of
the adapter.

BuHer
Address
Bus .
Address
Decode .. Control
Signals

.. Interrupt

Data Data
Data
Bus
.. ,..... Output
BuHer 25-Pln 0
I--

~
Wrap
BuHer ~

- Connector

Control
Output
-.. . Control Wrap
and ~
~ BuHer Signal Input

Parallel Portion Block Diagram

Printer Application
The following discusses the use of the parallel portion of the
adapter to connect to a parallel printer. Hexadecimal addresses in
this section begin with an X, which is replaced with a 3 to indicate
port 1, or a 2 to indicate port 2.

Data Latch (hex X78, X7C)

Writing to this address causes data to be stored in the printer's

data buffer. Reading this address sends the contents of the
printer's data buffer to the system microprocessor.

Printer Controls (hex X7 A, X7E)

Printer control signals are stored at this address to be read by the

system microprocessor. The following are bit definitions for this
byte.

August 31, 1984

Personal Computer AT Serial/Parallel Adapter 21
Bit 7 Not used

Bit 6 Not used

Bit 5 Not used

Bit 4 +IRQ Enable-A logicall in this position allows an

interrupt to occur when '-ACK' changes from active to
inactive.

Bit 3 +SLCT IN-A logicall in this bit position selects the

printer.

Bit 2 -INIT-A logical 0 starts the printer (50-microsecond

pulse, minimum).

Bit 1 +AUTO FD XT-A logicall causes the printer to

line-feed after a line is printed.

Bit 0 +STROBE-A 0.5-microsecond minimum, high, active

pulse clocks data into the printer. Valid data must be
present for a minimum of 0.5 microsecond before and
after the strobe pulse.

Printer Status - (hex X79, X7D)

Printer status is stored at this address to be read by the

microprocessor. The following are bit definitions for this byte.

Bit 7 -BUSY-When this signal is active, the printer is busy

and cannot accept data. It may become active during
data entry, while the printer is offline, during printing,
when the print head is changing positions, or while in an
error state.

Bit 6 -ACK-This bit represents the current state of the

printer's '-ACK' signal. A 0 means the printer has
received the character and is ready to accept another.
Normally, this signal will be active for approximately 5
microseconds before' -BUSY' stops.

August 31, 1984

22 Personal Computer AT Serial/ParaUel Adapter
Bit 5 + PE-A logical 1 means the printer has detected the
end of paper.

Bit 4 + SLCT-A logical 1 means the printer is selected.

Bit 3 -Error-A logical 0 means the printer has encountered
an error condition.

Bit 2 Unused.

Bit 1 Unused.

Bit 0 Unused.

August 31, 1984

Personal Computer AT Serial/ParaDel Adapter 23
Parallel Interface
The adapter has a 25-pin, D-shell connector at the rear of the
adapter. The following figure shows the signals and their pin
assignments. Typical printer input signals also are shown.

o
~ 0

o
o 0

13 ~ 0 25

- -Strobe 1
-
Data Bit 0 2
Data Bit 1 3
Data Bit 2 4
Data Bit 3 5
Data Bit 4 6
Data Bit 5 7
Data Bit 6 8
Data Bit 7 9 Seri al
Exte rnal
-ACK 10 Parallel
Devic e
Ada pter
-BUSY 11
PE 12
SLCT 13
-AUTO FEED XT 14
-ERROR 15
-INIT 16
-SLCT IN 17
Ground 18·25

- ----
August 31, 1984
24 Personal Computer AT Serial/Parallel Adapter
Specifications
The following figures list characteristics of the output driver.

Sink current 24mA Max

Sou rce Current -2.6 mA Max
High- Level Output Voltage 2.4 Vdc Min
Low-Level Output Voltage 0.5 Vdc Max
Parallel Data and Processor IRQ

Sink Current 16 mA Max

Source Current 0.55 mA Max
High Level Output Voltage 5Vdc Minus Pull-Up
Low Level Output VoltaQe 0.4 Vdc Max
Parallel Control

Sink Current 24mA Max

Source Current -15 mA Max
High Level Output Voltage 2.0 Vdc Min
Low Level Output Voltage 0.5 Vdc Max
Parallel Processor Interface (Except IRQ)

The following are the specifications for the serial interface.

Function Condition

On Spacing condition (binary 0, positive voltage).

Off Marking condition (binary 1, negative voltage).

Voltage Function
Above +15 Vdc Invalid
+3 Vdc to +15 Vdc On
-3 Vdc to +3 Vdc Invalid
-3 Vdc to -15 Vdc Off
Below -15Vdc Invalid

Serial Port Functions

August 31, 1984

Personal Computer AT Serial/Parallel Adapter 25
Notes:

August 31, 1984

26 Personal Computer AT Serial/Parallel Adapter
 >-
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RECEIVE DATA

Serial/Printer Adapter (Sheet 3 of 3)

Notes:

August 31, 1984

30 Personal Computer AT Serial/Parallel Adapter
----
-=_--
...... -- --- Personal Computer
-:S~5: Hardware Reference
Library

mMBinary
Synchronous
Communications
Adapter

6361499
ii
Contents

Description .................................... 1
Programming Considerations ...................... 3
Typical Programming Sequence ................ 3
USART Programming ........................ 5
Interface ...................................... 9
Specifications ................................. 11
Logic Diagrams ................................ 13

iii
iv
Description

The IBM Binary Synchronous Communications (BSC) Adapter

provides an RS-232C-compatible communications interface for
the IBM Personal Computer family of products. All system
control, voltage, and data signals are provided through a 2- by
31-position card-edge connector. External interface is in the
form of Electronic Industries Association (EIA) drivers and
receivers connected to an RS-232C, standard 25-pin, D-shell
connector.

The adapter is programmed to operate in a binary synchronous

mode. Maximum transmission rate is 9600 bits per second (bps).
The main feature of the adapter is an Intel 8251A Universal
Synchronous/ Asynchronous Receiver/Transmitter (USART).
An Intel 8255A-5 Programmable Peripheral Interface (PPI) also
is used for expanded modem operation, and an Intel 8253-5
Programmable Interval Timer provides time-outs and generates
interrupts.

The following is a block diagram of the BSC adapter.

Timer
EIA
~ Drivers/
8253
Receivers
,-- Data
Syste m Comm unications
Bus Equipm ent
'I ,-'I
~
Data
I
Bus Z~ 14-- I I
I I :;:; USART
I I
I I Control v: I I
I
I I
I ~ t-: 8251A_
I
I
I
I
I

E=
I I v:f-- I I
I I v:; Programmable I
I I
I
L.J
Address
~n
~
''';ph",'
Interface
L.J
I

~
[;j r-----
[;j
= 14--- L-

'////////;) 8255A5

Bse Adapter Block Diagram

BSC Adapter 1
2 BSe Adapter
Programming Considerations

Before starting data transmission or reception, the system unit

programs the BSC adapter to define control and gating ports,
timer functions and counts, and the communications environment.

Typical Programming Sequence

The 8255A-5 Programmable Peripheral Interface (PPI) is set for
the proper mode by selecting address hex 3A3 and writing the
control word. This defines port A as an input, port B as an output
for modem control and gating, and port C for 4-bit input and
4-bit output. An output to port C sets the adapter to the wrap
mode, disallows interrupts, and gates external clocks (address =
hex 3A2, data = hex OD). The adapter is now isolated from the
communication interface, and setup continues.

Bit 4 of the PPI's port B brings the USART reset pin high, holds
it, then drops it. This resets the internal registers of the USART.

Bse Adapter 3
The PPI's port assignments are as follows:

8255 Port A Assignments Address: hex 3AO for BSe

Input Port hex 380 for Alternate BSe

Bit 7 6 5 4 3 2 1 0

II~
o = Ring Indicate is on from Interface
o = Data Carrier Defect is on from Interface
Oscillating = Transmit Clock Active
o = Clear-to-Send is on from Interface
Oscillating = Receive Clock Active
1 = TxRDY Active
1 = Timer 2 Output Active
1 = Timer 1 Output Active

8255 Port B Assignments Address: hex 3A 1 for BSe

Output Port hex 381 for Alternate BSe

Bit 7 6 5 4 3 2 1 0

II~~
o = Turn on Data Signal Rate Selector
o = Turn on Select Standby
o = Turn on Test
1 = Not Used
1 = Reset 8251A
1 = Gate Timer 2
1 = Gate Timer 1
1 = Gate Timers 1 and 2 to Interrupt Level 4

8255 Port e Assignments Address: hex 3A2 for BSe

hex 382 for Alternate BSe

Bit 7 6 5 4 3 2 1 0

II~~
1 = Gate Internal Clock (Output Bit)
1 = Gate External Clock (Output Bit)
1 = Electronic Wrap (Output Bit)
o = Enable Timer 1 and 2, Interrupt 6 and
Receive Interrupt 3
Oscillating = Receive Data (Input Bit)
Oscillating = Timer 0 Output (Input Bit)
o = Test Indicate Active (Input Bit)
o = BSC Adapter

The USART uses the 8253-5 Programmable Interval Timer (PIT)

in the synchronous mode for inactivity time-outs to interrupt the
system unit after a preselected amount of time has elapsed from
the start of a communication operation. Counter 0 is not used for
synchronous operation. Counters 1 and 2 connect to

4 BSe Adapter
interrupt-level 4 and, being programmed to terminal-count values,
provide the desired time delay before generating a level-4
interrupt. These interrupts signal the system that a predetermined
amount of time has elapsed without a TxRDY (level 4) or an
RxRDY (level 3) interrupt being sent to the system unit.

USART Programming
After the support devices on the BSC adapter are programmed,
the USAR T is loaded with a set of control words that defines the
communication environment. The control words consist of mode
instructions and command instructions.

Both the mode and command instructions must conform to a

specified sequence for proper device operation. The mode
instruction must be inserted immediately after a reset operation
before using the USART for data communications. The required
synchronization characters for the defined communication
technique are then loaded into the USART (usually hex 32 for
BSC). All control words written to the USART after the mode
instruction wi11load the command instruction. Command
instructions can be written to the USART in the data block any
time during its operation.

To return to the mode instruction, the master reset bit in the

command instruction word is set to start an internal reset
operation, which places the USART back into the mode
instruction. Command instructions must follow the mode
instructions or synchronization characters.

BSC Adapter 5
The following represents a typical data block and shows the mode
instruction and command instruction.

3A9C/D = 1 Mode Instruction 1

3A9 c/o = 1 SYNC Character 1

3A9Cio = 1 SYNC Character 2

3A9Cio = 1 Command Instruction

3A8C/D = 0
I
~ Data
I
~

3A9 c/o = 1 Command Instruction

3A8Cio = 1 ~~ Data
~
3A9 c/o = 1 Command Instruction

Typical Data Block

The following are the communications interrupt levels.

• Interrupt level 4
Transmit

Timer 1

Timer 2

• Interrupt level 3
- Receive

6 BSC Adapter
The following are device addresses.

Hex Address
Device Register Name Function
Primary Alternate

3AO 380 8255 Port A Data Internal/External Sensing

3A1 381 8255 Port B Data External Modem Interface
3A2 382 8255 Port C Data Internal Control
3A3 383 8255 Mode Set 8255 Mode Initialization
3A4 384 8253 Counter 0 LSB Not Used in Sync. Mode
3A4 384 8253 Counter 0 MSB Not Used in Sync. Mode
3A5 385 8253 Counter 1 LSB Inactivity Time Outs
3A5 385 8253 Counter 1 MSB Inactivity Time Outs
3A6 386 8253 Counter 2 LSB Inactivity Time Outs
3A6 385 8253 Counter 2 MSB Inactivity Time Outs
3A7 387 8253 Mode Register 8253 Mode Set
3A8 388 8251 Data Select Data
3A9 389 8251 Command/Status USART Status

Device Address Summary

Bse Adapter 7
8 BSC Adapter
Interface

The IBM Binary Synchronous Communications Adapter

conforms to interface signal levels standardized by the Electronic
Industries Association (EIA) RS-232C Standard. The following
figure shows these levels.

Driver EIA RS232C/CCITT V24·V28 Signal Levels

+15 Vdc - - - - - - - - - - - ,

Active/Data ~ 0

+5 Vdc
+5 Vdc

I nval id Level

-5 Vdc
-5 Vdc

Inactive/Data = 1

-15 Vdc

Receiver EIA RS232C/CCITT V24-V28 Signal Levels

+25Vdc .----------~

Active/Data ~ 0

+3 Vdc
+3 Vdc
I nvalid Level
-3 Vdc
-3 Vdc

I nactive/Data ~ 1

-25 Vdc

Interface Voltage Levels

BSC Adapter 9
Pins 11, 18, and 25 on the interface connector are not
standardized by the EIA. These lines are designated as 'select
standby,' 'test,' and 'test indicate.' 'Select standby' is used to
support the switched network backup facility of a modem that
provides this option. 'Test' and 'test indicate' support a modem
wrap function on modems designated for business-machine,
controlled-modem wraps.

10 BSe Adapter
Specific a tions
25-Pin D-Shell
Connector
o
13
•• • 25
•• •
• ••
•• •
•
• •
•
• •
• 14

Signal Name - Description Pin

No Connection 1
Transmitted Data 2
Received Data 3
Request to Send 4
Clear to Send 5
Data Set Ready 6
Signal Ground 7
Received Line Signal Detector 8
No Connection 9
No Connection 10 Binary
External Select Standby* 11 Synchro nous
Device No Connection 12 Commun ications
Adapter
No Connection 13
No Connection 14
Transmitter Signal Element Timing 15
No Connection 16
Receiver Signal Element Timing 17
Test (IBM Modems Only)* 18
No Connection 19
Data Terminal Ready 20
No Connection 21
Ring Indicator 22
Data Signal Rate Selector 23
No Connection 24
Test Indicate (IBM Modems Only)* 25

*Not standardized by EIA (Electronic Industries Association).

Connector Specifications
Bse Adapter 11
12 BSC Adapter
Logic Diagrams

lID BUS 8255 PCO IIIITERIiIAl CLOCK

••
,..
+AO
+A1
31
31

3D
lOR
8255 PCI 10DEI CLOCI

OSC 30 Ell IODEI

+12 k-+t<~---1 REG RECEIIE GLOCI

""
+5 VOLTS
+A3 28

+A4 "21 21
+A5
+ ..
-IB03
" ""
+A1
+IR04
""
24 DATA SET
+.. AO-Al
+A9
23 " READY

""
21
21
CLEAR TO SEND

20
20
. RECEIVE DATA

"
18
18
IRO 4 CARRIER DETECT
11
11
18

"
15
15
RillS lID.

14
-lOR + RESET
-lOW
"
13
13
12
12
+1£111
10
'.0
+00
10

+12 VOLTS
+01
+D2
-12 VOLTS
+03
+04 J'
13 +5V
+D5 25 TEST liD
12
+08 24 SELECT STAY
+5 JOLTS
+01 23 RATE SElECT
+flESET 10 +--~--~----~--~--"3
22 RIIIG Ilia
T T i-T B2a

1••• =T
GND 1
BOARD TO CARD
CDIINECTOR
1C1
T 2C1=T
f--+---~----~--~-BO'
1&2 1BC2

+--+----+----+--+--13'

1L _,
rrn-_
+'"----11:r-,,-,---,.. ,, ,,
L'

,.,,----"I>'-=,,"-,---801/831 l ~-1-- J
14
" ----<..->----101 _1""'1.
Ell CARD TO
CABLE CO••ECTOR
-'"

Binary Synchronous Communications Adapter (Sheet 1 of 2)

Bse Adapter 13
Binary Synchronous Communications Adapter (Sheet 2 of 2)

14 BSe Adapter
II~UL&ROIIIID

BSC Adapter 15
16 BSe Adapter
----
-- ----
- - --- Personal Computer
--_.-
- - ---
- ---
-- Hardware Reference
Library

mM Synchronous Data
Link Control (SDLC)
Communications
Adapter

6361497
ii
Contents

Description .................................... 1
8273 SDLC Protocol Controller ................ 2
8255A-5 Programmable Peripheral Interface ...... 2
8253-5 Programmable Interval Timer ............ 4
Programming Considerations ...................... 5
Initializing the Adapter (Typical Sequence) ....... 5
8253-5 Programmable Interval Timer ............ 5
Address and Interrupt Information .............. 6
Interface ...................................... 7
Specifications .................................. 9
Logic Diagrams ................................ 11

iii
iv
Description

The IBM Synchronous Data Link Control (SDLC)

Communications Adapter provides communications support to
the system in a half-duplex synchronous mode. The adapter
receives address, data, and control signals from the system board
through the internal bus. Electronic Industries Association (EIA)
drivers and receivers connect to an RS232-C standard 25-pin,
D-shell, male connector.

The adapter is programmed by communications software to

operate in a half -duplex mode. Maximum transmission rate is
9600 bits per second, as generated by the attached modem or
other data communications equipment.

The SDLC adapter uses an Intel 8273 SDLC Protocol Controller

and an Intel 8255A-5 Programmable Peripheral Interface (PPI)
for an expanded external modem interface. An Intel 8253
Programmable Interval Timer (PIT) generates timing and
interrupt signals. Internal test-loop capability is provided for
diagnostic purposes.

The following figure is a block diagram of the IBM SDLC

Communications Adapter.

Data
Bus
Buffer

System EIA
Drivers DCE
Bus
Receivers

Address
Address Decode Modem
Logic Status
' - - - - - - + I Controller Change
Logic

SDLC Communications Adapter Block Diagram

SDLC Communications Adapter 1

8273 SDLC Protocol Controller
The 8273 SDLC Protocol Controller has three operations-
transmission, reception, and port read-with each operation
consisting of three phases:

Command: Commands and/or requirements for the operation

are issued by the system unit's microprocessor.

Execution: Executes the command, manages the data link, and

may transfer data to or from memory using direct memory access
(DMA), and thus freeing the system unit's microprocessor except
for minimal interruptions.

Result: Shows the effect of the command by returning the

interrupt results.

Support of these phases is through the internal registers and

control blocks of the controller.

8255A-5 Programmable Peripheral Interface

The 8255A-5 PPI has three 8-bit ports-A, B, and C.
Descriptions of each bit of these ports follow.

8255A-5 Port A Assignments* Hex Address 380

Bit 7 6 5 4 3 2 1 0

~
0= Ring Indicator is on from Interface
0= Data Carrier Detect is on from Interface
Oscillating = Transmit Clock Active
0= Clear to Send is on from Interface
Oscillating = Receive Clock Active
1 = Modem Status Changed
1 = Timer 2 Output Active
1 = Timer 1 Output Active

* Port A is defined as an input port

2 SDLC Communications Adapter

8255A-5 Port B Assignments* Hex Address 381

Bit 7 6 5 4 3 2 1 0

~
0= Turn On Data Signal Rate Select at
Modem Interface
0= Turn On Select Standby at Modem
Interface
0= Turn On Test
1 = Reset Modem Status Changed Logic
1 = Reset 8273
1 = Gate Timer 2
1 = Gate Timer 1
1 = Enable Level 4 Interrupt

* Port B is defineq as an output port

8255A-5 Port C Assignments* Hex Address 382

Bit 7 6 5 4 3 2 1 0

III ~ = 1 Go<, '""",' C'ooklO",,", 6'"

1 = Gate External Clock (Output Bit)
1 = Electronic Wrap (Output Bit)
0= Gate Interrupts 3 and 4 (Output Bit)
Oscillating = Receive Data (Input Bit)
Oscillating = Timer 0 Output (Input Bit)
0= Test Indicate Active (Input Bit)
Not Used

*Port C is defined for internal control and gating functions. It has three input
and four output bits. The four output bits are defined during initialization, but
only three are used.

SDLC Communications Adapter 3

8253-5 Programmable Interval Timer
The 8253-5 PIT is driven by a microprocessor clock signal that is
divided by 2. The PIT's three counters provide the following
output:

Counter 0 Programmed to generate a square-wave signal that is

used as an input to timer 2. Also connected to port
C, bit 5 of the PIT.

Counter 1 Connected to PPI port A, bit 7, and interrupt-level 4.

Counter 2 Connected to PPI port A, bit 6, and interrupt-level 4.

4 SDLC Communications Adapter

Programming Considerations

Initializing the Adapter (Typical Sequence)

Before the 8273 SDLC Protocol Controller is started, the support
devices on the adapter must be set to the correct modes of
operation.

Setup of the 8255A-5 Programmable Peripheral Interface is

accomplished by selecting the mode set address for the PPI and
by writing the appropriate control word to hex 98 to set ports A,
B, and C to the modes described previously in this section.

Next, a bit pattern sent to port C disallows interrupts, sets wrap

mode on, and gates the external clock pins (address is hex 382,
data is hex OD). The adapter is now isolated from the
communications interface.

The controller reset line is brought high through bit 4 of port B,

held, then dropped. This action resets the internal registers of the
controller.

8253-5 Programmable Interval Timer

The PIT's counters 1 and 2 terminal-count values are set to values
that will provide the desired time delay before a level-4 interrupt
is generated. These interrupts may be used to indicate to the
communication programs that a predetermined amount of time
has elapsed without a result interrupt (interrupt-level 3). The
terminal-count values for these counters are set for any time delay
the programmer requires. Counter 0 also is set to mode 3
(generates square-wave signal used to drive counter 2 input).

The counter modes are set up by selecting the address for the
PIT's counter-mode register and by writing the control word for
each individual counter to the device separately.

SDLC Communications Adapter 5

When the support devices are set to the correct modes and the
8273 SDLC Protocol Controller is reset, it is ready to be set up
for the operating mode that defines the communications
environment in which it will be used.

Address and Interrupt Information

The following tables provide address and interrupt information
for the SDLC adapter.

Hex Code Device Register Name Function

380 8255 Port A Data Internal/External Sensing
381 8255 Port B Data External Modem Interface
382 8255 Port C Data Internal Control
383 8255 Mode Set 8255 Mode Initialization
384 8253 Counter 0 LSB Square Wave Generator
384 8253 Counter 0 MSB Square Wave Generator
385 8253 Counter 1 LSB Inactivity Time-Outs
385 8253 Counter 1 MSB Inactivity Time-Outs
386 8253 Counter 2 LSB Inactivity Time-Outs
386 8253 Counter 2 MSB Inactivity Time-Outs
387 8253 Mode Register 8253 Mode Set
388 8273 Command/Status Out = Command In = Status
389 8273 Parameter/Result Out = Parameter In = Status
38A 8273 Transmit INT Status DMA/INT
38B 8273 Receive INT Status DMA/INT
38C 8273 Data DPC (Direct Program Control)

SDLC Communications Adapter Device Addresses

Interrupt Level 3 Transmit/Receive Interrupt

Interrupt Level 4 Timer 1 Interrupt
Timer 2 Interrupt
Clear to Send Changed
Data Set Ready Changed
DMA Level 1 is used for Transmit and Receive

Interrupt Information

6 SDLC Communications Adapter

Interface

The SDLC Communications Adapter conforms to interface signal

levels standardized by the Electronic Industries Association
(EIA) RS232-C Standard. These levels are shown in the
following figure.

Drivers Receivers

+15VdC~ + 25 Vdc

+5Vdc ~ + 3 Vdc

Invalid Level

- 5 Vdc - 3 Vdc

~
-15VdC~
Inactive Level: Data =1

L-25VdO
Additional lines used but not standardized by the ErA are pins 11,
18, and 25. These lines are designated as 'select standby,' 'test,'
and 'test indicate,' respectively. 'Select standby' supports the
switched network backup facility of a modem that has this option.
'Test' and 'test indicate' support a modem-wrap function for
modems that are designed for business-machine controlled
modem-wraps. Two jumpers on the adapter (PI and P2) connect
'test' and 'test indicate' to the interface.

SDLC Communications Adapter 7

8 SDLC Communications Adapter
Specifications
25-Pin D-Shell
Connector
o
13 • • 25
• •
• •
• •
• •
• •
• •
• •
•• •
• •
• •
• • 14

0
Signal Name - Description Pin
No Connection 1
Transmitted Data 2
Received Data 3
Request to Send 4
Clear to Send 5
Data Set Ready 6
Signal Ground 7
Received Line Signal Detector 8
No Connection 9
No Connection 10 Synchronous
External Select Standby* 11 Data Lin k
Device No Connection 12 Control
Commu nications
No Connection 13
Adapter
No Connection 14
Transmitter Signal Element Timing 15
No Connection 16
Receiver Signal Element Timing 17
Test (IBM Modems Only)* 18
No Connection 19
Data Terminal Ready 20
No Connection 21
Ring Indicator 22
Data Signal Rate Selector 23
No Connection 24
Test Indicate (IBM Modems Only)* 25

*Not standardized by EIA (Electronic Industries Association),

Connector Specifications
SDLC Communications Adapter 9
10 SOLC Communications Adapter
Logic Diagrams

The following pages contain the logic diagrams for the IBM
Synchronous Data Link Control (SDLC) Adapter.

SDLC Communications Adapter 11

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SOLC Communications Adapter (Sheet 1 of 2)

12 SDLC Communications Adapter

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CO••ECTOR CABLE CONNECTOR SOLC Communications Adapter (Sheet 2 of 2)
------
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Personal Computer
Hardware Reference
Library

mM Cluster Adapter

6361495
ii
Contents

Description. ................................... 1
8031 Microcomputer ........................ 5
Cluster Adapter I/O Register Definitions ....... 12
Programming Considerations ..................... 18
Interface ..................................... 83
System Processor I/O Interface ............... 83
Cluster Adapter Switch Settings ............... 84
System Processor Memory Interface ............ 90
System Processor Interrupt Interface ........... 90
8255 Programmable Peripheral Interface (PPI) ... 91
Cluster Bus Interface ....................... 94
Specifications ................................. 96
Logic Diagrams ................................ 97

Index ........................................ Index ... 1

iii
iv
Description

The Cluster Adapter is a 10.16 cm (4 inch) high by 25.4 cm (10

inch) wide communication adapter used for linking up to 64 IBM
Personal Computers (PCs). The transmission rate is 375,000 bits
per second (bps). A multi-drop bus architecture passively links
(cluster operation is unaffected if the power to any station is off)
the PCs to a coaxial cable. The coaxial cable bus can be a
maximum length of 1 kilometer (3280 feet) and requires a
75-ohm (n) terminating resistor at both ends to minimize signal
reflection. The coaxial cable drop can be a maximum length of 5
meters (16.4 feet) and a minimum length of 1 meter (3.3 feet).

The following is an example of a cluster:

75D 75D
Resistor Resistor

CLUSTER EXAMPLE

The PCs share the bus through a distributed-access protocol

called carrier sense multiple access with collision avoidance
(CSMA/CA). With this protocol, each PC (station) that wants
to transmit, calculates its own access-window wait time after no
signal is sensed on the bus. The wait time differs for each station
and changes with each transmission to prevent collisions (two
stations transmitting at the same time). If cluster traffic is light
(no signal is on the coaxial cable for approximately 2.8
milliseconds), a station that wants to transmit establishes cluster
synchronization by transmitting all l's (111 ... 1) for 150

Cluster Adapter 1
microseconds (p,s), thereby forcing a carrier sense transition
(On-to-Off). The station can then calculate its access-window
wait time.

Because the PCs are passively connected and operate under a

distributed-access protocol, the operation of the cluster is
unaffected if the power to any single station is off.

The Cluster Adapter sends and receives frames consisting of

link-control and information fields to and from other Cluster
Adapters in the cluster.

The Cluster Adapter consists of the following components:

• 8031 8-bit Microcomputer

• 8031 Accessible ROM
• 8031 Accessible RAM
• System Processor (8088) Interface
• Adapter Status Register
8088 Accessible ROM
• 8255 Programmable Peripheral Interface (PPI)
• Cyclic Redundancy Checking (CRC) Hardware
Cluster Interface

2 Cluster Adapter
The following is a block diagram of the Cluster Adapter:

Cluster Coaxial Cable

~

T
Cluster
Serial
Interface

I
Data
BK ROM/4K RAM
Address

CRC
H/W
-

~
Data Buffer PO P2 P3
8255 8031 8088 ROM
PB PA PC P1 8K

J I
I Switches
Addr I
I Register
Status I

Processor
Interface
I

System Processor Bus

Cluster Adapter Block Diagram

Cluster Adapter 3
 DANGER
TO HELP PROTECT FROM LIGHTNING AND
OTHER SOURCES OF ELECTRICAL SHOCK, IBM
REQUIRES THAT THE COAXIAL CABLE
SHIELDING BE GROUNDED, AND NEITHER THE
FRAME NOR COVERS OF THE IBM PERSONAL
COMPUTER CAN BE USED AS THE GROUNDING
POINT.

• To ensure proper operation of the cluster, the shielding of the

coaxial cable cannot be grounded at more than one point.

• If compliance to electrical codes require multiple ground

points, then triaxial cable (double shielded) must be used. In
using the triaxial cable, only the outer shielding can be
grounded and under no circumstances should the outer shield
be connected to the inner shield.

• This installation should be performed by a licensed electrician.

4 Cluster Adapter
8031 Microcomputer
The 8031 Microcomputer is the controlling processor for the
Cluster Adapter. The 8031 has an 8K x 8-bit ROM, and a 4K x
8-bit static RAM.

The 8031 consists of the following:

• A processor

• A dynamic 128 x 8-bit read/write data memory

• 32 I/O lines

• 2 16-bit timer/event counters

• A five-source, two-priority-Ievel, nested interrupt structure

• A serial I/O port for mUltiprocessor communications

• I/O expansion or a full duplex Universal

Synchronous/ Asynchronous Receiver/Transmitter (USART)

• An on-chip oscillator and clock circuits.

The 8031 also provides addressing for up to 64K bytes of

program memory and 64K bytes of data memory.

The 8031 is operated at 12 Megahertz (MHz), yielding a

single-cycle time of 1 p,s.

Program and data address spaces on the adapter are combined

into a 64K-byte address space by ORing -Program Store Enable
( -PSEN) and -Read (-RD). The memory address space includes
not only the 8K x 8-bit ROM and 4K x 8-bit static RAM, but also
the 8255 port and control registers and the 2653 registers
necessary for CRC calculation.

Cluster Adapter 5
8031 Ports

The 8031 on the Cluster Adapter provides external memory

addresses through ports 0 and 2.

• Port 0 is an 8-bit, open-drain, bidirectional, I/O port used as

the multiplexed low-order address and data bus.

• Port 2 is a bidirectional I/O port and provides the high-order

address byte for the external memory.

Port 1 of the 8031 is an 8-bit, bidirectional, I/O port used on the

adapter for status conditions.

Port 3 is an 8-bit, bidirectional, I/O port used as a serial port and

as a source for external memory and serial-transmission control
lines.

6 Cluster Adapter
The following is a summary of the 8031 port signals:

Port 0 Port 2 Port 3 Port 1

External Memory
Address
Low Order High Order Transmission
Byte and Address and Control
Bits Data Bus Byte Only Lines Status
7 A7/D7 A15 -RD Direction to 8031
6 A6/D6 A14 -WR Error
5 A5/D5 A13 -CRC INT Communication
Port Busy
4 A4/D4 A12 -RTS RX Virtual 1/0
Frame Available
3 A3/D3 A11 +Internal Loop RX Frame in (FIFO)
2 A2ID2 A10 -Carrier Sense Data Available for
8088 (0 = Active)
1 A1/D1 A9 +TXD Command or Data
Available for 8031
0 AO/DO A8 +RXD Command in
Progress

Summary of 8031 Port Signals

Cluster Adapter 7
Serial Transmission and Control Lines

The serial transmission lines are:

+Receive Data (+RXD) The + RXD line provides the

serial port's receiver data input.

+ Transmit Data (+ TXD) The + TXD line provides the serial

port's transmitter data output.

The serial transmission control lines are:

-Request to Send (-RTS) The -RTS signal enables the

adapter's transmitter to send data
on the cluster cable bus.

+ Internal Loop The + Internal Loop line is used in

the diagnostic mode. When high,
it activates the internal loop back
feature so the Cluster Adapter can
receive the data it is transmitting
without interference or being
attached to the bus.

-Carrier Sense -Carrier Sense is an input signal to

port 3 that indicates the current
state of the cluster; it is low (0)
when the cluster is busy.

8 Cluster Adapter
The memory control lines are:

-Write (-WR) The -WR line latches the data

byte from port 0 into the external
data memory.

-Read (-RD) The -RD line enables external

data memory to port o.

The interrupt line is:

-CRC Interrupt (-CRC INT) The -CRC INT line is used to

indicate a successful or
unsuccessful comparison in CRC
values. The signal source is -INT
from the 2653 Polynomial
Checker Generator.

8K X 8-Bit ROM
The 8K x 8-bit ROM contains the 8031 code necessary for
hardware initialization and the data link control program
(DLCP). The DLCP is the lowest level of software for the
Cluster Adapter. The DLCP resides in the 8K by 8-bit ROM on
the Cluster Adapter, which is accessible by the 8031
Microcomputer.

4K X 8-Bit Static RAM

The 4K x 8-bit static RAM is available to the 8031 for read/write
storage necessary to implement the DLCP. The available space is
used to buffer frames and to store control and cluster
information. The 4K x 8-bit static RAM is implemented using
two 2K x 8-bit static RAM modules.

Cluster Adapter 9
The following is the 8031 memory map:

Start Address (Hex) Function

0000 DlCP ROM
2000 RAM
3000 8255 Port A
3001 8255 Port 8
3002 8255 Port C
3003 8255 Control
3004 2653 Character Register
3005 2653 Status Register
3006 2653 Mode Register
3007 2653 CRC Upper flower Registers

8031 Memory Map

8088 Accessible ROM

The 8088 (System Processor) accessible ROM is an 8K x 8-bit
ROM and contains the 8088 code necessary to perform the
remote initial program load (IPL) and power-on diagnostic
functions.

2653 Polynomial Generator Checker

The 2653 Polynomial Generator Checker is used by the 8031
Microcomputer to compute the Cyclic Redundancy Check (CRC)
value for transmitted or received data blocks for error checking.

10 Cluster Adapter
 The 2653 is programmed by the 8031 in the automatic mode to
generate the American National Standards Institute (ANSI)
CRC-16 values. Two 8-bit characters are read from the 2653
character register into the Block Check Character (BCC)
generation unit to calculate the 16-bit check character.

Programming is achieved as follows:

• The Clear CRC command, hex 02, is issued to the 2653

command register at address hex 3005.

• The Automatic Accumulation Mode command, hex 49, is

issued to the 2653 mode register at address hex 3006.

• The Start Accumulation command, hex 01, is issued to the

2653 command register at address hex 3005.

• Characters to be accumulated are written to the character

register at address hex 3004.

The accumulated CRC value may be read by the 8031 from

address hex 3007 (the 2653 CRC upper and lower registers) in
two read operations. The 2653 alternately provides the upper and
lower values.

The 2653 is activated upon proper decoding of addresses in the

range of hex 3004 through hex 3007 and the occurrence of -Read
Strobe (-RS) or -Write (-WR). This allows the input to the
. -Read/Write (-R/W) pin of the 2653 to become stable prior to
the fall of -Clear Entry 1 (-CEl), as required.

Cluster Adapter 11
Cluster Adapter 110 Register Definitions
The following defines the Cluster Adapter I/O registers:

I/O Address
Adapter (Hex) Device
Adapter 1 0790 Adapter Status Reg ister
0791 Adapter Command/Data (Output)
Adapter Result/Data (Input)
0792 Adapter Interrupt Register
0793 Adapter Reset Control
Adapter 2 0890 Adapter Status Register
0891 Adapter Command/Data (Output)
Adapter Result/Data (Input)
0892 Adapter Interrupt Register
0893 Adapter Reset Control
Adapter 3 1390 Adapter Status Register
1391 Adapter Command/Data (Output)
Adapter Result/Data (Input)
1392 Adapter Interrupt Register
1393 Adapter Reset Control
Adapter 4 2390 Adapter Status Register
2391 Adapter Command/Data (Output)
Adapter Result/Data (Input)
2392 Adapter Interrupt Register
2393 Adapter Reset Control

Cluster Adapter I/O Registers

12 Cluster Adapter
Adapter Status Register
The adapter status is provided to the system data bus by a
74LS373 transparent latch.

The following are the bit assignments:

Bit Definition (1 = Active Unless Noted)

7 Direction (1 = data expected from 8088 to 8031)
6 Error
5 Communication Port Busy
4 RX Virtual I/O Frame Available
3 RX Frame in First in First Out (FIFO)
2 Data Available for 8088 (0 = active)
1 Command/Data Available for 8031
0 Command in Progress

Status Register Bit Definitions

The outputs of the transparent latch, though not enabled on the

bus, continuously follow the inputs provided by the 8031 and
8255. Upon decoding of the read-status I/O address, the
latch-enable input to the transparent latch goes low, latching the
inputs of the current state and enabling the data onto the bus.

The status bits are latched during the active read time to preserve
the integrity of the data. When the outputs are disabled and the
latch-enable input to the latch goes high at the end of the read
cycle, the outputs of the transparent latch again monitor the
inputs in real time.

Cluster Adapter 13
 Definition of Bits at Port 0791
(for Adapter 1)
(Command or Parameters for 8031)
Bit Definition
7 Command or Data Bit 7
6 Command or Data Bit 6
5 Command or Data Bit 5
4 Command or Data Bit 4
3 Command or Data Bit 3
2 Command or Data Bit 2
1 Command or Data Bit 1
0 Command or Data Bit 0

Cluster Adapter Command/Data Register (Output)

Definition of Bits at Port 0791

(for Adapter 1)
(Result or Data from 8031)
Bit Definition
7 Result or Data Bit 7
6 Result or Data Bit 6
5 Result or Data Bit 5
4 Result or Data Bit 4
3 Result or Data Bit 3
2 Result or Data Bit 2
1 Result or Data Bit 1
0 Result or Data Bit 0

Cluster Adapter Result/Data Register (Input)

14 Cluster Adapter
 Definition of Bits at Port 0792 (for Adapter 1)
Bit Definitions
7-2 Not used.
1 Received Frame(s) Available. One or more information frames have
been received and may be read using either the BIOS Receive
Frame or Receive Virtual 1/0 Frame command (1 = active).
0 Cluster BIOS Command Complete. The Cluster BIOS command
intiated with the Initiate Transmit bit set is complete. The result
must be obtained by issuing the same Cluster BIOS command with
the Finish Transmit bit set (1 = active).

Cluster Interrupt Status Bits

Note: Both bits 1 and 0 are set to indicate interrupt due to

Cluster Status command complete.

Definition of Bits at Port 0793 (for Adapter 1 )

Bit Definitions
7 -1 Not used.
0 Reset Cluster Adapter. The adapter microprocessor as well as all
other logic on the adapter will be held in a reset condition until
there is an output with this Reset Adapter bit set to zero (1 = active).

Note: Any output to the reset register will also disable the adapter from
generating interrupts.

Cluster Adapter Reset Register Bit Definitions

Cluster Adapter 15
Cluster Adapter Interrupts
The Cluster Adapter may be set (one jumper selectable) to allow
interrupts on either interrupt-level 3 or interrupt-level 7. An
adapter error detected by diagnostic tests is reported if the
interrupt jumper is missing. The received frames must be
available or the Transmit operation complete (if initiated by a
Transmit command with the Initiate Transmit bit set).

Up to four Cluster Adapters can be installed at a station. Each

adapter can be enabled/disabled and all are similar in operation.
If enabled, the adapter generates interrupts on levels 3 or 7
provided one of the following conditions is met:

• A received frame is available.

• The Transmit Frame command is complete.
• The Cluster Status command is complete.

The following description is for adapter 1:

1. Interrupts are enabled by executing an output instruction to

the adapter's interrupt enable register.

2. Interrupts are disabled by writing the hex 00 instruction to the

adapter's reset register. Also, additional interrupts are
disabled by generating the interrupt request. The adapter
must be re-enabled after each interrupt if additional interrupts
are desired.

16 Cluster Adapter
3. To avoid resetting the adapter, data bit 0 must be set to a 0
when an output is sent to the adapter's reset register.

No interrupt handler is provided for the cluster, and must be

provided by the user who requires interrupt capability.

The interrupt condition is provided in the adapter's interrupt

register, as described in the Cluster Adapter Interrupt Status
Bits table.

Cluster Adapter 17
Programming Considerations

The data link control program (DLCP) is the lowest level of

software for the Cluster Adapter. The DLCP resides in the 8K
by 8-bit ROM, which is accessible by the 8031 Microcomputer.

The Cluster Adapter basic input! output system (BIOS) code

resides in an 8K-byte 8088 accessible ROM on the Cluster
Adapter at address hex DOOOO.

Note: The Cluster Adapter decodes a 32K-byte range starting

at hex DOOOO. High-level cluster BIOS commands are
processed by the cluster BIOS into the appropriate low-level
. commands and parameters. The low-level commands and
parameters are then passed to the 8031 Microcomputer, which
performs the requested command. After the command is
complete, the 8031 Microcomputer transfers the results back
to the DLCP BIOS routine, which fills in the requester's link
control block (LCB) with the results and then return through
an interrupt return (IRET) to the requester that issued the
INT hex 5A.

The cluster BIOS level interface allows the higher layer

communication program to transmit to and receive data from the
specified destination through the bus. The basic unit of
information transmitted using DLCP is a frame. A frame consists
of a control field and an optional data field.

18 Cluster Adapter
The following functions are implemented in the DLCP to
interface with the higher layer communication program and to
ensure reliable data transfer between stations on the bus:

• Higher layer communication program BIOS interface to the

communication software
• Frame assembly, reception and transmission
• CRC generation and checking
• Carrier sense multiple access with collision avoidance
(CSMA/CA)
• Error detection and recovery
• Cluster status monitoring
• Remote IPL

Cluster Adapter 19
Higher Layer Communication Program BIOS
Interface
When the Power switch is set to On, the hex 5A software
interrupt vector is set to the address of the Cluster Adapter BIOS
by the adapter's self-test diagnostic code.

Notes:

1. The DLCP must be initialized before it can process most of its

commands.

2. Interrupt hex 5A is reserved for the Cluster Adapter BIOS and

should not be changed.

The higher layer communication program must access the Cluster

Adapter BIOS through an interrupt hex 5A instruction. The
program must set the Extra Segment (ES) Register output to the
segment and the Base Index (BX) Register output to the offset of
the Link Control Block (LCB) before invoking the cluster DLCP
BIOS. All parameters, the return code, and the cluster status are
passed through the LeB.

20 Cluster Adapter
The format of the LCB is shown below:

Link Control Block (LCB) Number of Bytes

Destination Station Physical Address 1
Source Station Physical Address 1
Command 1
Buffer 1 Length 2
Buffer 1 Address 2 (Offset)
2 (Segment)
Buffer 2 Length 2
Buffer 2 Address 2 (Offset)
2 (Segment)
Return Code 1
Cluster Status 1
Select Adapter 1

Structure of Link Control Block (LCB)

Notes:

1. The internal variables and buffers of the DLCP are in the

RAM resident on the adapter and are not directly accessible
from the higher layer communication program.

2. Select Adapter is used to select the adapter for which the

command is intended (0 for adapter 1, 1 for adapter 2, 2 for
adapter 3, and 3 for adapter 4).

3. For the length and address fields, the word values are ordered
least-significant byte first.

Cluster Adapter 21
The contents of buffer 1 and buffer 2 together form the
information field of the frame. For example, buffer 1 can be used
to store header bytes while buffer 2 can be used to store the
actual data to be transferred.

The return code indicates the success or failure of the function

requested, and the error code if the function fails. The LCB
status indicates the current status of the cluster. This field is valid
as a result of the DLCP Status command. The LCB status field is
also used by some commands to store an extended return code.

Frame Transmission
Transmit or Transmit Virtual Information frames are sent by the
DLCP to complete the corresponding DLCP BIOS commands. The
DLCP on its own initiative transmits various frames. The
following response frames are issued in response to a received
frame:

Ack Reception OK with no problems

Frame Reject All receive buffers full
Not Connected Not connected to sending station
Bad Error Frame out of sequence (rejected)
Duplicate Address Duplicate station address exists on the
cluster

22 Cluster Adapter
The following control frame is transmitted by the DLCP when the
Power switch is set to On or at initialization:

Initializing Broadcast to all stations to indicate that the

source station is in the process of initializing and
all connections to that station should be set to
the disconnected state. Also, if any station has
the same station address, it sends a
duplicate-address response back to the
initializing station.

In addition, the DLCP determines if it is necessary to send a

connect frame to establish connection with the destination
station. If this station's Cluster Status table indicates that it is not
connected to the destination station, the DLCP transmits a
connect frame to establish connection and then transmits the
information frame. If a not-connected control frame is received
in response to the transmission of a frame, the DLCP transmits a
connect frame to establish connection, then transmits the
information frame.

Cluster Adapter 23
Frame Format
The basic unit of information transmitted is a frame. The
On-to-Off transition of the 'carrier sense' signal identifies the
beginning of a frame, and the Off-to-On transition identifies the
end. A frame consists of fixed control fields and an optional
variable length information field. The following shows the format
of a frame:

Field Number of Bytes Note

Desti nation Address 1 Control
Source Address 1 Field
Transmit Window Token 1
Control 1
Sequence 1
Byte Count 2
Control CRC 2
Information 1 to 578 Information
Data CRC 2 Field

Frame Format

Note: The minimum and maximum total number of bytes

transmitted for a frame is 9 and 587, respectively. The
transmission time for a frame ranges from approximately 1
millisecond (ms) for a minimum length frame up to
approximately 16.5 ms for the maximum length frame.
However, additional time may be required to gain access to
the cluster before a frame can be sent.

24 Cluster Adapter
Control Field Format

The control field consists of the following:

Destination Address - The destination address can be any

number from hex 00 through hex 3F; that is, 64 station addresses
are supported. Address hex FF is reserved as the broadcast
address that all stations respond to. Addresses hex FE through
hex FO are reserved for use as multicast addresses.

Source Address - The source address is used to tell the DLCP

the senders station address. The DLCP uses the source address
as an index into a Cluster Status Table, which is used to maintain
the status of connected stations and sequence numbers for each
possible sender. Station addresses hex 00 through hex 3F are the
only supported source addresses.

Transmit Window Token - This value is updated for every

transmission and is used in an algorithm to determine how long
each station must wait after Carrier Sense Off before
transmitting.

Control Byte - The control byte is used to identify the function

of a frame. There are two basic types of frames used in the
cluster, information frames and control frames. Information
frames are used to transfer information from one station to
another, and control frames are used to assure reliable transfer of
information across the cluster bus.

Cluster Adapter 25
The following types of frames are used by the DLCP:

Acknowledge (hex 10) Confirm receipt of a frame.

Initializing (hex 21) Indicates that the source station is

re-initializing. Existing connections to this station
should be cleared.

Virtual Disk (hex 82) Identifies that this frame contains a data
block and was transmitted as a result of the source
station issuing a Transmit Virtual Frame DLCP
command. One buffer is reserved for this frame.

Information (hex 83) Signifies the frame contains a data block and
was transmitted as a result of the source station
issuing a Transmit Frame DLCP command. There is a
first-in-first-out (FIFO) buffer set aside for this
frame.

Connect (hex 04) Establishes the virtual point-to-point

connection between a pair of stations.

Broadcast (hex 45) Signifies that the frame is a broadcast or

multicast frame.

Not Connected (hex 16) Indicates that the receiving station is not
connected to the sending station.

Frame Reject (hex 17) Sent by the receiving station when it has
received an information frame or a virtual disk frame
and the DLCP does not have buffer space available to
store the frame.

Bad Error (hex 18) Sent by the receiving station to indicate that a
frame is out of sequence.

Duplicate Address (hex 19) Sent by the receiving station in

response to an initializing control frame to indicate
that more than one station has the same address.

26 Cluster Adapter
Are You There? (hex lA) Sent to each station to poll for status in
the cluster. Each station that is on sends a response
to this query. An Acknowledge response frame is sent
by stations that are initialized. A Frame Reject
response is sent by stations that are not initialized.

Note: The most-significant four bits of the frame-control byte

have the following meaning:

Sequenced Information Bit 7

Broadcast Information Bit 6
Broadcast Control Bit 5
Response Bit 4

Frame Sequence Byte - If one of the acknowledge frames did

not reach the transmitting station, the frame sequence byte is used
to make sure that no duplicate information frames are received.
The least-significant four bits in the Cluster Status Entry are used
for maintaining a sequence number for transmitted and received
frames. The first two bits are used for the sequence number for
received frames. The two least-significant bits are used for the
sequence number for transmitted frames. The sequence numbers
are incremented each time a transmitting station sends an
information frame and each time the receiving station accepts an
information frame. If a mismatch occurs between the two
stations, the sender marks the destination station in the
disconnected state and sends a connect frame to try to reconnect
with the destination station. If the connection attempt is
successful, the frame is transmitted again.

Cluster Adapter 27
Byte Count - The byte count is the number of information bytes
to be transmitted. If the frame is a control frame, the byte count
is zero. There are two bytes allocated for the byte count.

Control CRC - A 16-bit cyclic redundancy check (eRe) is

calculated and appended to the end of the control block. A
hardware eRe generator is used. The receiving station compares
the control eRe received with the eRe calculated from the
received data and makes sure they are the same. If they are not
the same, the receiving station ignores the rest of the frame.

Data CRC - A 16-bit eRe is calculated and appended to the

end of the data block. The receiving station compares the data
eRe received with the eRe calculated from the received
information bytes and makes sure they are the same. If they are
not the same, the receiving station ignores the received frame.

Information Field

This field is for an information frame only. The information field

is absent in the control frames. The maximum number of
information bytes that can be transmitted in a frame is 578.

28 Cluster Adapter
Cluster Access Protocol
Collision avoidance is used with the Cluster Adapter. To avoid
collisions, each station waits a different amount of time after
'carrier sense' goes inactive before transmitting.

Stations get access to the cluster by timing from the end of the
current transmission (-Carrier Sense On-to-Off transition) until
its transmit time is reached, and then it may transmit. See also
"Collision Avoidance (Medium or High Activity)" on page 30.

Each station maintains two flags to determine that it is permitted

to transmit.

1. Synchronized Transmit Period.

2. Transmit Window.

The Synchronized Transmit Period is set and the Transmit

Window is cleared when the Carrier Sense Interrupt routine is
entered. Also, timer 0 is reloaded with the count corresponding
to this station's calculated Transmit Access Window. Timer 0
counts while 'carrier sense' is off and overflows when this
station's Transmit Access Window is reached. Timer O's overflow
causes an interrupt that sets the Transmit Window flag and then
reloads timer 0 with the count corresponding to the end of the
synchronized transmit period. When timer 0 interrupts again on
overflow, the Synchronized Transmit Period flag is reset to
indicate that the synchronized transmit period is finished.

Cluster Adapter 29
Collision Avoidance (Medium or High Activity)

The following shows the timing during medium or high activity in

the cluster:

Carrier
Sense
On
Off l 1..._ _ _ _ _ _ _ _ __

I- TR --I 1 I 2 I ... 163 I 64 I

I- T1--I
r- T2 ----i
r- T64 -------1

Synchronized On----------~L_
Transmit Off
Period

Transmit On -------I
Window Off
Slot 2

30 Cluster Adapter
Collision Avoidance (Medium or High Activity)
TR= Time allocated for a receiver to start transmitting a
response.
T1 = Time delay for 1st Transmit Access Window.
T2 = Time delay for 2nd Transmit Access Window.

T64 = Time delay for 64th Transmit Access Window.

SN= Station N's address with the bits in reverse order.
Token = Transmit Window Token which is decremented by 2
for each transmitted frame.

Delay time for Station N = TR + «Token + SN) mod 128) x

transmit window12.

Notes:

1. TR is approximately 200 f.LS.

2. Transmit Access Window is approximately 40 f.LS.

A station must see its Transmit Window flag change from Off to
On before it is permitted to transmit. The case where it does not
see the change is covered in the next section.

Collision Avoidance (Light Activity)

If cluster activity is light (1480 f.LS average access time since the
previous transmission on the cluster) enough that the
Synchronized Transmit Period (STP) flag is reset, then
synchronization needs to be re-established to avoid collisions.

Cluster Adapter 31
The method used to re-establish synchronization is to transmit all
l's in the cluster for approximately 150 p,s and then to time the
carrier sense On-to-Off condition to this station's transmit slot
time. (See also "Collision Avoidance (Light Activity)" on page
33).

Transmit
Data ~ ---lI---------rulf··lJlJ
AlIl's Transmit Frame

~~f~
Carrier
Sense I
~ TR -11 I 2 I ... I 641
\-T1 -1
t- T2 -----I
r- T64 --------I

On
Synchronized
Transmit Off L
Period
On
Transmit Off
Window
Slot 2

32 Cluster Adapter
Collision Avoidance (Light Activity)
TR= Time allocated for a receiver to start transmitting a
response.
T1 = Time delay for 1st Transmit Access Window.
T2 = Time delay for 2nd Transmit Access Window.

T64 = Time delay for 64th Transmit Access Window.

Note: Average cluster access time is 1480 /LS if the cluster is

lightly loaded.

A station that is initializing waits the time of two complete

synchronization periods before sending its broadcast initializing
frame to allow it to become synchronized with the cluster. If no
frames are received in that time, it uses the procedure above to
establish a synchronized transmit period.

Frame Reception
The leading edge of the 'carrier sense' signal is used to interrupt
the 8031 Microcomputer. The 8031 interrupt service routine
updates its Transmit Window Token to the value transmitted with
the frame, and also sets the timer 0 counter to the calculated
Transmit Access Window based on the new token value. If the
frame is not addressed to this station, the DLCP ignores the rest
of the frame and leaves the interrupt routine.

If the frame is addressed to the station, the DLCP checks the

Cluster Adapter status to see if it can accept the frame. If this
station is not connected to the source station then a
not-connected control frame is transmitted to the source station.
If the frame is out of sequence, an bad error control frame is
transmitted to the source station.

If the DLCP can accept the frame, a check is made that a receive
buffer is available. If a buffer cannot be obtained, a frame- reject
control frame is sent back to the transmitting station. This
indicates that the frame cannot be accepted at this time and
another attempt should be made. If the frame is received

Cluster Adapter 33
correctly, DLCP transmits an Acknowledge frame to the
transmitting station and return the control to the interrupted 8031
program.

Error Detection and Recovery

The DLCP can detect various cluster errors and tries to recover
from them. If it is not able to recover after a specified number of
retries, it notifies the calling program with the returned error
code. The list of errors that can be detected is in the figure
below:

Type of Error Action Taken Retry Count (Seconds)

Cluster Busy Timeout Report Error N/A 1.0
Cluster Access Timeout Report Error N/A 13.0
No Response Retransmit Frame 8 0.20
Frame Reject Retransmit Frame 1 0.24
after Delay 2 0.09
3 0.16
4 0.25
5 0.36
6 0.49
7 0.64
Not Connected or Bad Transmit Connect N/A N/A
Error Control Frame and
If Successful
Retransmit Frame
Command Timeout Reset Adapter and N/A 120.0
Report Error

Detectable Errors and Recovery

34 Cluster Adapter
After correctly receiving a control frame or an information frame,
the receiving station sends a response frame. If all receive buffers
are in use, a Frame Reject response frame is transmitted. If the
frame is out of sequence, a Bad Error response frame is
transmitted.

If the transmitting station did not get a confirmation of receipt

after a certain time period, it assumes that the receiving station
never got the frame and it transmits the same frame again. If the
transmitting station still does not get a reply after eight retries, it
assumes that the receiving station is not available and resets the
Connected bit in the corresponding Cluster Adapter status entry.

Cluster Status Table

The DLCP keeps track of the status and sequence numbers for
°
connection with stations through 63 in the Cluster Table in the
°
Cluster Adapter's RAM space. Offset in the Cluster Table
corresponds to the status for connection to station 0, offset 1 for
station 1, and so on. The offset corresponding to a station's own
address is used to store a duplicate-station address indicator.

Cluster Adapter 35
The bits for each Cluster Status Table byte are designated in the
following chart:

Cluster Status Entry (1 Byte)

C 7 1 = Connected
RBl 6 Response 10
RBO 5 Response 10
F' 4 1 = Response Pending
RS1 3 Received Frame Sequence
RSO 2 Received Frame Sequence
TS1 1 Transmitted Frame Sequence
TSO 0 Transmitted Frame Sequence

Cluster Status Table Entry

Bit 7- Connected (C) is set to 1 when your station has

sent a connect frame and an acknowledge frame
has been received, or when a connect frame has
been received and an acknowledge has been sent.
Connected is reset when a not-connected, bad
error, or initializing control frame is received.

Bit 6, 5 - Response ID

The following table defines the meaning of these

two bits:

Bit 6 Bit 5
RB1 RBO Type of Response

0 0 Acknowledge

0 1 Frame Reject
1 0 Not Connected

Response 10 in Cluster Table Status Entry

36 Cluster Adapter
Bit 4 - Pending (P) is set to 1 by the transmitting station to
indicate that it is waiting for an acknowledge frame
from the destination station, and is reset by the
interrupt handler when a response is received or upon
a time-out.

Bit 3, 2 - Received Frames Sequence Number is incremented

every time a new data-sequenced information frame is
successfully received. This sequence number and the
transmitted frame sequence number are reset to 0
when a connection is established between two
stations.

Bit 1, 0 - Transmitted Frames Sequence Number is incremented

every time a sequenced information frame is
successfully transmitted; that is, an acknowledge is
received from the destination station.

Remote IPL
A vector is established at bootstrap vector INT hex 19 to the
Remote System Reset Program Loader for the cluster, which is
located in adapter 1's ROM. The original contents of the
bootstrap vector are stored at vector INT hex SB. The disk server
station address is stored at the least-significant byte of vector INT
hex El. The number of the adapter from which to IPL is stored
at the word corresponding to the segment at vector INT hex El.

Cluster Adapter 37
The following actions are performed by the Remote System Reset
Program Loader:

1. The Remote System Reset Program Loader (in the Cluster

Adapter's 8088 accessible ROM) uses a portion of the top lK
bytes of memory for variable and buffer space.

2. The bootstrap vector is restored with its original vector (which

was temporarily saved at INT hex SB). The INT hex SB
vector is set to point to the adapter's diagnostic routines.

3. The variables of DLCP are initialized by executing a DLCP

BIOS Cluster Initialization command (hex 00) with
parameters provided by a table of constants in the adapter's
8088 ROM.

4. The user timer-interrupt vector at vector hex 1C is saved at

interrupt vector hex E2 and replaced with the address of a
routine to update a timer count variable used for time-outs by
the Remote System Reset Program Loader. It is restored
before this routine is left.

S. A broadcast frame requesting IPL is sent using the DLCP

BIOS command's Transmit Broadcast Frame (hex 08) to all
stations in the cluster. The format of the data portion of the
frame is:

Command = hex 91 (Request for IPL)

Session ID = hex 0000 (2 bytes)

38 Cluster Adapter
6. An acknowledge information frame is expected with the
following data:

Command = hex 92 (Response to IPL request)

Session ID = hex xxxx (2 bytes)
Status = hex 00 (non-zero is irrecoverable error)

xxxx = any hexidecimal number

The server station's address is saved at the least-significant

byte of vector INT hex E 1.

Up to eight retries are made unless a response from the disk

server station is received. Approximately 4 seconds are
allowed between retries. After the eight retries have been
used, the user timer-interrupt vector is restored and then
control is passed to the bootstrap routine.

Note: If a Keep-Alive command is received from the disk

server station, an additional 30 seconds is allowed.

7. Next, the Remote IPL program requests a data block

containing program code from the disk server station. The
request has the following form:

Command = hex 93 Request IPL data block

Session ID = hex xxxx (2 bytes)
Status = hex 00 (Non-zero is a irrecoverable
error)

xxxx = any hexidecimal number

The request is sent using the DLCP BIOS command's

Transmit Frame (hex 03). Retries are made for up to 20
seconds if the return code indicates a Frame Reject or a No
Response error.

Cluster Adapter 39
8. The disk server sends a response containing the next data
block. The response has the following form:

Command = hex 94 Response with IPL data

block
Session ID = hex xxxx (2 bytes)
Status = hex 00 (N on-zero is a irrecoverable
error)
Sector # = hex xxxx Relative sector number
Data Block = [0-512 bytes] Data Block containing
program code.

xxxx = any hexidecimal number

The DLCP BIOS Receive Frame command (hex 02) is issued

to read the response frame containing the block of program
code. Approximately 20 seconds are allowed to receive a
valid response from the disk server station. If a Keep-Alive
command is received from the disk server station, an
additional 30 seconds are allowed. There is no limit to the
number of Keep-Alive commands that are accepted. On
time-out, the user timer-interrupt vector is restored and
control is passed to the Bootstrap Loader by INT hex 19.

The received sector number must start at zero and increment

for each block of program code received. If the received
sector number is incorrect or if the status is non-zero, then the
user timer-interrupt vector is restored and control is passed to
the bootstrap vector by INT hex 19. The sector number is
two bytes long with the least-significant byte first in the
received data.

40 Cluster Adapter
 The received program code is inserted in memory starting at
location hex 07CO:0000 and continuing upward. The end of
the program code is determined when a frame is received that
does not contain 512 bytes of program code.

9. The above two steps are repeated until the end of the program
code is received. The user timer-interrupt vector is restored
and control passes to the loaded program by a jump to hex
07CO:0000.

Notes:

1. The Remote IPL function is performed, even if local drives are

attached, if the Remote IPL switch on Cluster Adapter 1 is
On. Remote IPL is supported only for Cluster Adapter 1.
The Remote IPL function can be stopped by pressing Control
Break, and normal loading from local diskette drives occurs.

2. For every block of data received, an arrow rotates in a

clockwise direction on the screen.

3. After power on or system reset, the cursor is moved to the

right three columns for about 1 second. Special ROM
diagnostic tests for the adapter can be executed by
immediately pressing" Ctrl D" on the keyboard. Also, a
request to load a general diagnostic program over the cluster
can be selected by pressing "Ctrl L" at which time a blinking
L is displayed. The adapter sends out a broadcast frame
requesting a diagnostic program load. (The first data byte of
the request frame is set to hex 90.)

Cluster Adapter 41
DLCP BIOS Commands
The DLCP BIOS commands are issued by the higher layer
communication program to send and receive information through
the cluster. The following are the DLCP BIOS commands:

Command Number (Hex) Command Name

00 Cluster Initialization
01 Receive Virtual Frame
02 Receive Frame
03 Transmit Frame
04 Reserved
05 Display CI uster Status
06 Cluster Status
07 Status
08 Broadcast Frame
09 Transmit Virtual Frame
OA Stop DLCP
OB Read Station Address
OC Set Multicast Address
OD Check Command In Progress
OE Read IPL Switch
OF Start DLCP
10 Dump Statistics
11 Diagnostic Function 1
12 Diagnostic Function 2
13 Diagnostic Function 3
14 Diagnostic Function 4
15 Diagnostic Function 5
16 Diagnostic Function 6
17 Diagnostic Function 7

DLCP BIOS Commands

42 Cluster Adapter
DLCP Return Codes

The following table indicates the Return Codes that are defined
for the cluster DLCP:

DLCP Return Codes

Return Code Meaning
Hex 00 Successful Completion
Hex 30 Initialization failed
Hex 31 Cluster busy timeout (carrier sense
active for 2 seconds)
Hex 32 Duplicate station address on cluster
Hex 33 No response from destination
Hex 34 Frame rejected at destination
Hex 35 Reserved
Hex 36 Cluster access timeout (could not gain
access to cluster within a 13 second timeout)
Hex 37 Information field too long (more than
578 bytes)
Hex 38 Information field empty
Hex 39 DLCP command in progress
Hex 3A Initialization required
Hex 3B Received frame not available
Hex 3C Error detected with 8031 (due to command
timeout or other processor interface error
Hex 3D Extended return code in cluster status field
Hex 3E Invalid initialization parameters (too many
or too large buffers specified)
Hex 3F Previous DLCP BIOS command initiated
with Initiate Transmit bit set is not complete

Cluster DLCP Return Codes

Note: A return code of hex 00 indicates successful completion

of the DLCP BIOS command. Most of the other return codes
indicate error conditions.

Cluster Adapter 43
Cluster Initialization (DLCP) = Hex 00
Function: This command initializes the DLCP and also transmits
an initializing frame to inform others in the cluster. If
another station in the cluster has the same address as
this station, it sends a response frame indicating
duplicate station address, and the return code is hex
32. The Initialization Control Block (ICB) must be
built by the calling program with the initialization
values indicated by the following:
Return Code Definition

hex 00 Successful completion

hex 30 Initialization failed
hex 32 Duplicate station address in the cluster
hex 39 Command in progress
hex 3C Error with 8031
hex 3E Invalid initialization parameters

Link Control Block (LCB)

Field Value at Entry Value at Exit
Destination Don't Care Unchanged
Source Don't Care Unchanged
Command =00 (Hex) Unchanged
Buffer 1 Length =OF (Hex) Unchanged
Buffer 1 Address Address of Initialization Unchanged
Control Block (ICB)
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter =0 for Adapter 1 Unchanged
= 1 for Adapter 2
=2 for Adapter 3
=3 for Adapter 4
Cluster Initialization (DlCP) = Hex 00

44 Cluster Adapter
Initialization Control Block (lCB)

The calling program must set the buffer 1 address field in the
LCB to the address of an initialization control block (ICB). The
figure below shows the composition and bytes that make up the
ICB:

Byte Byte Definition Value

o (Bits) 7 6 5 4 3 2 1 0 o
(Value) 0 0 0 0 0 NVB MM1 MM2
1 Number of Large Buffers 4
2 Number of Small Buffers 10
3 Large Buffer Size 584 -0- 8
4 Small Buffer Size 40
5 Maximum Number of Retries for No Response 8
6 Maximum Number of Retries for Rejected Frame 2
7 Transmit Access Window (TAW) 40 -0- 2
8 Time Period Reserved for Response 200 -0- 20
9 Time from Frame Start to First Byte 150 -0- 2
10 Time Between Control Field and Data Field 100 -0- 2
11 Timeout Waiting for Response to be Received 300 -0- 6
12 Timeout Waiting for Next Byte to be Received 300 -0- 6
13 Timeout Waiting for Command to Complete 7
14 Timeout Waiting to Access Cluster 200

Initialization Control Block (ICB)

Cluster Adapter 45
Byte 0 - Bits 7,6,5,4, and 3 are reserved and must be set to O.

Bit 2 - No Virtual Buffer (NVB), when set to zero,

allocates a receive buffer for Virtual Frames.

Bit 1 and 0 - These bits are set to enable the first

portion of all frames to be received (even if they are
not addressed to this station).

The following figure shows the Monitor Mode (MM)

bit definitions:

MM1 MMO Monitor Mode Condition

0 0 Normal Mode
0 1 Receives All Frames on Cluster
1 0 Invalid Setting
1 1 Receives Only Frames from or to Multicast
Address or This Station Address

Monitor Mode Bit Definitions

Note: In Monitor Mode, only the first portion of a frame (up

to the size of the small buffer minus 7 bytes) is received. The
first byte is set to the value of Transmit Window Token, and
the second byte corresponds to the first data byte of the
information field of the frame.

46 Cluster Adapter
Byte 1 - This byte indicates the number of large buffers
allocated in the 8031 RAM for incoming frames.

Byte 2- This byte indicates the number of small buffers

allocated in the 8031 RAM for incoming frames.

Byte 3 - This byte indicates the large buffer size (each unit
represents 8 bytes). Six bytes of the large buffer are
reserved for control information.

Byte 4- This byte indicates the small buffer size (each unit
represents 1 byte). Six bytes of the small buffer are
reserved for control information.

Byte 5 - This byte indicates the maximum number of times a

frame is transmitted with no response from the
destination station.

Byte 7 - This byte is used to specify the Transmit Access

Window (TAW) time period in f.LS. For a 40 f.LS
TAW, set this byte to 20. After every transmitted
frame, an Access Time Period is allocated, which is
64 times the TAW time period.

Byte 8- The value of this byte times TAW divided by 2

equals the amount of time (f.Ls.) reserved after each
frame for a response frame to be transmitted.

Cluster Adapter 47
Byte 9 - The value of this byte times 2 equals the delay in p,s
after the start of a transmit frame before the first
byte (destination) is transmitted.

Byte 10 - The value of this byte times 2 equals the delay in p,s
between the control field and data field of a frame.

Byte 11 - The value of this byte times 6 equals the time

allowed in p,s for a response frame to be received.

Byte 12 - The value of this byte times 6 equals the time

allowed in p,s for the next byte of a frame to be
received.

Byte 13 - The value of this byte times 16.7 equals the number
of seconds allowed for any command in progress to
finish before the 8031 indicates error hex 3C to the
Cluster Adapter BIOS code.

Byte 14 - The value of this byte times 67 milliseconds equals

the amount of time allowed waiting to access the
cluster before error hex 36 is returned.

48 Cluster Adapter
Receive Virtual Frame = Hex 01
Function: This command is used to retrieve a data frame sent by
the disk server (using Transmit Virtual Frame).

Notes:

1. There is only one virtual frame buffer for this type of data
frame.

2. The destination, command, and cluster status fields in the

LCB are modified.
Return Code Destination

hex 00 Successful completion

hex 32 Duplicate station address in the cluster
hex 37 Information field too long
hex 38 No information field present
hex 39 Command in progress
hex 3A Initialization required
hex 3B No receive frame exists
hex 3C Error detected with 8031

Cluster Adapter 49
 Link Control Block (LCB)
Field Value at Entry Value at Exit
Destination Don't Care Destination
Source Don't Care Source
Command = 01 (Hex) Frame Control
Buffer 1 Length Length of Calling Length of Received Data if
Program's Buffer 1 Less Tha n Buffer 1 Le ngth
Buffer 1 Address Points to Calling Unchanged
Program's Buffer 1
Buffer 2 Length Length of Ca II i ng Length of Received Data
Program's Buffer 2 Placed in This Buffer
Buffer 2 Address Points to Calling Unchanged
Program's Buffer 2
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Frame Sequence
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Receive Virtual I/O Frame Hex 01

50 Cluster Adapter
Receive Frame (from FIFO queue) = Hex 02
Function: This command is used to retrieve a data frame sent
from another station (using Transmit Frame) from the
First-In-First-Out (FIFO) queue.

The FIFO queue can contain four full size frames and
10 small frames.

Note: The field's destination, command, and cluster status in

the LCB are modified.

Note: If the adapter is in Monitor mode, the first byte

returned is the Transmit Window Token. The second byte is
the first data byte of the information field of the received
frame.
Return Code Definition

hex 00 Successful completion

hex 32 Duplicate station address in the cluster
hex 37 Information field too long
hex 38 No information field present
hex 39 Command in progress
hex 3A Initialization required
hex 3B No receive frame exists
hex 3C Error detected with 8031

Cluster Adapter 51
 Link Control Block (LCB)
Field Value at Entry Value at Exit
Desti nation Don't Care Destination
Source Don't Care Source
Command = 02 (Hex) Frame Control
Buffer 1 Length Length of Calling Length of Received Data if
Program's Buffer 1 Less Than Buffer 1 Length
Buffer 1 Address Points to Calling Unchanged
Program's Buffer 1
Buffer 2 Length Length of Calling Length of Received Data
Program's Buffer 2 Placed in This Buffer
Buffer 2 Address Points to Calling Unchanged
Program's Buffer 2
Return Code Don't Care Set to Return Code
CI uster Status Don't Care Frame Sequence
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Receive Frame (from FIFO Queue) Hex 02

52 Cluster Adapter
Transmit Frame = Hex 03
Function: This command is used to transmit a data frame to
another station where it can be retrieved by using the
Receive Frame command.

Note: See also "Special Transmit Mode Command Bits" on

page 81
Return Code Definition

hex 00 Successful completion

hex 31 Cluster always busy
hex 32 Duplicate station address in the cluster
hex 33 No response from destination
hex 34 Exceed allowed number of rejected frames

hex 36 Cluster access time-out

hex 37 Information field too long (frame is not
sent)
hex 38 No information field present (frame is not
sent)
hex 39 Command in progress
hex 3A Initialization required
hex 3C Error detected with 8031

Cluster Adapter 53
 Link Control Block (LCB)
Field Value at Entry Value at Exit
Destination Destination Unchanged
Source Don't Care Unchanged
Command =03 (Hex) Unchanged
Buffer 1 Length Length of Calling Unchanged
Program's Buffer 1
Buffer 1 Address Points to Calling Unchanged
Program's Buffer 1
Buffer 2 Length Length of Calling Unchanged
Program's Buffer 2
Buffer 2 Address Points to Calling Unchanged
Program's Buffer 2
Return Code Don't Care Set to Return Code
CI uster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Transmit Frame = Hex 03

54 Cluster Adapter
Display Cluster Status = Hex 05
Function: This command is used to determine and then display
the cluster status. The On/Off status of 64 stations is
displayed. Stations that have the Power switch set to
On are displayed in reverse video. Your station is
displayed in reverse video and blinking. If another
station in the cluster has the same address as your
station, a long beep sounds. Only those stations that
are initialized can be displayed.

Note: The screen should be cleared before issuing this

command.

Note: Type of status (destination field):

hex 00 = report stations that are On

hex FF = report stations that are initialized

Return Code Definition

hex 00 Successful completion

hex 31 Cluster always busy
hex 36 Cluster access time-out
hex 39 Command in progress
hex 3C Error detected with 8031

Cluster Adapter 55
 Link Control Block (LCB)
Field Value at Entry Value at Exit
Destination Type of Status Unchanged
Source Don't Care Unchanged
Command = 05 (Hex) Unchanged
Buffer 1 Length Number of Stations Unchanged
to Display
Buffer 1 Address Don't Care Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Extended Return Code on
Error
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Display Cluster Status = Hex 05

56 Cluster Adapter
This page explains the cluster status that may appear on your
screen.

NN is any station address from 0 to 63.

The station you are using is indicated on the screen

in blinking reverse video, and the box is marked by
two asterisks.

Stations that have their Power switches set to On

are displayed in reverse video, and their boxes are
marked by two Xs.

Another station has the same address as your

station; a long beep sounds every 3 seconds, the
box is displayed in blinking reverse video, and is
marked by an X and an asterisk.

A station address not in the cluster is indicated by a

box displayed in normal video and not marked with
XS or asterisks.

Cluster Adapter 57
Cluster Status = Hex 06
Function: This command determines the stations' OnlOff
status. The status bytes are stored in buffer 1 (as
determined by the buffer 1 pointer in the LCB). The
first byte's least-significant bit is the status of station
O. Bit 1 represents station 1. The least-significant bit
of the second byte is the status of station 8, and so on.
The number of stations checked is a parameter of this
command. Only those stations that are initialized are
reported.

Notes:

1. Type of status (destination field):

hex 00 = report stations that are On
hex FF = report stations initialized
2. See also "Special Transmit Mode Command Bits" on page 81
3. The size of the buffer required to store the cluster status bytes
is (number of stations to check + 7)-;.-8.
Return Code Definition

hex 00 Successful completion

hex 31 Cluster always busy
hex 36 Cluster access time-out
hex 39 Command in progress
hex 3C Error detected with 8031

58 Cluster Adapter
 Link Control Block (LCB)
Field Value at Entry Value at Exit
Destination Type of Status Unchanged
Source Don't Care Unchanged
Command = 06 (Hex) Unchanged
Buffer 1 Length N umber of Stations Unchanged
to Check
Buffer 1 Address Points to Calling Unchanged
Program's Buffer 1
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Extended Return Code
on Error
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Cluster Status Hex06

Cluster Adapter 59
Status - Hex 07

Function: This command is used to return the status of the

connection with a particular station,
Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031

Link Control Block (LCB)

Field Value at Entry Value at Exit
Desti nation Stations for Wh ich Unchanged
Status is Desired
Source Don't Care Unchanged
Command = 07 (Hex) Unchanged
Buffer 1 Length Don't Care Unchanged
Buffer 1 Address Don't Care Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
CI uster Status Don't Care Cluster Status
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Status = Hex 07

60 Cluster Adapter
Transmit Broadcast Frame = Hex 08
Function: This command is used to transmit a data frame to
another station where it can be retrieved by using the
Receive Frame command. No acknowledgment to the
frame is sent by the receiving stations.

Note: Transmit Frame and Transmit Virtual Frames are

converted to Broadcast Frames if the destination station
number is greater than 127.

Note: See also "Special Transmit Mode Command Bits" on

page 81..
Return Code Definition

hex 00 Successful completion

hex 31 Cluster always busy
hex 32 Duplicate station address in cluster
hex 36 Cluster access time-out
hex 37 Information field too long (frame is not
sent)
hex 38 No information field present (frame is not
sent)
hex 39 Command in progress
hex 3A Initialization required
hex 3C Error detected with 8031

Cluster Adapter 61
 Link Control Block (LCB)
Field Value at Entry Value at Exit
Destination Destination Unchanged
Source Don't Care Unchanged
Command = 08 (Hex) Unchanged
Buffer 1 Length Length of Calling Unchanged
Program's Buffer 1
Buffer 1 Address Points to Calling Unchanged
Program's Buffer 1
Buffer 2 Length Length of Calling Unchanged
Program's Buffer 2
Buffer 2 Address Points to Calling Unchanged
Program's Buffer 2
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Transmit Broadcast Frame Hex 08

62 Cluster Adapter
Transmit Virtual Frame = Hex 09
Function: This command is used to transmit a data frame
containing sector information from the disk server
station. The information can be retrieved only by
using the Receive Virtual Frame command.

Note: See "Special Transmit Mode Command Bits" on page

81
Return Code Definition

hex 00 Successful completion

hex 31 Cluster always busy
hex 32 Duplicate station address in cluster
hex 33 No response from destination
hex 34 Frame rejected at destination

hex 36 Cluster access time-out

hex 37 Information field too long (frame is not
sent)
hex 38 No information field present (frame is not
sent)
hex 39 Command in progress
hex3A Initialization required
hex 3C Error detected with 8031

Cluster Adapter 63
 link Control Block (LCB)
Field Value at Entry Value at Exit
Destination Desti nation Unchanged
Source Don't Care Unchanged
Command = 09 (Hex) Unchanged
Buffer 1 Length Length of Calling Unchanged
Program's Buffer 1
Buffer 1 Address Points to Calling Unchanged
Program's Buffer 1
Buffer 2 Length Length of Calling Unchanged
Program's Buffer 2
B uffe r 2 Add ress Points to Calling Unchanged
Program's Buffer 2
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Transmit Virtual Disk Frame Hex 09

64 Cluster Adapter
Stop DLCP = Hex OA
Function: This command is used to temporarily inhibit the
DLCP from receiving or transmitting frames. Issue a
Start DLCP command to leave the stopped state.

Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3A Initialization required
hex 3C Error detected with 8031

Link Control Block (LCB)

Field Value at Entry Value at Exit
Destination Don't Care Unchanged
Source Don't Care UnChanged
Command = OA (Hex) Unchanged
Buffer 1 Length Don't Care Unchanged
Buffer 1 Address Don't Care Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Dont' Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Stop DlCP = Hex OA

Cluster Adapter 65
Read Station Address = Hex OB
Function: This command is used to return the address and state
of the remote IPL switch of this station.
Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex3C Error detected with 8031

Link Control Block (LCB)

Field Value at Entry Value at Exit
Destination Don't Care Unchanged
Source Don't Care This station's address
Command =OB (Hex) Unchanged
Buffer 1 Length Don't Care Unchanged
Buffer 1 Address Don't Care Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care 00 = No IPL FF = IPL
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Read Address = Hex 08

66 Cluster Adapter
Set Multicast Address = Hex OC
Function: This command is used to set the desired multicast
address. The multicast address is a variation of the
broadcast address (hex FF). More than one station
may be assigned the same multicast address. A
default value of hex FF is set when a cluster
Initialization command is issued to the DLCP. A
frame sent, using the Transmit Broadcast Frame
command (8), to the group multicast address is
received by all stations that share the multicast
address.
Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031

Link Control Block (lCB)

Field Value at Entry Value at Exit
Destination Desired Multicast Unchanged
Address
Source Don't Care Unchanged
Command = OC (Hex) Unchanged
Buffer 1 length Don't Care Unchanged
Buffer 1 Address Don't Care Unchanged
Buffer 2 length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Set Multicast Address = Hex DC

Cluster Adapter 67
Check Inside DLCP Flag = Hex on
Function: This command is used to return an indication that a
DLCP command is already in progress. This
command is necessary orily for programs that call
DLCP from inside an interrupt routine. If a DLCP
command is already in progress, the interrupt routine
should return to the interrupted program to allow the
current DLCP command to finish.
Return Code Definition

hex 00 Command not in progress

hex 39 Command in progress
hex 3C Error detected with 8031

Link Control Block (LeB)

Field Value at Entry Value at Exit
Oes~ination Don't Care Unchanged
Source Don't Care Unchanged
Command = 00 (Hex) Unchanged
Buffer 1 Length Don't Care Unchanged
Buffer 1 Address Don't Care Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Check Inside DLCP Flag = Hex 00

68 Cluster Adapter
Read IPL Switch = Hex OE
Function: This command is used to read the state of the Remote
IPL switch on the requesting station.

Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031

Link Control Block (LCB)

Field Value at Entry Value at Exit
Desti nation Don't Care Unchanged
Source Don't Care This station's address
Command = OE (Hex) Unchanged
Buffer 1 Le ngth Don't Care Unchanged
Buffer 1 Address Don't Care Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care IPL Switch (00 = No IPL
FF = IPL)
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Read IPL Switch = Hex OE

Cluster Adapter 69
Start DLCP = Hex OF
Function: This command is used to release the DLCP from the
stopped state. It enables the DLCP to receive and
transmit frames.
Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3A Initialization required
hex 3C Error detected with 8031

Link Control Block (LCB)

Field Value at Entry Value at Exit
Destination Don't Care Unchanged
Source Don't Care Unchanged
Command = OF (Hex) Unchanged
Buffer 1 Length Don't Care Unchanged
Buffer 1 Address Don't Care Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Add ress Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Start DLCP = Hex OF

70 Cluster Adapter
Dump Statistics = Hex 10
Function: This command is used to transfer the current
communication statistics block from the adapter.

Link Control Block (LCB)

Field Value at Entry Value at Exit
Destination Don't Care Unchanged
Source Don't Care Unchanged
Command = 10 (Hex) Unchanged
Buffer 1 Length 12 bytes Unchanged
Buffer 1 Address Points to Calling Unchanged
Program's Buffer 1
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Dump Statistics = Hex 10

Cluster Adapter 71
Communication Statistics Block (CSB)

The Cluster Adapter returns information regarding previous

activity in the CSB.

Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031

The figure below shows the composition and definition of the

CSB bytes:

Byte Definition
0 Number of Times No Response Received (LSB)
1 Number of Times No Response Received (MSB)
2 Number of Times Frame Rejects Received
3 Number of Control Frames Correctly Received (LSB)
4 Number of Control Frames Correctly Received (MSB)
5 Number of Data Frames Correctly Received (LSB)
6 Number of Data Frames Correctly Received (MSB)
7 Number of Control Frames with CRC Error
8 Number of Data Frames with CRC Error
9 Number of Duplicate Frames Received
10 Number of Received Frames That Were Rejected
11 Number of Transmit Collisions

Communication Statistic Block

72 Cluster Adapter
Diagnostic Function 1 = Hex 11
Function: This command is used to run an internal diagnostic
test.

(Reserved for diagnostic use only.)

Bit 1 Test adapter processor-to-processor interface

Bit 2 Reserved
Bit 3 Test driver and receiver logic (terminating plug required
for diagnostic use)
Bit 4 Test interrupt logic (set transmit interrupt status bit)
Bit 5 Test interrupt logic (set receive interrupt status bit)
Bit 6 Clear transmit and receive interrupt status bits (no
interrupt)
Bit 7 Set transmit and receive interrupt status bits (no
interrupt)
Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031
hex 3D Error detected by 8031 diagnostic test
(reason for error in Cluster Status field)

Cluster Adapter 73
 Link Control Block (LCB)
Field Value at Entry Value at Exit
Destination Test Number ** Unchanged
Source Don't Care Unchanged
Command = 11 (Hex) Unchanged
Buffer 1 Length Don't Care Unchanged
Buffer 1 Address Don't Care Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Don't Care Unchanged
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Extended Return Code
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Diagnostic Function 1 = Hex 11

Note: ** Test number (Destination field)

74 Cluster Adapter
Diagnostic Function 2 = Hex 12
Function: This command is used to transfer data to the adapter's
RAM from a buffer in system memory. The data in
buffer 1 is transferred to the address specified by
buffer 2 in the 8031 address space.

(Reserved for diagnostic use only.)

Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031

Link Control Block (LCB)

Field Value at Entry Value at Exit
Destination Don't Care Unchanged
Source Don't Care Unchanged
Command = 12 (Hex) Unchanged
Buffer 1 Length Length of Calling Unchanged
Program's Buffer 1
Buffer 1 Address Poi nts to Buffer 1 Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Set Offset to Address Unchanged
in 8031 RAM Space
to Place Data
Return Code Don't Care Set to Ret u rn Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Diagnostic Function 2 = Hex 12

Cluster Adapter 75
Diagnostic Function 3 = Hex 13
Function: This command is used to transfer data from the
adapter's RAM to a buffer in system memory. The
data is transferred starting at the address specified by
the buffer 2 address (offset) in 8031 memory to
buffer 1 in the main system's memory.

(Reserved for diagnostic use only.)

Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031

Link Control Block (LCB)

Field Value at Entry Value at Exit
Destination Don't Care Unchanged
Source Don't Care Unchanged
Command = 13 (Hex) Unchanged
Buffer 1 Length Length of Calling Unchanged
Program's Buffer 1
Buffer 1 Address Poi nts to Buffer 1 Unchanged
Buffer 2 Lerigth Don't Care Unchanged
Buffer 2 Address Set Offset to Address Unchanged
in 8031 RAM Space
from Which to get
Data
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Diagnostic Function 3 = Hex 13

76 Cluster Adapter
Diagnostic Function 4 = Hex 14
Function: This command is used to transfer data to the 8031 's
internal RAM from a buffer in system memory. The
data in buffer 1 is transferred to the address specified
by buffer 2 address in 8031 memory.

(Reserved for diagnostic use only.)

Note: Extreme care must be used to prevent destroying data

in the 8031 's stack and registers in this internal chip RAM.
Also, there are only 128 bytes of RAM.
Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031

Link Control Block (lCB)

Field Value at Entry Value at Exit
Desti nat ion Don't Care Unchanged
Source Don't Care Unchanged
Command = 14 (Hex) Unchanged
Buffer 1 Length Length of Calling Unchanged
Program's Buffer 1
Buffer 1 Address Po i nts to Buffer 1 Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Set Offset to Address Unchanged
in 8031 on Chip
Space to Place Data
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Ada pter 2
= 2 for Adapter 3
= 3 for Adapter 4

Diagnostic Function 4 = Hex 14

Cluster Adapter 77
Diagnostic Function 5 = Hex 15
Function: This command is used to transfer data from the
8031 's internal RAM to a buffer in system memory.
The data is transferred starting at the address
specified by buffer 2 address (offset) in 8031 memory
to buffer 1 in the main system's memory.

(Reserved for diagnostic use only.)

Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031

link Control Block (LCB)

Field Value at Entry Value at Exit
Desti nation Don't Care Unchanged
Source Don't Care Unchanged
Command = 15 (Hex) Unchanged
Buffer 1 Length Length of Calling Unchanged
Program's Buffer 1
Buffer 1 Address Points to Buffer 1 Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Set Offset to Address Unchanged
in 8031 RAM from
Which to Get Data
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Diagnostic Function 5 = Hex 15

78 Cluster Adapter
Diagnostic Function 6 = Hex 16
Function: This command is used to execute an 8031 program at
the address specified by the buffer 2 address field. A
"Call" is made to that address and it is expected that
the called program sets the 8031 accumulator to a
return code value before returning. This return code
is placed in the Cluster Status field if non-zero.

(Reserved for diagnostic use only.)

Return Code Definition

hex 00 Successful completion

hex 39 Command in progress
hex 3C Error detected with 8031
hex 3D Extended return code in cluster status

Link Control Block (LCB)

Field Value at Entry Value at Exit
Destination Don't Care Unchanged
Source Don't Care Unchanged
Command = 16 (Hex) Unchanged
Buffer 1 Length Don't Care Unchanged
Buffer 1 Address Don't Care Unchanged
Buffer 2 Length Don't Care Unchanged
Buffer 2 Address Set Offset to Address Unchanged
in 8031 RAM Space
where a Callable
Program Exists
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Extended Return Code
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Diagnostic Function 6 = Hex 16

Cluster Adapter 79
Diagnostic Function 7 = Hex 17
Function: This command is used to transmit any type of frame
to another station. For example, a control frame may
be sent to another station.

(Reserved for diagnostic use only.)

Return Code Definition

hex 00 Successful completion

hex 31 Cluster always busy
hex 32 Duplicate station address in cluster
hex 33 No response from destination
hex 34 Exceeded allowed rejected frames
hex 36 Cluster access time-out
hex 37 Information field too long
hex 39 Command in progress
hex 3A Initialization required
hex 3C Error detected with 8031

Link Control Block (LCB)

Field Value at Entry Value at Exit
Destination Destination Unchanged
Source Frame Type Unchanged
Command = 17 (Hex) Unchanged
Buffer 1 Length Length of Calling Unchanged
Program's Buffer 1
Buffer 1 Address Points to Calling Unchanged
Program's Buffer 1
Buffer 2 Length Length of Calling Unchanged
Program's Buffer 2
Buffer 2 Address Points to Calling Unchanged
Program's Buffer 2
Return Code Don't Care Set to Return Code
Cluster Status Don't Care Unchanged
Select Adapter = 0 for Adapter 1 Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4

Diagnostic Function 7 = Hex 17

80 Cluster Adapter
Special Transmit Mode Command Bits
The three most-significant bits in the command field of the LCB
have the following meanings for transmit commands:

Name Bit Meaning

Initiate Transmit 7 Initiate transmit operation but return before
complete with return code set to immediate
result.
Finish Transmit 6 Wait for previously started transmit operation
to complete. Return with return code in LCB
set to result of transmit operation.
Return Status 5 If the transmit operation is complete, the
return code is set to hex 00 (transmit.operation
complete result available). Otherwise the
return code is set to hex 3F (transmit operation
not complete).

Special Transmit Command Bits

Notes:

1. These special transmit command bits are valid only for the
following DLCP BIOS commands:

Transmit Frame (hex 03)

Cluster Status (hex 06)
Transmit Broadcast (hex 08)
Transmit Virtual Frame (hex 09)

2, A transmit operation started with the Initiate Transmit bit set

to 1 must be finished by issuing the same transmit command,
with a different LCB and the Finish Transmit bit set to 1. If
the immediate return code was not zero, the transmit
operation is already complete.

3. If an interrupt handler is being used for receive frames, an

interrupt is also generated when the transmit operation is
complete for transmit operations initiated with the Initiate
Transmit bit set. The Transmit Interrupt status bit is set to 1
to indicate that the transmit operation is complete. This bit is
bit 0 of adapter port hex 0792 (for adapter 1).

Cluster Adapter 81
82 Cluster Adapter
Interface

System Processor 1/0 Interface

Four Cluster Adapters can be installed at each station. The
Cluster Adapter number is selected by switch positions 1 through
4 of switch block 2. These positions correspond to 1/ 0 address
bits 10, 11, 12, and 13. An adapter is selected when a select
switch is On, and the adapter receives a high level (1) on the
corresponding 110 address bit.

Note: High level is 1 and low level is 0.

If mUltiple Cluster Adapters are installed at a station, each

adapter can have only one address select switch set to On. A
station cannot have two Cluster Adapters with the same address.

Notes:

1. When more than one address select switch is On, the Cluster
Adapter decodes and responds to all I/O addresses selected.
2. Cluster Adapter 1 is the only adapter that decodes and
responds to all memory addresses; therefore, if more than one
Cluster Adapter is set as number 1 (Cl), undesirable results
occur.
3. If a Cluster Adapter does not have a select switch set to On, it
does not respond.

Cluster Adapter 83
Cluster Adapter Switch Settings
Cluster Adapter addresses and functions can be selected by two
eight-switch dual in-line package (DIP) switch blocks. The
following shows the switch assignments:

Notes:

1. Switch 8 of switch block 1 selects remote initial program load

(IPL) when in the On position.
2. Switch 7 of switch block 1 is reserved. It must be in the Off
position.

Switch Legend Function

SW-8 IPL Remote IPL
SW-7 N/A Reserved (Must be Off)
SW-6 A5 Station Address Bit 5
SW-5 A4 Station Address Bit 4
SW-4 A3 Station Address Bit 3
SW-3 A2 Station Address Bit 2
SW-2 A1 Station Address Bit 1
SW-1 AO Station Address Bit 0

Switch Block 1 Bit Assignments

Switch Legend Function

SW-8 N/A Reserved
SW-7 ROY 1/0 Channel Ready
SW-6 N/A Reserved
SW-5 N/A Reserved
SW-4 C4 Select Adapter 4
SW-3 C3 Select Adapter 3
SW-2 C2 Select Adapter 2
SW-1 C1 Select Adapter 1

Switch Block 2 Bit Assignments

84 Cluster Adapter
The following shows the station-address switch settings on switch
block 1.

Switch Block 1 Switch Settings

Station SW 1 SW2 SW3 SW4 SW5 SW6

0 Off Off Off Off Off Off
1 On Off Off Off Off Off
2 Off On Off Off Off Off
3 On On Off Off Off Off
4 Off Off On Off Off Off
5 On Off On Off Off Off
6 Off On On Off Off Off
7 On On On Off Off Off
8 Off Off Off On Off Off
9 On Off Off On Off Off
10 Off On Off On Off Off
11 On On Off On Off Off
12 Off Off On On Off Off
13 On Off On On Off Off
14 Off On On On Off Off

Notes:
1. Bit switches 7 and 8 are not appl icable to the station address.
2. "On" represents the closed/on position.
3. "Off" represents the open/off position.

Station Address Switch Settings

Cluster Adapter 85
 Switch Block 1 Switch Settings
Station SW 1 SW2 SW3 SW4 SW5 SW6
15 On On On On Off Off
16 Off Off Off Off On Off
17 On Off Off Off On Off
18 Off On Off Off On Off
19 On On Off Off On Off
20 Off Off On Off On Off
21 On Off On Off On Off
22 Off On On Off On Off
23 On On On Off On Off
24 Off Off Off On On Off
25 On Off Off On On Off
26 Off On Off On On Off
27 On On Off On On Off
28 Off Off On On On Off
29 On Off On On On Off
30 Off On On On On Off
31 On On On On On Off
32 Off Off Off Off Off On

Station Address Switch Settings

86 Cluster Adapter
 Switch Block 1 Switch Settings
Station SW1 SW2 SW3 SW4 SW5 SW6
33 On Off Off Off Off On
34 Off On Off Off Off On
35 On On Off Off Off On
36 Off Off On Off Off On
37 On Off On Off Off On
38 Off On On Off Off On
39 On On On Off Off On
40 Off Off Off On Off On
41 On Off Off On Off On
42 Off On Off On Off On
43 On On Off On Off On
44 Off Off On On Off On
45 On Off On On Off On
46 Off On On On Off On
47 On On On On Off On
48 Off Off Off Off On On
49 On Off Off Off On On
50 Off On Off Off On On

Station Address Switch Settings

Cluster Adapter 87
 Switch Block 1 Switch Settings

Station SW 1 SW2 SW3 SW4 SW5 SW6

51 On On Off Off On On
52 Off Off On Off On On
53 On Off On Off On On
54 Off On On Off On On
55 On On On Off On On
56 Off Off Off On On On
57 On Off Off On On On
58 Off On Off On On On
59 On On Off On On On
60 Off Off On On On On
61 On Off On On On On
62 Off On On On On On
63 On On On On On On

Station Address Switch Settings

88 Cluster Adapter
The following I/O addresses are assigned to the Cluster
Adapters:

I/O Address
Adapter (Hex) Device
Adapter 1 0790 Adapter Status Register
0791 Adapter Command/Data (Output)
Adapter Result/Data (Input)
0792 Adapter Interrupt Register
0793 Adapter Reset Control
Adapter 2 0890 Adapter Status Register
0891 Adapter Command/Data (Output)
Adapter Result/Data (Input)
0892 Adapter Interrupt Register
0893 Adapter Reset Control
Adapter 3 1390 Adapter Status Register
1391 Adapter Command/Data (Output)
Adapter Result/Data (Input)
1392 Adapter Interrupt Register
1393 Adapter Reset Control
Adapter 4 2390 Adapter Status Register
2391 Adapter Command/Data (Output)
Adapter Result/Data (Input)
2392 Adapter Interrupt Register
2393 Adapter Reset Control

Cluster Adapter I/O Summary

The Adapter Reset command resets the 8031 and 8255 on a

Cluster Adapter by writing a 1 to that adapter's Adapter
Reset/Interrupt Disable port address. This sets a 74LS74 latch,
which remains set until a 0 is written to the same port. The latch
must remain set for a minimum of 2 MS, which is the minimum
reset time of the 8031 operating at 12 MHz.

The interrupts on a Cluster Adapter can be disabled by writing a

o to the Adapter Reset/Interrupt Disable port, when -lOW is
active (0).

Cluster Adapter 89
The Cluster Adapter can drive the I/O Channel Ready line low in
synchronization with the system clock when the processor reads
from the adapter card. This enables a longer read cycle from the
expansion slots. The option is selected by setting the I/O
Channel Ready switch (switch 7 of switch block 2) to On.

System Processor Memory Interface

The memory addresses assigned to the Cluster Adapter are hex
DOOOO through hex D7FFF. These addresses are fully decoded
only on adapter 1, and are selected by setting the C 1 select switch
(SW2-1) to On. Each station must have one Cluster Adapter
selected as number 1.

System Processor Interrupt Interface

The Cluster Adapter provides an interrupt interface to the system
processor with Interrupt Request 3 (IRQ3) or Interrupt Request 7
(lRQ7). The desired interrupt is selected using the interrupt
select jumper on the Cluster Adapter. The selection of the
interrupt is dependent on the programming requirements.

90 Cluster Adapter
The following is a sequence of the interrupt process for adapter 1:

1. The system processor enables interrupts by writing to the

adapter interrupt enable register at address hex 0792.

2. Upon receipt of an interrupt condition, the 8031 sends a

negative active (0) pulse of 10 IJ-S on the port C bit 0 (PCO)
line of the 8255 which is connected to IRQ3 or IRQ7. The
low-to-high transition of this line prevents this adapter and
other Cluster Adapters in the system from generating further
interrupt requests. The 8031 processor also sets either Port
C1 (PCl) or Port C2 (PC2) of the 8255 to indicate the
source of the interrupt. PC 1 corresponds to a transmit
interrupt, and PC2 corresponds to a receive interrupt. If both
PC 1 and PC2 are set, the source of the interrupt is the
completion of a Cluster Status command.

3. The system processor reads I/O addresses hex 0792, OB92,

1392, and 2392 on each Cluster Adapter to determine the
cause of the interrupt. After all pending requests are handled,
the system processor re-enables interrupts on all desired
adapters.

8255 Programmable Peripheral Interface

(PPI)
The 8255 is used to provide an asynchronous interface between
the system processor and the 8031 Microcomputer without the
use of interrupts or direct memory access (DMA).

Cluster Adapter 91
PortA
Port A is operated in mode 2 as a strobed, bidirectional, I/O bus.
In this mode, all eight bits of Port A (PAO through PA7) are
dedicated to data transfer between the microcomputer (8031) and
the system processor (8088).

PortH
Port B is operated in mode o. The low-order six bits (PBO
through PB5) provide the station address, and the high-order bit
(PB7) provides the Remote IPL (On/Off) status. Bit 7 (PB6 is
reserved). The source of information for Port B is switch block 1.
When a bit switch is On, the bit is active (low). The
microprocessor code in the 8031 complements the Port B
information to produce logical 1 active bits.

Port C
When port C is operated in mode 2, five lines are dedicated as
handshaking signals. The following four handshaking signals are
used by the Cluster Adapter:

• -Output Buffer Full (-OBF)

A low signal on the -OBF (PC7) line indicates that the

microcomputer (8031) has written data to Port A. -OBF
provides status to the adapter status register.

• -Acknowledge (-ACK)

A low signal on the -ACK (PC6) line enables the tri-state

output buffer of Port A to send out data to the system
processor (8088); otherwise the output is in a high
impedance state.

92 Cluster Adapter
• Input Buffer Full (IBF)

A high signal on the IBF (PC5) output indicates that data

from the 8088 has been loaded into Port A. IBF provides
input to the adapter status register and to the 8031.

• -Strobe Input (-STB)

A low signal on the -STB (PC4) loads data from the 8088
into Port A.

The following is a summary of the 8255 port signals:

8255 Port Signals

PortA Port B Port C
Bit Mode 2 Mode 0 Mode 2
7 Data Bit 7 Remote IPL -OBF
6 Data Bit 6 Reserved -ACK
5 Data Bit 5 Station Address Bit 5 +IBF
4 Data Bit 4 Station Address Bit 4 -STB
3 Data Bit 3 Station Address Bit 3 Reserved
2 Data Bit 2 Station Address Bit 2 Receive Frame Interrupt
1 Data Bit 1 Station Address Bit 1 TX Complete Interrupt
0 Data Bit 0 Station Address Bit 0 Interrupt Request

Summary of 8255 Port Signals

Cluster Adapter 93
Cluster Bus Interface
The bus interface consists of a transmitter, receiver, carrier sense
circuitry, and internalloopback-mode logic. They are the
interface between the 8031 serial port and the 75Q coaxial cable.

Cluster Adapter Transmitter

The Cluster Adapter transmitter consists of an Am26LS29
tri-state, single-ended, line driver. This driver features a high
capacitive-load drive capability with buffered outputs, individual
rise-time control, and output short-circuit protection.

To transmit data to the bus, the microprocessor code in the 8031

must first enable the -RTS signal on the port 3 interface. Data
can then be sent to the bus bit-by-bit from + TXD on port 3.

The transmitter is electrically isolated from the logic circuits on

the Cluster Adapter by an HCPL-2531 high-speed optocoupler,
which uses a light-emitting diode and an integrated light detector
to obtain electrical insulation.

Cluster Adapter Receiver

The Cluster Adapter receiver consists of an Am26LS34
high-performance, differential line receiver.

The received signal is amplified by a 5535 Operational Amplifier

and is provided to the Am26LS34. To receive the digital data, the
microprocessor code in the 8031 must ensure that the + Internal
Loop signal on port 3 is inactive. Data can then be received
bit-by-bit at port 3 from +RXD.

The receiver is also electrically isolated from the logic circuits on

the Cluster Adapter by an HCPL-2531 high-speed optocoupler.

94 Cluster Adapter
Carrier Sense Circuitry
The carrier sense circuitry provides information about the state of
the Cluster Adapter. This information is needed to implement
the collision avoidance protocol. The amplified signal received
from the bus is passed through a comparator to detect the
negative voltage state (less than approximately -150 millivolts).
This negative portion of the signal is inverted into + NRXD and
then ORed with the positive portion (greater than approximately
+ 150 millivolts) of the +RXD signal. The result is then sent to
the clear input of a 74LS161 counter. As long as this ORed
signal (CLR) is active (0), the counter is held reset. When the
signal goes inactive (1), the counter begins counting on the rising
edges of the 8031 +ALE signal. On the fourth +ALE pulse, the
counter is disabled and the -Carrier Sense signal goes inactive (1).
The time delay between the bus going inactive and -Carrier Sense
going inactive is 1.5 fJ,S.

Internal Loopback Mode

The Cluster Adapter provides logic to allow the 8031 to receive
the data it is transmitting without interference from the bus by
wrapping the transmitter to the receiver on the Cluster Adapter.

The adapter is placed into internal loop back mode when the 8031
microprocessor code sets the + Internal Loop signal active (1).
This mode returns any data transmitted on + TXD to +RXD.
Notice that -RTS mayor may not be active. If -RTS is active, the
data not only returns to +RXD, but also is transmitted to the bus.

Cluster Adapter 95
Specifications

Ballpoint
Pen

Rocker
Switch

Shield

96 Cluster Adapter
Logic Diagrams

The following pages contain logic diagrams.

Cluster Adapter 97
 ."'~~
+Al~

...
+ All

...

DECOUI'lI.StAPS
tl-(:5, CHI!, C14, CIS. Cl~

Cluster Adapter (Sheet 1 of 3)

98 Cluster Adapter
HR'UDR BIT 1
+11' IOOR BIT 0

+ RlD
+ TID
- CIIC un
:~~~R"L lOIlP
-CAflRIERS[ISE

{7.<>-C>'~
,~,
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Cluster Adapter 99
 I 018
.---------''--'0 lUZ I

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Cluster Adapter (Sheet 2 of 3)

1 00 Cluster Adapter
 I-----I-I~-----~----------I

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Cluster Adapter (Sheet 3 of 3)
102 Cluster Adapter
Index

adapter reset 89
address switch settings 85

B
BIOS interface 20
block diagram 3

c
check inside DLCP flag 68
cluster access protocol 29
Cluster Adapter 1
adapter reset 89
address switch settings 85
BIOS interface 20
block diagram 3
bus interface 94
check inside DLCP flag 68
cluster access protocol 29
cluster initialization (DLCP initialization) 44
cluster status 58
cluster status table 35
collision avoidance 30
control field format 25
diagnostic function 1 73

Index-l
 diagnostic function 2 75
diagnostic function 3 76
diagnostic function 4 77
diagnostic function 5 78
diagnostic function 6 79
diagnostic function 7 80
display cluster status 55
DLCP BIOS commands 42
dump statistics 71
error detection and recovery 34
frame format 24
frame reception 33
frame transmission 22
I/O addresses 83
I/O register definitions 12
Intel 8031 memory map 10
Intel 8031 port signals 5
Intel 8255 port signals 91
interrupt interface 90
interrupts 16
Link Control Block (LCB) 21
memory interface 90
polynomial generator checker 10
programming considerations 18
read IPL switch 69
read station address 66
receive frame 51
receive virtual frame 49
remote IPL 37
set Multicast address 67
special transmit mode command bits 81
start DLCP 70
status 60
status register bit definitions 13
stop DLCP 65
switch blocks bit assignments 84
switch settings 84
transmit broadcast frame 61
transmit frame 53
transmit virtual frame 63
Cluster Adapter switch settings 84
cluster bus interface 94
cluster initialization (DLCP initialization) 44

Index-2
cluster status 58
cluster status table 35
collision avoidance 30
control field format 25

data link control program (DLCP) 18

diagnostic function 1 73
diagnostic function 2 75
diagnostic function 3 76
diagnostic function 4 77
diagnostic function 5 78
diagnostic function 6 79
diagnostic function 7 80
display cluster status 55
DLCP BIOS commands 42
dump statistics 71

error detection and recovery 34

frame format 24
frame reception 33
frame transmission 22

Index-3
I

I/O addresses 83
I/O register definitions 12
Intel 8031 memory map 10
Intel 8031 port signals 5
Intel 8255 port signals 91
interrupt interface 90
interrupts 16

link control block (LCB) 21

memory interface 90

polynomial generator checker 10

programming considerations 18

read IPL switch 69

read station address 66

Index-4
receive frame 51
receive virtual frame 49
remote IPL 37

s
set multicast address 67
special transmit mode command bits 81
start DLCP 70
status 60
status register bit definitions 13
stop DLCP 65
switch blocks bit assignments 84

T
transmit broadcast frame 61
transmit frame 53
transmit virtual frame 63

Index-5
Index-6
-- - ---
-
---
--- -
--
- --- - Personal Computer
--_.-
-
----- --- Hardware Reference
Library

mM Game Control
Adapter

6361493
ii
Contents

Description .................................... 1
Programming Considerations ...................... 3
Address Decode ............................ 3
Data Bus Buffer/Driver ...................... 3
Trigger Buttons ............................. 3
Joystick Positions ........................... 3
II 0 Channel Description ..................... 4
Interface ...................................... 5
Specifications .................................. 7
Logic Diagram ................................. 9

iii
iv
Description

The IBM Game Control Adapter allows up to four paddles or two

joysticks to be attached to the system. This adapter fits into one
of the system board's or expansion board's expansion slots. The
game control interface cable attaches to the rear of the adapter.
In addition, four inputs for switches are provided. Paddle and
joystick positions are determined by changing resistive values sent
to the adapter. The adapter, when used with system software,
converts the present resistive value to a relative paddle or joystick
position. On receipt of an output signal, four timing circuits are
started. By determining the time required for the circuit to
timeout (a function of the resistance), the paddle position can be
determined. This adapter could be used as a general purpose 1/0
card with four analog (resistive) inputs plus four digital input
points.

A9-AO ....
L 10 ) ...
~

" Convert
A Resistive Input
AEN Instruction Resistance
... Decode Digital K 4 I
lOW
...
Pulse "
lOR
... r--- r--

f4-- Typical Frequency

07-00 833 Hz
.A .A
Data Bus
8
Buffer / K... 4
" Driver
Digital Inputs
~ 4 I
~
Game Control Adapter Block Diagram

Game Control Adapter 1

2 Game Control Adapter
Programming Considerations

Address Decode
The select on the Game Control Adapter is generated by two
74LS138s as an address decoder. AEN must be inactive while
the address is hex 201 in order to generate the select. The select
allows a write to fire the one-shots, or a read to give the values of
the trigger buttons and one-shot outputs.

Data Bus Buffer/Driver

The data bus is buffered by a 74LS244 buffer/driver. For an In
from address hex 201, the Game Control Adapter will drive the
data bus; at all other times, the buffer is left in the high
impedance state.

Trigger Buttons
The trigger button inputs are read by an In from address hex 201.
A trigger button is on each joystick or paddle. These values are
seen on data bits 7 through 4. These buttons default to an open
state and are read as 1. When a button is pressed, it is read as O.
Software should be aware that these buttons are not debounced in
hardware.

Joystick Positions
The joystick position is indicated by a potentiometer for each
coordinate. Each potentiometer has a range of 0 to 100 kilohms
that varies the time constant for each of the four one-shots. As
this time constant is set at different values, the output of the
one-shot will be of varying durations.

Game Control Adapter 3

All four one-shots are fired at once by an Out to address hex 201.
All four one-shot outputs will go true after the fire pulse and will
remain high for varying times depending on where each
potentiometer is set.

These four one-shot outputs are read by an In from address hex

201 and are seen on data bits 3 through O.

110 Channel Description

A9-AO: Address lines 9 through 0 are used to address the
Game Control Adapter.

07-00: Data lines 7 through 0 are the data bus.

lOR, lOW: I/O Read and I/O Write are used when reading
from or writing to an adapter (In, Out).

AEN: When active, the adapter must be inactive and the

data bus driver inactive.

+5 Vdc: Power for the Game Control Adapter.

GND: Common ground.

The following I/O channel lines are not used:

MEMR,MEMW ALE,T/C
DACKO-DACK3 CLK,OSC

IRQ7-IRQ2 -5 Vdc

DRQ3-DRQl +12 Vdc

I/O CURDY -12 Vdc

I/O CUCK RESETORV

A19-A10

4 Game Control Adapter

Interface
The Game Control Adapter has eight input lines; four digital
inputs and four resistive inputs. The inputs are read with one In
from address hex 201.

The four digital inputs each have a I-kilohm pullup resistor to +5

Vdc. With no drives on these inputs, a 1 is read. For a 0 reading,
the inputs must be pulled to ground.

The four resistive pullups, measured to +5 Vdc, will be converted

to a digital pulse with a duration proportional to the resistive load,
according to the following equation:

Time = 24.2 f.LS + 0.011 (r) f.LS

The user must first begin the conversion by an Out to address hex
201. An In from address hex 201 will force the digital pulse to go
high and remain high for the duration according to the resistance
value. All four bits (bit 3-bit 0) function in the same manner;
their digital pulse will all go high simultaneously and will reset
independently according to the input resistance value.

Bit 7 Bit 6 I Bit 5 Bit4 Bit 3 Bit 2 I Bit 1 BitO

Digital Inputs Resistive Inputs

The typical input to the Game Control Adapter is a set of

joysticks or game paddles.

The joysticks will typically be a set of two (A and B). These will
have one or two buttons each with two variable resistances each,
with a range of 0 to 100 kilohms. One variable resistance will
indicate the X coordinate and the other variable resistance will
indicate the Y coordinate.

Game Control Adapter S

The joystick should be attached to give the following input data:

Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 BitO

B-#2 B-#1 A-#2 A-#1 B-Y B-X A-Y A-X
Button Button Button Button Coordinate Coordinate Coordinate Coordinate

The game paddles will consist of two (A and B) or four (A, B, C,

and D) paddles. These will have one button each and one
variable resistance each, with a range of 0 to 100 kilohms. The
game paddles should be attached to give the following input data:

Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 BitO

0 C B A 0 C B A
Button Button Button Button Coordinate Coordinate Coordinate Coordinate

The following "Joystick Schematic Diagram" may be used for

attaching game controllers.

15-Pin Male D-Shell

Connector

Joystick B Joystick A
,.....-------------,
: 1
,.-
--
---"'-", I
r--------------...
2 1 X-Coordinate
1
X-Coordinate I 9 ••..;.1_ _-1--.
I ,• ' J Button
I
1
1
Butto~;r--..------r! .,.
0 ~ i !, ~r-
I
1
1
1
V-Coordinate
I !~
" '2
:~! ~!~J
5• ,,
__ ,1
1

. __ 1_ _V-Coordinate
1 ?4-------r----I1_. 6 '
I 1'3 .~I ~I ____ -.~
I
I
I
,1'4
, •7,,
"
I'
1
IL _____________ .JI :',__
'·5 :,
: L: ____________ _
-- -_
-_ , ....I

Note: Potentiometer for X- and V-Coordinates has a range of 0

to 100 k-ohms. Button is normally open; closed when
pressed.
Joystick Schematic Diagram

6 Game Control Adapter

Specifications

15-Pin D-Shell
Connector

0
• • 9
• •
• •
•
• ••
• •
•
B • • 15
0

At Standard TTL Levels

Adapter
Voltage Pin No.
+5Vdc 1
Button 4 2
Position 0 3
Ground 4
Ground 5
Position 1 6
Button 5 7
External +5Vdc 8 GameC ontrol
Devices +5Vdc 9 Adapter

Button 6 10
Position 2 11
Ground 12
Position 3 13
Button 7 14
+5Vdc 15

Connector Specifications

Game Control Adapter 7

8 Game Control Adapter
 I/O CHANNEL

A9 A22 6~
74LS138
."
•
§,
API
i-+5v--------, 1
A8
A7
AS
A13
A24 5
I
'"". I
I
I 8
A25 1
1 1
,.
A5 A26
A17 3
:
a
U2
-
YO
15 1
IK 1
1
15

•5 ~
74LS138
L'-- 10 II 12J
14
AEN All , G18 10
7
"" '""0
1
G1
A
Ul
1
A2 A1'
1
•
~~
3
" A18
-
os
ClO
"C7
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lOW Sl3
~
,
10 U3
8 -
FIRE

."
~ ---4<~
--+
NE558 ~
5
lOA 81.
13 U3

74LS244
--------:=:=-
11

lJ5l!!~
1
-
ENAB
j Ifi
I
."
----I
API
~
~ T~
Ts
T
RST
ONV
n
13
,C4
.01vl
13
141
AP1
12.U-i •
13
I
r I .La14 i3
,
11

d
I
07 A1
11
'"
10
I,. ,
•
I IK I
I
GN04 ~_OlVI
I 15 2

06
05
04
,.
A3

A5
14
Ifi
IB
IY3
IY2
IYI
1A3
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!AI
•
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I
1
L' , 7
I
I
8 _J
U4
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J.01 J Ifi
L ___ ...J
I 3

-4--- -
t= ~2
3 17 1
03 AS 1Y4 114 O. A
02 A7
5 1Y3 1A3
15
,8
O. • 7 I :!:: CI2
C':l 01 AS ,7
2Y2 1A1 13
11 16
0,
00
C 10
15
I-Olv!
DO A9 ~ 0

S
(D
~
110 CHANNEL
f'
~

QUAOTIMER 1~II~I - ~

15·PIN
O-SHELL
11
Q .5V 83
CI C2 OJ
" C5 RECEPTACLE

=
....
...
'5V
." 047p1
+

-=->
Q GNO
GNO
SI
831

~
.....
ICARIl ADDRESS = 201)

...
(D

\C Game Control Adapter (Sheet 1 of 1)

Notes:

10 Game Control Adapter