CA-3086

Data Sheet December 15, 2011 FN483.6

General Purpose NPN Transistor Array

The CA3086 consists of five general-purpose silicon NPN transistors on a common monolithic substrate. Two of the transistors are internally connected to form a differentially connected pair. The transistors of the CA3086 are well suited to a wide variety of applications in low-power systems at frequencies from DC to 120MHz. They may be used as discrete transistors in conventional circuits. However, they also provide the very significant inherent advantages unique to integrated circuits, such as compactness, ease of physical handling and thermal matching.

Applications
Power Applications from DC to 120MHz General-Purpose Use in Signal Processing Systems Operating in the DC to 190MHz Range Temperature Compensated Amplifiers See Application Note, AN5296 Application of the CA3018 Integrated-Circuit Transistor Array for Suggested Applications

Pinout
CA3086 (PDIP, SOIC) TOP VIEW
1 2 3 4 5 6 7 Q3 Q2 Q4 Q5 Q1 14 13 SUBSTRATE 12 11 10 9 8

Ordering Information
PART NUMBER (BRAND) CA3086 CA3086M96 (3086) TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 14 Ld PDIP 14 Ld SOIC Tape and Reel PKG. DWG. # E14.3 M14.15

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright Intersil Americas Inc. 2003, 2011. All Rights Reserved. Intersil (and design) is a registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.

CA-3086
Absolute Maximum Ratings
The following ratings apply for each transistor in the device: Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . .15V Collector-to-Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . .20V Collector-to-Substrate Voltage, VCIO (Note 1) . . . . . . . . . . . . .20V Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . .5V Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 110 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 130 N/A Maximum Power Dissipation (Any one transistor) . . . . . . . . .300mW Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)

Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES: 1. The collector of each transistor in the CA3086 is isolated from the substrate by an integral diode. The substrate (Terminal 13) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. To avoid undesirable coupling between transistors, the substrate (Terminal 13) should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground. 2. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications
PARAMETER

TA = 25oC, For Equipment Design SYMBOL V(BR)CBO V(BR)CEO V(BR)ClO V(BR)EBO ICBO ICEO hFE TEST CONDITIONS lC = 10A, IE = 0 IC = 1mA, IB = 0 IC = 10A, ICI = 0 IE = 10A, IC = 0 VCB = 10V, IE = 0, VCE = 10V, IB = 0, VCE = 3V, IC = 1mA MIN 20 15 20 5 40 TYP 60 24 60 7 0.002 (Figure 2) 100 MAX 100 5 UNITS V V V V nA A

Collector-to-Base Breakdown Voltage Collector-to-Emitter Breakdown Voltage Collector-to-Substrate Breakdown Voltage Emitter-to-Base Breakdown Voltage Collector-Cutoff Current (Figure 1) Collector-Cutoff Current (Figure 2) DC Forward-Current Transfer Ratio (Figure 3)

Electrical Specifications
PARAMETER

TA = 25oC, Typical Values Intended Only for Design Guidance SYMBOL hFE VCE = 3V TEST CONDITIONS IC = 10mA IC = 10A VBE VCE = 3V IE = 1 mA IE = 10mA TYPICAL VALUES 100 54 0.715 0.800 -1.9 0.23 3.25 V V mV/oC V dB UNITS

DC Forward-Current Transfer Ratio (Figure 3) Base-to-Emitter Voltage (Figure 4)

VBE Temperature Coefficient (Figure 5) Collector-to-Emitter Saturation Voltage Noise Figure (Low Frequency)

VBE/T VCE SAT NF

VCE = 3V, lC = 1 mA IB = 1mA, IC = 10mA f = 1kHz, VCE = 3V, IC = 100A, RS = 1k

CA-3086
Electrical Specifications
PARAMETER Low-Frequency, Small-Signal EquivalentCircuit Characteristics: Forward Current-Transfer Ratio (Figure 6) Short-Circuit Input Impedance (Figure 6) Open-Circuit Output Impedance (Figure 6) Open-Circuit Reverse-Voltage Transfer Ratio (Figure 6) Admittance Characteristics: Forward Transfer Admittance (Figure 7) Input Admittance (Figure 8) Output Admittance (Figure 9) Reverse Transfer Admittance (Figure 10) Gain-Bandwidth Product (Figure 11) Emitter-to-Base Capacitance Collector-to-Base Capacitance Collector-to-Substrate Capacitance yFE yIE yOE yRE fT CEBO CCBO CClO VCE = 3V, IC = 3mA VEB = 3V, IE = 0 VCB = 3V, IC = 0 VC l = 3V, IC = 0 hFE hIE hOE hRE f = 1MHz,VCE = 3V, lC = 1mA 31 - j1.5 0.3 + j0.04 0.001 + j0.03 See Figure 10 550 0.6 0.58 2.8 mS mS mS MHz pF pF pF TA = 25oC, Typical Values Intended Only for Design Guidance (Continued) SYMBOL TEST CONDITIONS f = 1kHz,VCE = 3V, IC = 1mA 100 3.5 15.6 1.8 X 10-4 k S TYPICAL VALUES UNITS

Typical Performance Curves

102 COLLECTOR CUTOFF CURRENT (nA) 10 1 10-1 10-2 10-3 10-4 IE = 0 VCB = 15V VCB = 10V VCB = 5V 103 COLLECTOR CUTOFF CURRENT (nA) 102 VCE = 10V 10 VCE = 5V 1 10-1 10-2 10-3 IB = 0

25

50

75

100

125

TEMPERATURE (oC)

25

50 75 TEMPERATURE (oC)

100

125

FIGURE 1. ICBO vs TEMPERATURE

FIGURE 2. ICEO vs TEMPERATURE

CA-3086 Typical Performance Curves

120 STATIC FORWARD CURRENT TRANSFER RATIO (hFE) 110 100 90 80 70 60 50 0.01 0.1 1 10 EMITTER CURRENT (mA) VCE = 3V TA = 25oC

(Continued)
0.8 hFE BASE-TO-EMITTER VOLTAGE (V) VCE = 3V TA = 25oC

0.7

VBE

0.6

0.5

0.4 0.01

0.1

1.0

10

EMITTER CURRENT (mA)

FIGURE 3. hFE vs IE

FIGURE 4. VBE vs IE

VCB = 3V NORMALIZED h PARAMETERS

100

VCE = 3V f = 1kHz TA = 25oC hIE hRE

BASE-TO-EMITTER VOLTAGE (V)

0.9 0.8 0.7 0.6 0.5 0.4 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) IE = 3mA IE = 1mA IE = 0.5mA

10

hFE = 100 hIE = 3.5k hRE = 1.88 x 10-4 hOE = 15.6S

AT 1mA

hOE

1.0

hFE

hRE 0.1 0.01 hIE 0.1 1.0 COLLECTOR CURRENT (mA) 10

FIGURE 5. VBE vs TEMPERATURE

FIGURE 6. NORMALIZED hFE, hIE, hRE, hOE vs IC

FORWARD TRANSFER CONDUCTANCE (gFE) AND SUSCEPTANCE (bFE) (mS)

INPUT CONDUCTANCE (gIE) AND SUSCEPTANCE (bIE) (mS)

40 30 20 10 0 -10 -20

COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 3V, IC = 1mA

6 5 4 3

COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 3V, IC = 1mA

gFE

bIE

2 1 0 gIE

bFE

0.1

10 FREQUENCY (MHz)

100

0.1

10 FREQUENCY (MHz)

100

FIGURE 7. yFE vs FREQUENCY

FIGURE 8. yIE vs FREQUENCY

CA-3086 Typical Performance Curves

6 OUTPUT CONDUCTANCE (gOE) AND SUSCEPTANCE (bOE) (mS) 5 4 3 2 1 0 0.1 1 10 FREQUENCY (MHz) 100

(Continued)
REVERSE TRANSFER CONDUCTANCE (gRE) AND SUSCEPTANCE (bRE) (mS) COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 3V, IC = 1mA gRE IS SMALL AT FREQUENCIES LESS THAN 500MHz bRE

COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 3V, IC = 1mA

0 -0.5 -1.0 -1.5 -2.0 1

bOE

gOE

10 FREQUENCY (MHz)

100

FIGURE 9. yOE vs FREQUENCY

FIGURE 10. yRE vs FREQUENCY

VCE = 3V GAIN BANDWIDTH PRODUCT (MHz) 1000 900 800 700 600 500 400 300 200 100 0 0 1

TA = 25oC

10

COLLECTOR CURRENT (mA)

FIGURE 11. fT vs IC

CA-3086 Dual-In-Line Plastic Packages (PDIP)

N INDEX AREA E1 1 2 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E

E14.3 (JEDEC MS-001-AA ISSUE D)

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E eA eC
C A B S C

MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93

MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240

MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280

eB

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).

E1 e eA eB L N

0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 -

2.54 BSC 7.62 BSC 10.92 3.81 14

2.93

CA-3086 Small Outline Plastic Packages (SOIC)

N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M B M

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L

MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93

MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497

MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574

A1 B C D E

e
B 0.25(0.010) M C A M B S

A1 0.10(0.004) C

e H h L N

0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050

1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27

NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

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