STM8L151G4 Ufqfpn28

September 2011 Doc ID 15962 Rev 7 1/124
1
STM8L151x4, STM8L151x6,
STM8L152x4, STM8L152x6
8-bit ultralow power MCU, up to 32 KB Flash, 1 KB Data EEPROM
RTC, LCD, timers, USART, I2C, SPI, ADC, DAC, comparators
Features
Operating conditions
Operating power supply range 1.8 V to
3.6 V (down to 1.65 V at power down)
Temp. range: - 40 C to 85, 105 or 125 C
Low power features
5 low power modes: Wait , Low power run
(5.1 A), Low power wait (3 A), Active-halt
with full RTC (1.3 A), Halt (350 nA)
Dynamic consumption: 195 A/MHz+440A
Ultralow leakage per I/0: 50 nA
Fast wakeup from Halt: 4.7 s
Advanced STM8 core
Harvard architecture and 3-stage pipeline
Max freq. 16 MHz, 16 CISC MIPS peak
Up to 40 external interrupt sources
Reset and supply management
Low power, ultrasafe BOR reset with 5
selectable thresholds
Ultralow power POR/PDR
Programmable voltage detector (PVD)
Clock management
1 to 16 MHz crystal oscillator
32 kHz crystal oscillator
Internal 16 MHz factory-trimmed RC
Internal 38 kHz low consumption RC
Clock security system
Low power RTC
BCD calendar with alarm interrupt
Auto-wakeup from Halt w/ periodic interrupt
LCD: up to 4x28 segments w/ step-up converter
Memories
Up to 32 KB of Flash program memory and
1 Kbyte of data EEPROM with ECC, RWW
Flexible write and read protection modes
Up to 2 Kbytes of RAM
DMA
4 channels; supported peripherals: ADC,
DAC, SPI, I2C, USART, timers
1 channel for memory-to-memory
12-bit DAC with output buffer
12-bit ADC up to 1 Msps/25 channels
T. sensor and internal reference voltage
2 Ultralow power comparators
1 with fixed threshold and 1 rail to rail
Wakeup capability
Timers
Two 16-bit timers with 2 channels (used as
IC, OC, PWM), quadrature encoder
One 16-bit advanced control timer with 3
channels, supporting motor control
One 8-bit timer with 7-bit prescaler
2 watchdogs: 1 Window, 1 Independent
Beeper timer with 1, 2 or 4 kHz frequencies
Communication interfaces
Synchronous serial interface (SPI)
Fast I2C 400 kHz SMBus and PMBus
USART (ISO 7816 interface and IrDA)
Up to 41 I/Os, all mappable on interrupt vectors
Up to 16 capacitive sensing channels
supporting touchkey, proximity, linear touch
and rotary touch sensors
Development support
Fast on-chip programming and non intrusive
debugging with SWIM
Bootloader using USART
96-bit unique ID

Table 1. Device summary
Reference Part number
STM8L151xx
(without LCD)
STM8L151C6, STM8L151C4,
STM8L151K6, STM8L151K4,
STM8L151G6, STM8L151G4
STM8L152xx
(with LCD)
STM8L152C6, STM8L152C4,
STM8L152K6, STM8L152K4
UFQFPN48
LQFP32 UFQFPN28
UFQFPN32
LQFP48
CSP
WLCSP28
www.st.com
Contents STM8L151xx, STM8L152xx
2/124 Doc ID 15962 Rev 7
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Ultralow power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11 Ultralow power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 System configuration controller and routing interface . . . . . . . . . . . . . . . 20
3.13 Touchsensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM8L151xx, STM8L152xx Contents
Doc ID 15962 Rev 7 3/124
3.16 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.2 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.18 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 64
9.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Contents STM8L151xx, STM8L152xx
4/124 Doc ID 15962 Rev 7
9.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.3.9 LCD controller (STM8L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.3.12 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.3.13 12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9.3.14 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.3.15 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
10.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
10.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
STM8L151xx, STM8L152xx List of tables
Doc ID 15962 Rev 7 5/124
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Medium density STM8L15x low power device features and peripheral counts . . . . . . . . . 11
Table 3. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4. Legend/abbreviation for table 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Medium density STM8L15x pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. Factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8. I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 12. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 13. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 14. Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 17. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 18. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 20. Total current consumption in Run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 21. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 22. Total current consumption and timing in Low power run mode at VDD = 1.65 V to
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 23. Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . 72
Table 24. Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V. . . . . 73
Table 25. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 75
Table 26. Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V . . . . . . . . . . . 75
Table 27. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 28. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 29. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 30. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 31. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 32. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 34. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 35. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 36. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 37. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 38. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 39. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 40. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 41. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 87
Table 42. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 43. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 44. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 45. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 46. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 47. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
List of tables STM8L151xx, STM8L152xx
6/124 Doc ID 15962 Rev 7
Table 48. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 49. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 50. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 51. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 52. DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 53. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 54. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 55. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 56. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 57. R
AIN
max for f
ADC
= 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 58. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 59. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 60. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 61. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 62. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 63. LQFP48 48-pin low profile quad flat package (7x7), package mechanical data . . . . . . 112
Table 64. UFQFPN48 ultra thin fine pitch quad flat pack no-lead 7 7 mm, 0.5 mm
pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 65. LQFP32 32-pin low profile quad flat package, package mechanical data . . . . . . . . . . . 115
Table 66. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 67. UFQFPN28 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4),
Table 68. WLCSP28 28-pin wafer level chip scale package,
STM8L151xx, STM8L152xx List of figures
Doc ID 15962 Rev 7 7/124
List of figures
Figure 1. Medium density STM8L15x device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2. Medium density STM8L15x clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. STM8L151Cx 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 4. STM8L151Kx 32-pin package pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5. STM8L151Gx UFQFPN 28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. STM8L151Gx WLCSP28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. STM8L152Cx 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. STM8L152Kx 32-pin package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 12. POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 13. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 14. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 15. Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 16. Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 17. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 18. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 19. Typical HSI frequency vs V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 20. Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 21. Typical VIL and VIH vs VDD (high sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 22. Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 23. Typical pull-up resistance R
PU
vs V
DD
with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 24. Typical pull-up current I
pu
vs V
DD
with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 25. Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 26. Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 27. Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 28. Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 29. Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 30. Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 31. Typical NRST pull-up resistance R
PU
vs V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 32. Typical NRST pull-up current I
pu
vs V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 33. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 34. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 35. SPI1 timing diagram - slave mode and CPHA=1
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 36. SPI1 timing diagram - master mode
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 37. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 38. ADC1 accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 39. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 40. Maximum dynamic current consumption on V
REF+
supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 41. Power supply and reference decoupling (V
REF+
not connected to V
DDA
). . . . . . . . . . . . . 107
Figure 42. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 107
Figure 43. LQFP48 48-pin low profile quad flat package outline (7x7) . . . . . . . . . . . . . . . . . . . . . . 112
Figure 44. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 45. UFQFPN48 7 x 7 mm recommended footprint (dimensions in mm) . . . . . . . . . . . . . . . . . 114
Figure 46. LQFP32 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 47. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . 116
List of figures STM8L151xx, STM8L152xx
8/124 Doc ID 15962 Rev 7
Figure 48. UFQFPN32 recommended footprint
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 49. UFQFPN28 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) 117
Figure 50. Recommended footprint (dimensions in mm)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 51. WLCSP28 28-pin wafer level chip scale package, package outline . . . . . . . . . . . . . . . 118
Figure 52. Medium density STM8L15x ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . 120
STM8L151xx, STM8L152xx Introduction
Doc ID 15962 Rev 7 9/124
1 Introduction
This document describes the features, pinout, mechanical data and ordering information of
the medium density STM8L15x devices (STM8L151Cx/Kx/Gx, STM8L152Cx/Kx
microcontrollers with a 16-Kbyte or 32-Kbyte Flash memory density). These devices are
referred to as medium density devices in the STM8L15x and STM8L16x reference manual
(RM0031) and in the STM8L Flash programming manual (PM0054).
For more details on the whole STMicroelectronics ultralow power family please refer to
Section 2.2: Ultralow power continuum on page 12.
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).For
information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
The medium density devices provide the following benefits:
Integrated system
Up to 32 Kbytes of medium-density embedded Flash program memory
1 Kbyte of data EEPROM
Internal high speed and low-power low speed RC.
Embedded reset
Ultralow power consumption
195 A/MHZ + 440 A (dynamic consumption)
0.9 A with LSI in Active-halt mode
Clock gated system and optimized power management
Capability to execute from RAM for Low power wait mode and Low power run
mode
Advanced features
Up to 16 MIPS at 16 MHz CPU clock frequency
Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access.
Short development cycles
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals.
Wide choice of development tools
All devices offer 12-bit ADC, DAC, two comparators, Real-time clock three 16-bit timers, one
8-bit timer as well as standard communication interface such as SPI, I2C and USART. A
4x28-segment LCD is available on the medium-density STM8L152xx line. Table 2: Medium
density STM8L15x low power device features and peripheral counts and Section 3 on page
13 give an overview of the complete range of peripherals proposed in this family.
The medium density STM8L15x microcontroller family is suitable for a wide range of
applications:
Medical and handheld equipment
Application control and user interface
PC peripherals, gaming, GPS and sport equipment
Alarm systems, wired and wireless sensors
Figure 1 on page 13 shows the general block diagram of the device family.
Description STM8L151xx, STM8L152xx
10/124 Doc ID 15962 Rev 7
2 Description
The medium density STM8L15x devices are members of the STM8L Ultralow power 8-bit
family. The medium density STM8L15x family operates from 1.8 V to 3.6 V (down to 1.65 V
at power down) and is available in the -40 to +85 C and -40 to +125 C temperature ranges.
The medium density STM8L15x Ultralow power family features the enhanced STM8 CPU
core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive In-Application debugging and ultrafast Flash programming.
All medium density STM8L15x microcontrollers feature embedded data EEPROM and low
power low-voltage single-supply program Flash memory.
They incorporate an extensive range of enhanced I/Os and peripherals.
The modular design of the peripheral set allows the same peripherals to be found in different
ST microcontroller families including 32-bit families. This makes any transition to a different
family very easy, and simplified even more by the use of a common set of development
tools.
Six different packages are proposed from 28 to 48 pins. Depending on the device chosen,
different sets of peripherals are included. .
All STM8L Ultralow power products are based on the same architecture with the same
memory mapping and a coherent pinout.
STM8L151xx, STM8L152xx Description
Doc ID 15962 Rev 7 11/124
2.1 Device overview

Table 2. Medium density STM8L15x low power device features and peripheral counts
Features STM8L151Gx STM8L15xKx STM8L15xCx
Flash (Kbytes) 16 32 16 32 16 32
Data EEPROM (Kbytes) 1
RAM-Kbytes 2 2 2
LCD No 4x17
(1)
4x28
(1)
Timers
Basic
1
(8-bit)
1
(8-bit)
1
(8-bit)
General purpose
2
(16-bit)
2
(16-bit)
2
(16-bit)
Advanced control
1
(16-bit)
1
(16-bit)
1
(16-bit)
Communication
interfaces
SPI 1 1 1
I2C 1 1 1
USART 1 1 1
GPIOs 26
(3)
30
(2)(3)
or 29
(1)(3)
41
(3)
12-bit synchronized ADC
(number of channels)
1
(18)
1
(22
(2)
or 21
(1)
)
1
(25)
12-Bit DAC
(number of channels)
1
(1)
1
(1)
1
(1)
Comparators COMP1/COMP2 2 2 2
Others
RTC, window watchdog, independent watchdog,
16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator
CPU frequency 16 MHz
Operating voltage 1.8 V to 3.6 V (down to 1.65 V at power down)
Operating temperature -40 to +85 C/ -40 to +105 C / -40 to +125 C
Packages
UFQFPN28 (4x4;
0.6 mm thickness)
WLCSP28
LQFP32(7x7)
UFQFPN32 (5x5;
0.6 mm thickness)
LQFP48
UFQFPN48 (4x4;
0.6 mm thickness)
1. STM8L152xx versions only
2. STM8L151xx versions only
3. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as
general purpose output only (PA1).
Description STM8L151xx, STM8L152xx
12/124 Doc ID 15962 Rev 7
2.2 Ultralow power continuum
The Ultralow power medium density STM8L151xx and STM8L152xx devices are fully pin-to-
pin, software and feature compatible. Besides the full compatibility within the family, the
devices are part of STMicroelectronics microcontrollers UtraLowPower strategy which also
includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a
continuum of performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 m ultralow leakage process.
Note: 1 The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices.
2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15x documentation for more information on these devices.
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the Ultralow power performance to range from 5 up to 33.3 DMIPs.
Shared peripherals
STM8L151xx/152xx and STM32L15xx share identical peripherals which ensure a very easy
migration from one family to another:
Analog peripherals: ADC1, DAC, and comparators COMP1/COMP2
Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L151xx/152xx and STM32L15xx
devices use a common architecture:
Same power supply range from 1.8 to 3.6 V, down to 1.65 V at power down
Architecture optimized to reach ultralow consumption both in low power modes and
Run mode
Fast startup strategy from low power modes
Flexible system clock
Ultrasafe reset: same reset strategy for both STM8L15x and STM32L15xxx including
power-on reset, power-down reset, brownout reset and programmable voltage detector.
Features
ST UtraLowPower continuum also lies in feature compatibility:
More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
Memory density ranging from 4 to 128 Kbytes
STM8L151xx, STM8L152xx Functional overview
Doc ID 15962 Rev 7 13/124
3 Functional overview
Figure 1. Medium density STM8L15x device block diagram
1. Legend:
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
DAC: Digital-to-analog converter
IC: Inter-integrated circuit multimaster interface
IWDG: Independent watchdog
LCD: Liquid crystal display
POR/PDR: Power on reset / power down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
16 MHz internal RC
Clock
Clocks
A
d
d
r
e
s
s
,

c
o
n
t
r
o
l

a
n
d

d
a
t
a

b
u
s
e
s
Debug module
SPI1
32 Kbytes
Interrupt controller
2 Kbytes RAM
to core and
peripherals
IWDG
(38 kHz clock)
(SWIM)
Port A
Port B
Port C
IC1
USART1

Power
VOLT. REG.
Port F
1-16 MHz oscillator
32 kHz oscillator
38 kHz internal RC
LCD driver
4x28
WWDG
STM8 Core
controller
and
CSS
1 Kbyte
Port D
Port E
Beeper
RTC
memory Program
Data EEPROM
@V
DD
V
DD18
V
DD1
=1.65 V
V
SS1
SWIM
SCL, SDA,
MOSI, MISO,
SCK, NSS
RX, TX, CK
ADC1_INx
DAC_OUT
COMP1_INP
COMP 1
COMP 2
COMP2_INP
V
DDA
V
SSA
SMB
@V
DDA
/V
SSA
Temp sensor
12-bit ADC1
V
REF+
V
REF-
3.6 V
12-bit DAC
12-bit DAC
NRST
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
PF0
BEEP
ALARM, CALIB
SEGx, COMx
POR/PDR
OSC_IN,
OSC_OUT
OSC32_IN,
OSC32_OUT
to
BOR
PVD
PVD_IN
RESET
DMA1
8-bit Timer 4
16-bit Timer 3
16-bit Timer 2
16-bit Timer 1
(4 channels)
2 channels
2 channels
3 channels
COMP2_INM
V
LCD
= 2.5 V
3.6 V
to
LCD booster
Internal reference
voltage
VREFINT out
V
REF+
Infrared interface
IR_TIM
Functional overview STM8L151xx, STM8L152xx
14/124 Doc ID 15962 Rev 7
3.1 Low power modes
The medium density STM8L15x devices support five low power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
Wait mode: The CPU clock is stopped, but selected peripherals keep running. An
internal or external interrupt, event or a Reset can be used to exit the microcontroller
from Wait mode (WFE or WFI mode). Wait consumption: refer to Table 21.
Low power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash and data EEPROM
are stopped and the voltage regulator is configured in Ultralow power mode. The
microcontroller enters Low power run mode by software and can exit from this mode by
software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode. Low power run mode consumption: refer to Table 22.
Low power wait mode: This mode is entered when executing a Wait for event in Low
power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an
event, the system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode. Low power wait mode consumption: refer to Table 23.
Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
can be triggered by RTC interrupts, external interrupts or reset. Active-halt
consumption: refer to Table 24 and Table 25.
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 s. Halt consumption: refer to
Table 26.
3.2 Central processing unit STM8
3.2.1 Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Doc ID 15962 Rev 7 15/124
Architecture and registers
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16 Mbyte linear memory space
16-bit stack pointer - access to a 64 Kbyte level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
20 addressing modes
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
3.2.2 Interrupt controller
The medium density STM8L15x features a nested vectored interrupt controller:
Nested interrupts with 3 software priority levels
32 interrupt vectors with hardware priority
Up to 40 external interrupt sources on 11 vectors
Trap and reset interrupts
16/124 Doc ID 15962 Rev 7
3.3 Reset and supply management
3.3.1 Power supply scheme
The device requires a 1.65 V to 3.6 V operating supply voltage (V
DD
). The external power
supply pins must be connected as follows:
V
SS1
; V
DD1
= 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for
I/Os and for the internal regulator. Provided externally through V
DD1
pins, the
corresponding ground pin is V
SS1
.
V
SSA ;
V
DDA
= 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for
analog peripherals (minimum voltage to be applied to V
DDA
is 1.8 V when the ADC1 is
used). V
DDA
and V
SSA
must be connected to V
DD1
and V
SS1
, respectively.
V
SS2
; V
DD2
= 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for
I/Os. V
DD2
and V
SS2
must be connected to V
DD1
and V
SS1
, respectively.
V
REF+
; V
REF-
(for ADC1): external reference voltage for ADC1. Must be provided
externally through V
REF+
and V
REF-
pin.
V
REF+
(for DAC): external voltage reference for DAC must be provided externally
through V
REF+
.
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active,
and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached,
the option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently (in which case, the V
DD
min value at power down is 1.65 V).
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains
under reset when V
DD
is below a specified threshold, V
POR/PDR
or V
BOR
, without the need
for any external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD
/V
DDA
power supply and compares it to the V
PVD
threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V
DD
/V
DDA
drops below the V
PVD
threshold and/or when
V
DD
/V
DDA
is higher than the V
PVD
threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3 Voltage regulator
The medium density STM8L15x embeds an internal voltage regulator for generating the 1.8
V power supply for the core and peripherals.
This regulator has two different modes:
Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low
power wait modes.
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
Doc ID 15962 Rev 7 17/124
3.4 Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock sources: 4 different clock sources can be used to drive the system
clock:
1-16 MHz High speed external crystal (HSE)
16 MHz High speed internal RC oscillator (HSI)
32.768 kHz Low speed external crystal (LSE)
38 kHz Low speed internal RC (LSI)
RTC and LCD clock sources: the above four sources can be chosen to clock the RTC
and the LCD, whatever the system clock.
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If a HSE clock
failure occurs, the system clock is automatically switched to HSI.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
18/124 Doc ID 15962 Rev 7
Figure 2. Medium density STM8L15x clock tree diagram
1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE
bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031).
2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE
bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031).
3.5 Low power real-time clock
The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.
Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,
year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31
day months are made automatically.
It provides a programmable alarm and programmable periodic interrupts with wakeup from
Halt capability.
Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 s) is
from min. 122 s to max. 3.9 s. With a different resolution, the wakeup time can reach
36 hours
Periodic alarms based on the calendar can also be generated from every second to
every year
HSE OSC
1-16 MHz
HS RC
16 MHz
LS RC
38 kHz
LSE OSC
32 768 kHz
HS
LS
RTC
prescaler
/1;2;4;8;16;32;64
PCLK
to peripherals
RTCCLK/2
to LCD
to WDG
SYSCLK
HSE
(1)
(2)
LS
LSE
OSC_OUT
OSC32_OUT
OSC_N
OSC32_N
clock output
CCO
prescaler
/1;2;4;8;16;32;64
HS
LS
HSE
LSE
CCO
to core and
memory
SYSCLK
Prescaler
/1;2;4;8;16;32;64;128
WDGCLK
RTCSEL[3:0]
LSE
(2)
CLKBEEPSEL[1:0]
to BEEP
BEEPCLK

ai15366g
CSS
configurable
.
/ 2
Peripheral
Clock enable (15 bits)
to RTC
RTCCLK
clock enable (1 bit)
LCDCLK
to LCD
SYSCLK
Halt
clock enable (1 bit)
LCD peripheral
RTCCLK
LCD peripheral
(1)
(2)
Doc ID 15962 Rev 7 19/124
3.6 LCD (Liquid crystal display)
The liquid crystal display drives up to 4 common terminals and up to 28 segment terminals
to drive up to 112 pixels.
Internal step-up converter to guarantee contrast control whatever V
DD
.
Static 1/2, 1/3, 1/4 duty supported.
Static 1/2, 1/3 bias supported.
Phase inversion to reduce power consumption and EMI.
Up to 4 pixels which can programmed to blink.
The LCD controller can operate in Halt mode.
Note: Unnecessary segments and common pins can be used as general I/O pins.
3.7 Memories
The medium densityL STM8L15x devices have the following main features:
Up to 2 Kbytes of RAM
The non-volatile memory is divided into three arrays:
Up to 32 Kbytes of medium-density embedded Flash program memory
1 Kbyte of data EEPROM
Option bytes.
The EEPROM embeds the error correction code (ECC) feature. It supports the read-while-
write (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.
The option byte protects part of the Flash program memory from write and readout piracy.
3.8 DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, DAC, I2C1, SPI1, USART1, the four Timers.
3.9 Analog-to-digital converter
12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel),
temperature sensor and internal reference voltage
Conversion time down to 1 s with f
SYSCLK
= 16 MHz
Programmable resolution
Programmable sampling time
Single and continuous mode of conversion
Scan capability: automatic conversion performed on a selected group of analog inputs
Analog watchdog
Triggered by timer
Note: ADC1 can be served by DMA1.
20/124 Doc ID 15962 Rev 7
3.10 Digital-to-analog converter (DAC)
12-bit DAC with output buffer
Synchronized update capability using TIM4
DMA capability
External triggers for conversion
Input reference voltage V
REF+
for better resolution
Note: DAC can be served by DMA1.
3.11 Ultralow power comparators
The medium density STM8L15x embeds two comparators (COMP1 and COMP2) sharing
the same current bias and voltage reference. The voltage reference can be internal or
external (coming from an I/O).
One comparator with fixed threshold (COMP1).
One comparator rail to rail with fast or slow mode (COMP2). The threshold can be one
of the following:
DAC output
External I/O
Internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4)
The two comparators can be used together to offer a window function. They can wake up
from Halt mode.
3.12 System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.
The highly flexible routing interface allows application software to control the routing of
different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog
signals to ADC1, COMP1, COMP2, DAC and the internal reference voltage V
REFINT
. It also
provides a set of registers for efficiently managing the charge transfer acquisition sequence
(Section 3.13: Touchsensing).
3.13 Touchsensing
Medium density STM8L15xxx devices provide a simple solution for adding capacitive
sensing functionality to any application. Capacitive sensing technology is able to detect
finger presence near an electrode which is protected from direct touch by a dielectric
(example, glass, plastic). The capacitive variation introduced by a finger (or any conductive
object) is measured using a proven implementation based on a surface charge transfer
acquisition principle. It consists of charging the electrode capacitance and then transferring
a part of the accumulated charges into a sampling capacitor until the voltage across this
capacitor has reached a specific threshold. In Medium density STM8L15xxx devices, the
acquiqition sequence is managed by software and it involves analog I/O groups and the
routing interface.
Doc ID 15962 Rev 7 21/124
Reliable touch sensing solutions can be quickly and easily implemented using the free
STM8 Touch Sensing Library.
3.14 Timers
Medium density STM8L15x devices contain one advanced control timer (TIM1), two 16-bit
general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).
All the timers can be served by DMA1.
Table 3 compares the features of the advanced control, general-purpose and basic timers.

3.14.1 TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
16-bit up, down and up/down autoreload counter with 16-bit prescaler
3 independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse
mode output
1 additional capture/compare channel which is not connected to an external I/O
Synchronization module to control the timer with external signals
Break input to force timer outputs into a defined state
3 complementary outputs with adjustable dead time
Encoder mode
Interrupt capability on various events (capture, compare, overflow, break, trigger)
Table 3. Timer feature comparison
Timer
Counter
resolution
Counter
type
Prescaler factor
DMA1
request
generation
Capture/compare
channels
Complementary
outputs
TIM1
16-bit up/down
Any integer
from 1 to 65536
Yes
3 + 1 3
TIM2
Any power of 2
from 1 to 128
2
None
TIM3
TIM4 8-bit up
Any power of 2
from 1 to 32768
0
22/124 Doc ID 15962 Rev 7
3.14.2 16-bit general purpose timers
16-bit autoreload (AR) up/down-counter
7-bit prescaler adjustable to fixed power of 2 ratios (1128)
2 individually configurable capture/compare channels
PWM mode
Interrupt capability on various events (capture, compare, overflow, break, trigger)
Synchronization with other timers or external signals (external clock, reset, trigger and
enable)
3.14.3 8-bit basic timer
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer overflow
or for DAC trigger generation.
3.15 Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
3.15.1 Window watchdog timer
The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
3.15.2 Independent watchdog timer
The independent watchdog peripheral (IWDG) can be used to resolve processor
malfunctions due to hardware or software failures.
It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.
3.16 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
Doc ID 15962 Rev 7 23/124
3.17 Communication interfaces
3.17.1 SPI
The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial
communication with external devices.
Maximum speed: 8 Mbit/s (f
SYSCLK
/2) both for master and slave
Full duplex synchronous transfers
Simplex synchronous transfers on 2 lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
Hardware CRC calculation
Slave/master selection input pin
Note: SPI1 can be served by the DMA1 Controller.
3.17.2 IC
The I
2
C bus interface (I
2
C1) provides multi-master capability, and controls all IC bus-
specific sequencing, protocol, arbitration and timing.
Master, slave and multi-master capability
Standard mode up to 100 kHz and fast speed modes up to 400 kHz.
7-bit and 10-bit addressing modes.
SMBus 2.0 and PMBus support
Hardware CRC calculation
Note: I
2
C1 can be served by the DMA1 Controller.
3.17.3 USART
The USART interface (USART1) allows full duplex, asynchronous communications with
external devices requiring an industry standard NRZ asynchronous serial data format. It
offers a very wide range of baud rates.
1 Mbit/s full duplex SCI
SPI1 emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
Single wire half duplex mode
Note: USART1 can be served by the DMA1 Controller.
3.18 Infrared (IR) interface
The medium density STM8L15x devices contain an infrared interface which can be used
with an IR LED for remote control functions. Two timer output compare channels are used to
generate the infrared remote control signals.
24/124 Doc ID 15962 Rev 7
3.19 Development support
Development tools
Development tools for the STM8 microcontrollers include:
The STice emulation system offering tracing and code profiling
The STVD high-level language debugger including C compiler, assembler and
integrated development environment
The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
Single wire data interface (SWIM) and debug module
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, CPU operation can also be monitored in real-
time by means of shadow registers.
Bootloader
A bootloader is available to reprogram the Flash memory using the USART1 interface. The
reference document for the bootloader is UM0560: STM8 bootloader user manual.
STM8L151xx, STM8L152xx Pin description
Doc ID 15962 Rev 7 25/124
4 Pin description
Figure 3. STM8L151Cx 48-pin pinout (without LCD)
1. Reserved. Must be tied to V
DD
.
Figure 4. STM8L151Kx 32-pin package pinout (without LCD)
1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package.
Figure 5. STM8L151Gx UFQFPN 28 package pinout
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24 23
12
13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
PA5
V
SS1
/V
SSA/
V
REF-
NRST/PA1
PA2
PA3
PA4
PA6
R
e
s
.

(
1
)
P
E
0
P
E
1
P
D
1
P
D
2
P
D
3
P
B
0
P
E
3
P
D
0
P
E
5
P
E
4
PA7
V
DD1
V
DDA
V
REF+
P
E
2
PB1
PB2
P
C
0
P
C
1
V
D
D
2
V
S
S
2
P
C
2
P
C
3
P
C
4
P
C
5
P
C
6
P
C
7
P
E
6
P
E
7
PB3
PB4
PB5
PB6
PB7
PF0
PD4
PD5
PD6
PD7 PA0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
32 31 30 29 28 27 26 25
PA5
V
SS1
NRST/PA1
PA2
PA3
PA4
PA6
V
DD1
P
D
3
P
B
0
P
B
1
P
D
0
P
D
1
P
D
2
P
B
3
P
B
2
PB5
PB4
PD4
PB7
PB6
PD7
PD6
PD5
P
C
0
P
C
3
P
C
2
P
C
1
P
C
4
P
C
5
P
C
6
P
A
0

ai18251
P
D
3
P
B
0
P
B
1
P
B
2
P
D
0
P
D
1
P
D
2
PA5
V
SS1
/V
SSA
/V
REF-
V
DD1
/V
DDA
/V
REF+
NRST/PA1
PA2
PA4 PB6
PB5
PB4
PB3
PC0
PD4
PB7
P
C
4
P
C
3
P
C
2
P
C
1
P
A
0
P
C
6
P
C
5
2
1
3
4
5
6
7
9 8 10 11 12 13 14
20
21
19
18
17
16
15
27 28 26 25 24 23 22
PA3
ai18250
Pin description STM8L151xx, STM8L152xx
26/124 Doc ID 15962 Rev 7
Figure 6. STM8L151Gx WLCSP28 package pinout
Figure 7. STM8L152Cx 48-pin pinout (with LCD)
Figure 8. STM8L152Kx 32-pin package pinout (with LCD)
1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package.
PA0
PA3
PA2
PA5
PD2
VREF-
VREF+ PD0
PD3
PB0
PA4
PA1
PC6
PC5 PC3
PC2
PC4
PB4
PB3
PB2
PD1 PB1
PB6
PB7
PB5
PD4
PC0
PC1
4 3 2 1
A
C
B
D
E
F
G
ai17084
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24 23
12
13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
PA5
V
SS1
/V
SSA/
V
REF-
NRST/PA1
PA2
PA3
PA4
PA6
V
L
C
D
P
E
0
P
E
1
P
D
1
P
D
2
P
D
3
P
B
0
P
E
3
P
D
0
P
E
5
P
E
4
PA7
V
DD1
V
DDA
V
REF+
P
E
2
PB1
PB2
P
C
0
P
C
1
V
D
D
2
V
S
S
2
P
C
2
P
C
3
P
C
4
P
C
5
P
C
6
P
C
7
P
E
6
P
E
7
PB3
PB4
PB5
PB6
PB7
PF0
PD4
PD5
PD6
PD7 PA0
PA5
V
SS1
NRST/PA1
PA2
PA3
PA4
PA6
V
DD1
P
D
3
P
B
0
P
B
1
V
L
C
D
P
D
1
P
D
2
P
B
3
P
B
2
PB5
PB4
PD4
PB7
PB6
PD7
PD6
PD5
P
C
0
P
C
3
P
C
2
P
C
1
P
C
4
P
C
5
P
C
6
P
A
0

1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
32 31 30 29 28 27 26 25
ai18252
Doc ID 15962 Rev 7 27/124

Table 4. Legend/abbreviation for table 5
Type I= input, O = output, S = power supply
Level
FT Five-volt tolerant
TT 3.6 V tolerant
Output HS = high sink/source (20 mA)
Port and control
configuration
Input float = floating, wpu = weak pull-up
Output T = true open drain, OD = open drain, PP = push pull
Reset state
Bold X (pin state after reset release).
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
under reset) and after internal reset release (i.e. at reset state).
Table 5. Medium density STM8L15x pin description
Pin
number
Pin name
T
y
p
e
I
/
O

l
e
v
e
l
Input Output
M
a
i
n

f
u
n
c
t
i
o
n
(
a
f
t
e
r

r
e
s
e
t
)
Default alternate
function
L
Q
F
P
4
8

a
n
d

U
F
Q
F
P
N
4
8
L
Q
F
P
3
2

a
n
d

U
F
Q
F
P
N
3
2

U
F
Q
F
P
N
2
8
W
L
C
S
P
2
8
f
l
o
a
t
i
n
g
w
p
u
E
x
t
.

i
n
t
e
r
r
u
p
t

H
i
g
h

s
i
n
k
/
s
o
u
r
c
e
O
D
P
P
2 1 1 C3 NRST/PA1
(1)
I/O X HS X X Reset PA1
3 2 2 B4
PA2/OSC_IN/
[USART1_TX]
(4)
/
[SPI1_MISO]
(4)
I/O X X X HS X X Port A2
HSE oscillator input /
[USART1 transmit] /
[SPI1 master in- slave
out] /
4 3 3 C4
PA3/OSC_OUT/[USART1
_RX]
(4)
/[SPI1_MOSI]
(4)
I/O X X X HS X X Port A3
HSE oscillator output /
[USART1 receive]/ [SPI1
master out/slave in]/
5 - - -
PA4/TIM2_BKIN/
LCD_COM0
(2)
/ADC1_IN2/
COMP1_INP
I/O
TT
(3)
X X X HS X X Port A4
Timer 2 - break input /
LCD COM 0 / ADC1
input 2 / Comparator 1
positive input
- 4 4 D3
PA4/TIM2_BKIN/
[TIM2_ETR]
(4)
/
LCD_COM0
(2)
/
ADC1_IN2/COMP1_INP
I/O
TT
(3)
[Timer 2 - external
trigger] / LCD_COM 0 /
ADC1 input 2 /
Comparator 1 positive
input
6 - - -
PA5/TIM3_BKIN/
LCD_COM1
(2)
/ADC1_IN1/
COMP1_INP
I/O
TT
(3)
LCD_COM 1 / ADC1
input 1/
input
28/124 Doc ID 15962 Rev 7
- 5 5 D4
PA5/TIM3_BKIN/
[TIM3_ETR]
(4)
/
LCD_COM1
(2)
/ADC1_IN1/
COMP1_INP
I/O
TT
(3)
[Timer 3 - external
trigger] / LCD_COM 1 /
ADC1 input 1 /
input
7 6 - -
PA6/[ADC1_TRIG]
(4)
/
LCD_COM2
(2)
/ADC1_IN0/
COMP1_INP
I/O
TT
(3)
[ADC1 - trigger] /
LCD_COM2 /
ADC1 input 0 /
input
8 - - - PA7/LCD_SEG0
(2)(5)
I/O FT X X X HS X X Port A7 LCD segment 0
24 13 12 E3
PB0
(6)
/TIM2_CH1/
LCD_SEG10
(2)
/
ADC1_IN18/COMP1_INP
I/O
TT
(3)
X
(6)
X
(6)
X HS X X Port B0
Timer 2 - channel 1 /
LCD segment 10 /
ADC1_IN18 /
input
25 14 13 G1
PB1/TIM3_CH1/
LCD_SEG11
(2)
/
ADC1_IN17/COMP1_INP
I/O
TT
(3)
X X X HS X X Port B1
LCD segment 11 /
ADC1_IN17 /
input
26 15 14 F2
PB2/ TIM2_CH2/
LCD_SEG12
(2)
/
ADC1_IN16/COMP1_INP
I/O
TT
(3)
LCD segment 12 /
ADC1_IN16/
input
27 - - -
PB3/TIM2_ETR/
LCD_SEG13
(2)
/
ADC1_IN15/COMP1_INP
I/O
TT
(3)
Timer 2 - external trigger
/ LCD segment 13
/ADC1_IN15 /
input
- 16 - -
PB3/[TIM2_ETR]
(4)
/
TIM1_CH2N/LCD_SEG13
(2)
/ADC1_IN15/
COMP1_INP
I/O
TT
(3)
[Timer 2 - external
trigger] / Timer 1 inverted
channel 2 / LCD
segment 13 /
ADC1_IN15 /
input
Table 5. Medium density STM8L15x pin description (continued)
Pin
number
Pin name
T
y
p
e
I
/
O

l
e
v
e
l
Input Output
M
a
i
n

f
u
n
c
t
i
o
n
(
a
f
t
e
r

r
e
s
e
t
)
Default alternate
function
L
Q
F
P
4
8

a
n
d

U
F
Q
F
P
N
4
8
L
Q
F
P
3
2

a
n
d

U
F
Q
F
P
N
3
2

U
F
Q
F
P
N
2
8
W
L
C
S
P
2
8
f
l
o
a
t
i
n
g
w
p
u
E
x
t
.

i
n
t
e
r
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Doc ID 15962 Rev 7 29/124
- - 15 E2
PB3/[TIM2_ETR]
(4)
/
TIM1_CH1N/
LCD_SEG13
(2)
/
ADC1_IN15/RTC_ALARM
/COMP1_INP
I/O
TT
(3)
[Timer 2 - external
trigger] / Timer 1 inverted
channel 1/ LCD segment
13 / ADC1_IN15 /
RTC alarm/ Comparator
1 positive input
28 - - -
PB4
(6)
/[SPI1_NSS]
(4)
/
LCD_SEG14
(2)
/
ADC1_IN14/COMP1_INP
I/O
TT
(3)
X
(6)
X
(6)
X HS X X Port B4
[SPI1 master/slave
select] / LCD segment
14 / ADC1_IN14 /
input
- 17 16 D2
PB4
(6)
/[SPI1_NSS]
(4)
/
LCD_SEG14
(2)
/
ADC1_IN14/
COMP1_INP/DAC_OUT
I/O
TT
(3)
X
(6)
X
(6)
X HS X X Port B4
[SPI1 master/slave
select] / LCD segment
14 / ADC1_IN14 /
DAC output /
input
29 - - -
PB5/[SPI1_SCK]
(4)
/
LCD_SEG15
(2)
/
ADC1_IN13/COMP1_INP
I/O
TT
(3)
[SPI1 clock] / LCD
segment 15 /
ADC1_IN13 /
input
- 18 17 D1
PB5/[SPI1_SCK]
(4)
/
LCD_SEG15
(2)
/
ADC1_IN13/DAC_OUT/
COMP1_INP
I/O
TT
(3)
[SPI1 clock] / LCD
segment 15 /
ADC1_IN13 / DAC
output/
input
30 - - -
PB6/[SPI1_MOSI]
(4)
/
LCD_SEG16
(2)
/
ADC1_IN12/COMP1_INP
I/O
TT
(3)
[SPI1 master out/slave
in]/
LCD segment 16 /
ADC1_IN12 /
input
- 19 18 F1
PB6/[SPI1_MOSI]
(4)
/
LCD_SEG16
(2)
/
ADC1_IN12/COMP1_INP/
DAC_OUT
I/O
TT
(3)
[SPI1 master out]/
slave in / LCD segment
16 / ADC1_IN12 / DAC
output / Comparator 1
positive input
Pin
number
Pin name
T
y
p
e
I
/
O

l
e
v
e
l
Input Output
M
a
i
n

f
u
n
c
t
i
o
n
(
a
f
t
e
r

r
e
s
e
t
)
Default alternate
function
L
Q
F
P
4
8

a
n
d

U
F
Q
F
P
N
4
8
L
Q
F
P
3
2

a
n
d

U
F
Q
F
P
N
3
2

U
F
Q
F
P
N
2
8
W
L
C
S
P
2
8
f
l
o
a
t
i
n
g
w
p
u
E
x
t
.

i
n
t
e
r
r
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H
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30/124 Doc ID 15962 Rev 7
31 20 19 E1
PB7/[SPI1_MISO]
(4)
/
LCD_SEG17
(2)
/
ADC1_IN11/COMP1_INP
I/O
TT
(3)
[SPI1 master in- slave
out] /
LCD segment 17 /
ADC1_IN11 /
input
37 25 21 B1 PC0
(5)
/I2C1_SDA I/O FT X X T
(7)
Port C0 I2C1 data
38 26 22 A1 PC1
(5)
/I2C1_SCL I/O FT X X T
(7)
Port C1 I2C1 clock
41 27 23 B2
PC2/USART1_RX/
LCD_SEG22/ADC1_IN6/
COMP1_INP/VREFINT
I/O
TT
(3)
X X X HS X X Port C2
USART1 receive /
LCD segment 22 /
ADC1_IN6 / Comparator
1 positive input / Internal
voltage reference output
42 28 24 A2
PC3/USART1_TX/
LCD_SEG23
(2)
/
ADC1_IN5/COMP1_INP/
COMP2_INM
I/O
TT
(3)
USART1 transmit /
LCD segment 23 /
ADC1_IN5 / Comparator
1 positive input /
Comparator 2 negative
input
43 29 25 C2
PC4/USART1_CK/
I2C1_SMB/CCO/
LCD_SEG24
(2)
/
ADC1_IN4/COMP2_INM/
COMP1_INP
I/O
TT
(3)
USART1 synchronous
clock / I2C1_SMB /
Configurable clock
output / LCD segment 24
/ ADC1_IN4 /
Comparator 2 negative
input / Comparator 1
positive input
44 30 26 A3
PC5/OSC32_IN
/[SPI1_NSS]
(4)
/
[USART1_TX]
(4)
I/O X X X HS X X Port C5
LSE oscillator input /
[SPI1 master/slave
select] / [USART1
transmit]
45 31 27 B3
PC6/OSC32_OUT/
[SPI1_SCK]
(4)
/
[USART1_RX]
(4)
I/O X X X HS X X Port C6
LSE oscillator output /
[SPI1 clock] / [USART1
receive]
Pin
number
Pin name
T
y
p
e
I
/
O

l
e
v
e
l
Input Output
M
a
i
n

f
u
n
c
t
i
o
n
(
a
f
t
e
r

r
e
s
e
t
)
Default alternate
function
L
Q
F
P
4
8

a
n
d

U
F
Q
F
P
N
4
8
L
Q
F
P
3
2

a
n
d

U
F
Q
F
P
N
3
2

U
F
Q
F
P
N
2
8
W
L
C
S
P
2
8
f
l
o
a
t
i
n
g
w
p
u
E
x
t
.

i
n
t
e
r
r
u
p
t

H
i
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h

s
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Doc ID 15962 Rev 7 31/124
46 - - -
PC7/LCD_SEG25
(2)
/
ADC1_IN3/COMP2_INM/
COMP1_INP
I/O
TT
(3)
LCD segment 25
/ADC1_IN3/ Comparator
negative input /
input
20 - 8 G3
PD0/TIM3_CH2/
[ADC1_TRIG]
(4)
/
LCD_SEG7
(2)
/ADC1_IN2
2/COMP2_INP/
COMP1_INP
I/O
TT
(3)
X X X HS X X Port D0
[ADC1_Trigger] / LCD
segment 7 / ADC1_IN22
/ Comparator 2 positive
positive input
- 9 - -
PD0/TIM3_CH2/
[ADC1_TRIG]
(4)
/
COMP1_INP
I/O
TT
(3)
X X X HS X X
Port
D0
(8)
[ADC1_Trigger] /
ADC1_IN22 /
positive input
21 - - -
PD1/TIM3_ETR/
LCD_COM3
(2)
/
COMP1_INP
I/O
TT
(3)
/ LCD_COM3 /
ADC1_IN21 /
comparator 2 positive
positive input
- 10 - -
PD1/TIM1_CH3N/[TIM3_
ETR]
(4)
/ LCD_COM3
(2)
/
COMP1_INP
I/O
TT
(3)
[Timer 3 - external
trigger]/ TIM1 inverted
channel 3 / LCD_COM3/
ADC1_IN21 /
positive input
- - 9 G2
PD1/TIM1_CH3/[TIM3_ET
R]
(4)
/LCD_COM3
(2)
/
COMP1_INP
I/O
TT
(3)
Timer 1 channel 3 /
[Timer 3 - external
trigger] / LCD_COM3/
ADC1_IN21 /
positive input
Pin
number
Pin name
T
y
p
e
I
/
O

l
e
v
e
l
Input Output
M
a
i
n

f
u
n
c
t
i
o
n
(
a
f
t
e
r

r
e
s
e
t
)
Default alternate
function
L
Q
F
P
4
8

a
n
d

U
F
Q
F
P
N
4
8
L
Q
F
P
3
2

a
n
d

U
F
Q
F
P
N
3
2

U
F
Q
F
P
N
2
8
W
L
C
S
P
2
8
f
l
o
a
t
i
n
g
w
p
u
E
x
t
.

i
n
t
e
r
r
u
p
t

H
i
g
h

s
i
n
k
/
s
o
u
r
c
e
O
D
P
P
32/124 Doc ID 15962 Rev 7
22 11 10 E4
PD2/TIM1_CH1
/LCD_SEG8
(2)
/
ADC1_IN20/COMP1_INP
I/O
TT
(3)
LCD segment 8 /
ADC1_IN20 /
input
23 12 - -
PD3/ TIM1_ETR/
LCD_SEG9
(2)
/ADC1_IN1
9/COMP1_INP
I/O
TT
(3)
/ LCD segment 9 /
ADC1_IN19 /
input
- - 11 F3
PD3/ TIM1_ETR/
LCD_SEG9
(2)
/
ADC1_IN19/TIM1_BKIN/
COMP1_INP/
RTC_CALIB
I/O
TT
(3)
/ LCD segment 9 /
ADC1_IN19 / Timer 1
break input / RTC
calibration / Comparator
1 positive input
33 21 20 C1
PD4/TIM1_CH2
/LCD_SEG18
(2)
/
ADC1_IN10/COMP1_INP
I/O
TT
(3)
LCD segment 18 /
ADC1_IN10/
input
34 22 - -
PD5/TIM1_CH3
/LCD_SEG19
(2)
/
ADC1_IN9/COMP1_INP
I/O
TT
(3)
LCD segment 19 /
ADC1_IN9/ Comparator
1 positive input
35 23 - -
PD6/TIM1_BKIN
/LCD_SEG20
(2)
/
ADC1_IN8/RTC_CALIB/
/VREFINT/
COMP1_INP
I/O
TT
(3)
LCD segment 20 /
ADC1_IN8 / RTC
calibration / Internal
voltage reference output
input
36 24 - -
PD7/TIM1_CH1N
/LCD_SEG21
(2)
/
ADC1_IN7/RTC_ALARM/
VREFINT/
COMP1_INP
I/O
TT
(3)
Timer 1 - inverted
channel 1/ LCD segment
21 / ADC1_IN7 / RTC
alarm / Internal voltage
reference output
/Comparator 1 positive
input
Pin
number
Pin name
T
y
p
e
I
/
O

l
e
v
e
l
Input Output
M
a
i
n

f
u
n
c
t
i
o
n
(
a
f
t
e
r

r
e
s
e
t
)
Default alternate
function
L
Q
F
P
4
8

a
n
d

U
F
Q
F
P
N
4
8
L
Q
F
P
3
2

a
n
d

U
F
Q
F
P
N
3
2

U
F
Q
F
P
N
2
8
W
L
C
S
P
2
8
f
l
o
a
t
i
n
g
w
p
u
E
x
t
.

i
n
t
e
r
r
u
p
t

H
i
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h

s
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/
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O
D
P
P
Doc ID 15962 Rev 7 33/124
14 - - - PE0
(5)
/LCD_SEG1
(2)
I/O FT X X X HS X X Port E0 LCD segment 1
15 - - -
PE1/TIM1_CH2N
/LCD_SEG2
(2)
I/O
TT
(3)
X X X HS X X Port E1
Timer 1 - inverted
channel 2 / LCD
segment 2
16 - - -
PE2/TIM1_CH3N
/LCD_SEG3
(2)
I/O
TT
(3)
Timer 1 - inverted
channel 3 / LCD
segment 3
17 - - - PE3/LCD_SEG4
(2)
I/O
TT
(3)
X X X HS X X Port E3 LCD segment 4
18 - - - PE4/LCD_SEG5
(2)
I/O
TT
(3)
19 - - -
PE5/LCD_SEG6
(2)
/
COMP1_INP
I/O
TT
(3)
LCD segment 6 /
ADC1_IN23
positive input
47 - - -
PE6/LCD_SEG26
(2)
/
PVD_IN
I/O
TT
(3)
LCD segment
26/PVD_IN
48 - - - PE7/LCD_SEG27
(2)
I/O
TT
(3)
32 - - -
PF0/ADC1_IN24/
DAC_OUT
I/O
TT
(3)
X X X HS X X Port F0 ADC1_IN24 / DAC_OUT
13 9 - - VLCD
(2)
S LCD booster external capacitor
13 - - - Reserved
(8)
Reserved. Must be tied to V
DD
10 - - - V
DD
S Digital power supply
11 - - - V
DDA
S Analog supply voltage
12 - - - V
REF+
S
ADC1 and DAC positive voltage
reference
- 8 7 G4 V
DD1
/V
DDA
/V
REF+
S
Digital power supply / Analog
supply voltage / ADC1 positive
voltage reference
9 7 6 F4 V
SS1
/V
SSA/
V
REF-
S
I/O ground / Analog ground voltage
/
ADC1 negative voltage reference
Pin
number
Pin name
T
y
p
e
I
/
O

l
e
v
e
l
Input Output
M
a
i
n

f
u
n
c
t
i
o
n
(
a
f
t
e
r

r
e
s
e
t
)
Default alternate
function
L
Q
F
P
4
8

a
n
d

U
F
Q
F
P
N
4
8
L
Q
F
P
3
2

a
n
d

U
F
Q
F
P
N
3
2

U
F
Q
F
P
N
2
8
W
L
C
S
P
2
8
f
l
o
a
t
i
n
g
w
p
u
E
x
t
.

i
n
t
e
r
r
u
p
t

H
i
g
h

s
i
n
k
/
s
o
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r
c
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O
D
P
P
34/124 Doc ID 15962 Rev 7
Note: The slope control of all GPIO pins, except true open drain pins, can be programmed. By
default, the slope control is limited to 2 MHz.
4.1 System configuration options
As shown in Table 5: Medium density STM8L15x pin description, some alternate functions
can be remapped on different I/O ports by programming one of the two remapping registers
described in the Routing interface (RI) and system configuration controller section in the
STM8L15x and STM8L16x reference manual (RM0031).
39 - - - V
DD2
S IOs supply voltage
40 - - - V
SS2
S IOs ground voltage
1 32 28 A4
PA0
(9)
/[USART1_CK]
(4)
/
SWIM/BEEP/IR_TIM
(10)
I/O X X
(9)
X
HS
(10)
X X Port A0
[USART1 synchronous
clock]
(4)
/ SWIM input
and output /
Beep output / Infrared
Timer output
1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1
pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031).
2. Available on STM8L152xx devices only.
3. In the 3.6 V tolerant I/Os, protection diode to V
DD
is not implemented.
4. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
5. In the 5 V tolerant I/Os, protection diode to V
DD
is not implemented.
6. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
7. In the open-drain output column, T defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V
DD
are
not implemented).
8. Available on STM8L151xx devices only.
9. The PA0 pin is in input pull-up during the reset phase and after reset release.
10. High Sink LED driver capability available on PA0.
Pin
number
Pin name
T
y
p
e
I
/
O

l
e
v
e
l
Input Output
M
a
i
n

f
u
n
c
t
i
o
n
(
a
f
t
e
r

r
e
s
e
t
)
Default alternate
function
L
Q
F
P
4
8

a
n
d

U
F
Q
F
P
N
4
8
L
Q
F
P
3
2

a
n
d

U
F
Q
F
P
N
3
2

U
F
Q
F
P
N
2
8
W
L
C
S
P
2
8
f
l
o
a
t
i
n
g
w
p
u
E
x
t
.

i
n
t
e
r
r
u
p
t

H
i
g
h

s
i
n
k
/
s
o
u
r
c
e
O
D
P
P
STM8L151xx, STM8L152xx Memory and register map
Doc ID 15962 Rev 7 35/124
5 Memory and register map
5.1 Memory mapping
The memory map is shown in Figure 9.
Figure 9. Memory map
1. Table 6 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.
2. The VREFINT_Factory_CONV byte represents the LSB of the V
REFINT
12-bit ADC conversion result. The
MSB have a fixed value: 0x6.
3. The TS_Factory_CONV_V90 byte represents the LSB of the V
90
12-bit ADC conversion result. The MSB
have a fixed value: 0x3.
4. Refer to Table 9 for an overview of hardware register mapping, to Table 8 for details on I/O port hardware
registers, and to Table 10 for information on CPU/SWIM/debug module controller registers.
GPIO and peripheral registers
0x00 0000
Reserved
Medium-density
(up to 32 Kbytes)
Reset and interrupt vectors
0x00 1000
0x00 13FF
RAM
0x00 07FF
(2 Kbytes)
(1)
(513 bytes)
(1)
0x00 1400
Data EEPROM
0x00 4800
0x00 48FF
0x00 4900
0x00 7FFF
0x00 8000
0x00 FFFF

0x00 0800
0x00 0FFF
0x00 47FF
0x00 7EFF
0x00 8080
0x00 807F
0x00 7F00
Reserved
Reserved
including
Stack
(1 Kbyte)
Option bytes
0x00 4FFF
0x00 5000
0x00 57FF
0x00 5800
Reserved
0x00 5FFF
Boot ROM
0x00 6000
0x00 67FF
(2 Kbytes)
0x00 6800
Reserved
CPU/SWIM/Debug/ITC
Registers
0x00 5000
GPIO Ports
0x00 5050
Flash
0x00 50C0
ITC-EXTI
0x00 50D3
RST
0x00 50E0
CLK
0x00 50F3
WWDG
0x00 5210
IWDG
0x00 5230
BEEP
0x00 5250
RTC
0x00 5280
SPI1
0x00 52B0
I2C1
0x00 52E0
USART1
TIM2
TIM3
TIM1
TIM4
IRTIM
ADC1
0x00 5070
DMA1
SYSCFG
DAC
LCD
RI
0x00 509E
0x00 50A0
0x00 50B0
0x00 5140
0x00 5200
0x00 52FF
0x00 5340
0x00 5380
0x00 5400
0x00 5430
0x00 5440
COMP
Flash program memory
WFE
0x00 50A6
0x00 50B2
PWR
0x00 4910
0x00 4911
0x00 4926
0x00 4925
0x00 4931
0x00 4932
0x00 4909
VREFINT_Factory_CONV
(2)
TS_Factory_CONV_V90
(3)
0x00 4912
Reserved
Unique ID
Reserved
Memory and register map STM8L151xx, STM8L152xx
36/124 Doc ID 15962 Rev 7

5.2 Register map

Table 6. Flash and RAM boundary addresses
Memory area Size Start address End address
RAM 2 Kbytes 0x00 0000 0x00 07FF
Flash program memory
16 Kbytes 0x00 8000 0x00 BFFF
32 Kbytes 0x00 8000 0x00 FFFF
Table 7. Factory conversion registers
Address Block Register label Register name
Reset
status
0x00 4910 -
VREFINT_Factory_
CONV
(1)
Internal reference voltage factory
conversion
0xXX
0x00 4911 -
TS_Factory_CONV_
V90
(2)
Temperature sensor output voltage 0xXX
1. The VREFINT_Factory_CONV byte represents the 8 LSB of the result of the VREFINT 12-bit ADC conversion performed in
factory. The MSB have a fixed value: 0x6.
2. The TS_Factory_CONV_V90 byte represents the 8 LSB of the result of the V90 12-bit ADC conversion performed in
factory. The 2 MSB have a fixed value: 0x3.
Table 8. I/O port hardware register map
Reset
status
0x00 5000
Port A
PA_ODR Port A data output latch register 0x00
0x00 5001 PA_IDR Port A input pin value register 0xXX
0x00 5002 PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x01
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005
Port B
PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0xXX
0x00 5007 PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A
Port C
PC_ODR Port C data output latch register 0x00
0x00 500B PB_IDR Port C input pin value register 0xXX
0x00 500C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
Doc ID 15962 Rev 7 37/124

0x00 500F
Port D
PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX
0x00 5011 PD_DDR Port D data direction register 0x00
0x00 5012 PD_CR1 Port D control register 1 0x00
0x00 5013 PD_CR2 Port D control register 2 0x00
0x00 5014
Port E
PE_ODR Port E data output latch register 0x00
0x00 5015 PE_IDR Port E input pin value register 0xXX
0x00 5016 PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019
Port F
PF_ODR Port F data output latch register 0x00
0x00 501A PF_IDR Port F input pin value register 0xXX
0x00 501B PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00
Table 8. I/O port hardware register map (continued)
Reset
status
Table 9. General hardware register map
Reset
status
0x00 501E
to
0x00 5049
Reserved area (44 bytes)
0x00 5050
Flash
FLASH_CR1 Flash control register 1 0x00
0x00 5051 FLASH_CR2 Flash control register 2 0x00
0x00 5052 FLASH _PUKR
Flash program memory unprotection key
register
0x00
0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00
0x00 5054 FLASH _IAPSR
Flash in-application programming status
register
0x00
0x00 5055
to
0x00 506F
38/124 Doc ID 15962 Rev 7
0x00 5070
DMA1
DMA1_GCSR
DMA1 global configuration & status
register
0xFC
0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00
0x00 5072 to
0x00 5074
0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00
0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00
0x00 5077 DMA1_C0NDTR
DMA1 number of data to transfer register
(channel 0)
0x00
0x00 5078 DMA1_C0PARH
DMA1 peripheral address high register
(channel 0)
0x52
0x00 5079 DMA1_C0PARL
DMA1 peripheral address low register
(channel 0)
0x00
0x00 507A Reserved area (1 byte)
0x00 507B DMA1_C0M0ARH
DMA1 memory 0 address high register
(channel 0)
0x00
0x00 507C DMA1_C0M0ARL
DMA1 memory 0 address low register
(channel 0)
0x00
0x00 507D to
0x00 507E
0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00
(channel 1)
0x00
0x00 5082 DMA1_C1PARH
(channel 1)
0x52
0x00 5083 DMA1_C1PARL
(channel 1)
0x00
Table 9. General hardware register map (continued)
Reset
status
Doc ID 15962 Rev 7 39/124
0x00 5084
DMA1
Reserved area (1 byte)
0x00 5085 DMA1_C1M0ARH
(channel 1)
0x00
0x00 5086 DMA1_C1M0ARL
(channel 1)
0x00
0x00 5087
0x00 5088
0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00
0x00 508B DMA1_C2NDTR
(channel 2)
0x00
0x00 508C DMA1_C2PARH
(channel 2)
0x52
0x00 508D DMA1_C2PARL
(channel 2)
0x00
0x00 508E Reserved area (1 byte)
0x00 508F DMA1_C2M0ARH
(channel 2)
0x00
0x00 5090 DMA1_C2M0ARL
(channel 2)
0x00
0x00 5091
0x00 5092
(channel 3)
0x00
0x00 5096
DMA1_C3PARH_
C3M1ARH
(channel 3)
0x40
0x00 5097
DMA1_C3PARL_
C3M1ARL
(channel 3)
0x00
0x00 5098 Reserved area (1 byte)
0x00 5099 DMA1_C3M0ARH
(channel 3)
0x00
0x00 509A DMA1_C3M0ARL
(channel 3)
0x00
0x00 509B to
0x00 509D
0x00 509E
SYSCFG
SYSCFG_RMPCR1 Remapping register 1 0x00
0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00
Reset
status
40/124 Doc ID 15962 Rev 7
0x00 50A0
ITC - EXTI
EXTI_CR1 External interrupt control register 1 0x00
0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00
0x00 50A2 EXTI_CR3 External interrupt control register 3 0x00
0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00
0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00
0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00
0x00 50A6
WFE
WFE_CR1 WFE control register 1 0x00
0x00 50A7 WFE_CR2 WFE control register 2 0x00
0x00 50A8 WFE_CR3 WFE control register 3 0x00
0x00 50A9
to
0x00 50AF
0x00 50B0
RST
RST_CR Reset control register 0x00
0x00 50B1 RST_SR Reset status register 0x01
0x00 50B2
PWR
PWR_CSR1 Power control and status register 1 0x00
0x00 50B3 PWR_CSR2 Power control and status register 2 0x00
0x00 50B4
to
0x00 50BF
0x00 50C0
CLK
CLK_DIVR Clock master divider register 0x03
0x00 50C1 CLK_CRTCR Clock RTC register 0x00
0x00 50C2 CLK_ICKR Internal clock control register 0x11
0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00
0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x80
0x00 50C5 CLK_CCOR Configurable clock control register 0x00
0x00 50C6 CLK_ECKR External clock control register 0x00
0x00 50C7 CLK_SCSR System clock status register 0x01
0x00 50C8 CLK_SWR System clock switch register 0x01
0x00 50C9 CLK_SWCR Clock switch control register 0bxxxx0000
0x00 50CA CLK_CSSR Clock security system register 0x00
0x00 50CB CLK_CBEEPR Clock BEEP register 0x00
0x00 50CC CLK_HSICALR HSI calibration register 0xxx
0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00
0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00
0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x
Reset
status
Doc ID 15962 Rev 7 41/124
0x00 50D0
to
0x00 50D2
0x00 50D3
WWDG
WWDG_CR WWDG control register 0x7F
0x00 50D4 WWDG_WR WWDR window register 0x7F
0x00 50D5
to
00 50DF
0x00 50E0
IWDG
IWDG_KR IWDG key register 0xXX
0x00 50E1 IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3
to
0x00 50EF
0x00 50F0
BEEP
BEEP_CSR1 BEEP control/status register 1 0x00
0x00 50F1
0x00 50F2
0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F
0x00 50F4
to
0x00 513F
Reset
status
42/124 Doc ID 15962 Rev 7
0x00 5140
RTC
RTC_TR1 Time register 1 0x00
0x00 5141 RTC_TR2 Time register 2 0x00
0x00 5142 RTC_TR3 Time register 3 0x00
0x00 5144 RTC_DR1 Date register 1 0x01
0x00 5148 RTC_CR1 Control register 1 0x00
0x00 5149 RTC_CR2 Control register 2 0x00
0x00 514A RTC_CR3 Control register 3 0x00
0x00 514B Reserved area (1 byte)
0x00 514C RTC_ISR1 Initialization and status register 1 0x00
0x00 514D RTC_ISR2 Initialization and Status register 2 0x00
0x00 514E
0x00 514F
0x00 5150 RTC_SPRERH
(1)
Synchronous prescaler register high 0x00
(1)
0x00 5151 RTC_SPRERL
(1)
Synchronous prescaler register low 0xFF
(1)
0x00 5152 RTC_APRER
(1)
Asynchronous prescaler register 0x7F
(1)
0x00 5154 RTC_WUTRH
(1)
Wakeup timer register high 0xFF
(1)
0x00 5155 RTC_WUTRL
(1)
Wakeup timer register low 0xFF
(1)
0x00 5156 to
0x00 5158
0x00 5159 RTC_WPR Write protection register 0x00
0x00 515A
0x00 515B
0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00
0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00
0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00
0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00
0x00 5160 to
0x00 51FF
Reset
status
Doc ID 15962 Rev 7 43/124
0x00 5200
SPI1
SPI1_CR1 SPI1 control register 1 0x00
0x00 5201 SPI1_CR2 SPI1 control register 2 0x00
0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00
0x00 5203 SPI1_SR SPI1 status register 0x02
0x00 5204 SPI1_DR SPI1 data register 0x00
0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07
0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00
0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00
0x00 5208
to
0x00 520F
0x00 5210
I2C1
I2C1_CR1 I2C1 control register 1 0x00
0x00 5211 I2C1_CR2 I2C1 control register 2 0x00
0x00 5212 I2C1_FREQR I2C1 frequency register 0x00
0x00 5213 I2C1_OARL I2C1 own address register low 0x00
0x00 5214 I2C1_OARH I2C1 own address register high 0x00
0x00 5215 Reserved (1 byte)
0x00 5216 I2C1_DR I2C1 data register 0x00
0x00 5217 I2C1_SR1 I2C1 status register 1 0x00
0x00 5218 I2C1_SR2 I2C1 status register 2 0x00
0x00 5219 I2C1_SR3 I2C1 status register 3 0x0x
0x00 521A I2C1_ITR I2C1 interrupt control register 0x00
0x00 521B I2C1_CCRL I2C1 clock control register low 0x00
0x00 521C I2C1_CCRH I2C1 clock control register high 0x00
0x00 521D I2C1_TRISER I2C1 TRISE register 0x02
0x00 521E I2C1_PECR I2C1 packet error checking register 0x00
0x00 521F
to
0x00 522F
Reset
status
44/124 Doc ID 15962 Rev 7
0x00 5230
USART1
USART1_SR USART1 status register 0xC0
0x00 5231 USART1_DR USART1 data register undefined
0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00
0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00
0x00 5234 USART1_CR1 USART1 control register 1 0x00
0x00 5239 USART1_GTR USART1 guard time register 0x00
0x00 523A USART1_PSCR USART1 prescaler register 0x00
0x00 523B
to
0x00 524F
Reset
status
Doc ID 15962 Rev 7 45/124
0x00 5250
TIM2
TIM2_CR1 TIM2 control register 1 0x00
0x00 5251 TIM2_CR2 TIM2 control register 2 0x00
0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00
0x00 5253 TIM2_ETR TIM2 external trigger register 0x00
0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00
0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00
0x00 5256 TIM2_SR1 TIM2 status register 1 0x00
0x00 5258 TIM2_EGR TIM2 event generation register 0x00
0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00
0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00
0x00 525B TIM2_CCER1 TIM2 capture/compare enable register 1 0x00
0x00 525C TIM2_CNTRH TIM2 counter high 0x00
0x00 525D TIM2_CNTRL TIM2 counter low 0x00
0x00 525E TIM2_PSCR TIM2 prescaler register 0x00
0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF
0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF
0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00
0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00
0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00
0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00
0x00 5265 TIM2_BKR TIM2 break register 0x00
0x00 5266 TIM2_OISR TIM2 output idle state register 0x00
0x00 5267 to
0x00 527F
Reset
status
46/124 Doc ID 15962 Rev 7
0x00 5280
TIM3
0x00 5281 TIM3_CR2 TIM3 control register 2 0x00
0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00
0x00 5283 TIM3_ETR TIM3 external trigger register 0x00
0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00
0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00
0x00 5288 TIM3_EGR TIM3 event generation register 0x00
0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00
0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00
0x00 528B TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00
0x00 528C TIM3_CNTRH TIM3 counter high 0x00
0x00 528D TIM3_CNTRL TIM3 counter low 0x00
0x00 528E TIM3_PSCR TIM3 prescaler register 0x00
0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF
0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF
0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00
0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00
0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00
0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00
0x00 5295 TIM3_BKR TIM3 break register 0x00
0x00 5296 TIM3_OISR TIM3 output idle state register 0x00
0x00 5297 to
0x00 52AF
Reset
status
Doc ID 15962 Rev 7 47/124
0x00 52B0
TIM1
0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00
0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00
0x00 52B3 TIM1_ETR TIM1 external trigger register 0x00
0x00 52B4 TIM1_DER TIM1 DMA1 request enable register 0x00
0x00 52B5 TIM1_IER TIM1 Interrupt enable register 0x00
0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00
0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00
0x00 52B8 TIM1_EGR TIM1 event generation register 0x00
0x00 52B9 TIM1_CCMR1 TIM1 Capture/Compare mode register 1 0x00
0x00 52BA TIM1_CCMR2 TIM1 Capture/Compare mode register 2 0x00
0x00 52BB TIM1_CCMR3 TIM1 Capture/Compare mode register 3 0x00
0x00 52BC TIM1_CCMR4 TIM1 Capture/Compare mode register 4 0x00
0x00 52BD TIM1_CCER1 TIM1 Capture/Compare enable register 1 0x00
0x00 52BE TIM1_CCER2 TIM1 Capture/Compare enable register 2 0x00
0x00 52BF TIM1_CNTRH TIM1 counter high 0x00
0x00 52C0 TIM1_CNTRL TIM1 counter low 0x00
0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00
0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00
0x00 52C3 TIM1_ARRH TIM1 Auto-reload register high 0xFF
0x00 52C4 TIM1_ARRL TIM1 Auto-reload register low 0xFF
0x00 52C5 TIM1_RCR TIM1 Repetition counter register 0x00
0x00 52C6 TIM1_CCR1H TIM1 Capture/Compare register 1 high 0x00
0x00 52C7 TIM1_CCR1L TIM1 Capture/Compare register 1 low 0x00
0x00 52C8 TIM1_CCR2H TIM1 Capture/Compare register 2 high 0x00
0x00 52C9 TIM1_CCR2L TIM1 Capture/Compare register 2 low 0x00
0x00 52CA TIM1_CCR3H TIM1 Capture/Compare register 3 high 0x00
0x00 52CB TIM1_CCR3L TIM1 Capture/Compare register 3 low 0x00
0x00 52CC TIM1_CCR4H TIM1 Capture/Compare register 4 high 0x00
0x00 52CD TIM1_CCR4L TIM1 Capture/Compare register 4 low 0x00
0x00 52CE TIM1_BKR TIM1 break register 0x00
0x00 52CF TIM1_DTR TIM1 dead-time register 0x00
0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00
0x00 52D1 TIM1_DCR1 DMA1 control register 1 0x00
Reset
status
48/124 Doc ID 15962 Rev 7
0x00 52D2
TIM1
TIM1_DCR2 TIM1 DMA1 control register 2 0x00
0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00
0x00 52D4
to
0x00 52DF
0x00 52E0
TIM4
0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00
0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00
0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00
0x00 52E4 TIM4_IER TIM4 Interrupt enable register 0x00
0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00
0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00
0x00 52E7 TIM4_CNTR TIM4 counter 0x00
0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00
0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00
0x00 52EA
to
0x00 52FE
0x00 52FF IRTIM IR_CR Infrared control register 0x00
0x00 5300
to
0x00 533F
0x00 5340
ADC1
ADC1_CR1 ADC1 configuration register 1 0x00
0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00
0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F
0x00 5343 ADC1_SR ADC1 status register 0x00
0x00 5344 ADC1_DRH ADC1 data register high 0x00
0x00 5345 ADC1_DRL ADC1 data register low 0x00
0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F
0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF
0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00
0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00
0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00
0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00
0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00
0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00
Reset
status
Doc ID 15962 Rev 7 49/124
0x00 534E
ADC1
ADC1_TRIGR1 ADC1 trigger disable 1 0x00
0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00
0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00
0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00
0x00 5352 to
0x00 537F
0x00 5380
DAC
DAC_CR1 DAC control register 1 0x00
0x00 5381 DAC_CR2 DAC control register 2 0x00
0x00 5382
to 0x00 5383
0x00 5384 DAC_SWTRIGR DAC software trigger register 0x00
0x00 5385 DAC_SR DAC status register 0x00
0x00 5386 to
0x00 5387
0x00 5388 DAC_RDHRH
DAC right aligned data holding register
high
0x00
0x00 5389 DAC_RDHRL DAC right aligned data holding register low 0x00
0x00 538A to
0x00 538B
0x00 538C DAC_LDHRH DAC left aligned data holding register high 0x00
0x00 538D DAC_LDHRL DAC left aligned data holding register low 0x00
0x00 538E
to 0x00 538F
0x00 5390 DAC_DHR8 DAC 8-bit data holding register 0x00
0x00 5391 to
0x00 53AB
0x00 53AC DAC_DORH DAC data output register high 0x00
0x00 53AD DAC_DORL DAC data output register low 0x00
0x00 53AE to
0x00 53FF
Reset
status
50/124 Doc ID 15962 Rev 7
0x00 5400
LCD
LCD_CR1 LCD control register 1 0x00
0x00 5401 LCD_CR2 LCD control register 2 0x00
0x00 5402 LCD_CR3 LCD control register 3 0x00
0x00 5403 LCD_FRQ LCD frequency selection register 0x00
0x00 5404 LCD_PM0 LCD Port mask register 0 0x00
0x00 5408 to
0x00 540B
LCD
0x00 540C LCD_RAM0 LCD display memory 0 0x00
0x00 540D LCD_RAM1 LCD display memory 1 0x00
0x00 540E LCD_RAM2 LCD display memory 2 0x00
0x00 540F LCD_RAM3 LCD display memory 3 0x00
0x00 5410 LCD_RAM4 LCD display memory 4 0x00
0x00 541A to
0x00 542F
Reset
status
Doc ID 15962 Rev 7 51/124

0x00 5430
RI
Reserved area (1 byte) 0x00
0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00
0x00 5432 RI_ICR2 Timer input capture routing register 2 0x00
0x00 5433 RI_IOIR1 I/O input register 1 undefined
0x00 5436 RI_IOCMR1 I/O control mode register 1 0x00
0x00 5439 RI_IOSR1 I/O switch register 1 0x00
0x00 543A RI_IOSR2 I/O switch register 2 0x00
0x00 543B RI_IOSR3 I/O switch register 3 0x00
0x00 543C RI_IOGCR I/O group control register 0x3F
0x00 543D RI_ASCR1 Analog switch register 1 0x00
0x00 543E RI_ASCR2 Analog switch register 2 0x00
0x00 543F RI_RCR Resistor control register 1 0x00
0x00 5440
COMP
COMP_CSR1 Comparator control and status register 1 0x00
0x00 5441 COMP_CSR2 Comparator control and status register 2 0x00
1. These registers are not impacted by a system reset. They are reset at power-on.
Reset
status
52/124 Doc ID 15962 Rev 7
Table 10. CPU/SWIM/debug module/interrupt controller registers
Address Block Register Label Register Name
Reset
Status
0x00 7F00
CPU
(1)
A Accumulator 0x00
0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x00
0x00 7F03 PCL Program counter low 0x00
0x00 7F04 XH X index register high 0x00
0x00 7F05 XL X index register low 0x00
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x03
0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CCR Condition code register 0x28
0x00 7F0B to
0x00 7F5F
CPU
0x00 7F60 CFG_GCR Global configuration register 0x00
0x00 7F70
ITC-SPR
ITC_SPR1 Interrupt Software priority register 1 0xFF
0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF
0x00 7F78
to
0x00 7F79
0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00
0x00 7F81
to
0x00 7F8F
Doc ID 15962 Rev 7 53/124
0x00 7F90
DM
DM_BK1RE DM breakpoint 1 register extended byte 0xFF
0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF
0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF
0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF
0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF
0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF
0x00 7F96 DM_CR1 DM Debug module control register 1 0x00
0x00 7F97 DM_CR2 DM Debug module control register 2 0x00
0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10
0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B
to
0x00 7F9F
1. Accessible by debug module only
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
Address Block Register Label Register Name
Reset
Status
Interrupt vector mapping STM8L151xx, STM8L152xx
54/124 Doc ID 15962 Rev 7
6 Interrupt vector mapping

Table 11. Interrupt mapping
IRQ
No.
Source
block
Description
Wakeup
from Halt
mode
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
mode)
Wakeup
from Wait
(WFE
mode)
(1)
Vector
address
RESET Reset Yes Yes Yes Yes 0x00 8000
TRAP Software interrupt - - - - 0x00 8004
0 Reserved 0x00 8008
1 FLASH
FLASH end of programing/
write attempted to
protected page interrupt
- - Yes Yes 0x00 800C
2 DMA1 0/1
DMA1 channels 0/1 half
transaction/transaction
complete interrupt
- - Yes Yes 0x00 8010
3 DMA1 2/3
DMA1 channels 2/3 half
transaction/transaction
complete interrupt
- - Yes Yes 0x00 8014
4 RTC
RTC alarm A/
wakeup/tamper 1/
tamper 2/tamper 3
Yes Yes Yes Yes 0x00 8018
5
EXTI E/F/
PVD
(2)
External interrupt port E/F
PVD interrupt
Yes Yes Yes Yes 0x00 801C
6 EXTIB/G External interrupt port B/G Yes Yes Yes Yes 0x00 8020
7 EXTID/H External interrupt port D/H Yes Yes Yes Yes 0x00 8024
8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028
9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C
13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C
16 LCD LCD interrupt - - Yes Yes 0x00 8048
17
CLK/TIM1/
DAC
CLK system clock switch/
CSS interrupt/
TIM 1 break/DAC
- - Yes Yes 0x00 804C
18
COMP1/
COMP2/
ADC1
COMP1 interrupt
COMP2 interrupt
ACD1 end of conversion/
analog watchdog/
overrun interrupt
STM8L151xx, STM8L152xx Interrupt vector mapping
Doc ID 15962 Rev 7 55/124
19 TIM2
TIM2 update/overflow/
trigger/break interrupt
- - Yes Yes 0x00 8054
20 TIM2
TIM2 capture/
compare interrupt
- - Yes Yes 0x00 8058
21 TIM3
trigger/break interrupt
- - Yes Yes 0x00 805C
22 TIM3
TIM3 capture/
compare interrupt
- - Yes Yes 0x00 8060
23 TIM1
Update /overflow/trigger/
COM
- - - Yes 0x00 8064
24 TIM1 Capture/compare - - - Yes 0x00 8068
25 TIM4
trigger interrupt
- - Yes Yes 0x00 806C
26 SPI1
SPI1 TX buffer empty/
RX buffer not empty/
error/wakeup interrupt
27 USART1
USART1 transmit data
register empty/
transmission complete
interrupt
- - Yes Yes 0x00 8074
28 USART1
USART1 received data
ready/overrun error/
idle line detected/parity
error/global error interrupt
- - Yes Yes 0x00 8078
29 I
2
C1 I
2
C1 interrupt
(3)
Yes Yes Yes Yes 0x00 807C
1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the
interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.
When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
2. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).
3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
Table 11. Interrupt mapping (continued)
IRQ
No.
Source
block
Description
Wakeup
from Halt
mode
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
mode)
Wakeup
from Wait
(WFE
mode)
(1)
Vector
address
Option bytes STM8L151xx, STM8L152xx
56/124 Doc ID 15962 Rev 7
7 Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.
All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See Table 12 for details on option byte addresses.
The option bytes can also be modified on the fly by the application in IAP mode, except for
the ROP and UBC values which can only be taken into account when they are modified in
ICP mode (with the SWIM).
Refer to the STM8L15x Flash programming manual (PM0054) and STM8 SWIM and Debug
Manual (UM0470) for information on SWIM programming procedures.

Table 12. Option byte addresses
Addr. Option name
Option
byte
No.
Option bits Factory
default
setting 7 6 5 4 3 2 1 0
0x00 4800
Read-out
protection
(ROP)
OPT0 ROP[7:0] 0xAA
0x00 4802
UBC (User
Boot code size)
OPT1 UBC[7:0] 0x00
0x00 4807 Reserved 0x00
0x00 4808
Independent
watchdog
option
OPT3
[3:0]
Reserved
WWDG
_HALT
WWDG
_HW
IWDG
_HALT
IWDG
_HW
0x00
0x00 4809
Number of
stabilization
clock cycles for
HSE and LSE
oscillators
OPT4 Reserved LSECNT[1:0] HSECNT[1:0] 0x00
0x00 480A
Brownout reset
(BOR)
OPT5
[3:0]
Reserved BOR_TH
BOR_
ON
0x01
0x00 480B Bootloader
option bytes
(OPTBL)
OPTBL
[15:0]
OPTBL[15:0]
0x00
0x00 480C 0x00
STM8L151xx, STM8L152xx Option bytes
Doc ID 15962 Rev 7 57/124

Table 13. Option byte description
Option
byte
No.
Option description
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L15x and STM8L16x reference manual (RM0031).
OPT1
UBC[7:0] Size of the user boot code area
0x00: no UBC
0x01: the UBC contains only the interrupt vectors.
0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt
vectors.
0x03 - Page 0 to 2 reserved for UBC, memory write-protected
0xFF - Page 0 to 254 reserved for UBC, memory write-protected
Refer to User boot code section in the STM8L15x and STM8L16x reference manual (RM0031).
OPT2 Reserved
OPT3
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent window watchdog off on Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
OPT4
HSECNT: Number of HSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
LSECNT: Number of LSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
Refer to Table 32: LSE oscillator characteristics on page 79.
Option bytes STM8L151xx, STM8L152xx
58/124 Doc ID 15962 Rev 7
OPT5
BOR_ON:
0: Brownout reset off
1: Brownout reset on
BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 19 for details on the thresholds according to
the value of BOR_TH bits.
OPTBL
OPTBL[15:0]:
This option is checked by the boot ROM code after reset. Depending on
content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the
CPU jumps to the bootloader or to the reset vector.
Refer to the UM0560 bootloader user manual for more details.
Table 13. Option byte description (continued)
Option
byte
No.
Option description
STM8L151xx, STM8L152xx Unique ID
Doc ID 15962 Rev 7 59/124
8 Unique ID
STM8 devices feature a 96-bit unique device identifier which provides a reference number
that is unique for any device and in any context. The 96 bits of the identifier can never be
altered by the user.
The unique device identifier can be read in single bytes and may then be concatenated
using a custom algorithm.
The unique device identifier is ideally suited:
For use as serial numbers
For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software cryptographic primitives and
protocols before programming the internal memory.
To activate secure boot processes

Table 14. Unique ID registers (96 bits)
Address
Content
description
Unique ID bits
7 6 5 4 3 2 1 0
0x4926
X co-ordinate on
the wafer
U_ID[7:0]
0x4927 U_ID[15:8]
0x4928
Y co-ordinate on
the wafer
U_ID[23:16]
0x4929 U_ID[31:24]
0x492A Wafer number U_ID[39:32]
0x492B
Lot number
U_ID[47:40]
0x492C U_ID[55:48]
0x492D U_ID[63:56]
0x492E U_ID[71:64]
0x492F U_ID[79:72]
0x4930 U_ID[87:80]
0x4931 U_ID[95:88]
Electrical parameters STM8L151xx, STM8L152xx
60/124 Doc ID 15962 Rev 7
9 Electrical parameters
9.1 Parameter conditions
Unless otherwise specified, all voltages are referred to V
SS
.
9.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A
= 25 C and T
A
= T
A
max (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean3E).
9.1.2 Typical values
Unless otherwise specified, typical data are based on T
A
= 25 C, V
DD
= 3 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean2E).
9.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
9.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Figure 10. Pin loading conditions
50 pF
STM8L PIN
STM8L151xx, STM8L152xx Electrical parameters
Doc ID 15962 Rev 7 61/124
9.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 11. Pin input voltage
9.2 Absolute maximum ratings
Stresses above those listed as absolute maximum ratings may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

V
IN
STM8L PIN
Table 15. Voltage characteristics
Symbol Ratings Min Max Unit
V
DD
- V
SS
External supply voltage (including V
DDA
and V
DD2
)
(1)
1. All power (V
DD1
, V
DD2
, V
DDA
) and ground (V
SS1
, V
SS2
, V
SSA
) pins must always be connected to the
external power supply.
- 0.3 4.0 V
V
IN
(2)
2. V
IN
maximum must always be respected. Refer to Table 16. for maximum allowed injected current values.
Input voltage on true open-drain pins
(PC0 and PC1)
V
SS
- 0.3 V
DD
+ 4.0
V
Input voltage on five-volt tolerant (FT)
pins (PA7 and PE0)
V
SS
- 0.3 V
DD
+ 4.0
Input voltage on 3.6 V tolerant (TT) pins V
SS
- 0.3 4.0
Input voltage on any other pin V
SS
- 0.3 4.0
V
ESD
Electrostatic discharge voltage
see Absolute maximum
ratings (electrical sensitivity)
on page 109
62/124 Doc ID 15962 Rev 7

Table 16. Current characteristics
Symbol Ratings Max. Unit
I
VDD
Total current into V
DD
power line (source) 80
mA
I
VSS
Total current out of V
SS
ground line (sink) 80
I
IO
Output current sunk by IR_TIM pin (with high sink LED driver
capability)
80
Output current sunk by any other I/O and control pin 25
Output current sourced by any I/Os and control pin - 25
I
INJ(PIN)
Injected current on true open-drain pins (PC0 and PC1)
(1)
- 5 / +0
Injected current on five-volt tolerant (FT) pins (PA7 and PE0)
(1)
1. Positive injection is not possible on these I/Os. A negative injection is induced by V
IN
<V
SS
. I
INJ(PIN)
must
never be exceeded. Refer to Table 15. for maximum allowed input voltage values.
- 5 / +0
Injected current on 3.6 V tolerant (TT) pins
(1)
- 5 / +0
Injected current on any other pin
(2)
2. A positive injection is induced by V
IN
>V
DD
while a negative injection is induced by V
IN
<V
SS
. I
INJ(PIN)
must
never be exceeded. Refer to Table 15. for maximum allowed input voltage values.
- 5 / +5
EI
INJ(PIN)
Total injected current (sum of all I/O and control pins)
(3)
3. When several inputs are submitted to a current injection, the maximum EI
INJ(PIN)
is the absolute sum of the
positive and negative injected currents (instantaneous values).
25
Table 17. Thermal characteristics
Symbol Ratings Value Unit
T
STG
Storage temperature range -65 to +150
C
T
J
Maximum junction temperature 150
Doc ID 15962 Rev 7 63/124
9.3 Operating conditions
Subject to general operating conditions for V
DD
and T
A
.
9.3.1 General operating conditions

Table 18. General operating conditions
Symbol Parameter Conditions Min. Max. Unit
f
SYSCLK
(1)
System clock
frequency
1.65 V s V
DD
< 3.6 V 0 16 MHz
V
DD
Standard operating
voltage
1.65
(2)
3.6 V
V
DDA
Analog operating
voltage
ADC and DAC
not used
Must be at the same
potential as V
DD
1.65
(2)
3.6 V
ADC or DAC
used
1.8 3.6 V
P
D
(3)
Power dissipation at
T
A
= 85 C for suffix 6
devices
LQFP48 288
mW
UFQFPN48 169
LQFP32 288
UFQFPN32 169
UFQFPN28 169
WLCSP28 286
Power dissipation at
T
A
= 125 C for suffix 3
devices and at
T
A
= 105 C for suffix 7
devices
LQFP48 77
UFQFPN48 156
LQFP32 85
UFQFPN32 131
UFQFPN28 42
WLCSP28 71
T
A
Temperature range
1.65 V s V
DD
< 3.6 V (6 suffix version) -40 85
C 1.65 V s V
DD
1.65 V s V
DD
T
J
Junction temperature
range
-40 C s T
A
< 85 C
(6 suffix version)
-40 105
(4)
C
-40 C s T
A
< 105 C
(7 suffix version)
-40 110
(4)
-40 C s T
A
< 125 C
(3 suffix version)
-40 130
1. f
SYSCLK
= f
CPU
2. 1.8 V at power-up, 1.65 V at power-down if BOR is disabled
3. To calculate P
Dmax
(T
A
), use the formula P
Dmax
=(T
Jmax
-T
A
)/O
JA
with T
Jmax
in this table and O
JA
in Thermal
characteristics table.
4. T
Jmax
is given by the test limit. Above this value the product behavior is not guaranteed.
64/124 Doc ID 15962 Rev 7
9.3.2 Embedded reset and power control block characteristics

Table 19. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min
Typ

Max Unit
t
VDD
V
DD
rise time rate
BOR detector
enabled
0
(1)

(1)
s/V
V
DD
fall time rate
BOR detector
enabled
20
(1)

(1)
t
TEMP
Reset release delay V
DD
rising 3 ms
V
PDR
Power-down reset threshold Falling edge 1.30
(2)
1.50 1.65 V
V
BOR0
Brown-out reset threshold 0
(BOR_TH[2:0]=000)
Falling edge 1.67 1.70 1.74
V
Rising edge 1.69 1.75 1.80
V
BOR1
(BOR_TH[2:0]=001)
Rising edge 1.96 2.04 2.07
V
BOR2
(BOR_TH[2:0]=010)
Rising edge 2.31 2.41 2.44
V
BOR3
(BOR_TH[2:0]=011)
Rising edge 2.54 2.66 2.7
V
BOR4
(BOR_TH[2:0]=100)
Rising edge 2.78 2.90 2.95
V
PVD0
PVD threshold 0
V
Rising edge 1.88 1.94 1.99
V
PVD1
PVD threshold 1
Rising edge 2.08 2.14 2.18
V
PVD2
PVD threshold 2
Rising edge 2.28 2.34 2.38
V
PVD3
PVD threshold 3
Rising edge 2.47 2.54 2.58
V
PVD4
PVD threshold 4
Rising edge 2.68 2.74 2.79
V
PVD5
PVD threshold 5
Rising edge 2.87 2.94 2.99
V
PVD6
PVD threshold 6
Rising edge 3.08 3.15 3.20
1. Data guaranteed by design, not tested in production.
2. Data based on characterization results, not tested in production.
Doc ID 15962 Rev 7 65/124
Figure 12. POR/BOR thresholds
9.3.3 Supply current characteristics
Total current consumption
The MCU is placed under the following conditions:
All I/O pins in input mode with a static value at V
DD
or V
SS
(no load)
All peripherals are disabled except if explicitly mentioned.
In the following table, data are based on characterization results, unless otherwise specified.
DD
and T
A
.
1.8 V
Vdd
Internal NRST
VBOR0
BOR threshold
BOR Threshold_0
PDR Threshold
with
BOR
without
BOR
Time
with
BOR
S
a
f
e

R
e
s
e
t
R
e
s
e
t
at power up
BOR activated by user for
power down detection
Vdd Vdd
Operating power supply
3.6 V
without BOR = Battery Iife extension
VPDR
S
a
f
e

R
e
s
e
t

r
e
l
e
a
s
e
BOR always active
66/124 Doc ID 15962 Rev 7

Table 20. Total current consumption in Run mode
Symbol
Para
meter
Conditions
(1)
Typ
Max
Unit
55 C
85 C
(2)
105C
(3)
125 C
(4)
I
DD(RUN)
Supply
current
in run
mode
(5)

All
peripherals
OFF,
code
executed
from RAM,
V
DD
from
1.65 V to
3.6 V
HSI RC osc.
(16 MHz)
(6)
f
CPU
= 125 kHz 0.39 0.47 0.49 0.52 0.55
mA
f
CPU
= 1 MHz 0.48 0.56 0.58 0.61 0.65
f
CPU
= 4 MHz 0.75 0.84 0.86 0.91 0.99
f
CPU
= 8 MHz 1.10 1.20 1.25 1.31 1.40
f
CPU
= 16 MHz 1.85 1.93 2.12
(8)
2.29
(8)
2.36
(8)
HSE external
clock
(f
CPU
=f
HSE
)
(7)

f
CPU
= 125 kHz 0.05 0.06 0.09 0.11 0.12
f
CPU
= 1 MHz 0.18 0.19 0.20 0.22 0.23
f
CPU
= 4 MHz 0.55 0.62 0.64 0.71 0.77
f
CPU
= 8 MHz 0.99 1.20 1.21 1.22 1.24
f
CPU
= 16 MHz 1.90 2.22 2.23
(8)
2.24
(8)
2.28
(8)
LSI RC osc.
(typ. 38 kHz)
f
CPU
= f
LSI
0.040 0.045 0.046 0.048 0.050
LSE external
clock
(32.768 kHz)
f
CPU
= f
LSE
0.035 0.040 0.048
(8)
0.050 0.062
I
DD(RUN)
Supply
current
in Run
mode
All
peripherals
OFF, code
executed
from Flash,
V
DD
from
1.65 V to
3.6 V
HSI RC
osc.
(9)
f
CPU
= 125 kHz 0.43 0.55 0.56 0.58 0.62
mA
f
CPU
= 1 MHz 0.60 0.77 0.80 0.82 0.87
f
CPU
= 4 MHz 1.11 1.34 1.37 1.39 1.43
f
CPU
= 8 MHz 1.90 2.20 2.23 2.31 2.40
f
CPU
= 16 MHz 3.8 4.60 4.75 4.87 4.88
HSE external
clock
(f
CPU
=f
HSE
)
(7)
f
CPU
= 125 kHz 0.30 0.36 0.39 0.44 0.47
f
CPU
= 1 MHz 0.40 0.50 0.52 0.55 0.56
f
CPU
= 4 MHz 1.15 1.31 1.40 1.45 1.48
f
CPU
= 8 MHz 2.17 2.33 2.44 2.56 2.77
f
CPU
= 16 MHz 4.0 4.46 4.52 4.59 4.77
LSI RC osc. f
CPU
= f
LSI
0.110 0.123 0.130 0.140 0.150
LSE ext.
clock
(32.768
kHz)
(10)
f
CPU
= f
LSE
0.100 0.101 0.104 0.119 0.122
1. All peripherals OFF, V
DD
from 1.65 V to 3.6 V, HSI internal RC osc. , f
CPU
=f
SYSCLK
2. For devices with suffix 6
Doc ID 15962 Rev 7 67/124
Figure 13. Typ. I
DD(RUN)
vs. V
DD
, f
CPU
= 16 MHz
1. Typical current consumption measured with code executed from RAM
5. CPU executing typical data processing
6. The run from RAM consumption can be approximated with the linear formula:
I
DD
(run_from_RAM) = Freq * 90 A/MHz + 380 A
7. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption
(I
DD HSE
) must be added. Refer to Table 31.
8. Tested in production.
9. The run from Flash consumption can be approximated with the linear formula:
I
DD
(run_from_Flash) = Freq * 195 A/MHz + 440 A
10. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
(I
DD LSE
1.50
1.75
2.00
2.25
2.50
2.75
3.00
1.6 2.1 2.6 3.1 3.6
V
DD
[V]
D
D
(
R
U
N
)
H
S

[
m
A
]
-40C
25C
90C
130C
ai18213
68/124 Doc ID 15962 Rev 7

Table 21. Total current consumption in Wait mode
Symbol Parameter
Conditions
(1)
Typ
Max
Unit
55C
85
C
(2)
105 C
(3)
125 C
(4)
I
DD(Wait)
Supply
current in
Wait mode
CPU not
clocked,
all peripherals
OFF,
code executed
from RAM
with Flash in
I
DDQ
mode
(5)
,
V
DD
from
1.65 V to 3.6 V
HSI
f
CPU
= 125 kHz 0.33 0.39 0.41 0.43 0.45
mA
f
CPU
= 1 MHz 0.35 0.41 0.44 0.45 0.48
f
CPU
= 4 MHz 0.42 0.51 0.52 0.54 0.58
f
CPU
= 8 MHz 0.52 0.57 0.58 0.59 0.62
f
CPU
= 16 MHz 0.68 0.76 0.79
0.82
(7)
0.85
(7)
HSE external
clock
(f
CPU
=f
HSE
)
(6)
f
CPU
= 125 kHz 0.032 0.056 0.068 0.072 0.093
f
CPU
= 1 MHz 0.078 0.121 0.144 0.163 0.197
f
CPU
= 4 MHz 0.218 0.26 0.30 0.36 0.40
f
CPU
= 8 MHz 0.40 0.52 0.57 0.62 0.66
f
CPU
= 16 MHz 0.760 1.01 1.05
1.09
(7)
1.16
(7)
LSI f
CPU
= f
LSI
0.035 0.044 0.046 0.049 0.054
LSE
(8)

external clock
(32.768
kHz)
f
CPU
= f
LSE
0.032 0.036 0.038 0.044 0.051
I
DD(Wait)
Supply
current in
Wait
mode
CPU not
clocked,
all peripherals
OFF,
code executed
from Flash,
V
DD
from
1.65 V to 3.6 V
HSI
f
CPU
= 125 kHz 0.38 0.48 0.49 0.50 0.56
mA
f
CPU
= 1 MHz 0.41 0.49 0.51 0.53 0.59
f
CPU
= 4 MHz 0.50 0.57 0.58 0.62 0.66
f
CPU
= 8 MHz 0.60 0.66 0.68 0.72 0.74
f
CPU
= 16 MHz 0.79 0.84 0.86 0.87 0.90
HSE
(6)

external clock
(f
CPU
=HSE)
f
CPU
= 125 kHz 0.06 0.08 0.09 0.10 0.12
f
CPU
= 1 MHz 0.10 0.17 0.18 0.19 0.22
f
CPU
= 4 MHz 0.24 0.36 0.39 0.41 0.44
f
CPU
= 8 MHz 0.50 0.58 0.61 0.62 0.64
f
CPU
= 16 MHz 1.00 1.08 1.14 1.16 1.18
LSI f
CPU
= f
LSI
0.055 0.058 0.065 0.073 0.080
LSE
(8)

external clock
(32.768 kHz)
f
CPU
= f
LSE
0.051 0.056 0.060 0.065 0.073
1. All peripherals OFF, V
DD
from 1.65 V to 3.6 V, HSI internal RC osc. , f
CPU
= f
SYSCLK
Doc ID 15962 Rev 7 69/124
Figure 14. Typ. I
DD(Wait)
vs. V
DD
, f
CPU
= 16 MHz
1)
1. Typical current consumption measured with code executed from Flash memory.
2. For temperature range 6.
5. Flash is configured in I
DDQ
mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.
6. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption
(I
DD HSE
(I
DD HSE
500
550
600
650
700
750
800
850
900
950
1000
1.6 2.1 2.6 3.1 3.6
V
DD
[V]
D
D
(
W
A
T
)
H
S
A
]
-40C
25C
90C
130C
ai18214
70/124 Doc ID 15962 Rev 7

Table 22. Total current consumption and timing in Low power run mode at V
DD
= 1.65 V to
3.6 V
Symbol Parameter
Conditions
(1)
Typ Max Unit
I
DD(LPR)
Supply current in Low
power run mode
LSI RC osc.
(at 38 kHz)
all peripherals OFF
T
A
= -40 C
to 25 C
5.1 5.4
A
T
A
= 55 C 5.7 6
T
A
= 85 C 6.8 7.5
T
A
= 105 C 9.2 10.4
T
A
= 125 C 13.4 16.6
with TIM2 active
(2)

T
A
= -40 C
to 25 C
5.4 5.7
T
A
= 55 C 6.0 6.3
T
A
= 85 C 7.2 7.8
T
A
= 105 C 9.4 10.7
T
A
= 125 C 13.8 17
LSE
(3)
external
clock
(32.768 kHz)
all peripherals OFF
T
A
= -40 C
to 25 C
5.25 5.6
T
A
= 55 C 5.67 6.1
T
A
= 85 C 5.85 6.3
T
A
= 105 C 7.11 7.6
T
A
= 125 C 9.84 12
with TIM2 active
(2)
T
A
= -40 C
to 25 C
5.59 6
T
A
= 55 C 6.10 6.4
T
A
= 85 C 6.30 7
T
A
= 105 C 7.55 8.4
T
A
= 125 C 10.1 15
1. No floating I/Os
2. Timer 2 clock enabled and counter running
(I
DD LSE
) must be added. Refer to Table 32
Doc ID 15962 Rev 7 71/124
Figure 15. Typ. I
DD(LPR)
vs. V
DD
(LSI clock source)
0
2
4
6
8
10
12
14
16
18
1.6 2.1 2.6 3.1 3.6
V
DD
[V]
ai18216
D
D
(
L
P
R
)
L
S
A
]
-40 C
25 C
90 C
130 C
72/124 Doc ID 15962 Rev 7

Figure 16. Typ. I
DD(LPW)
vs. V
DD
(LSI clock source)
Table 23. Total current consumption in Low power wait mode at V
DD
= 1.65 V to 3.6 V
Symbol Parameter
Conditions
(1)
Typ Max Unit
I
DD(LPW)
Supply current in
Low power wait mode
LSI RC osc.
(at 38 kHz)
all peripherals OFF
T
A
= -40 C to 25 C 3 3.3
A
T
A
= 55 C 3.3 3.6
T
A
= 85 C 4.4 5
T
A
= 105 C 6.7 8
T
A
= 125 C 11 14
with TIM2 active
(2)

T
A
= -40 C to 25 C 3.4 3.7
T
A
= 55 C 3.7 4
T
A
= 85 C 4.8 5.4
T
A
= 105 C 7 8.3
T
A
= 125 C 11.3 14.5
LSE external
clock
(3)
(32.768 kHz)
all peripherals OFF
T
A
= -40 C to 25 C 2.35 2.7
T
A
= 55 C 2.42 2.82
T
A
= 85 C 3.10 3.71
T
A
= 105 C 4.36 5.7
T
A
= 125 C 7.20 11
with TIM2 active
(2)
T
A
= -40 C to 25 C 2.46 2.75
T
A
= 55 C 2.50 2.81
T
A
= 85 C 3.16 3.82
T
A
= 105 C 4.51 5.9
T
A
= 125 C 7.28 11
1. No floating I/Os.
2. Timer 2 clock enabled and counter is running.
(I
DD LSE
Doc ID 15962 Rev 7 73/124

Table 24. Total current consumption and timing in Active-halt mode at V
DD
= 1.65 V to 3.6 V
Symbol Parameter
Conditions
(1)
Typ Max Unit
I
DD(AH)
Supply current in
Active-halt mode
LSI RC
(at 38 kHz)
LCD OFF
(2)
T
A
= -40 C to 25 C 0.9 2.1
A
T
A
= 55 C 1.2 3
T
A
= 85 C 1.5 3.4
T
A
= 105 C 2.6 6.6
T
A
= 125 C 5.1 12
LCD ON
(static duty/
external
V
LCD
)
(3)
T
A
= -40 C to 25 C 1.4 3.1
T
A
= 55 C 1.5 3.3
T
A
= 85 C 1.9 4.3
T
A
= 105 C 2.9 6.8
T
A
= 125 C 5.5 13
LCD ON
(1/4 duty/
external
V
LCD
)
(4)
T
A
= -40 C to 25 C 1.9 4.3
T
A
= 55 C 1.95 4.4
T
A
= 85 C 2.4 5.4
T
A
= 105 C 3.4 7.6
T
A
= 125 C 6.0 15
LCD ON
(1/4 duty/
internal
V
LCD
)
(5)
T
A
= -40 C to 25 C 3.9 8.75
T
A
= 55 C 4.15 9.3
T
A
= 85 C 4.5 10.2
T
A
= 105 C 5.6 13.5
T
A
= 125 C 6.8 16.3
74/124 Doc ID 15962 Rev 7
I
DD(AH)
Supply current in
Active-halt mode
LSE external
clock
(32.768 kHz)
(6)
LCD OFF
(7)
T
A
= -40 C to 25 C 0.5 1.2
A
T
A
= 55 C 0.62 1.4
T
A
= 85 C 0.88 2.1
T
A
= 105 C 2.1 4.85
T
A
= 125 C 4.8 11
LCD ON
(static duty/
external
V
LCD
)
(3)
T
A
= -40 C to 25 C 0.85 1.9
T
A
= 55 C 0.95 2.2
T
A
= 85 C 1.3 3.2
T
A
= 105 C 2.3 5.3
T
A
= 125 C 5.0 12
LCD ON
(1/4 duty/
external
V
LCD
)
(4)
T
A
= -40 C to 25 C 1.5 2.5
T
A
= 55 C 1.6 3.8
T
A
= 85 C 1.8 4.2
T
A
= 105 C 2.9 7.0
T
A
= 125 C 5.7 14
LCD ON
(1/4 duty/
internal
V
LCD
)
(5)
T
A
= -40 C to 25 C 3.4 7.6
T
A
= 55 C 3.7 8.3
T
A
= 85 C 3.9 9.2
T
A
= 105 C 5.0 14.5
T
A
= 125 C 6.3 15.2
I
DD(WUFAH)
Supply current during
wakeup time from
Active-halt mode
(using HSI)
2.4 mA
t
WU_HSI(AH)
(8)(9)
Wakeup time from
Active-halt mode to
Run mode (using HSI)
4.7 7 s
t
WU_LSI(AH)
(8)
(9)
Wakeup time from
Active-halt mode to
Run mode (using LSI)
150 s
1. No floating I/O, unless otherwise specified.
2. RTC enabled. Clock source = LSI
3. RTC enabled, LCD enabled with external V
LCD
= 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.
4. RTC enabled, LCD enabled with external V
LCD
, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
5. LCD enabled with internal LCD booster V
LCD
= 3 V , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD
connected.
(I
DD LSE
) must be added. Refer to Table 32
7. RTC enabled. Clock source = LSE
8. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after t
WU
.
9. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
Table 24. Total current consumption and timing in Active-halt mode at V
DD
= 1.65 V to 3.6 V
Symbol Parameter
Conditions
(1)
Typ Max Unit
Doc ID 15962 Rev 7 75/124


Table 25. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal
Symbol Parameter Condition
(1)
Typ Unit
I
DD(AH)
(2)
Supply current in Active-halt
mode
V
DD
= 1.8 V
LSE 1.15
A
LSE/32
(3)
1.05
V
DD
= 3 V
LSE 1.30
LSE/32
(3)
1.20
V
DD
= 3.6 V
LSE 1.45
LSE/32
(3)
1.35
1. No floating I/O, unless otherwise specified.
2. Based on measurements on bench with 32.768 kHz external crystal oscillator.
3. RTC clock is LSE divided by 32.
Table 26. Total current consumption and timing in Halt mode at V
DD
= 1.65 to 3.6 V
Symbol Parameter Condition
(1)
Typ Max Unit
I
DD(Halt)
Supply current in Halt mode
(Ultra low power ULP bit =1 in
the PWR_CSR2 register)
T
A
= -40 C to 25 C 350
1400
(2)
nA
T
A
= 55 C 580 2000
T
A
= 85 C 1160
2800
(2)
T
A
= 105 C 2560
6700
(2)
T
A
= 125 C 4.4
13
(2)
A
I
DD(WUHalt)
Supply current during wakeup
time from Halt mode (using
HSI)
2.4 mA
t
WU_HSI(Halt)
(3)(4)
Wakeup time from Halt to Run
mode (using HSI)
4.7 7 s
t
WU_LSI(Halt)
(3)(4)
Wakeup time from Halt mode
to Run mode (using LSI)
150 s
1. T
A
= -40 to 125 C, no floating I/O, unless otherwise specified.
3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
4. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after t
WU
.
76/124 Doc ID 15962 Rev 7
Current consumption of on-chip peripherals

Table 27. Peripheral current consumption
Symbol Parameter
Typ.
V
DD
= 3.0 V
Unit
I
DD(TIM1) TIM1 supply current
(1)
13
A/MHz
I
(1)
8
I
(1)
8
I
DD(TIM4) TIM4 timer supply current
(1)
3
I
DD(USART1) USART1 supply current
(2)
6
I
DD(SPI1) SPI1 supply current
(2)
3
I
DD(I2C1) I
2
C1 supply current
(2)
5
I
DD(DMA1) DMA1 supply current
(2)
3
I
DD(WWDG) WWDG supply current
(2)
2
I
DD(ALL) Peripherals ON
(3)
44 A/MHz
I
DD(ADC1) ADC1 supply current
(4)
1500
A
I
DD(DAC) DAC supply current
(5)
370
I
DD(COMP1) Comparator 1 supply current
(6)
0.160
I
DD(COMP2) Comparator 2 supply current
(6)
Slow mode 2
Fast mode 5
I
DD(PVD/BOR)
Power voltage detector and brownout Reset unit supply current
(7)
2.6
I
DD(BOR) Brownout Reset unit supply current
(7)
2.4
I
DD(IDWDG)
Independent watchdog supply current
including LSI supply
current
0.45
excluding LSI
supply current
0.05
1. Data based on a differential I
DD
measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
DD
measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins
toggling. Not tested in production.
3. Peripherals listed above the I
DD(ALL)
parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.
DD
measurement between ADC in reset configuration and continuous ADC conversion.
DD
measurement between DAC in reset configuration and continuous DAC conversion of
V
DD
/2. Floating DAC output.
DD
measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2
enabled with static inputs. Supply current of internal reference voltage excluded.
7. Including supply current of internal reference voltage.
Doc ID 15962 Rev 7 77/124

9.3.4 Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
DD
and T
A
.

LSE external clock (LSEBYP=1 in CLK_ECKCR)
DD
and T
A
.

Table 28. Current consumption under external reset
Symbol Parameter Conditions Typ Unit
I
DD(RST)
Supply current under
external reset
(1)
All pins are externally
tied to V
DD
V
DD
= 1.8 V 48
A V
DD
= 3 V 76
V
DD
= 3.6 V 91
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
Table 29. HSE external clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
HSE_ext
External clock source
frequency
(1)
1. Data guaranteed by Design, not tested in production.
1 16 MHz
V
HSEH
OSC_IN input pin high level
voltage
0.7 x V
DD
V
DD
V
V
HSEL
OSC_IN input pin low level
voltage
V
SS
0.3 x V
DD
C
in(HSE)
OSC_IN input
capacitance
(1)
2.6 pF
I
LEAK_HSE
OSC_IN input leakage
current
V
SS
< V
IN
< V
DD
1 A
Table 30. LSE external clock characteristics
Symbol Parameter Min Typ Max Unit
f
LSE_ext External clock source frequency
(1)
32.768 kHz
V
LSEH
(2)
OSC32_IN input pin high level voltage 0.7 x V
DD
V
DD
V
V
LSEL
(2)
OSC32_IN input pin low level voltage V
SS
0.3 x V
DD
C
in(LSE) OSC32_IN input capacitance
(1)
0.6 pF
I
LEAK_LSE
OSC32_IN input leakage current 1 A
1. Data guaranteed by Design, not tested in production.
78/124 Doc ID 15962 Rev 7
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Figure 17. HSE oscillator circuit diagram
HSE oscillator critical g
m
formula
R
m
: Motional resistance (see crystal specification), L
m
: Motional inductance (see crystal specification),
C
m
: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),
C
L1
=C
L2
=C: Grounded external capacitance
g
m
>> g
mcrit
Table 31. HSE oscillator characteristics
f
HSE
High speed external oscillator
frequency
1 16 MHz
R
F
Feedback resistor 200 kO
C
(1)
Recommended load capacitance
(2)
20 pF
I
DD(HSE)
HSE oscillator power consumption
C = 20 pF,
f
OSC
= 16 MHz
2.5 (startup)
0.7 (stabilized)
(3)
mA
C = 10 pF,
f
OSC
=16 MHz
2.5 (startup)
0.46 (stabilized)
(3)
g
m
Oscillator transconductance 3.5
(3)
mA/V
t
SU(HSE)
(4)
Startup time V
DD
is stabilized 1 ms
1. C=C
L1
=C
L2
is approximately equivalent to 2 x crystal C
LOAD
.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R
m
value.
Refer to crystal manufacturer for more details
3. Data guaranteed by Design. Not tested in production.
4. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This
value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
OSC_OUT
OSC_IN
f
HSE
to core
C
L1
C
L2
R
F
STM8
Resonator
Consumption
control
g
m
R
m
C
m
L
m
C
O
Resonator
g
mcri t
2 H f
HSE
( )
2
R
m
2Co C + ( )
2
=
Doc ID 15962 Rev 7 79/124
LSE crystal/ceramic resonator oscillator
The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Figure 18. LSE oscillator circuit diagram
Table 32. LSE oscillator characteristics
f
LSE
Low speed external oscillator
frequency
32.768 kHz
R
F
Feedback resistor AV = 200 mV 1.2 MO
C
(1)
Recommended load capacitance
(2)
8 pF
I
DD(LSE)
LSE oscillator power consumption
1.4
(3)
A
V
DD
= 1.8 V 450
nA V
DD
= 3 V 600
V
DD
= 3.6 V 750
g
m
Oscillator transconductance 3
(3)
A/V
t
SU(LSE)
(4)
Startup time V
DD
is stabilized 1 s
1. C=C
L1
=C
L2
is approximately equivalent to 2 x crystal C
LOAD
.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small R
m
value.
Refer to crystal manufacturer for more details.
4. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
OSC_OUT
OSC_IN
f
LSE

C
L1
C
L2
R
F
STM8
Resonator
Consumption
control
g
m
R
m
C
m
L
m
C
O
Resonator
80/124 Doc ID 15962 Rev 7
Internal clock sources
DD
, and T
A
.
High speed internal RC oscillator (HSI)
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.

Figure 19. Typical HSI frequency vs V
DD
Table 33. HSI oscillator characteristics
Symbol Parameter
Conditions
(1)
Min Typ Max Unit
f
HSI
Frequency V
DD
= 3.0 V 16 MHz
ACC
HSI
Accuracy of HSI
oscillator (factory
calibrated)
V
DD
= 3.0 V, T
A
= 25 C -1
(2)
1
(2)
%
V
DD
= 3.0 V, 0 C s T
A
s 55 C -1.5 1.5 %
V
DD
= 3.0 V, -10 C s T
A
s 70 C -2 2 %
V
DD
= 3.0 V, -10 C s T
A
s 85 C -2.5 2 %
V
DD
= 3.0 V, -10 C s T
A
s 125 C -4.5 2 %
1.65 V s V
DD
s 3.6 V,
-40 C s T
A
s 125 C
-4.5 3 %
TRIM
HSI user trimming
step
(3)
Trimming code = multiple of 16 0.4 0.7 %
Trimming code = multiple of 16 1.5 %
t
su(HSI)
HSI oscillator setup
time (wakeup time)
3.7 6
(4)
s
I
DD(HSI)
HSI oscillator power
consumption
100 140
(4)
A
1. V
DD
= 3.0 V, T
A
= -40 to 125 C unless otherwise specified.
3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16
(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 STM8L15x internal RC oscillator calibration application note for
more details.
4. Guaranteed by design, not tested in production.
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6
V
DD
[V]
H
S

f
r
e
q
u
e
n
c
y

[
M
H
z
]
-40C
25C
90C
130C
Doc ID 15962 Rev 7 81/124
Low speed internal RC oscillator (LSI)
In the following table, data are based on characterization results, not tested in production.

Figure 20. Typical LSI frequency vs. V
DD
Table 34. LSI oscillator characteristics
Symbol
Parameter
(1)
1. V
DD
= 1.65 V to 3.6 V, T
A
Conditions
(1)
Min Typ Max Unit
f
LSI
Frequency 26 38 56 kHz
t
su(LSI)
LSI oscillator wakeup time 200
(2)
s
I
DD(LSI)
LSI oscillator frequency
drift
(3)
3. This is a deviation for an individual part, once the initial frequency has been measured.
0 C s T
A
s 85 C -12 11 %
25
27
29
31
33
35
37
39
41
43
45
1.6 2.1 2.6 3.1 3.6
VDD [V]
L
S

f
r
e
q
u
e
n
c
y

[
k
H
z
]
-40C
25C
90C
130C
82/124 Doc ID 15962 Rev 7
9.3.5 Memory characteristics
T
A

Flash memory

Table 35. RAM and hardware registers
V
RM
Data retention mode
(1)
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.
Halt mode (or Reset) 1.65 V
Table 36. Flash program and data EEPROM memory
Symbol Parameter Conditions Min Typ
Max
(1)
Unit
V
DD
Operating voltage
(all modes, read/write/erase)
f
SYSCLK
= 16 MHz 1.65 3.6 V
t
prog
Programming time for 1 or 64 bytes

(block)
erase/write cycles (on programmed byte)
6 ms
Programming time for 1 to 64 bytes (block)
write cycles (on erased byte)
3 ms
I
prog
Programming/ erasing consumption
T
A
=+25 C, V
DD
= 3.0 V
0.7 mA
T
A
=+25 C, V
DD
= 1.8 V
t
RET
(2)
Data retention (program memory) after 10000
erase/write cycles at T
A
= 40 to +85 C
(6 suffix)
T
RET
= +85 C 30
(1)
years
Data retention (program memory) after 10000
A
= 40 to +125 C
(3 suffix)
T
RET
= +125 C 5
(1)
Data retention (data memory) after 300000
A
= 40 to +85 C
(6 suffix)
T
RET
= +85 C 30
(1)
Data retention (data memory) after 300000
A
= 40 to +125 C
(3 suffix)
T
RET
= +125 C 5
(1)
N
RW
(3)
Erase/write cycles

(program memory) T
A
= 40 to +85 C
(6 suffix),
T
A
= 40 to +125 C
(3 suffix)
10
(1)
kcycles
Erase/write cycles

(data memory)
300
(1)
(4)
2. Conforming to JEDEC JESD22a117
3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation
addresses a single byte.
4. Data based on characterization performed on the whole data memory.
Doc ID 15962 Rev 7 83/124
9.3.6 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V
SS
or
above V
DD
(for standard pins) should be avoided during normal product operation. However,
in order to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.

9.3.7 I/O port pin characteristics
General characteristics
DD
and T
A
unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 37. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
I
INJ
Injected current on true open-drain pins (PC0 and
PC1)
-5 +0
mA
Injected current on all five-volt tolerant (FT) pins -5 +0
Injected current on all 3.6 V tolerant (TT) pins -5 +0
Injected current on any other pin -5 +5
84/124 Doc ID 15962 Rev 7

Table 38. I/O static characteristics
Symbol Parameter
Conditions
(1)
Min
Typ

Max Unit
V
IL Input low level voltage
(2)
Input voltage on true open-drain
pins (PC0 and PC1)
V
SS
-0.3 0.3 x V
DD
V
Input voltage on five-volt
tolerant (FT) pins (PA7 and
PE0)
V
SS
-0.3 0.3 x V
DD
Input voltage on 3.6 V tolerant
(TT) pins
V
SS
-0.3 0.3 x V
DD
Input voltage on any other pin V
SS
-0.3 0.3 x V
DD
V
IH Input high level voltage
(2)
pins (PC0 and PC1)
with V
DD
< 2 V
0.70 x V
DD
5.2
V
pins (PC0 and PC1)
with V
DD
> 2 V
5.5
PE0)
with V
DD
< 2 V
0.70 x V
DD
5.2
PE0)
with V
DD
> 2 V
5.5
Input voltage on 3.6 V tolerant
(TT) pins
3.6
Input voltage on any other pin 0.70 x V
DD
V
DD
+0.3
V
hys
Schmitt trigger voltage
hysteresis
(3)
I/Os 200
mV
True open drain I/Os 200
I
lkg
Input leakage current
(4)
V
SS
s V
IN
s V
DD
High sink I/Os
- - 50
(5)
nA
V
SS
s V
IN
s V
DD
True open drain I/Os
- - 200
(5)
V
SS
s V
IN
s V
DD
PA0 with high sink LED driver
capability
- - 200
(5)
R
PU
Weak pull-up equivalent
resistor
(2)(6)
V
IN
=V
SS
30 45 60 kO
C
IO
I/O pin capacitance 5 pF
1. V
DD
= 3.0 V, T
A
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
Doc ID 15962 Rev 7 85/124
Figure 21. Typical V
IL
and V
IH
vs V
DD
(high sink I/Os)
Figure 22. Typical V
IL
and V
IH
vs V
DD
(true open drain I/Os)
6. R
PU
pull-up equivalent resistor based on a resistive transistor(corresponding I
PU
current characteristics described in
Figure 24).
0
0.5
1
1.5
2
2.5
3
1.6 2.1 2.6 3.1 3.6
V
DD
[V]
V
L

a
n
d

V
H

[
V
]
-40C
25C
90C
130C
0
0.5
1
1.5
2
2.5
3
1.6 2.1 2.6 3.1 3.6
V
DD
[V]
V
L

a
n
d

V
H

[
V
]
-40C
25C
90C
130C
86/124 Doc ID 15962 Rev 7
Figure 23. Typical pull-up resistance R
PU
vs V
DD
with V
IN
=V
SS
Figure 24. Typical pull-up current I
pu
vs V
DD
with V
IN
=V
SS
30
35
40
45
50
55
60
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
DD
[V]
P
u
l
l
-
U
p

r
e
s
i
s
t
a
n
c
e

[
k
]
-40C
25C
90C
130C
0
20
40
60
80
100
120
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6
V
DD
[V]
P
u
l
l
-
U
p

c
u
r
r
e
n
t

[
A
]
-40C
25C
90C
130C
Doc ID 15962 Rev 7 87/124
Output driving current
DD
and T
A

Table 39. Output driving current (high sink ports)
I/O
Type
Symbol Parameter Conditions Min Max Unit
H
i
g
h

s
i
n
k
V
OL
(1)
1. The I
IO
current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
Output low level voltage for an I/O pin
I
IO
= +2 mA,
V
DD
= 3.0 V
0.45 V
I
IO
= +2 mA,
V
DD
= 1.8 V
0.45 V
I
IO
= +10 mA,
V
DD
= 3.0 V
0.7 V
V
OH
(2)
2. The I
IO
current sourced must always respect the absolute maximum rating specified in Table 16 and the
sum of I
IO
VDD
.
Output high level voltage for an I/O pin
I
IO
= -2 mA,
V
DD
= 3.0 V
V
DD
-0.45 V
I
IO
= -1 mA,
V
DD
= 1.8 V
V
DD
-0.45 V
I
IO
= -10 mA,
V
DD
= 3.0 V
V
DD
-0.7 V
Table 40. Output driving current (true open drain ports)
I/O
Type
O
p
e
n

d
r
a
i
n
V
OL
(1)
1. The I
IO
of I
IO
VSS
.
I
IO
= +3 mA,
V
DD
= 3.0 V
0.45
V
I
IO
= +1 mA,
V
DD
= 1.8 V
0.45
Table 41. Output driving current (PA0 with high sink LED driver capability)
I/O
Type
I
R V
OL
(1)
1. The I
IO
of I
IO
VSS
.
I
IO
= +20 mA,
V
DD
= 2.0 V
0.45 V
88/124 Doc ID 15962 Rev 7

Figure 25. Typ. V
OL
@ V
DD
= 3.0 V (high sink
ports)
Figure 26. Typ. V
OL
@ V
DD
= 1.8 V (high sink
ports)
0
0.25
0.5
0.75
1
0 2 4 6 8 10 12 14 16 18 20
OL [mA]
V
O
L
[
V
]
-40C
25C
90C
130C
ai18226
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 1 2 3 4 5 6 7 8
OL [mA]
V
O
L
[
V
]
-40C
25C
90C
130C
ai18227
Figure 27. Typ. V
OL
@ V
DD
= 3.0 V (true open
drain ports)
Figure 28. Typ. V
OL
@ V
DD
= 1.8 V (true open
drain ports)
ai18228
0
0.1
0.2
0.3
0.4
0.5
0 1 2 3 4 5 6 7
OL [mA]
V
O
L
[
V
]
-40C
25C
90C
130C
0
0.1
0.2
0.3
0.4
0.5
0 1 2 3 4 5 6 7
OL [mA]
V
O
L
[
V
]
-40C
25C
90C
130C
all8229
Figure 29. Typ. V
DD -
V
OH
@ V
DD
= 3.0 V (high
sink ports)
Figure 30. Typ. V
DD -
V
OH
@ V
DD
= 1.8 V (high
sink ports)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
0 2 4 6 8 10 12 14 16 18 20
OH [mA]
V
D
D

-

V
O
H
[
V
]
-40C
25C
90C
130C
ai12830
0
0.1
0.2
0.3
0.4
0.5
0 1 2 3 4 5 6 7
OH [mA]
V
D
D

-

V
O
H
[
V
]
-40C
25C
90C
130C
all823l
Doc ID 15962 Rev 7 89/124
NRST pin
DD
and T
A

Figure 31. Typical NRST pull-up resistance R
PU
vs V
DD

Table 42. NRST pin characteristics
Symbol Parameter Conditions Min
Typ

Max Unit
V
IL(NRST) NRST input low level voltage
(1)
V
SS
0.8
V
V
IH(NRST) NRST input high level voltage
(1)
1.4 V
DD
V
OL(NRST) NRST output low level voltage
(1)
I
OL
= 2 mA
for 2.7 V s V
DD
s 3.6
V
0.4
I
OL
= 1.5 mA
for V
DD
< 2.7 V
V
HYST NRST input hysteresis
(3)
10%V
DD
(2)
mV
R
PU(NRST)
NRST pull-up equivalent resistor
(1)
30 45 60 kO
V
F(NRST) NRST input filtered pulse
(3)
50
ns
V
NF(NRST) NRST input not filtered pulse
(3)
300
2. 200 mV min.
30
35
40
45
50
55
60
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V
DD
[V]
P
u
l
l
-
u
p

r
e
s
i
s
t
a
n
c
e

[
k
]
-40C
25C
90C
130C
90/124 Doc ID 15962 Rev 7
Figure 32. Typical NRST pull-up current I
pu
vs V
DD

The reset network shown in Figure 33 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V
IL(NRST)
max. level specified
in Table 42. Otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If the NRST signal is used to reset the
external circuitry, attention must be paid to the charge/discharge time of the external
capacitor to fulfill the external devices reset timing conditions. The minimum recommended
capacity is 10 nF.
0
20
40
60
80
100
120
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6
V
DD
[V]
P
u
l
l
-
U
p

c
u
r
r
e
n
t

[
A
]
-40C
25C
90C
130C
Doc ID 15962 Rev 7 91/124
Figure 33. Recommended NRST pin configuration
EXTERNAL
RESET
CIRCUIT
STM8
Filter
R
PU
V
DD
INTERNAL RESET
NRST
0.1 F
(Optional)
92/124 Doc ID 15962 Rev 7
9.3.8 Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, f
SYSCLK
frequency and V
DD
supply voltage
conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 43. SPI1 characteristics
Symbol Parameter Conditions
(1)
Min Max Unit
f
SCK
1/t
c(SCK)
SPI1 clock frequency
Master mode 0 8
MHz
Slave mode 0 8
t
r(SCK)
t
f(SCK)
SPI1 clock rise and fall
time
Capacitive load: C = 30 pF - 30 ns
t
su(NSS)
(2)
NSS setup time Slave mode 4 x 1/f
SYSCLK
-
t
h(NSS)
(2)
NSS hold time Slave mode 80 -
t
w(SCKH)
(2)
t
w(SCKL)
(2)
SCK high and low time
Master mode,
f
MASTER
= 8 MHz, f
SCK
= 4 MHz
105 145
t
su(MI)
(2)
t
su(SI)
(2)
Data input setup time
Master mode 30 -
Slave mode 3 -
t
h(MI)
(2)
t
h(SI)
(2)
Data input hold time
Master mode 15 -
Slave mode 0 -
t
a(SO)
(2)(3)
Data output access time Slave mode - 3x 1/f
SYSCLK
t
dis(SO)
(2)(4)
Data output disable time Slave mode 30 -
t
v(SO)
(2)
Data output valid time Slave mode (after enable edge) - 60
t
v(MO)
(2)
Data output valid time
Master mode (after enable
edge)
- 20
t
h(SO)
(2)
Data output hold time
Slave mode (after enable edge) 15 -
t
h(MO)
(2)
Master mode (after enable
edge)
1 -
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.
Doc ID 15962 Rev 7 93/124
(1)
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
ai14134
S
C
K

I
n
p
u
t CPHA=0
MOSI
I NPUT
MISO
OUT PUT
CPHA=0
MSB OUT
MSB IN
BI T6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BI T1 IN
NSS input
t
SU(NSS) t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO) t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
ai14135
S
C
K

I
n
p
u
t CPHA=1
MOSI
I NPUT
MISO
OUT PUT
CPHA=1
MSB OUT
MSB IN
BI T6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BI T1 IN
t
SU(NSS) t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
NSS input
94/124 Doc ID 15962 Rev 7
Figure 36. SPI1 timing diagram - master mode
(1)
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
ai14136
S
C
K

I
n
p
u
t CPHA=0
MOSI
OUTUT
MISO
INPUT
CPHA=0
MSBIN
MSB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
BI T1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
S
C
K

I
n
p
u
t CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)
Doc ID 15962 Rev 7 95/124
I
2
C - Inter IC control interface
DD
, f
SYSCLK
, and T
A
The STM8L I
2
C interface (I2C1) meets the requirements of the Standard I
2
C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).

Note: For speeds around 200 kHz, the achieved speed can have a 5% tolerance
For other speed ranges, the achieved speed can have a 2% tolerance
The above variations depend on the accuracy of the external components used.
Table 44. I2C characteristics
Symbol Parameter
Standard mode
I
2
C
Fast mode I
2
C
(1)
1. f
SYSCLK
must be at least equal to 8 MHz to achieve max fast I
2
C speed (400 kHz).
Unit
Min
(2)
2. Data based on standard I
2
C protocol requirement, not tested in production.
Max
(2)
Min
(2)
Max
(2)
t
w(SCLL)
SCL clock low time 4.7 1.3
s
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100
ns
t
h(SDA)
SDA data hold time 0 0 900
t
r(SDA)
t
r(SCL)
SDA and SCL rise time 1000 300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time 300 300
t
h(STA)
START condition hold time 4.0 0.6
s
t
su(STA)
Repeated START condition setup
time
4.7 0.6
t
su(STO)
STOP condition setup time 4.0 0.6 s
t
w(STO:STA)
STOP to START condition time (bus
free)
4.7 1.3 s
C
b
Capacitive load for each bus line 400 400 pF
96/124 Doc ID 15962 Rev 7
Figure 37. Typical application with I
2
C bus and timing diagram
1)
1. Measurement points are done at CMOS levels: 0.3 x V
DD
and 0.7 x V
DD
9.3.9 LCD controller (STM8L152xx only)
In the following table, data are guaranteed by design. Not tested in production.

REPEATED START
START
STOP
START
t
f(SDA)
t
r(SDA)
t
su(SDA)
t
h(SDA)
t
f(SCL)
t
r(SCL)
t
w(SCLL)
t
w(SCLH)
t
h(STA)
t
su(STO)
t
su(STA)
t
w(STO:STA)
SDA
SCL
4.7kO
SDA
STM8L
SCL
V
DD
100O
100O
V
DD
4.7kO
I
2
C BUS
Table 45. LCD characteristics
Symbol Parameter Min Typ Max. Unit
V
LCD
LCD external voltage 3.6 V
V
LCD0
LCD internal reference voltage 0 2.6 V
V
LCD1
V
LCD2
V
LCD3
V
LCD4
V
LCD5
V
LCD6
V
LCD7
C
EXT
V
LCD
external capacitance 0.1 2 F
I
DD
Supply current
(1)
at V
DD
= 1.8 V
1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.
3 A
Supply current
(1)
at V
DD
= 3 V 3 A
R
HN
(2)
High value resistive network (low drive) 6.6 MO
R
LN
(3)
Low value resistive network (high drive) 360 kO
V
33
Segment/Common higher level voltage V
LCDx
V
V
23
Segment/Common 2/3 level voltage 2/3V
LCDx
V
V
12
LCDx
V
V
13
LCDx
V
V
0
Segment/Common lowest level voltage 0 V
Doc ID 15962 Rev 7 97/124
VLCD external capacitor (STM8L152xx only)
The application can achieve a stabilized LCD reference voltage by connecting an external
capacitor C
EXT
to the V
LCD
pin. C
EXT
is specified in Table 45.
9.3.10 Embedded reference voltage

2. R
HN
is the total high value resistive network.
3. R
LN
is the total low value resistive network.
Table 46. Reference voltage characteristics
Symbol Parameter Conditions Min Typ Max. Unit
I
REFINT
Internal reference voltage
consumption
1.4 A
T
S_VREFINT
(1)(2)
ADC sampling time when reading
the internal reference voltage
5 10 s
I
BUF
(2)
Internal reference voltage buffer
consumption (used for ADC)
13.5 25 A
V
REFINT out
Reference voltage output
1.202
(3)
1.224
1.242
(3)
V
I
LPBUF
(2)
Internal reference voltage low
power buffer consumption (used for
comparators or output)
730 1200 nA
I
REFOUT
(2)
Buffer output current
(4)
1 A
C
REFOUT
Reference voltage output load 50 pF
t
VREFINT
Internal reference voltage startup
time
2 3 ms
t
BUFEN
(2)
Internal reference voltage buffer
startup time once enabled
(1)
10 s
ACC
VREFINT
Accuracy of V
REFINT
stored in the
VREFINT_Factory_CONV byte
(5)
5 mV
STAB
VREFINT
Stability of V
REFINT
over
temperature
-40 C s T
A
s 125
C
20 50 ppm/C
Stability of V
REFINT
over
temperature
0 C s T
A
s 50 C 20 ppm/C
STAB
VREFINT
Stability of V
REFINT
after 1000 hours TBD ppm
1. Defined when ADC output reaches its final value 1/2LSB
3. Tested in production at V
DD
= 3 V 10 mV.
4. To guaranty less than 1% V
REFOUT
deviation
5. Measured at V
DD
= 3 V 10 mV. This value takes into account V
DD
accuracy and ADC conversion accuracy.
98/124 Doc ID 15962 Rev 7
9.3.11 Temperature sensor

9.3.12 Comparator characteristics
In the following table, data are guaranteed by design, not tested in production, unless
otherwise specified.

Table 47. TS characteristics
Symbol Parameter Min Typ Max. Unit
V
90
(1)
DD
= 3 V 10 mV. The 8 LSB of the V
90
ADC conversion result are stored in the
TS_Factory_CONV_V90 byte.
Sensor reference voltage at 90C 5 C, 0.580 0.597 0.614 V
T
L
V
SENSOR
linearity with temperature 1 2 C
Avg_slope
(2)
Average slope 1.59 1.62 1.65 mV/C
I
DD(TEMP)
(2)
Consumption 3.4 6 A
T
START
(2)(3)
3. Defined for ADC output reaching its final value 1/2LSB.
Temperature sensor startup time 10 s
T
S_TEMP
(2)
ADC sampling time when reading the
temperature sensor
10 s
Table 48. Comparator 1 characteristics
Symbol Parameter Min Typ
Max
(1)
1. Based on characterization, not tested in production.
Unit
V
DDA
Analog supply voltage 1.65 3.6 V
T
A
Temperature range -40 125 C
R
400K
R
400K
value 300 400 500
kO
R
10K
R
10K
value 7.5 10 12.5
V
IN
Comparator 1 input voltage range 0.6 V
DDA
V
V
REFINT Internal reference voltage
(2)
DD
= 3 V 10 mV.
1.202 1.224 1.242
t
START
Comparator startup time 7 10
s
t
d
Propagation delay
(3)

3. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3 10
V
offset
Comparator offset error 3 10 mV
I
COMP1
Current consumption
(4)

4. Comparator consumption only. Internal reference voltage not included.
160 260 nA
Doc ID 15962 Rev 7 99/124
In the following table, data are guaranteed by design, not tested in production.

9.3.13 12-bit DAC characteristics

Table 49. Comparator 2 characteristics
Symbol Parameter Conditions Min Typ
Max
(1)
1. Based on characterization, not tested in production.
Unit
V
DDA
T
A
V
IN
Comparator 2 input voltage range 0 V
DDA
V
t
START
Comparator startup time
Fast mode 15 20
s
Slow mode 20 25
t
d slow
Propagation delay in slow mode
(2)
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
1.65 V s V
DDA

s 2.7 V
1.8 3.5
2.7 V s V
DDA
s
3.6 V
2.5 6
t
d fast
Propagation delay in fast mode
(2)
1.65 V s V
DDA

s 2.7 V
0.8 2
2.7 V s V
DDA
s
3.6 V
1.2 4
V
offset
Comparator offset error 4 20 mV
I
COMP2
Current consumption
(3)
3. Comparator consumption only. Internal reference voltage not included.
Fast mode 3.5 5
A
Slow mode 0.5 2
Table 50. DAC characteristics
V
DDA
V
REF+
Reference supply voltage 1.8 V
DDA
100/124 Doc ID 15962 Rev 7
I
VREF
Current consumption onV
REF+

supply
V
REF+
= 3.3 V, no
load, middle code
(0x800)
130 220
A
V
REF+
= 3.3 V, no
load, worst code
(0x000)
220 350
I
VDDA
Current consumption on V
DDA

supply
V
DDA
= 3.3 V, no
load, middle code
(0x800)
210 320
V
DDA
= 3.3 V, no
load, worst code
(0x000)
320 520
T
A
R
L
Resistive load
(1)

(2)
DACOUT buffer ON 5 kO
R
O
Output impedance DACOUT buffer OFF 8 10 kO
C
L
Capacitive load
(3)
50 pF
DAC_OUT DAC_OUT voltage
(4)
DACOUT buffer ON 0.2 V
DDA
-0.2 V
DACOUT buffer OFF 0 V
REF+
-1 LSB V
t
settling
Settling time (full scale: for a 12-
bit input code transition between
the lowest and the highest input
codes when DAC_OUT reaches
the final value 1LSB)
R
L
>5 kO, C
L
s 50 pF 7 12 s
Update rate
Max frequency for a correct
DAC_OUT (@95%) change when
small variation of the input code
(from code i to i+1LSB).
R
L
> 5 kO, C
L
s
50 pF
1 Msps
t
WAKEUP
Wakeup time from OFF state.
Input code between lowest and
highest possible codes.
R
L
>5 kO, C
L
s 50 pF 9 15 s
PSRR+
Power supply rejection ratio (to
VDDA) (static DC measurement)
R
L
> 5 kO, C
L
s 50 pF -60 -35 dB
1. Resistive load between DACOUT and GNDA
2. Output on PF0 (48-pin package only)
3. Capacitive load at DACOUT pin
4. It gives the output excursion of the DAC
Table 50. DAC characteristics (continued)
Doc ID 15962 Rev 7 101/124
In the following table, data based on characterization results, not tested in production.


Table 51. DAC accuracy
Symbol Parameter Conditions Typ Max Unit
DNL Differential non linearity
(1)
R
L
>5 kO, C
L
s 50 pF
DACOUT buffer ON
(2)
1.5 3
12-bit
LSB
No load
DACOUT buffer OFF
1.5 3
INL Integral non linearity
(3)
R
L
>5 kO, C
L
s 50 pF
DACOUT buffer ON
(2)
2 4
No load
DACOUT buffer OFF
2 4
Offset Offset error
(4)
R
L
>5 kO, C
L
s 50 pF
DACOUT buffer ON
(2)
10 25
No load
DACOUT buffer OFF
5 8
Offset1 Offset error at Code 1
(5)
DACOUT buffer OFF 1.5 5
Gain error Gain error
(6)
R
L
>5 kO, C
L
s 50 pF
DACOUT buffer ON
(2)
+0.1/-0.2 +0.2/-0.5
%
No load
DACOUT buffer OFF
+0/-0.2 +0/-0.4
TUE Total unadjusted error
R
L
>5 kO, C
L
s 50 pF
DACOUT buffer ON
(2)
12 30
12-bit
LSB
No load
DACOUT buffer OFF
8 12
1. Difference between two consecutive codes - 1 LSB.
2. For 48-pin packages only. For 28-pin and 32-pin packages, DAC output buffer must be kept off and no load must be
applied.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023.
4. Difference between the value measured at Code (0x800) and the ideal value = V
REF+
/2.
5. Difference between the value measured at Code (0x001) and the ideal value.
6. Difference between the ideal slope of the transfer function and the measured slope computed from Code 0x000 and 0xFFF
when buffer is ON, and from Code giving 0.2 V and (V
DDA
-0.2) V when buffer is OFF.
Table 52. DAC output on PB4-PB5-PB6
(1)
1. 32 or 28-pin packages only. The DAC channel can be routed either on PB4, PB5 or PB6 using the routing
interface I/O switch registers.
Symbol Parameter Conditions Max Unit
R
int
Internal resistance
between DAC output and
PB4-PB5-PB6 output
2.7 V < V
DD
< 3.6 V 1.4
kO
2.4 V < V
DD
< 3.6 V 1.6
2.0 V < V
DD
< 3.6 V 3.2
1.8 V < V
DD
< 3.6 V 8.2
102/124 Doc ID 15962 Rev 7
9.3.14 12-bit ADC1 characteristics

Table 53. ADC1 characteristics
V
DDA
V
REF+
Reference supply
voltage
2.4 V s V
DDA
s 3.6 V 2.4 V
DDA
V
1.8 V s V
DDA
s 2.4 V V
DDA
V
V
REF-
Lower reference voltage V
SSA
V
I
VDDA
Current on the VDDA
input pin
1000 1450 A
I
VREF+
Current on the VREF+
input pin
400
700
(peak)
(1)
A
450
(average)
(1)
A
V
AIN
Conversion voltage
range
0
(2)
V
REF+
T
A
R
AIN
External resistance on
V
AIN

on PF0 fast channel
50
(3)
kO
on all other channels
C
ADC
Internal sample and
hold capacitor
on PF0 fast channel
16 pF
on all other channels
f
ADC
ADC sampling clock
frequency
2.4 Vs V
DDA
s 3.6 V
without zooming
0.320 16 MHz
1.8 Vs V
DDA
s 2.4 V
with zooming
0.320 8 MHz
f
CONV
12-bit conversion rate
V
AIN
on PF0 fast
channel
1
(4)(5)
MHz
V
AIN
on all other
channels
760
(4)(5)
kHz
f
TRIG
External trigger
frequency
t
conv
1/f
ADC
t
LAT
External trigger latency 3.5 1/f
SYSCLK
Doc ID 15962 Rev 7 103/124
t
S
Sampling time
V
AIN
on PF0 fast
channel
V
DDA
< 2.4 V
0.43
(4)(5)
s
V
AIN
on PF0 fast
channel
2.4 V s V
DDA
s 3.6 V
0.22
(4)(5)
s
V
AIN
on slow channels
V
DDA
< 2.4 V
0.86
(4)(5)
s
V
AIN
on slow channels
2.4 V s V
DDA
s 3.6 V
0.41
(4)(5)
s
t
conv
12-bit conversion time
12 + t
S
1/f
ADC
16 MHz 1
(4)
s
t
WKUP
Wakeup time from OFF
state
3 s
t
IDLE
(6)
Time before a new
conversion
T
A
= +25 C 1
(7)
s
T
A
= +70 C 20
(7)
ms
T
A
= +125 C 2
(7)
ms
t
VREFINT
Internal reference
voltage startup time
refer to
Table 46
ms
1. The current consumption through V
REF
is composed of two parameters:
- one constant (max 300 A)
- one variable (max 400 A), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 A and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 A at
1Msps
2. V
REF-
or V
DDA
must be tied to ground.
4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 kO.
5. Value obtained for continuous conversion on fast channel.
6. The time between 2 conversions, or between ADC ON and the first conversion must be lower than t
IDLE.
7. The t
IDLE
maximum value is on the Z revision code of the device.
Table 53. ADC1 characteristics (continued)
104/124 Doc ID 15962 Rev 7
In the following three tables, data are guaranteed by characterization result, not tested in
production.

Table 54. ADC1 accuracy with V
DDA
= 3.3 V to 2.5 V
Symbol Parameter Conditions Typ Max Unit
DNL Differential non linearity
f
ADC
= 16 MHz 1 1.6
LSB
f
ADC
= 8 MHz 1 1.6
f
ADC
= 4 MHz 1 1.5
INL Integral non linearity
f
ADC
= 16 MHz 1.2 2
f
ADC
= 8 MHz 1.2 1.8
f
ADC
= 4 MHz 1.2 1.7
TUE Total unadjusted error
f
ADC
= 16 MHz 2.2 3.0
f
ADC
= 8 MHz 1.8 2.5
f
ADC
= 4 MHz 1.8 2.3
Offset Offset error
f
ADC
= 16 MHz 1.5 2
LSB
f
ADC
= 8 MHz 1 1.5
f
ADC
= 4 MHz 0.7 1.2
Gain Gain error
f
ADC
= 16 MHz
1 1.5 f
ADC
= 8 MHz
f
ADC
= 4 MHz
DDA
= 2.4 V to 3.6 V
Symbol Parameter Typ Max Unit
DNL Differential non linearity 1 2 LSB
INL
Integral non linearity
1.7 3 LSB
TUE
Total unadjusted error
2 4 LSB
Offset Offset error 1 2 LSB
Gain Gain error 1.5 3 LSB
DDA
= V
REF
+
= 1.8 V to 2.4 V
Symbol Parameter Typ Max Unit
DNL Differential non linearity 1 2 LSB
INL
Integral non linearity
2 3 LSB
TUE
Total unadjusted error
3 5 LSB
Offset Offset error 2 3 LSB
Gain Gain error 2 3 LSB
Doc ID 15962 Rev 7 105/124
Figure 38. ADC1 accuracy characteristics
Figure 39. Typical connection diagram using the ADC
1. Refer to Table 53 for the values of R
AIN
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high C
parasitic
value will downgrade conversion accuracy. To remedy
this, f
ADC
should be reduced.
E
O
E
G
1 LSB
IDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
T
=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
E
O
=Offset Error: deviation between the first actual
transition and the first ideal one.
E
G
=Gain Error: deviation between the last ideal
transition and the last actual one.
E
D
=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
E
L
=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1 2 3 4 5 6 7 4093 4094 4095 4096
(1)
(2)
E
T
E
D
E
L
(3)
V
DDA
V
SSA ai14395b
V
REF+
4096
(or depending on package)]
V
DDA
4096
[1LSB
IDEAL
=

ai17090c
STM8L15xxx
V
DD
ANx
L
50 nA
0.6 V
V
T
R
AN
(1)
Cparasitic
V
AN
0.6 V
V
T
R
ADC
C
ADC
(1)
12-bit
converter
Sample and hold ADC
converter
106/124 Doc ID 15962 Rev 7
Figure 40. Maximum dynamic current consumption on V
REF+
supply pin during ADC
conversion

General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 41 or Figure 42,
depending on whether V
REF+
is connected to V
DDA
or not. Good quality ceramic 10 nF
capacitors should be used. They should be placed as close as possible to the chip.
ADC clock
Sampling (n cycles) Conversion (12 cycles)
I
ref+
300A
700A
Table 57. R
AIN
max for f
ADC
= 16 MHz
(1)
Ts
(cycles)
Ts
(s)
R
AIN
max (kohm)
Slow channels Fast channels
2.4 V < V
DDA
< 3.6 V 1.8 V < V
DDA
< 2.4 V 2.4 V < V
DDA
< 3.3 V 1.8 V < V
DDA
< 2.4 V
4 0.25 Not allowed Not allowed 0.7 Not allowed
9 0.5625 0.8 Not allowed 2.0 1.0
16 1 2.0 0.8 4.0 3.0
24 1.5 3.0 1.8 6.0 4.5
48 3 6.8 4.0 15.0 10.0
96 6 15.0 10.0 30.0 20.0
192 12 32.0 25.0 50.0 40.0
384 24 50.0 50.0 50.0 50.0
Doc ID 15962 Rev 7 107/124
REF+
not connected to V
DDA
)
REF+
connected to V
DDA
)
V
REF+
STM8L STM8L
V
DDA
V
SSA
/V
REF-
1 F // 10 nF
1 F // 10 nF 1 F // 10 nF
Supply
External
reference
ai17031b
V
REF+
/V
DDA
STM8L
1 F // 10 nF
V
REF-
/V
SSA
ai17032b
Supply
108/124 Doc ID 15962 Rev 7
9.3.15 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000 standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to V
DD
and V
SS

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC61967-2 which specifies the board and the loading of each pin.
Table 58. EMS data
Level/
Class
V
FESD
Voltage limits to be applied on
any I/O pin to induce a functional
disturbance
V
DD
= 3.3 V, T
A
= +25 C,
f
CPU
= 16 MHz,
conforms to IEC 61000
3B
V
EFTB
Fast transient voltage burst limits
to be applied through 100 pF on
V
DD
and V
SS
pins to induce a
functional disturbance
V
DD
= 3.3 V, T
A
= +25 C,
f
CPU
= 16 MHz,
conforms to IEC 61000
Using HSI
4A
Using HSE 2B
Doc ID 15962 Rev 7 109/124

Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.

Static latch-up
LU: 3 complementary static tests are required on 6 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.

Table 59. EMI data
(1)
1. Not tested in production.
Monitored
frequency band
Max vs.
Unit
16 MHz
S
EMI
Peak level
V
DD
= 3.6 V,
T
A
= +25 C,
LQFP32
conforming to
IEC61967-2
0.1 MHz to 30 MHz -3
dBV 30 MHz to 130 MHz 9
130 MHz to 1 GHz 4
SAE EMI Level 2 -
Table 60. ESD absolute maximum ratings
Symbol Ratings Conditions
Maximum
value
(1)
Unit
V
ESD(HBM)
(human body model)
T
A
= +25 C
2000
V
V
ESD(CDM)
(charge device model)
500
Table 61. Electrical sensitivities
Symbol Parameter Class
LU Static latch-up class II
110/124 Doc ID 15962 Rev 7
9.4 Thermal characteristics
The maximum chip junction temperature (T
Jmax
) must never exceed the values given in
Table 18: General operating conditions on page 63.
The maximum chip-junction temperature, T
Jmax
, in degree Celsius, may be calculated using
the following equation:
T
Jmax
= T
Amax
+ (P
Dmax
x O
JA
)
Where:
T
Amax
is the maximum ambient temperature in C
O
JA
is the package junction-to-ambient thermal resistance in C/W
P
Dmax
is the sum of P
INTmax
and P
I/Omax
(P
Dmax
= P
INTmax
+ P
I/Omax
)
P
INTmax
is the product of I
DD
and

V
DD
, expressed in Watts. This is the maximum chip
internal power.
P
I/Omax
represents the maximum power dissipation on output pins
Where:
P
I/Omax
=

E (V
OL
*I
OL
) + E((V
DD
-V
OH
)*I
OH
),
taking into account the actual V
OL
/I
OL
and

V
OH
/I
OH
of the I/Os at low and high level in
the application.

Table 62. Thermal characteristics
(1)
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
Symbol Parameter Value Unit
O
JA
Thermal resistance junction-ambient
LQFP 48- 7 x 7 mm
65 C/W
O
JA
UFQFPN 48- 7 x 7mm
32 C/W
O
JA
LQFP 32 - 7 x 7 mm
59 C/W
O
JA
UFQFPN 32 - 5 x 5 mm
38 C/W
O
JA
UFQFPN28 - 4 x 4 mm
118 C/W
O
JA
WLCSP28
70 C/W
STM8L151xx, STM8L152xx Package characteristics
Doc ID 15962 Rev 7 111/124
10 Package characteristics
10.1 ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Package characteristics STM8L151xx, STM8L152xx
112/124 Doc ID 15962 Rev 7
10.2 Package mechanical data
Figure 43. LQFP48 48-pin low profile quad flat package outline (7x7)

5B_ME
L
A1 K
L1
c
A
A2
ccc C
D
D1
D3
E3 E1 E
24
25
36
37
b
48
1
Pin 1
identification
12
13
Table 63. LQFP48 48-pin low profile quad flat package (7x7), package mechanical data
Dim.
mm inches
(1)
Min Typ Max Min Typ Max
A 1.6 0.063
A1 0.05 0.15 0.002 0.0059
A2 1.35 1.4 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.2 0.0035 0.0079
D 8.8 9 9.2 0.3465 0.3543 0.3622
D1 6.8 7 7.2 0.2677 0.2756 0.2835
D3 5.5 0.2165
E 8.8 9 9.2 0.3465 0.3543 0.3622
E1 6.8 7 7.2 0.2677 0.2756 0.2835
E3 5.5 0.2165
e 0.5 0.0197
L 0.45 0.6 0.75 0.0177 0.0236 0.0295
L1 1 0.0394
k 0.0 3.5 7.0 0.0 3.5 7.0
ccc 0.08 0.0031
Number of pins
N 48
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 15962 Rev 7 113/124
Figure 44. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this
back-side pad to PCB ground.
A0B9_M_V2
114/124 Doc ID 15962 Rev 7
Figure 45. UFQFPN48 7 x 7 mm recommended footprint (dimensions in mm)

Table 64. UFQFPN48 ultra thin fine pitch quad flat pack no-lead 7 7 mm, 0.5 mm
pitch package mechanical data
Symbol
millimeters inches
(1)
Min Typ Max Typ Min Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T 0.152 0.0060
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e 0.500 0.0197
7.30
7.30
0.20
0.30
0.55
0.50
5.80
6.20
6.20 5.60
5.60
5.80
0.75
ai15697
48
1
12
13 24
25
36
37
Doc ID 15962 Rev 7 115/124
Figure 46. LQFP32 32-pin low profile quad flat package outline

5V_ME
L
A1 K
L1
c
A
A2
ccc C
D
D1
D3
E3 E1 E
16
17 24
25
b
32
1
Pin 1
identification 8
9
Table 65. LQFP32 32-pin low profile quad flat package, package mechanical data
Dim.
mm inches
(1)
A 1.6 0.063
A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.4 1.45 0.0531 0.0551 0.0571
b 0.3 0.37 0.45 0.0118 0.0146 0.0177
c 0.09 0.2 0.0035 0.0079
D 8.8 9 9.2 0.3465 0.3543 0.3622
D1 6.8 7 7.2 0.2677 0.2756 0.2835
D3 5.6 0.2205
E 8.8 9 9.2 0.3465 0.3543 0.3622
E1 6.8 7 7.2 0.2677 0.2756 0.2835
E3 5.6 0.2205
e 0.8 0.0315
L 0.45 0.6 0.75 0.0177 0.0236 0.0295
L1 1 0.0394
k 0.0 3.5 7.0 0.0 3.5 7.0
ccc 0.1 0.0039
Number of pins
N 32
116/124 Doc ID 15962 Rev 7

Figure 47. UFQFPN32 - 32-lead ultra thin fine pitch
quad flat no-lead package outline
(5 x 5)
(1)(2)(3)
Figure 48. UFQFPN32 recommended
footprint
(1)(4)
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-
side pad to PCB ground.
4. Dimensions are in millimeters.
Seating plane
ddd C
C
A3 A1
A
D
e
9 16
17
24
32
Pin # 1 ID
R = 0.30
8
E
L
L
D2
1
b E2
A0B8_ME

Bottom view
Table 66. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data
Dim.
mm inches
(1)
A 0.5 0.55 0.6 0.0197 0.0217 0.0236
A1 0.00 0.02 0.05 0 0.0008 0.0020
A3 0.152 0.006
b 0.18 0.23 0.28 0.0071 0.0091 0.0110
D 4.90 5.00 5.10 0.1929 0.1969 0.2008
D2 3.50 0.1378
E 4.90 5.00 5.10 0.1929 0.1969 0.2008
E2 3.40 3.50 3.60 0.1339 0.1378 0.1417
e 0.500 0.0197
L 0.30 0.40 0.50 0.0118 0.0157 0.0197
ddd 0.08 0.0031
Number of pins
N 32
Doc ID 15962 Rev 7 117/124

Figure 49. UFQFPN28 28-lead very very thin fine
pitch quad flat no-lead package outline
(4 x 4)
(1)
Figure 50. Recommended footprint
(dimensions in mm)
(1)

A0B0_MB
e
b
T
Al
L
Ll
Table 67. UFQFPN28 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4),
Dim.
mm inches
(1)
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0 0 0.050 0 0 0.002
D 3.900 4.000 4.100 0.1535 0.1575 0.1614
E 3.900 4.000 4.100 0.1535 0.1575 0.1614
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
L1 0.250 0.350 0.450 0.0098 0.0138 0.0177
T 0.152 0.0060
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e 0.500 0.0197
Number of pins
N 28
118/124 Doc ID 15962 Rev 7
Figure 51. WLCSP28 28-pin wafer level chip scale package, package outline

Bump side
Die D
Notch
Side view
Detail A
Wafer back side
A1 ball
location
Bump
eee Z
A1
Detail A
rotated by 90 C
aaa
D
ME_A0AM
Seating plane
A2
A
X Y
(4X)
Z
Z 0.10
b(28x)
E
e1
e3
e2
e4
G
F
Dim.
mm inches
(1)
A 0.440 0.590 0.640 0.0173 0.0232 0.0252
A1 0.165 0.190 0.215 0.0065 0.0075 0.0085
A2 0.375 0.400 0.425 0.0148 0.0157 0.0167
b 0.265 0.270 0.275 0.0104 0.0106 0.0108
D 1.677 1.697 1.717 0.0660 0.0668 0.0676
E 2.815 2.835 2.855 0.1108 0.1116 0.1124
e1 1.190 1.200 1.210 0.0469 0.0472 0.0476
e2 0.390 0.400 0.410 0.0154 0.0157 0.0161
e3 0.390 0.400 0.410 0.0154 0.0157 0.0161
e4 2.390 2.400 2.410 0.0941 0.0945 0.0949
Doc ID 15962 Rev 7 119/124
F 0.239 0.249 0.259 0.0094 0.0098 0.0102
G 0.208 0.218 0.228 0.0082 0.0086 0.0090
eee 0.050 0.0020
Number of pins
N 28
package mechanical data (continued)
Dim.
mm inches
(1)
Device ordering information STM8L151xx, STM8L152xx
120/124 Doc ID 15962 Rev 7
11 Device ordering information
Figure 52. Medium density STM8L15x ordering information scheme
STM8 L 151 C 4 U 6
Product class
STM8 microcontroller
Pin count
C = 48 pins
K = 32 pins
G = 28 pins
Example:
Sub-family type
151 = Ultralow power
152 = Ultralow power with LCD
Family type
L = Low power
Temperature range
3 = - 40 C to 125 C
7 = - 40 C to 105 C
6 = - 40 C to 85 C
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please contact the ST sales office nearest to you.
Program memory size
4 = 16 Kbytes
6 = 32 Kbytes
Package
U = UFQFPN
T = LQFP
Y = WLCSP
STM8L151xx, STM8L152xx Revision history
Doc ID 15962 Rev 7 121/124
12 Revision history

Table 69. Document revision history
Date Revision Changes
06-Aug-2009 1 Initial release
10-Sep-2009 2
Updated peripheral naming throughout document.
Added Figure 3: STM8L151Cx 48-pin pinout (without LCD) on
page 30
Added capacitive sensing channels in Features on page 1
Updated PA7, PC0 and PC1 in Table 7: Medium density STM8L15x
pin description
Changed CLK and REMAP register names in Table 13
Changed description of WDGHALT in Table 12
Added typical power consumption values in Table 18 to Table 26
Correct VIH max in Table 37
11-Dec-2009 3
Added WLCSP28 package
Modified Figure 8: Memory map on page 31 and added 2 notes.
Modified Low power run mode in Section 3.1: Low power modes on
page 15
Added Section 8: Unique ID on page 52
Modified Table 10: Interrupt mapping on page 47 (added reserved
area at address 0x00 8008)
Modified OPT4 option bits in Table 11: Option byte addresses on
page 49
Table 12: Option byte description on page 50: modified OPT0
description (disable instead of enable) and OPT1 description
Added OPTBL option bytes
Modified Section 9: Electrical parameters on page 53
02-Apr-2010 4
Changed title of the document (STM8L151x4, STM8L151x6,
STM8L152x4, STM8L152x6)
Changed pinout (V
SS1
, V
DD1
, V
SS2
, V
DD 2
instead of V
SS
, V
DD,
V
SSIO
, V
DDIO
Changed packages
Changed first page
Modified note 1 in Table 7: Medium density STM8L15x pin
description on page 37
Added note to PA7, PC0, PC1 and PE0 in Table 7: Medium density
STM8L15x pin description on page 37
Modified Figure 8: Memory map on page 31
Modified Table 68: WLCSP28 28-pin wafer level chip scale
package, package mechanical data on page 118 (min and max
columns swapped)
Modified Figure 51: WLCSP28 28-pin wafer level chip scale
package, package outline on page 118 (A1 ball location)
Section : on page 69: renamed Rm, Lm and Cm
EXTI_CONF replaced with EXTI_CONF1 in Table 13: General
hardware register map on page 51
Updated Section 9: Electrical parameters on page 53
Revision history STM8L151xx, STM8L152xx
122/124 Doc ID 15962 Rev 7
23-Jul-2010 5
Modified Introduction and Description
Modified Table 3: Legend/abbreviation for table 4 on page 27 and
Table 7: Medium density STM8L15x pin description on page 37 (for
PA0, PA1, PB0 and PB4 and for reset states in the floating input
column)
Modified Figure 1: Low density STM8L151xx device block diagram
on page 14, Figure 2: Low density STM8L15x clock tree diagram on
page 19, Figure 3.1: Low power modes on page 15 and Figure 3.5:
Low power real-time clock on page 19.
Modified CLK_PCKENR2 and CLK_HSICALR reset values in
Table 13: General hardware register map on page 51
Modified notes below Figure 8: Memory map on page 31
Modified PA_CR1 reset value in Table 7 on page 32
Modified reset values for Px_IDR registers in Table 7 on page 32
Modified Table 14: Voltage characteristics on page 54, Table 15:
Current characteristics on page 55
Modified V
IH
in Table 37: I/O static characteristics on page 77
Modified Table 20: Total current consumption in Wait mode on
page 61
Modified Figure 36: Typical application with I2C bus and timing
diagram 1) on page 89
Modified I
L
value in Figure 38: Typical connection diagram using the
ADC1 on page 96
Modified R
H
and R
L
in Table 45: LCD characteristics on page 103
Added graphs in Section 9: Electrical parameters on page 53
Modified note 3 below Table 44: Reference voltage characteristics
on page 89
Modified note 1 below Table 45: TS characteristics on page 91
Changed V
ESD(CDM)
value in Table 55 on page 100
Updated notes for UFQFPN32 and UFQFPN48 packages.
11-Mar-2011 6
Modified note on true open drain I/Os and I/O level columns in
Table 7: Medium density STM8L15x pin description on page 37.
Remapping option removed for USART1_TX, USART1_RX, and
USART1_CK on PC2, PC3 and PC4 in Table 7: Medium density
STM8L15x pin description on page 37.
Modified IDWDG_KR reset value in Table 13: General hardware
register map on page 51.
Replaced VREF_OUT with VREFINT and TIMx_TRIG with
TIMx_ETR.
Added Table 10: Factory conversion registers on page 49. Modified
reset values for TIM1_DCR1, IWDG_KR, RTC_DR1, RTC_DR2,
RTC_SPRERH, RTC_SPRERL, RTC_APRER, RTC_WUTRH, and
RTC_WUTRL in Table 13: General hardware register map on
page 51.
Added notes to certain values in Section 9.3.9: Embedded reference
voltage on page 89 and Section 9.3.10: Temperature sensor on
page 91.
STM8L151xx, STM8L152xx Revision history
Doc ID 15962 Rev 7 123/124

11-Mar-2011 6 contd
Modified OPT1 and OPT4 description in Table 12: Option byte
description on page 50.
Updated Section 9: Electrical parameters on page 53 standard
I/Os replaced with high sink I//Os.
Updated R
HN and
R
HN
descriptions in Table 45: LCD characteristics
on page 103.
Added Tape & Reel option to Figure 52: Medium density STM8L15x
ordering information scheme on page 120.
06-Sep-2011 7
Features: updated bullet point concerning capacitive sensing
channels.
Section 3.1: Low power modes: updated Wait mode and Halt mode
definitions.
Section 3.4: Clock management: added kHz to 32.768 in the
System clock sources bullet point.
Section 3.12: System configuration controller and routing interface:
replaced last sentence concerning management of charge transfer
acquisition sequence.
Added Section 3.13: Touchsensing
Section 3.19: Development support: updated the Bootloader.
Table 5: Medium density STM8L15x pin description: added LQFP32
to second column (same pinout as UFQFPN32); Timer X - trigger
replaced by Timer X - external trigger; added note at the end of
this table concerning the slope control of all GPIO pins.
Table 11: Interrupt mapping: merged footnotes 1 and 2; updated
some of the source blocks and descriptions.
Section 7: Option bytes: replaced PM0051 by PM0054 and UM0320
by UM0470.
Table 13: Option byte description: replaced the factory default
setting (0xAA) for OPT0.
NRST pin: updated text above Figure 33; updated Figure 33:
Recommended NRST pin configuration on page 91.
Table 47: TS characteristics: removed typ and max values for the
parameter T
S_TEMP
; added min value for same.
Table 48: Comparator 1 characteristics: added typ value for
Comparator offset error; added footnote 1.
Table 49: Comparator 2 characteristics: updated t
START
, t
dslow
, t
dfast
,
V
offset
, I
COMP2
; added footnotes 1. and 3.
Table 50: DAC characteristics: updated max value for DAC_OUT
voltage (DACOUT buffer ON).
Section 9.3.14: 12-bit ADC1 characteristics: updated.
Replaced Figure 44: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package
outline and Figure 45: UFQFPN48 7 x 7 mm recommended footprint
(dimensions in mm).
Figure 52: Medium density STM8L15x ordering information scheme:
removed TR = Tape & Reel.
STM8L151xx, STM8L152xx
124/124 Doc ID 15962 Rev 7

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