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8 A Instruction Set Format

The document discusses different types of instruction set architectures based on the number of addresses in instructions. It describes four types: three-address, two-address, one-address, and zero-address instructions. Three-address instructions use separate fields for operands and destination. Two-address instructions have one implicit operand. One-address instructions use an implied accumulator register. Zero-address instructions are found in stack-based computers and do not explicitly specify operands or destination.

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102 views2 pages

8 A Instruction Set Format

The document discusses different types of instruction set architectures based on the number of addresses in instructions. It describes four types: three-address, two-address, one-address, and zero-address instructions. Three-address instructions use separate fields for operands and destination. Two-address instructions have one implicit operand. One-address instructions use an implied accumulator register. Zero-address instructions are found in stack-based computers and do not explicitly specify operands or destination.

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abhinavsaini0589
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Unit-3 Instruction Set Architecture (Lecture-8) Lecture 8:

Unit -3 Instruction Set Architecture

Instruction Set based classification of computers Three address instructions Two address instructions One address instructions Zero address instructions

Instruction Set Architecture (ISA) is an abstraction on the interface between the hardware and the low-level software. It comprises of: Instruction Formats Addressing Modes Operation in Instruction Set Instruction Format It is the representation of the instruction. It contains the various Instruction Fields: opcode field specify the operations to be performed Address field(s) designate memory address(es) or processor register(s) Mode field(s) determine how the address field is to be interpreted to get effective address or the operand The number of address fields in the instruction format: depend on the internal organization of CPU The three most common CPU organizations : - Single accumulator organization: ADD X /* AC AC + M[X] */ - General register organization: ADD R1, R2, R3 /* R1 R2 + R3 */ ADD R1, R2 /* R1 R1 + R2 */ MOV R1, R2 /* R1 R2 */ ADD R1, X /* R1 R1 + M[X] */ - Stack organization: PUSH X /* TOS M[X] */ ADD ADDRESS INSTRUCTIONS: Three-address Instructions - Program to evaluate X = (A + B) * (C + D): ADD R1, A, B ADD R2, C, D MUL X, R1, R2 - Results in short program - Instruction becomes long (many bits)

/* R1 M[A] + M[B] */ /* R2 M[C] + M[D] */ /* M[X] R1 * R2 */

Unit-3 Instruction Set Architecture (Lecture-8) Two-address Instructions - Program to evaluate X = (A + B) * (C + D): MOV R1, A ADD R1, B MOV R2, C ADD R2, D MUL R1, R2 MOV X, R1

/* R1 M[A] */ /* R1 R1 + M[A] */ /* R2 M[C] */ /* R2 R2 + M[D] */ /* R1 R1 * R2 */ /* M[X] R1 */

One-address Instructions - Use an implied AC register for all data manipulation - Program to evaluate X = (A + B) * (C + D): LOAD A /* AC M[A] */ ADD B /* AC AC + M[B] */ STORE T /* M[T] AC */ LOAD C /* AC M[C] */ ADD D /* AC AC + M[D] */ MUL T /* AC AC * M[T] */ STORE X /* M[X] AC */ Zero-address Instructions - Can be found in a stack-organized computer - Program to evaluate X = (A + B) * (C + D): PUSH A PUSH B ADD PUSH C PUSH D ADD MUL POP X

/* TOS A */ /* TOS B */ /* TOS (A + B) */ /* TOS C */ /* TOS D */ /* TOS (C + D) */ /* TOS (C + D) * (A + B) */ /* M[X] TOS */

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